From patchwork Fri Jan 3 06:04:03 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vishwaroop A X-Patchwork-Id: 854995 Received: from NAM02-BN1-obe.outbound.protection.outlook.com (mail-bn1nam02on2070.outbound.protection.outlook.com [40.107.212.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B09A813B2A4; Fri, 3 Jan 2025 06:04:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.212.70 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735884289; cv=fail; b=M1ruiVLg0PtgOCEh7YtJXZ4jIZ5jauzka/R00FMt92sgi8eet3/e5yFG4MmvUFwZJO0s24o7nhqzUe84zyn4HJyRPoL1FoZGW+YS5iTu4h++Zi544Ezu1aAe/aW/15zSawvI+9niO3xaEjHqPf/76DYlp/30egzKft8++jfBGq0= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735884289; c=relaxed/simple; bh=4kaJY8q9FAhBZcx/7L5l123mY5sYYEKau5kVSxHaRR8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=jXW19NVljRNzdH7VDg6644N63RvOKs5cl1eclKlRkulF+Ktz+I00rVtguOhmx+2EGI/uRQgXACx4KwnUd0ZzIAEuN9/V5RvC98sE7/X0joa8HJqHcJGL1JJYSo1ziH8+Eb9h/poNwVppgGQHBlsOVaEEkxVwWlxt75Iwx6uPBHM= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=ajeNiJ7f; arc=fail smtp.client-ip=40.107.212.70 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="ajeNiJ7f" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=Pi/BwosY2+g5GJuzHPXyW3WYsB2ECzyZSDAjjUpsiF1+qVV2cuSMUbnOzNOjOMeNrnB456Uf+HDYXoWxz4MRAjAcC01852v9wA0TjpKd+gwQj+W0QfjEmCm03ZldeXR/VasSmAPwKvRgxJA++jfepOik85kkrIwIPxS+R5HfAoHK3mvBL+h/S7XK38xZTcPI6+Jv8C+tcmtirWeg8B/vzT5iwtrBGJr4JhReSJhZUC58j0smD0v3TL2oeWfqGeZD+zXeeD0NDntHkS0QIegpnFLkiuhVcnH7nGPphJloFO8Q31upOt9RRCP6OszQYlp9uC9Y1mWiKw7oJupb3NHadQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=d6UpUd9yyKwF5dVgltUuKkugUuKM24a5sAlTMF8TBE0=; b=sTlnDgQ6QWA9U3hkkC3IgMtprUfNS8MeD3Z3cucEGQJGWFlGAhRZvmeKYUJ0cPvnv+/NkSSLOzEtiCXLkVww21hpAm36lmq2PyGmFpFleidnR/Wqa0dvdjAkG/+HsHR1W56UztMd8sjbs8f7fjPdDJGLUMzPa0u1IYStu+QFLnGiXMiVKwAM1v0ZR6BWps8/GZt+aVhClD/A7qh4v3VjnoVH2RPpXGXKxTfI0GGB3I9m9eCyTDm7IC9hVhYbEN8b1tP2vaOkCJC5MTlUMKNbo13+Qj4QubWuqpzEosuxObOpppxjzQ75iex/95KCqhpfVubVVROEWotnRSIk3RZviA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=gmail.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=d6UpUd9yyKwF5dVgltUuKkugUuKM24a5sAlTMF8TBE0=; b=ajeNiJ7fFOYYFo9Q5BcTsNR/+TCKhfVFM52uCtEdN/gRPePuJik3pDQpfbkXMXIYcvFotiBcc87BVY8YwVrVKphWYsIpi8Tzxfr8W3hOz4Gc0hJz/eVB4igfM3+GspnJ92OZeKtIUAojz0zIUwkirL7GYFEzEbfkti9CmHKzXhmUPHMO77iAbnRHEhbqEAk++772gH0sp4vPICI5IEq+bvfm3mgq8w5SwY4TWYe85V151uZJxBzk840cl99uVHvpmNYuiXYaaUwF8XxwbQFVL428CkN9IEA31VO9LgAojgP6Wv90dDwFU1NAHQlzvr9zcQF75U2JEArlY7Bbon1NPQ== Received: from SN7PR18CA0010.namprd18.prod.outlook.com (2603:10b6:806:f3::9) by BL3PR12MB6402.namprd12.prod.outlook.com (2603:10b6:208:3b2::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8314.14; Fri, 3 Jan 2025 06:04:37 +0000 Received: from SN1PEPF0002636C.namprd02.prod.outlook.com (2603:10b6:806:f3:cafe::5e) by SN7PR18CA0010.outlook.office365.com (2603:10b6:806:f3::9) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.8314.14 via Frontend Transport; Fri, 3 Jan 2025 06:04:36 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by SN1PEPF0002636C.mail.protection.outlook.com (10.167.241.137) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8314.11 via Frontend Transport; Fri, 3 Jan 2025 06:04:36 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Thu, 2 Jan 2025 22:04:28 -0800 Received: from rnnvmail204.nvidia.com (10.129.68.6) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Thu, 2 Jan 2025 22:04:27 -0800 Received: from build-va-bionic-20241022.nvidia.com (10.127.8.12) by mail.nvidia.com (10.129.68.6) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Thu, 2 Jan 2025 22:04:24 -0800 From: Vishwaroop A To: , , , , , , , , , CC: Subject: [PATCH V1 2/6] spi: tegra210-quad: Update dummy sequence configuration Date: Fri, 3 Jan 2025 06:04:03 +0000 Message-ID: <20250103060407.1064107-3-va@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250103060407.1064107-1-va@nvidia.com> References: <20250103060407.1064107-1-va@nvidia.com> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002636C:EE_|BL3PR12MB6402:EE_ X-MS-Office365-Filtering-Correlation-Id: 74809e57-8ac4-4806-1576-08dd2bbc8091 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|36860700013|82310400026|376014|921020; X-Microsoft-Antispam-Message-Info: Tx8jC+ZumRFkmcBTfqctk1Sfii3jSl4n4pusxiYIEvsqxfPYQvOcMDq/f/Te9xhJtajP/1HHqZcuwSczY6UjAzT1l94uz8P4P86zoyjrLaVlrldGG+5hHSJsTk9M17NFZlzKEBRmjYMK49fbBXHzucSSK5gVxpxQgmAlyWXPSROakt8iyqmvBnYdHW1j2I8gDXYlC7VY4JHMoWrXNeNN1NjaqRlaFkVbU+iiRDNf+Yp1j1f/bz856CX9FZ+AluTz7fC7oXg7S2qD8gqgtZiEjFG5LhsqqEsOYTn9+YDtgNXO6QGL1PdoMK3DsR70ph0biIkJZXZ8xkUtNhYweu52WnNqSRlgBAhFTYlklPeF0XA07mGVq6+nlDyhRYmP8a3y696B24RMbunAjIRtku/FK8GgPjoXNZO110q6mlA8Y2fbtJQWu3Ox+j3pmtQ2Pm4sK6nPYRQwZgS+jgBzevM2kxJoMAbMW82YVeSP4csiVMOafVZPuuMYQYsgLe18Ywx2wrFnhxQquTXzWDPasc+ZyvziaW+57dPUDepQBfIUFxKPxEljOCKG1d1cg8kLoGXooEBUEVlfpIj6lJyoXODRtPsS+g3EbSYEgxM65/B4kwEkhFJrDUdDeE8YQN4L5vLM4/nbzgLQ87ie1DhKUAo5eRTqzg06I+p31URHmzpAWF5meoxc8YDKlAu+TLSFDpQri50rOPAQD0KpAV8gRgaTj4PbMtVtfYYFtIlnV/L8cpHtW2lIYzHv8JooMe213/QG1/tlBjJEJaEjgJ6aC/hsIAaW/U4A0AFBTKhotxFAklC4jTW4y5d1wEo/Z+e5IKNuDyTxnVjTAuQPuUNq24Mja7qT46kYBQdkNkU1JSwURMf8LgmxDw/QNqWWCdFsYGAdx+xmcmFa7jdZPs5slYhKvF3E4rHef6Whk/Re9/6DCWHwfbuSEQzectDwGO5gsx70vwMMv2UK9/IT3zKND0cbWBDCRCVGoo+i6DXCBmG01OssJnJe6CFJQkojjqBGVhzr2HBYpcljjoh6XxqzCKPumByhANyo2w8I17HKIYUt12HUlYI0tSr5aHH112rOgqAqfeGCRjbYVPRWzPhpmO1xWq8udEiJQo1lR02yALUwO2t18HBeob+pFQMRtDrTl3t4cyXDk3ZUL8M9CMy/lVljUbm1JasvXZzYlL5xukR7UA8FADU4Td/6yUTk8+wbVEVpsisj+c5fpiD9+ZrzQmGZFWQx9mWc6wi9zvHyiY1xJcluEAjJdKNUyOer9UAptYrQKutAQ2gGi0wgQFS9ANdFrohDrkg7p4ka1SZpM4ch6s2e80pkUfDd39Dd9OzioGtTwKmhFGYUlKZ6Q89VYJ1WhdB9U2QxZeVDDOGLEjRFoY2DlYdPBKWG7EA7gUJ1CUt/EAzGWVGfZrFEd8fqvZX20foQWA5Rrp5rpFQtius38sBCzrxgw25k/jxwyMh/ZX7gBzIf/fdM3O11aGd2RMmrh07CFG6cmlx5SoywKmUuiUQ= X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(1800799024)(36860700013)(82310400026)(376014)(921020); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Jan 2025 06:04:36.6066 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 74809e57-8ac4-4806-1576-08dd2bbc8091 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002636C.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL3PR12MB6402 Adding support for the dummy sequence configuration. The dummy sequence introduces a delay between the command and the data phases of a transfer. This delay, measured in clock cycles, allows the slave device to prepare for data transmission, ensuring data integrity and proper synchronization. Change-Id: I4dc347a247830452754f83e88aa95a7d231722cd Signed-off-by: Vishwaroop A --- drivers/spi/spi-tegra210-quad.c | 31 ++++++++++++++++++++++++++----- 1 file changed, 26 insertions(+), 5 deletions(-) diff --git a/drivers/spi/spi-tegra210-quad.c b/drivers/spi/spi-tegra210-quad.c index 08e49a876894..02478e8efc8f 100644 --- a/drivers/spi/spi-tegra210-quad.c +++ b/drivers/spi/spi-tegra210-quad.c @@ -22,6 +22,7 @@ #include #include #include +#include #define QSPI_COMMAND1 0x000 #define QSPI_BIT_LENGTH(x) (((x) & 0x1f) << 0) @@ -156,10 +157,14 @@ #define DATA_DIR_RX BIT(1) #define QSPI_DMA_TIMEOUT (msecs_to_jiffies(1000)) -#define DEFAULT_QSPI_DMA_BUF_LEN (64 * 1024) -#define CMD_TRANSFER 0 -#define ADDR_TRANSFER 1 -#define DATA_TRANSFER 2 +#define DEFAULT_QSPI_DMA_BUF_LEN SZ_64K + +enum tegra_qspi_transfer_type { + CMD_TRANSFER = 0, + ADDR_TRANSFER = 1, + DUMMY_TRANSFER = 2, + DATA_TRANSFER = 3 +}; struct tegra_qspi_soc_data { bool has_dma; @@ -1089,6 +1094,13 @@ static int tegra_qspi_combined_seq_xfer(struct tegra_qspi *tqspi, xfer->len); address_value = *((const u32 *)(xfer->tx_buf)); break; + case DUMMY_TRANSFER: + if (xfer->dummy_data) { + tqspi->dummy_cycles = xfer->len * 8 / xfer->tx_nbits; + break; + } + transfer_phase++; + fallthrough; case DATA_TRANSFER: /* Program Command, Address value in register */ tegra_qspi_writel(tqspi, cmd_value, QSPI_CMB_SEQ_CMD); @@ -1300,7 +1312,9 @@ static bool tegra_qspi_validate_cmb_seq(struct tegra_qspi *tqspi, list_for_each_entry(xfer, &msg->transfers, transfer_list) { transfer_count++; } - if (!tqspi->soc_data->cmb_xfer_capable || transfer_count != 3) + if (!tqspi->soc_data->cmb_xfer_capable) + return false; + if (transfer_count > 4 || transfer_count < 3) return false; xfer = list_first_entry(&msg->transfers, typeof(*xfer), transfer_list); @@ -1310,6 +1324,13 @@ static bool tegra_qspi_validate_cmb_seq(struct tegra_qspi *tqspi, if (xfer->len > 4 || xfer->len < 3) return false; xfer = list_next_entry(xfer, transfer_list); + if (transfer_count == 4) { + if (xfer->dummy_data != 1) + return false; + if ((xfer->len * 8 / xfer->tx_nbits) > QSPI_DUMMY_CYCLES_MAX) + return false; + xfer = list_next_entry(xfer, transfer_list); + } if (!tqspi->soc_data->has_dma && xfer->len > (QSPI_FIFO_DEPTH << 2)) return false; From patchwork Fri Jan 3 06:04:05 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vishwaroop A X-Patchwork-Id: 854994 Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2062.outbound.protection.outlook.com [40.107.92.62]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 66B571B140D; Fri, 3 Jan 2025 06:05:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.92.62 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735884305; cv=fail; b=bAt6JMl3pp5bAvCB0O9NkxxV18Ewr6x72VT5KxRGKV9JvNUTLLhCDeHng+7e4sYzZSYUICMPDJMRLqN6Rk6uTUPC2jFioZVD0/OB3IyTd3xY3VyHat16iAJnGvZMRjPPgUazPWWBf8EAFOhJ9wZL7Wzu9P58VeUQK2IzbuDSM+8= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735884305; c=relaxed/simple; bh=fjFZXacRjlO46ED7wsWdDLW3BUe4m8VXI4rQx6OOkOE=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=pGzxY89SpYPJ7WKn4xGwqZkuGe5kQTwZIrM82MRr3+k4hoLcFttfo6iizQuqemt2TSlJ8IRKibWTkVByH73Uf2Y1W0+byYGltxXHNlHR0zmmCPoFlVifliigPN0F4KBLcJBgm2WTxUlHc+V+wNMseXKr7QQnn9dpgtkw8rcl+SI= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=Tkk/VZlb; arc=fail smtp.client-ip=40.107.92.62 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="Tkk/VZlb" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=LefkAeqckosZBNYhkAfA7iHroiftvpaMkx+NPNZE1HMo3agFR3KeWQ5o/+lQZwODIbiDrs4ZHCMNvhkF1zoq+XWGZvcxVB8iEWFpgXeCc/niUC6mkt2xIiEdG1rOdbjknhjfhXYEmyUTnzXczxAEty2fF97xLsHqR2XnO5XuG5JXS6vHNpBVAfVloSuqrs8PCYtClo/ewp6mEIG300jWdyinQDHuPWYVz6ZxHVuc2fhD99XnNSmaHuvuZfA9PFoLAHc8jyx2x2GHpxpSGHZeGtVRkjoJatfb6lV5hCGewC1Y038Qsdo95mmBVsx5bZusUQEuV28B/cH5L01owQ44uw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=1TKqPKRKHFV1ybDnw3fWZCMmtWrBHiBlzsYqDrfmAws=; b=RV5ZuiUaRLLeiv/GbW8lpIsI+9vhwiSLLoNK4usWoE8Z0FIZN8OHu9xH+G41e/vxhAvFrc9BY9v1RtNLirHFk/S/fyytOt32vTALrX0OYcQGyeu2ZRDYkkogkOyBLfLX0Se0IhXQZOIRv6twzMpUiDjYLR617Xq8VIbqyYuADqjnKK7pmyyZaFwWiS8Mg0YYD2LtsebU/zeqi8euEOFYRyYYHN//0X8KJUoqMW0YDNSS6me+a27EftH6E5o0ZVvgZ9ql7BgJrTFscdgZJ8/Btb33PZOsWnnH6nuXdGNDImPjodEjfKK2zAk52VzMY7HnNIv55jCs86IRJqqghCM6tg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=gmail.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=1TKqPKRKHFV1ybDnw3fWZCMmtWrBHiBlzsYqDrfmAws=; b=Tkk/VZlbHX7vReUtubeELHRZTqm3SvWWUtEQS+Qt5UZIn8mkeXtDJbKPubT7d/dFTus9QtHJike7KQCffWIzbMa26XD3u6KZwRZDK2trdgE3/M9Ow7g1b0ZDtzstr7Bl02Rjhn9JCgTOtTZPfPfmDBpF+q89qp3bZ/Xyhgwrn03+xymHjm+LAhf53iTHrL7EfjD6qROYfcworJzbQzEiTl54tyOgiLSHNudshjj+f+LUGAvjAHTpZnhB0XIqPvYS73/noHVyDZhT93MI/PXMRq1mwQiLf/0scQWmkxnLiXJOvm3sFsThlyHfKYmdM02ATPc7QS6NtNy356Lxy31dmQ== Received: from LV3P220CA0009.NAMP220.PROD.OUTLOOK.COM (2603:10b6:408:234::18) by BL3PR12MB6545.namprd12.prod.outlook.com (2603:10b6:208:38c::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8293.20; Fri, 3 Jan 2025 06:04:55 +0000 Received: from MN1PEPF0000F0E4.namprd04.prod.outlook.com (2603:10b6:408:234:cafe::fe) by LV3P220CA0009.outlook.office365.com (2603:10b6:408:234::18) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.8293.16 via Frontend Transport; Fri, 3 Jan 2025 06:04:55 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by MN1PEPF0000F0E4.mail.protection.outlook.com (10.167.242.42) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8314.11 via Frontend Transport; Fri, 3 Jan 2025 06:04:55 +0000 Received: from rnnvmail205.nvidia.com (10.129.68.10) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Thu, 2 Jan 2025 22:04:40 -0800 Received: from rnnvmail204.nvidia.com (10.129.68.6) by rnnvmail205.nvidia.com (10.129.68.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Thu, 2 Jan 2025 22:04:39 -0800 Received: from build-va-bionic-20241022.nvidia.com (10.127.8.12) by mail.nvidia.com (10.129.68.6) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Thu, 2 Jan 2025 22:04:36 -0800 From: Vishwaroop A To: , , , , , , , , , CC: Subject: [PATCH V1 4/6] spi: tegra210-quad: remove redundant error handling code Date: Fri, 3 Jan 2025 06:04:05 +0000 Message-ID: <20250103060407.1064107-5-va@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250103060407.1064107-1-va@nvidia.com> References: <20250103060407.1064107-1-va@nvidia.com> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MN1PEPF0000F0E4:EE_|BL3PR12MB6545:EE_ X-MS-Office365-Filtering-Correlation-Id: 9957d9db-8809-4229-40af-08dd2bbc8b94 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|376014|1800799024|36860700013|82310400026|921020; X-Microsoft-Antispam-Message-Info: SC2s1dzawXLpZRnS+TjsBMh0JzPJqNd/qPjj0xOiRwyhzyx9ib0QPYDCXY0+zh/5JzmbsLT4nHhUZ0rivI4eTMIsIA5taZhH1mkiZccnMR2Wy1Z3rNnld6qUKFELdLJAj5XCT6djX5tttXJzdiWk6zbjiuH3RQBlg/++FEdVj0K32CnaEN49mRiiSCGcqQnC8N6DJq4fs6xI2jAMONm0Z7NSMkdUlo2koTbMXH/W/yqJ1iEjoZqApfSyOMlUnT/XOKHFrueQlCaEGlPFkhfDPVoyimPBxMTT+3lAaNwO0UVH2MbTrHKDeV+kG/qMaXTgrcFqJfoocGK5FOu+i0PvoWaKlCMUibOG7LPZGAZ52YTUcYxo7syqvBmEpsokpKx+QrTsS+OLO9gQmSGHowREtPUFOcaUT9ar8s+GPU+Ft3Sc2F/N+xZIWekeqUCRAXYppSVmE3wksDTvntZlGGHUfN8GkZDelWADzJ2pIfDCi/VFQyV/q0cUTdFFDiIaAGfSbKzkcGDqgpUEJOobAKrGUvkmuCBQxLsObuDRlFvLyx1+nJurw1E3caxxsh7cvEzRi74Cem0j0manHnE1SPh9bimug8ZmmFHpev99cj32FwkOLqB/A4OdrKKF0odUIBxJ7cJzKrQalYDLz6cpoTJjB1uqTOA+svEg4xiWMWyCoPEU7WPUuPUUHgZwmHj44AFrKvftJ7blS9dsiFVEzrek2nnQb0eDY6Fty9hQJV33cdlCLXFwuFud12SNeoaThEEdeQwaRNFPpH+pu1XuLzOqRMB0pygA82Y+8BIJ1RDzkERCF++a9VOEMww2yoYfectfzkTGLSA1PDY4ibsXA671dlIdmOqmHCbfsfoJrO2/V6CnZd0DbRrstRmcShmmDzkbWUvZ02iIUaQ1WVRA5+AHjzBq6EI4se3SFpNWoK1SxaKIlZ1OREEUfrx/MJ5GwbJMwLtZrZ7k0DIPbQrW1SMRFrcpqR4lCYdU/9N1i4mTZwrPWEvCXuHRoQzqk56MZdhE27Gi3SrqQnyIGG9MmdSA5qSkRhjBF9XMcGJwtuq/8281za14rrv6la8lWLPPRl2tnJaAMxYLuAHP5kYyKkuNd20VHoMxaai87hXEJW9oObTuOlLvsB7BsW4omD/dUe8b7Oye4Eem+zKhJTRWSrM9jrnV8gS0u9sASOtQnPhkvVdkKz4QPT8ObWD/+g09L86RFm/dEPmgKJhhx4UWbrg1I1j8DXA983LFB+K6xOLxwph2Lf8vSUFoEcEDLXy5O1tKzHHnD3BHDP5yRBEyVVwWR9d7kh0rS6sZaCXurJTr23E/EgioZOQaLVVXLskgOSBkEbBugOE6I6bJwVpwIG0OlVxP7BdnRdvjrahM8JcWdhR215DEjrgHFDo2b0SRDNp7tyEZ1fQeWHfuzj3wXzF2/hTgPvYqzbo1UfJ4N/6wVKvUxtm2nIfffhIrg2KyEfGH8ULSlOBT3xD1xaIlRfJc7mx72j1IbIqfLjhjF0XAVRk5wcOx8AAZxIYg+r7Th+0F X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(376014)(1800799024)(36860700013)(82310400026)(921020); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Jan 2025 06:04:55.0042 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9957d9db-8809-4229-40af-08dd2bbc8b94 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000F0E4.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL3PR12MB6545 Remove unnecessary error handling code that terminated transfers and executed delay on errors. This code was redundant as error handling is already done at a higher level in the SPI core. Fixes: 1b8342cc4a38 ("spi: tegra210-quad: combined sequence mode") Change-Id: I9e77732db64d7a1674b7e87048c7b59d8dbab645 Signed-off-by: Vishwaroop A --- drivers/spi/spi-tegra210-quad.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/spi/spi-tegra210-quad.c b/drivers/spi/spi-tegra210-quad.c index 43d6587fad09..2d7a2e3da337 100644 --- a/drivers/spi/spi-tegra210-quad.c +++ b/drivers/spi/spi-tegra210-quad.c @@ -1187,10 +1187,6 @@ static int tegra_qspi_combined_seq_xfer(struct tegra_qspi *tqspi, exit: msg->status = ret; - if (ret < 0) { - tegra_qspi_transfer_end(spi); - spi_transfer_delay_exec(xfer); - } return ret; } From patchwork Fri Jan 3 06:04:07 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vishwaroop A X-Patchwork-Id: 854993 Received: from NAM04-BN8-obe.outbound.protection.outlook.com (mail-bn8nam04on2083.outbound.protection.outlook.com [40.107.100.83]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B38931B3930; Fri, 3 Jan 2025 06:05:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.100.83 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735884320; cv=fail; b=oCL4pnRyRVxp9T0scZ8vpvQVU/JKPyvwVci5zEgXvUieOaapr0K6Kdq715jPP3pXbBDeoeTKVvJ4MoQRRiTGeCtBWjJwl5lFb1kf/XdV5QqC8kpHwNxqVUpBoQXOtMeU5gIh35xEqhDYPHlA6sx9k96uzQN+S6IyceI5m3knvaU= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735884320; c=relaxed/simple; bh=7fsVUHTnB9ufRAf1frFjvio3iWosoZajJE6m4uy6Tc8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=mGFNz3JZDiKx1dS6VzCZ9s6oEAHKClCAsfdJAPmJS/TjTpjPZkzOLNU3dlSX5QZ+A22JBYoloNJvZGpH4h09PivqQHaCqdGb9dUq1oXW4lr9oigrmVo8f1bCW61btwFL6so/9sb7FpODt2to3BJGytTxoK9XWwlRQbTJsOD/G5E= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=tgHkgq5g; arc=fail smtp.client-ip=40.107.100.83 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="tgHkgq5g" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=oZwct2NXHmB/bbDVM1Q2dCDQXOkpufWPrMhHEr7oWKYK6NfmsSOguSSxGOLb7+zhb/WbgchywlP4ejfMtZSRGsX1UhRYz9cyFk//d+UJzTEW3KWHRd8a06TCmRncIm7vBd+lW07iwO5niF7nRMhLHUGHXh+5GsD0dMEE+2JLUN5gfU4c+wGC496xPLvqZ2/0U8D6ZTO3N4SlStMD9TSm/jGcdyd8XbDH5oUY4R2ErVY0O9zmZDIC90hsBT3LaznafS4SkjsLMKvJA70retk6zFQh4nywbiPTf5QR8VZdV1QdJ1jokIzTFF+Ff+qgIFm3xPSng8tSHoNr5uN0BMNblw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=S6qVPy9nXDFZQ91ewpMGHL+gGXO9Upb0TeG2tGeBwaA=; b=w/YvdMui/G+tZDJswbgxj0b5k983/q3SkXxTOzgF3xlrYGH7UUghQTj5R2M6J9AKvYgfvs5y06aeG2nrTcOT8pkcrFkFMZCab1ID42bdgMxA9fNes/sirivDLDAP/lK7AqCoj9sYgBEmd+tBLZw2URXcJGb8i3MD+elnPOH6xxFYeQsuQueuecPu/KfiW9O4offUuQACFgrnhlxr4AX1HW3H6PnAb3MyLt4RK7nHeFQmEQf/yJR8S6qiXenssKqqYmnNeacehKdenmq6M8R0C3bI21DpQO2FETRwBHpY8Za8mB7qveiLSkB0jesUKjZqzUAAb91shRnA+z/BKPkEvg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=gmail.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=S6qVPy9nXDFZQ91ewpMGHL+gGXO9Upb0TeG2tGeBwaA=; b=tgHkgq5gk4EGTo+Iy8lV4mdBIc9J2uBeKwfdF6kI77sImuPV0UWB+dGXDyao/kenRv6NpV9E9YSgjLTloz7xQ1b9GrPy3qvNesZLoQKCDa1rCqWDl2HBzAKGMfLqP4kCFUISPcSMxFmfsgHl0HeX15pFRuhmQ4sBrC/p3e02dT/IpTASuHR9Ln3B1eEG5qcYUEfe4xEYupVtPNv9GOmf/3Bi2vpsBKvebI/N11xFt4xaRtXn9j6X89C2xZdx46PXneqJa/bgv1lWbdgPL+VEawqqcd+JGOJB9WLMP0WpN3ykbRjNG4Ezext9Gt/C0TmCRjjpFfAOn4xx6Ed/ntPW/Q== Received: from LV3P220CA0004.NAMP220.PROD.OUTLOOK.COM (2603:10b6:408:234::16) by BY5PR12MB4178.namprd12.prod.outlook.com (2603:10b6:a03:20e::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8314.14; Fri, 3 Jan 2025 06:05:05 +0000 Received: from MN1PEPF0000F0E4.namprd04.prod.outlook.com (2603:10b6:408:234:cafe::25) by LV3P220CA0004.outlook.office365.com (2603:10b6:408:234::16) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.8314.13 via Frontend Transport; Fri, 3 Jan 2025 06:05:04 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by MN1PEPF0000F0E4.mail.protection.outlook.com (10.167.242.42) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8314.11 via Frontend Transport; Fri, 3 Jan 2025 06:05:04 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Thu, 2 Jan 2025 22:04:50 -0800 Received: from rnnvmail204.nvidia.com (10.129.68.6) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Thu, 2 Jan 2025 22:04:50 -0800 Received: from build-va-bionic-20241022.nvidia.com (10.127.8.12) by mail.nvidia.com (10.129.68.6) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Thu, 2 Jan 2025 22:04:46 -0800 From: Vishwaroop A To: , , , , , , , , , CC: Subject: [PATCH V1 6/6] spi: tegra210-quad: Introduce native DMA support Date: Fri, 3 Jan 2025 06:04:07 +0000 Message-ID: <20250103060407.1064107-7-va@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250103060407.1064107-1-va@nvidia.com> References: <20250103060407.1064107-1-va@nvidia.com> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MN1PEPF0000F0E4:EE_|BY5PR12MB4178:EE_ X-MS-Office365-Filtering-Correlation-Id: afbe2ff1-5f19-461a-9e03-08dd2bbc9142 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|376014|36860700013|82310400026|921020; X-Microsoft-Antispam-Message-Info: J3B1V8ExPztcu5PlRo4/SLY9BcAOtp1ttWFvwgRwvGFOoA2kiqBd3sC0Zu5eotjdw4B+vJXf5Q2nzvxpk30xku7UVkjbxVGpWdSp2SjlRHrnPmn6e2/ea3jw039u7OJcVgWfPMTX8UuLwj04OsRnw8OR71wuOrxAteZo4M8AmdTRXEN8/mtTx+Hb41sp4fQgK80ZNIhLylG3REiud7NNhITdPbZ2cQ4SlChjX+M62g1LYnCUshpltHfRVxvs5PcKFPllxYbrYv0KC6nv6SkAGWRqYoJiMOcykg79SySGlwWXcl822U+S1LI9vw5X6rsUL6NnzotPxq2tKQBpuUa0EVL34vbSuAI5Z/XT2lelfMHqOILWixPfUDZ18b1dXtS+I6vhfJMINwsXbD3pn11GBatQaaT/ZdeT84iFNKsCdwVTzrX9lA0r2Nq1/wQ0EfiVAwvFx4+lRjFYCo033D2Fde++9iMXRQs56I2BYSnDuf5hEKNeimGZNxUoprlXpIp39c/X/0C6Y7LhkyUtGgFlTiJ8wfEqh5UD+tU0+lTcjcuclNR0V8pCpePUfQhgMa6hIhb2y6qMBTy45TcGON5xbgft/+a0jrsWduI7IWiF595bKg2Inv0EGqzvMxUQg6CYuikknsA4NXkVoQGr07/A2SrdK580g7f6i0XUSzXbet7lJMB7xrQ/qGUAdT4IHxZxLJ6VKJNw1AB/SSp3yVyzPOaf3nb1iY+fl6vQjFUbDYaEdviZYbDLlNcuauGYmijNiJbquImTSN2rfM73Nf6H8q8CJRxBG7lI/oY0XeOxN+RZLUJadsQpWWHxMbu8pJwn1z2fELlP1Aef44Wyzjcv1yXnl+7xk3SVe8hK2VBA6lIOLftWRfPPmPm0hJoTmufREJVDehvMg9PTgw6kd2DwVM9GUIDj7YYZBQNCQNu+cCT7t4uIjlHzCjN/6wDOoUuws8Ftyu8vZdFA7/hxxo81HqIW4nIODrwHn+CzuEOnRRdy67xhJ1Lxa35hFvuXXunvqUKLO09RnKPHOAV2KfCmqo3aUpaZCADnq3Is0cF8e1+7lMqE1Chq9kxGPpZnVDVkXK6ebSnPMvpwzRrhvz4FZmylg+3vG+3DVnML5XXIHFAVM+wiDK0bx2qKz7v9UzrGP2ocvcNZ7Lw/q7Bfj6BUjT8FKqsFNHxVGCP2AnyR8ljyd0c1Lb9Z9teh+9XR2/8zm6OLvY0+J5VSmKEt7rsPtuCBarhuS+QGKT6ZL2W7RmZkzI7cjugg2Bc/33y+TKBEI35MMmRthhA4nJ25UzRDoCAUXBe5dHSuTpXubooyDPECx34E9Mo+giyvw7UleCdxs4jylLRmnQG5pWhByelb9sYV+S0GkyjwiFbBWw3ij4YC1QS3QP76tCM63/Pk/Q/FHnrEJrqOEH0ux/3dBr0WxfQrGN0GTRlrr23n0wGiRLpa5/cO6F3oqlPfvkQigpf3Tui6CLxO0lbamiZIoE8gR2QkIIKeuzJM2XnLGMOWFCtI6sEfwPG2P+AmkpH+m51q X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(1800799024)(376014)(36860700013)(82310400026)(921020); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Jan 2025 06:05:04.5355 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: afbe2ff1-5f19-461a-9e03-08dd2bbc9142 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000F0E4.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4178 Previous generations of Tegra supported DMA operations by an external DMA controller, but the QSPI on Tegra234 devices now have an internal DMA controller. Internal DMA: Uses the QSPI controller's built-in DMA engine, which is limited in capabilities and tied directly to the QSPI module. External DMA: Utilizes a separate, GPCDMA DMA controller that can transfer data between QSPI and any memory location. Native DMA Initialization: Introduce routines to initialize and configure native DMA channels for both transmit and receive paths. Set up DMA mapping functions to manage buffer addresses effectively. Enhance Transfer Logic: Implement logic to choose between CPU-based and DMA-based transfers based on data size. Change-Id: Icf3ef4767947cef67821c092ecd9ea6bccb2a4e4 Signed-off-by: Vishwaroop A --- drivers/spi/spi-tegra210-quad.c | 218 ++++++++++++++++++-------------- 1 file changed, 126 insertions(+), 92 deletions(-) diff --git a/drivers/spi/spi-tegra210-quad.c b/drivers/spi/spi-tegra210-quad.c index 04f41e92c1e2..066caee85c52 100644 --- a/drivers/spi/spi-tegra210-quad.c +++ b/drivers/spi/spi-tegra210-quad.c @@ -111,6 +111,9 @@ #define QSPI_DMA_BLK 0x024 #define QSPI_DMA_BLK_SET(x) (((x) & 0xffff) << 0) +#define QSPI_DMA_MEM_ADDRESS_REG 0x028 +#define QSPI_DMA_HI_ADDRESS_REG 0x02c + #define QSPI_TX_FIFO 0x108 #define QSPI_RX_FIFO 0x188 @@ -167,9 +170,9 @@ enum tegra_qspi_transfer_type { }; struct tegra_qspi_soc_data { - bool has_dma; bool cmb_xfer_capable; bool supports_tpm; + bool has_ext_dma; unsigned int cs_count; }; @@ -605,17 +608,21 @@ static void tegra_qspi_dma_unmap_xfer(struct tegra_qspi *tqspi, struct spi_trans len = DIV_ROUND_UP(tqspi->curr_dma_words * tqspi->bytes_per_word, 4) * 4; - dma_unmap_single(tqspi->dev, t->tx_dma, len, DMA_TO_DEVICE); - dma_unmap_single(tqspi->dev, t->rx_dma, len, DMA_FROM_DEVICE); + if (t->tx_buf) + dma_unmap_single(tqspi->dev, t->tx_dma, len, DMA_TO_DEVICE); + if (t->rx_buf) + dma_unmap_single(tqspi->dev, t->rx_dma, len, DMA_FROM_DEVICE); } static int tegra_qspi_start_dma_based_transfer(struct tegra_qspi *tqspi, struct spi_transfer *t) { struct dma_slave_config dma_sconfig = { 0 }; + dma_addr_t rx_dma_phys, tx_dma_phys; unsigned int len; u8 dma_burst; int ret = 0; u32 val; + bool has_ext_dma = tqspi->soc_data->has_ext_dma; if (tqspi->is_packed) { ret = tegra_qspi_dma_map_xfer(tqspi, t); @@ -634,60 +641,85 @@ static int tegra_qspi_start_dma_based_transfer(struct tegra_qspi *tqspi, struct len = tqspi->curr_dma_words * 4; /* set attention level based on length of transfer */ - val = 0; - if (len & 0xf) { - val |= QSPI_TX_TRIG_1 | QSPI_RX_TRIG_1; - dma_burst = 1; - } else if (((len) >> 4) & 0x1) { - val |= QSPI_TX_TRIG_4 | QSPI_RX_TRIG_4; - dma_burst = 4; - } else { - val |= QSPI_TX_TRIG_8 | QSPI_RX_TRIG_8; - dma_burst = 8; + if (has_ext_dma) { + val = 0; + if (len & 0xf) { + val |= QSPI_TX_TRIG_1 | QSPI_RX_TRIG_1; + dma_burst = 1; + } else if (((len) >> 4) & 0x1) { + val |= QSPI_TX_TRIG_4 | QSPI_RX_TRIG_4; + dma_burst = 4; + } else { + val |= QSPI_TX_TRIG_8 | QSPI_RX_TRIG_8; + dma_burst = 8; + } + + tegra_qspi_writel(tqspi, val, QSPI_DMA_CTL); } - tegra_qspi_writel(tqspi, val, QSPI_DMA_CTL); tqspi->dma_control_reg = val; dma_sconfig.device_fc = true; - if (tqspi->cur_direction & DATA_DIR_TX) { - dma_sconfig.dst_addr = tqspi->phys + QSPI_TX_FIFO; - dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; - dma_sconfig.dst_maxburst = dma_burst; - ret = dmaengine_slave_config(tqspi->tx_dma_chan, &dma_sconfig); - if (ret < 0) { - dev_err(tqspi->dev, "failed DMA slave config: %d\n", ret); - return ret; - } - tegra_qspi_copy_client_txbuf_to_qspi_txbuf(tqspi, t); - ret = tegra_qspi_start_tx_dma(tqspi, t, len); - if (ret < 0) { - dev_err(tqspi->dev, "failed to starting TX DMA: %d\n", ret); - return ret; + if ((tqspi->cur_direction & DATA_DIR_TX)) { + if (has_ext_dma) { + dma_sconfig.dst_addr = tqspi->phys + QSPI_TX_FIFO; + dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; + dma_sconfig.dst_maxburst = dma_burst; + ret = dmaengine_slave_config(tqspi->tx_dma_chan, &dma_sconfig); + if (ret < 0) { + dev_err(tqspi->dev, "failed DMA slave config: %d\n", ret); + return ret; + } + + tegra_qspi_copy_client_txbuf_to_qspi_txbuf(tqspi, t); + ret = tegra_qspi_start_tx_dma(tqspi, t, len); + if (ret < 0) { + dev_err(tqspi->dev, "failed to starting TX DMA: %d\n", ret); + return ret; + } + } else { + if (tqspi->is_packed) + tx_dma_phys = t->tx_dma; + else + tx_dma_phys = tqspi->tx_dma_phys; + tegra_qspi_copy_client_txbuf_to_qspi_txbuf(tqspi, t); + tegra_qspi_writel(tqspi, lower_32_bits(tx_dma_phys), + QSPI_DMA_MEM_ADDRESS_REG); + tegra_qspi_writel(tqspi, (upper_32_bits(tx_dma_phys) & 0xff), + QSPI_DMA_HI_ADDRESS_REG); } } if (tqspi->cur_direction & DATA_DIR_RX) { - dma_sconfig.src_addr = tqspi->phys + QSPI_RX_FIFO; - dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; - dma_sconfig.src_maxburst = dma_burst; - ret = dmaengine_slave_config(tqspi->rx_dma_chan, &dma_sconfig); - if (ret < 0) { - dev_err(tqspi->dev, "failed DMA slave config: %d\n", ret); - return ret; - } - - dma_sync_single_for_device(tqspi->dev, tqspi->rx_dma_phys, - tqspi->dma_buf_size, - DMA_FROM_DEVICE); - - ret = tegra_qspi_start_rx_dma(tqspi, t, len); - if (ret < 0) { - dev_err(tqspi->dev, "failed to start RX DMA: %d\n", ret); - if (tqspi->cur_direction & DATA_DIR_TX) - dmaengine_terminate_all(tqspi->tx_dma_chan); - return ret; + if (has_ext_dma) { + dma_sconfig.src_addr = tqspi->phys + QSPI_RX_FIFO; + dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; + dma_sconfig.src_maxburst = dma_burst; + ret = dmaengine_slave_config(tqspi->rx_dma_chan, &dma_sconfig); + if (ret < 0) { + dev_err(tqspi->dev, "failed DMA slave config: %d\n", ret); + return ret; + } + dma_sync_single_for_device(tqspi->dev, tqspi->rx_dma_phys, + tqspi->dma_buf_size, DMA_FROM_DEVICE); + ret = tegra_qspi_start_rx_dma(tqspi, t, len); + if (ret < 0) { + dev_err(tqspi->dev, "failed to start RX DMA: %d\n", ret); + if (tqspi->cur_direction & DATA_DIR_TX) + dmaengine_terminate_all(tqspi->tx_dma_chan); + return ret; + } + } else { + if (tqspi->is_packed) + rx_dma_phys = t->rx_dma; + else + rx_dma_phys = tqspi->rx_dma_phys; + + tegra_qspi_writel(tqspi, (rx_dma_phys & 0xffffffff), + QSPI_DMA_MEM_ADDRESS_REG); + tegra_qspi_writel(tqspi, ((rx_dma_phys >> 32) & 0xff), + QSPI_DMA_HI_ADDRESS_REG); } } @@ -726,9 +758,6 @@ static int tegra_qspi_start_cpu_based_transfer(struct tegra_qspi *qspi, struct s static void tegra_qspi_deinit_dma(struct tegra_qspi *tqspi) { - if (!tqspi->soc_data->has_dma) - return; - if (tqspi->tx_dma_buf) { dma_free_coherent(tqspi->dev, tqspi->dma_buf_size, tqspi->tx_dma_buf, tqspi->tx_dma_phys); @@ -759,16 +788,26 @@ static int tegra_qspi_init_dma(struct tegra_qspi *tqspi) u32 *dma_buf; int err; - if (!tqspi->soc_data->has_dma) - return 0; + if (tqspi->soc_data->has_ext_dma) { + dma_chan = dma_request_chan(tqspi->dev, "rx"); + if (IS_ERR(dma_chan)) { + err = PTR_ERR(dma_chan); + goto err_out; + } - dma_chan = dma_request_chan(tqspi->dev, "rx"); - if (IS_ERR(dma_chan)) { - err = PTR_ERR(dma_chan); - goto err_out; - } + tqspi->rx_dma_chan = dma_chan; - tqspi->rx_dma_chan = dma_chan; + dma_chan = dma_request_chan(tqspi->dev, "tx"); + if (IS_ERR(dma_chan)) { + err = PTR_ERR(dma_chan); + goto err_out; + } + + tqspi->tx_dma_chan = dma_chan; + } else { + tqspi->rx_dma_chan = NULL; + tqspi->tx_dma_chan = NULL; + } dma_buf = dma_alloc_coherent(tqspi->dev, tqspi->dma_buf_size, &dma_phys, GFP_KERNEL); if (!dma_buf) { @@ -779,14 +818,6 @@ static int tegra_qspi_init_dma(struct tegra_qspi *tqspi) tqspi->rx_dma_buf = dma_buf; tqspi->rx_dma_phys = dma_phys; - dma_chan = dma_request_chan(tqspi->dev, "tx"); - if (IS_ERR(dma_chan)) { - err = PTR_ERR(dma_chan); - goto err_out; - } - - tqspi->tx_dma_chan = dma_chan; - dma_buf = dma_alloc_coherent(tqspi->dev, tqspi->dma_buf_size, &dma_phys, GFP_KERNEL); if (!dma_buf) { err = -ENOMEM; @@ -1056,6 +1087,7 @@ static int tegra_qspi_combined_seq_xfer(struct tegra_qspi *tqspi, struct spi_message *msg) { bool is_first_msg = true; + bool has_ext_dma = tqspi->soc_data->has_ext_dma; struct spi_transfer *xfer; struct spi_device *spi = msg->spi; u8 transfer_phase = 0; @@ -1128,15 +1160,12 @@ static int tegra_qspi_combined_seq_xfer(struct tegra_qspi *tqspi, if (WARN_ON(ret == 0)) { dev_err(tqspi->dev, "QSPI Transfer failed with timeout: %d\n", ret); - if (tqspi->is_curr_dma_xfer && - (tqspi->cur_direction & DATA_DIR_TX)) - dmaengine_terminate_all - (tqspi->tx_dma_chan); - - if (tqspi->is_curr_dma_xfer && - (tqspi->cur_direction & DATA_DIR_RX)) - dmaengine_terminate_all - (tqspi->rx_dma_chan); + if (tqspi->is_curr_dma_xfer && has_ext_dma) { + if (tqspi->cur_direction & DATA_DIR_TX) + dmaengine_terminate_all(tqspi->tx_dma_chan); + if (tqspi->cur_direction & DATA_DIR_RX) + dmaengine_terminate_all(tqspi->rx_dma_chan); + } /* Abort transfer by resetting pio/dma bit */ if (!tqspi->is_curr_dma_xfer) { @@ -1197,6 +1226,7 @@ static int tegra_qspi_non_combined_seq_xfer(struct tegra_qspi *tqspi, struct spi_device *spi = msg->spi; struct spi_transfer *transfer; bool is_first_msg = true; + bool has_ext_dma = tqspi->soc_data->has_ext_dma; int ret = 0, val = 0; msg->status = 0; @@ -1251,10 +1281,12 @@ static int tegra_qspi_non_combined_seq_xfer(struct tegra_qspi *tqspi, QSPI_DMA_TIMEOUT); if (WARN_ON(ret == 0)) { dev_err(tqspi->dev, "transfer timeout\n"); - if (tqspi->is_curr_dma_xfer && (tqspi->cur_direction & DATA_DIR_TX)) - dmaengine_terminate_all(tqspi->tx_dma_chan); - if (tqspi->is_curr_dma_xfer && (tqspi->cur_direction & DATA_DIR_RX)) - dmaengine_terminate_all(tqspi->rx_dma_chan); + if (tqspi->is_curr_dma_xfer && has_ext_dma) { + if (tqspi->cur_direction & DATA_DIR_TX) + dmaengine_terminate_all(tqspi->tx_dma_chan); + if (tqspi->cur_direction & DATA_DIR_RX) + dmaengine_terminate_all(tqspi->rx_dma_chan); + } tegra_qspi_handle_error(tqspi); ret = -EIO; goto complete_xfer; @@ -1323,7 +1355,7 @@ static bool tegra_qspi_validate_cmb_seq(struct tegra_qspi *tqspi, return false; xfer = list_next_entry(xfer, transfer_list); } - if (!tqspi->soc_data->has_dma && xfer->len > (QSPI_FIFO_DEPTH << 2)) + if (!tqspi->soc_data->has_ext_dma && xfer->len > (QSPI_FIFO_DEPTH << 2)) return false; return true; @@ -1388,30 +1420,32 @@ static irqreturn_t handle_dma_based_xfer(struct tegra_qspi *tqspi) if (tqspi->cur_direction & DATA_DIR_TX) { if (tqspi->tx_status) { - dmaengine_terminate_all(tqspi->tx_dma_chan); - err += 1; - } else { + if (tqspi->tx_dma_chan) + dmaengine_terminate_all(tqspi->tx_dma_chan); + err++; + } else if (tqspi->tx_dma_chan) { wait_status = wait_for_completion_interruptible_timeout( &tqspi->tx_dma_complete, QSPI_DMA_TIMEOUT); if (wait_status <= 0) { dmaengine_terminate_all(tqspi->tx_dma_chan); dev_err(tqspi->dev, "failed TX DMA transfer\n"); - err += 1; + err++; } } } if (tqspi->cur_direction & DATA_DIR_RX) { if (tqspi->rx_status) { - dmaengine_terminate_all(tqspi->rx_dma_chan); - err += 2; - } else { + if (tqspi->rx_dma_chan) + dmaengine_terminate_all(tqspi->rx_dma_chan); + err++; + } else if (tqspi->rx_dma_chan) { wait_status = wait_for_completion_interruptible_timeout( &tqspi->rx_dma_complete, QSPI_DMA_TIMEOUT); if (wait_status <= 0) { dmaengine_terminate_all(tqspi->rx_dma_chan); dev_err(tqspi->dev, "failed RX DMA transfer\n"); - err += 2; + err++; } } } @@ -1474,28 +1508,28 @@ static irqreturn_t tegra_qspi_isr_thread(int irq, void *context_data) } static struct tegra_qspi_soc_data tegra210_qspi_soc_data = { - .has_dma = true, + .has_ext_dma = true, .cmb_xfer_capable = false, .supports_tpm = false, .cs_count = 1, }; static struct tegra_qspi_soc_data tegra186_qspi_soc_data = { - .has_dma = true, + .has_ext_dma = true, .cmb_xfer_capable = true, .supports_tpm = false, .cs_count = 1, }; static struct tegra_qspi_soc_data tegra234_qspi_soc_data = { - .has_dma = false, + .has_ext_dma = false, .cmb_xfer_capable = true, .supports_tpm = true, .cs_count = 1, }; static struct tegra_qspi_soc_data tegra241_qspi_soc_data = { - .has_dma = false, + .has_ext_dma = true, .cmb_xfer_capable = true, .supports_tpm = true, .cs_count = 4,