From patchwork Fri Jan 3 16:38:00 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 855123 Received: from mail-ej1-f44.google.com (mail-ej1-f44.google.com [209.85.218.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DD9BA1FBEAF for ; Fri, 3 Jan 2025 16:38:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.44 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735922313; cv=none; b=LUWPUTyjL6XRf445Kd3bO+qNL91n/ljRykb5PSNXMpBkbuBFjtYyDCZGdE0f4QKCVTKQ7aByh2DVRaU9PDdOV8rZH7BUxKsl6S1x/IUK2xibxQb5468RURc5Et8dCh7XC6EkTyZ1Ocuyx8ZkjmppuYXPmvac9Q8KClfwQ9I6UNk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735922313; c=relaxed/simple; bh=rKeDJdkJUvYXPSfCRoD0lCN7VYkcnSZTWQUumgyTv/g=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=F9ZfsiBsz7OYD3td7CWeg/wbE3RITtP8CXAg9POp/rhzFO6gMi5cYRBOR7VXG9KM7XT3Tb2BlVq9+6tkyr5QAILfOy3BaUAvEfKoaJowCVvqe26qVatrS/kUifcr+py1O3e/Hs0YJKSEdCvWKcoh6I1DRav8OlmBZrclFjaAvv4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=k/gZQEJt; arc=none smtp.client-ip=209.85.218.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="k/gZQEJt" Received: by mail-ej1-f44.google.com with SMTP id a640c23a62f3a-aa6a92f863cso2137821066b.1 for ; Fri, 03 Jan 2025 08:38:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1735922310; x=1736527110; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=uRfd2J8GP5C8knwZHf/66JpMVkPptrjLbcLPhoT3Dxw=; b=k/gZQEJtA+7erqO0VL71gsC9OEB1TUiEe3Dx7ue0FuvNGsZOnEH0+ZryT0kxWczm8M XELKmsV1Yjn1bbdjBx/x9anoTcTS8VfmLBMr6+h9Iexrh8iUkih3EwGEZjC8cf0q7BsN BpyyqxWZtwlFPs34r//r+6q/y8nNQ3qyV75hW4OrFjzkNmhivEXyasDqwtLkkhPgyilC +T0ZbO/EKcuZ2ee41u6udGg2IPQWKmzYgOoLC6OUPBiYKO/wRo0LB/wWudPdtxHZQV03 YSCKCdEKHXpmPhuVE8gPUMatpoQrgMjZv19Cna20WSqBMOw9zcsrWvqNHgX7bZXJq8Mx n/4A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1735922310; x=1736527110; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uRfd2J8GP5C8knwZHf/66JpMVkPptrjLbcLPhoT3Dxw=; b=ekAh0/agv7Q/OwEIRgYwp4VahkqBzZW5ycvTgGLYAdj3e4htKOwYCpWs2BXTcAvc0q NK1eW1fi4lscxfr5A+UxCp6P30c/unXk0HU1FjHW+nybWgL6GAV0Ko3kOzuNTbC8k1zw LtdeH4Lk+ITPrQP6sFgS0TSQdbSlYtOJqAf9gKfVQd88HLvSAVhuXvjyq9wboEnjPxz8 K607J+ILojG84QUt3nBugCV0Yq0nmM3sv9d9P+dsHgeEA0Q8H0qLXUqfyZBirvGQ+yYi V/TzAuTyjzt/ewepDCh0PZr9Bt+QyETLzuGUChUawjeG3M4hz9UQoB/dTTkcbO3/K87M QYxg== X-Forwarded-Encrypted: i=1; AJvYcCVgyjtw8l/guwbVaKs61yd/LxWntjRqjlRo9YB2F7sxsHRNQ2uxRWxqJo+bjqFcbpDvU91HlCppwQ==@vger.kernel.org X-Gm-Message-State: AOJu0YxD/6vWkSczrD/CGm6XcDjDngNhStvoFGzcfLDltG5HLQW65SFb hayHx70vagtYcMhKK4R3ALDWWtIP7IDCljDpSaxe9QBwHLLcHfKRcRS7VRxPB2Y= X-Gm-Gg: ASbGncvJmISjSdSMgdJFHpzQgbLyX73yKwUNXOeIIPN7EW2ijbkrEm350EPeiFPjqx+ kGg8dkpynnCiLl7mFpW+X8wW79jCYgTHfDV2HjsKJi2xYDJBGP4ngHE7VtJ8WBPx0sFsp5eh5yO IHjIqi4bIQPgVGU9Wg1UUdJCNn1ZS3aY5+yu6teAAU4/1yRVynCXaQYK7IyNkbMimcxzbHPw4dn Bd3yTywA8gT08zAJli8BRaqGppP+BeF4QONOgBZXZOWiI+spn5DIyv0QNqaA8fOVpX52zcmvfzA uPDbOuCYRrM= X-Google-Smtp-Source: AGHT+IEDncREyuqiaeFdEZrch8doNfoioGsr8GniNw17HEMgfl8Mb5jP1IALi9TIgf4Be+b+F0vcRQ== X-Received: by 2002:a17:907:944f:b0:aac:439:10ce with SMTP id a640c23a62f3a-aac2ba3c11amr5503329166b.27.1735922310189; Fri, 03 Jan 2025 08:38:30 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.102]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aac0e8953b6sm1932984066b.65.2025.01.03.08.38.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Jan 2025 08:38:29 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: rafael@kernel.org, daniel.lezcano@linaro.org, rui.zhang@intel.com, lukasz.luba@arm.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, ulf.hansson@linaro.org Cc: claudiu.beznea@tuxon.dev, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, Claudiu Beznea Subject: [PATCH 1/6] clk: renesas: r9a08g045: Add clocks, resets and power domain support for the TSU IP Date: Fri, 3 Jan 2025 18:38:00 +0200 Message-ID: <20250103163805.1775705-2-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250103163805.1775705-1-claudiu.beznea.uj@bp.renesas.com> References: <20250103163805.1775705-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Add clocks, resets and power domains for the TSU IP available on the Renesas RZ/G3S SoC. Signed-off-by: Claudiu Beznea --- drivers/clk/renesas/r9a08g045-cpg.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/clk/renesas/r9a08g045-cpg.c b/drivers/clk/renesas/r9a08g045-cpg.c index 0e7e3bf05b52..bc44e08e7eb9 100644 --- a/drivers/clk/renesas/r9a08g045-cpg.c +++ b/drivers/clk/renesas/r9a08g045-cpg.c @@ -241,6 +241,7 @@ static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = { DEF_MOD("gpio_hclk", R9A08G045_GPIO_HCLK, R9A08G045_OSCCLK, 0x598, 0), DEF_MOD("adc_adclk", R9A08G045_ADC_ADCLK, R9A08G045_CLK_TSU, 0x5a8, 0), DEF_MOD("adc_pclk", R9A08G045_ADC_PCLK, R9A08G045_CLK_TSU, 0x5a8, 1), + DEF_MOD("tsu_pclk", R9A08G045_TSU_PCLK, R9A08G045_CLK_TSU, 0x5ac, 0), DEF_MOD("vbat_bclk", R9A08G045_VBAT_BCLK, R9A08G045_OSCCLK, 0x614, 0), }; @@ -279,6 +280,7 @@ static const struct rzg2l_reset r9a08g045_resets[] = { DEF_RST(R9A08G045_GPIO_SPARE_RESETN, 0x898, 2), DEF_RST(R9A08G045_ADC_PRESETN, 0x8a8, 0), DEF_RST(R9A08G045_ADC_ADRST_N, 0x8a8, 1), + DEF_RST(R9A08G045_TSU_PRESETN, 0x8ac, 0), DEF_RST(R9A08G045_VBAT_BRESETN, 0x914, 0), }; @@ -353,6 +355,8 @@ static const struct rzg2l_cpg_pm_domain_init_data r9a08g045_pm_domains[] = { DEF_REG_CONF(CPG_BUS_MCPU3_MSTOP, BIT(4)), 0), DEF_PD("adc", R9A08G045_PD_ADC, DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(14)), 0), + DEF_PD("tsu", R9A08G045_PD_TSU, + DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(15)), 0), DEF_PD("vbat", R9A08G045_PD_VBAT, DEF_REG_CONF(CPG_BUS_MCPU3_MSTOP, BIT(8)), GENPD_FLAG_ALWAYS_ON), From patchwork Fri Jan 3 16:38:01 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 854977 Received: from mail-ej1-f43.google.com (mail-ej1-f43.google.com [209.85.218.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C7B601FC0EB for ; Fri, 3 Jan 2025 16:38:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735922315; cv=none; b=Cy9VeWGcugypmrgEBv0aymSDL/JGdbQEU77ClakVHWOKp6lCwTLh5FtjvJaxx/DkY72Uo30Hn4tug9FJNwBZf+6LCqju7mbpwMIpvMle7NYAwqC4IBddNf14NsC9XcVw8IHIHBH/d23PrDhQfisYmN34BWoIzHu2itCDhrtaXuk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735922315; c=relaxed/simple; bh=vpTcFyTpxAUWxXlbXnvHItbsODwPD9kf9XkrqqjjlH0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=J0+icr/wnS1nuGTUtl1qU5VlSEdBB7+tF94fulocrqwzO/zS5MgM0j8GY1PCdWnZAfox798A3OiV9a9T23qwz0T4hu5xoaMlGQ8hOVpaiv3mw4BwTvo4bV1pylW16oD5Gh0RuNapHW66FzpcGiWyhqTSWMlfqBlQQDmw+/5iHMc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=qRB7LCsf; arc=none smtp.client-ip=209.85.218.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="qRB7LCsf" Received: by mail-ej1-f43.google.com with SMTP id a640c23a62f3a-aaf6b1a5f2bso675965366b.1 for ; Fri, 03 Jan 2025 08:38:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1735922312; x=1736527112; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=MKO092aqGvuaWEK1ec47bOLS5kCK+a7HRvUCASG+XdU=; b=qRB7LCsfEUXtUCJCCYE1O+T7QP6Q/nbrT7YYV7oRxfNPItosEmNCItcK7PZsE086JI H2lUPBlxf1xm3NdU9otdAXG58Dqe8YO5KkyxdBSsh6pLw5xtffBYN6q7vnYp/XceGSkb O1YmJnNSMm79TsDD89qy1OdImNWIWqSvO0ADY3zGTddttxG9WKXQhPYzaOaALI1+YxGc j1AuZAiyt3HMdCuHaLHYdM33tPDCRtQ6vYkCElHbsjmHAD5vP4wgZLpOrqurrp3zN8tS c9BCIzmdTikuRiF6WbaOD67HszImnYJI6j+ch1byDrBivBGz7lbnl8Zx9oqWf2EyPLgf 9TIw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1735922312; x=1736527112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MKO092aqGvuaWEK1ec47bOLS5kCK+a7HRvUCASG+XdU=; b=hgWGORvw8tDJPXLKmfVUSyhdlhSFhN98hbutzQ71vFYtRKd8W0RT6Sye3caYr8vcwi 4uXsbasE7qq/JhmIsrt/AsbIYpZJz4Tk6EH2ckeigSAFwsZg4bNyHym6wgbyH50WNG4A IVcMsgbBbb8s1lhh0BKr6+mfKzyLTnCWqSipriGD4DygkZcV2IM31W6FWkpoHk5pv+Jf NBOPpm1ChLe80Bsv5eQXGv7DkjeTW3I520dB5XPPtXKiLPHqI21EJgvrd+OMn6yNAOL6 cBadq9TNCXy1g+Dk8TH5VZZq/bwpaG0TlQx9OwQuPKd/5eUM/6n4I+6hiP1gZxmms0Tl bUNg== X-Forwarded-Encrypted: i=1; AJvYcCXBqlldX88XFWE5q1qjdBjcv3MU75UBZGzqoVP/+sxeFhVYdMWEmCRDEp2qqwWxDposqClwgOl1cA==@vger.kernel.org X-Gm-Message-State: AOJu0YxTKyqxxYLRp+AP44UEjHBO/kDzjm+bsWVAb8niWjGx5/TzFD7f fFzvht3b2hFIgR9rmWBccuKQQDWphCSHitaUkxSUzwukCchEcyMJXJUiw6Q+aKg= X-Gm-Gg: ASbGncvISqyX/0CgY5Tej+8lFvpujIdEo8S8oxnk9bVs0EhoDC6eoNIE9qhGvpD/+eG CSUTzjXUc2QoMw8b4vsnQiE45vYrQfyeRbj+HCDpdceiUDzDPx8PEF7zTsY4Zy1jZPbvfm011SR V6l2P+7sOh5dKUL36mlSSPV9HkN4Pp63E9qm/d2eOGkvE1BVBZiek1tAaE2U4ffz9DqWW18b1Us UBBs+n1en90l08RPlXmvtNtMMOMa1z4EycYTkbtfdvENofxxeE2qWWipeiVom3ZLJ5h3hDPQpJ9 JeIHVQd71MY= X-Google-Smtp-Source: AGHT+IHotX0t/tDNEmrDmtZY7hNyawr8SL8uDODoko36MDXxVpeudAHOQDSv7TvNphEb+Zb8F3tSTg== X-Received: by 2002:a17:906:4fcb:b0:aa6:7ff9:d248 with SMTP id a640c23a62f3a-aac0812631emr4709225166b.8.1735922312040; Fri, 03 Jan 2025 08:38:32 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.102]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aac0e8953b6sm1932984066b.65.2025.01.03.08.38.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Jan 2025 08:38:31 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: rafael@kernel.org, daniel.lezcano@linaro.org, rui.zhang@intel.com, lukasz.luba@arm.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, ulf.hansson@linaro.org Cc: claudiu.beznea@tuxon.dev, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, Claudiu Beznea Subject: [PATCH 2/6] thermal: of: Export non-devres helper to register/unregister thermal zone Date: Fri, 3 Jan 2025 18:38:01 +0200 Message-ID: <20250103163805.1775705-3-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250103163805.1775705-1-claudiu.beznea.uj@bp.renesas.com> References: <20250103163805.1775705-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea On the Renesas RZ/G3S (and other Renesas SoCs, e.g., RZ/G2{L, LC, UL}), clocks are managed through PM domains. These PM domains, registered on behalf of the clock controller driver, are configured with GENPD_FLAG_PM_CLK. In most of the Renesas drivers used by RZ SoCs, the clocks are enabled/disabled using runtime PM APIs. During probe, devices are attached to the PM domain controlling their clocks. Similarly, during removal, devices are detached from the PM domain. The detachment call stack is as follows: device_driver_detach() -> device_release_driver_internal() -> __device_release_driver() -> device_remove() -> platform_remove() -> dev_pm_domain_detach() In the upcoming Renesas RZ/G3S thermal driver, the struct thermal_zone_device_ops::change_mode API is implemented to start/stop the thermal sensor unit. Register settings are updated within the change_mode API. In case devres helpers are used for thermal zone register/unregister the struct thermal_zone_device_ops::change_mode API is invoked when the driver is unbound. The identified call stack is as follows: device_driver_detach() -> device_release_driver_internal() -> device_unbind_cleanup() -> devres_release_all() -> devm_thermal_of_zone_release() -> thermal_zone_device_disable() -> thermal_zone_device_set_mode() -> rzg3s_thermal_change_mode() The device_unbind_cleanup() function is called after the thermal device is detached from the PM domain (via dev_pm_domain_detach()). The rzg3s_thermal_change_mode() implementation calls pm_runtime_resume_and_get()/pm_runtime_put_autosuspend() before/after accessing the registers. However, during the unbind scenario, the devm_thermal_of_zone_release() is invoked after dev_pm_domain_detach(). Consequently, the clocks are not enabled, as the device is removed from the PM domain at this time, leading to an Asynchronous SError Interrupt. The system cannot be used after this. Add thermal_of_zone_register()/thermal_of_zone_unregister(). These will be used in the upcomming RZ/G3S thermal driver. Signed-off-by: Claudiu Beznea --- drivers/thermal/thermal_of.c | 8 +++++--- include/linux/thermal.h | 14 ++++++++++++++ 2 files changed, 19 insertions(+), 3 deletions(-) diff --git a/drivers/thermal/thermal_of.c b/drivers/thermal/thermal_of.c index fab11b98ca49..8fc35d20db60 100644 --- a/drivers/thermal/thermal_of.c +++ b/drivers/thermal/thermal_of.c @@ -329,11 +329,12 @@ static bool thermal_of_should_bind(struct thermal_zone_device *tz, * * @tz: a pointer to the thermal zone structure */ -static void thermal_of_zone_unregister(struct thermal_zone_device *tz) +void thermal_of_zone_unregister(struct thermal_zone_device *tz) { thermal_zone_device_disable(tz); thermal_zone_device_unregister(tz); } +EXPORT_SYMBOL_GPL(thermal_of_zone_unregister); /** * thermal_of_zone_register - Register a thermal zone with device node @@ -355,8 +356,8 @@ static void thermal_of_zone_unregister(struct thermal_zone_device *tz) * - ENOMEM: if one structure can not be allocated * - Other negative errors are returned by the underlying called functions */ -static struct thermal_zone_device *thermal_of_zone_register(struct device_node *sensor, int id, void *data, - const struct thermal_zone_device_ops *ops) +struct thermal_zone_device *thermal_of_zone_register(struct device_node *sensor, int id, void *data, + const struct thermal_zone_device_ops *ops) { struct thermal_zone_device_ops of_ops = *ops; struct thermal_zone_device *tz; @@ -429,6 +430,7 @@ static struct thermal_zone_device *thermal_of_zone_register(struct device_node * return ERR_PTR(ret); } +EXPORT_SYMBOL_GPL(thermal_of_zone_register); static void devm_thermal_of_zone_release(struct device *dev, void *res) { diff --git a/include/linux/thermal.h b/include/linux/thermal.h index 69f9bedd0ee8..adbb4092a064 100644 --- a/include/linux/thermal.h +++ b/include/linux/thermal.h @@ -195,13 +195,23 @@ struct thermal_zone_params { /* Function declarations */ #ifdef CONFIG_THERMAL_OF +struct thermal_zone_device *thermal_of_zone_register(struct device_node *sensor, int id, void *data, + const struct thermal_zone_device_ops *ops); struct thermal_zone_device *devm_thermal_of_zone_register(struct device *dev, int id, void *data, const struct thermal_zone_device_ops *ops); +void thermal_of_zone_unregister(struct thermal_zone_device *tz); void devm_thermal_of_zone_unregister(struct device *dev, struct thermal_zone_device *tz); #else +static inline +struct thermal_zone_device *thermal_of_zone_register(struct device_node *sensor, int id, void *data, + const struct thermal_zone_device_ops *ops) +{ + return ERR_PTR(-ENOTSUPP); +} + static inline struct thermal_zone_device *devm_thermal_of_zone_register(struct device *dev, int id, void *data, const struct thermal_zone_device_ops *ops) @@ -209,6 +219,10 @@ struct thermal_zone_device *devm_thermal_of_zone_register(struct device *dev, in return ERR_PTR(-ENOTSUPP); } +static inline void thermal_of_zone_unregister(struct thermal_zone_device *tz) +{ +} + static inline void devm_thermal_of_zone_unregister(struct device *dev, struct thermal_zone_device *tz) { From patchwork Fri Jan 3 16:38:02 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 855122 Received: from mail-ej1-f45.google.com (mail-ej1-f45.google.com [209.85.218.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 911741FC103 for ; Fri, 3 Jan 2025 16:38:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735922317; cv=none; b=pzSJTwnCdY+lEKnlXr3KzOvANnCZbHswku/BCPXCoCH6tu+ttyi9PvpU1xt19k1KHK6iJh2DYGrXSdQgLYjmJRCbGRzUCgV8FPRlG+OS2OUgyyhDyFpyDoyGLC0j38B8EpFC5XKbgi4WdOxDTULkjcJ6C/WrF2APCTSuMawHusM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735922317; c=relaxed/simple; bh=by0/KQXncjgvS4hPgMtbUixzVUWVB8vOz9ZHoJHsfvc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=FRPLY/l6U/H5t5+DS5Xj7tG4f62G06wONsWGs23qAMS1cib6wTspIYHpK+mxu/dgv1rHK9AS4dFiDAGBELDnmTbZ7/3MAw0VZNWw58egQfoNi8FRIOuTjYxiOwJlmY8vNJjYqlKuYO8HNZJk2LJyk0B+yd9uj4I7MdEyQk6TkCo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=N2+qqblB; arc=none smtp.client-ip=209.85.218.45 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="N2+qqblB" Received: by mail-ej1-f45.google.com with SMTP id a640c23a62f3a-aaeef97ff02so1407336366b.1 for ; Fri, 03 Jan 2025 08:38:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1735922314; x=1736527114; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=evyYwVG9jAAn2LfhNe4V0lOQ6hGXTx/eRi/lhEE4KRI=; b=N2+qqblBJABy/HiJ39CiJSTr/k9VsvnKY93fbC1hgknuHymghaGPTQr0RaGu+kry5g Es8S6jaR4nOgQXBjMFm11ZR302yKOFcCS18Jq+myD/g+NwIottNepYn7x0ZD7xCHOgap 9rn/LuWiYxtmrFQ3GiMadGW1R+Jrbt9D75JyV3mQKWv4FbbZMgUl4tVkrQ4ykxerMwcq TkXqq/GpcVAesymgPtK1q/U0EtHUZbYspfx0Eys6ki5PvJZ83xjbb5ezfU0A9q/k0a3T wdMq7ilwNd481GuvlPOgXM+wmMAlqIZe0/GkdPM2tk0KjLkuSsCzrat00siwnucI78Np qFyw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1735922314; x=1736527114; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=evyYwVG9jAAn2LfhNe4V0lOQ6hGXTx/eRi/lhEE4KRI=; b=TtSzWkP8iE5QUkFQ9A3NKcEjejB8TbK+jVhCZxK9S1JccthkdZIFh3631Pr00mJfq7 OKzH2j8R4qF9GPw4m2xdZ7s6ogulKDyfxZYAvreeWKaJCV5jU9IylVOhYOb37IxkKZJx 7pAiXbSK4gPMJYRo29x0CFqTP21tcE1v3tVNzl42rkKasKr4uC8frx7ipvpalQ4wWO6I dPp/6pv9FhYpXDtBdcDZp8UgSoTpmtdLa5C2UfJ1nb9bjMCv212SfuXy1NLOnSzWtqmH hwDF3DTlsud5VqDd9kFlK63Iu01/jtNKZ2/Nn8nEdO4Cg/gYixc9sX4mA/8SdLNAM4vY Jbhw== X-Forwarded-Encrypted: i=1; AJvYcCVQD68/R4itB/OudP8I5w3x8fWeM+WtSi2gRBSrnuPOAhPANp7JZxeuhvaE4apqFY2bcCtQzZk6Eg==@vger.kernel.org X-Gm-Message-State: AOJu0YxXgWEkTuPkPktd2ZeNlFQlOe5u+9LU6R2ReNE4gtbNw8OqVC6j o23O/lNvpMiCWlNbY3DSr+C7JbjjAVeSw2wGlUzUU9OlCFzjxRR+wGQA8HPD64Q= X-Gm-Gg: ASbGncvkcitnScehRAUGFkzCZGaHsEV2trZaNxbYWI9DZGgfV0WgjPzAl4jGrTs3ABu +mbcICxPu/GMFxLV55lkxKcxQXagV+oj7/XQRQyRO2RvW6qCiN4SgeokcCLKzTSuHRNbh9bH/zy T+OnZxYu5vOptDhyCEIf329UheWIHmhBSEofVYPFYUBSYg2YfIp/B+Suy+nsA/EBHD8FQJ1PLYU 8MJptGH2hIviWQc9fawOiJKQyrQfPBOGWIBAoS+5Mre7Q0uaOWpY4hYQ5gBJ1DiJLcKtSuWRxrf Uts20QI7lwU= X-Google-Smtp-Source: AGHT+IGZziQN526Qz2cC4SM+sDiCIJGAjK04HVz8g4TFUK5HQL4oXUkqdbEpUHeE3KBwEfQsCEVxQA== X-Received: by 2002:a17:907:1c85:b0:aa6:29dc:11b with SMTP id a640c23a62f3a-aac3342c7f4mr4934010766b.16.1735922313975; Fri, 03 Jan 2025 08:38:33 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.102]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aac0e8953b6sm1932984066b.65.2025.01.03.08.38.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Jan 2025 08:38:33 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: rafael@kernel.org, daniel.lezcano@linaro.org, rui.zhang@intel.com, lukasz.luba@arm.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, ulf.hansson@linaro.org Cc: claudiu.beznea@tuxon.dev, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, Claudiu Beznea Subject: [PATCH 3/6] dt-bindings: thermal: r9a08g045-tsu: Document the TSU unit Date: Fri, 3 Jan 2025 18:38:02 +0200 Message-ID: <20250103163805.1775705-4-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250103163805.1775705-1-claudiu.beznea.uj@bp.renesas.com> References: <20250103163805.1775705-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea The Renesas RZ/G3S SoC includes a Thermal Sensor Unit (TSU) block designed to measure the junction temperature. The temperature is measured using the RZ/G3S ADC, with a dedicated ADC channel directly connected to the TSU. Add documentation for it. Signed-off-by: Claudiu Beznea --- .../thermal/renesas,r9a08g045-tsu.yaml | 93 +++++++++++++++++++ 1 file changed, 93 insertions(+) create mode 100644 Documentation/devicetree/bindings/thermal/renesas,r9a08g045-tsu.yaml diff --git a/Documentation/devicetree/bindings/thermal/renesas,r9a08g045-tsu.yaml b/Documentation/devicetree/bindings/thermal/renesas,r9a08g045-tsu.yaml new file mode 100644 index 000000000000..573e2b9d3752 --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/renesas,r9a08g045-tsu.yaml @@ -0,0 +1,93 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/thermal/renesas,r9a08g045-tsu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/G3S Thermal Sensor Unit + +description: + The thermal sensor unit (TSU) measures the temperature(Tj) inside + the LSI. + +maintainers: + - Claudiu Beznea + +$ref: thermal-sensor.yaml# + +properties: + compatible: + const: renesas,r9a08g045-tsu + + reg: + maxItems: 1 + + clocks: + items: + - description: TSU module clock + + power-domains: + maxItems: 1 + + resets: + items: + - description: TSU module reset + + io-channels: + items: + - description: ADC channel which reports the TSU temperature + + io-channel-names: + items: + - const: tsu + + "#thermal-sensor-cells": + const: 0 + +required: + - compatible + - reg + - clocks + - power-domains + - resets + - io-channels + - io-channel-names + - '#thermal-sensor-cells' + +additionalProperties: false + +examples: + - | + #include + + tsu: thermal@10059000 { + compatible = "renesas,r9a08g045-tsu"; + reg = <0x10059000 0x1000>; + clocks = <&cpg CPG_MOD R9A08G045_TSU_PCLK>; + resets = <&cpg R9A08G045_TSU_PRESETN>; + power-domains = <&cpg>; + #thermal-sensor-cells = <0>; + io-channels = <&adc 8>; + io-channel-names = "tsu"; + }; + + thermal-zones { + cpu-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsu>; + + trips { + sensor_crit: sensor-crit { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + target: trip-point { + temperature = <100000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + }; From patchwork Fri Jan 3 16:38:03 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 854976 Received: from mail-ej1-f44.google.com (mail-ej1-f44.google.com [209.85.218.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2BDCC1FC7DF for ; Fri, 3 Jan 2025 16:38:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.44 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735922320; cv=none; b=kJB2yNL0Umx158yrjZ5ySWrNmUaJGU7SYc7z2TBP1+mv1zL3e3VXzdI2SJfXaxMRrhEJNzPyJMO+1nsOPYG+Ufi5xRR2Sx0J9dCTxKPEK4Cn6LeT4z8NwSjNDZPH0y/j38mYy2xWTXRS3oUZFoBcNpRER1nm2CKqfs16BEOfB4s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735922320; c=relaxed/simple; bh=ed1nSj2/6ODoZSIgxzoGaGfEmusLx1u4UI33afkgvm8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=qtEnHJaAnngbYla4x2byNDekhPHT510W3DNSTe51uGHeFQsw0ciLvxM0ccD3DGCpMpQ1FbK9yGyozXjmmoCcb1I6byfsNoEkUlT7qcdKHwBe5z3ezOu4yC1heqUs5ItAn6mBqA7gGh6nUkUd/8x43RrrGZT3UviMg7q1AlDse/Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=LpAoo6Qc; arc=none smtp.client-ip=209.85.218.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="LpAoo6Qc" Received: by mail-ej1-f44.google.com with SMTP id a640c23a62f3a-aaee0b309adso1392087866b.3 for ; Fri, 03 Jan 2025 08:38:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1735922316; x=1736527116; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8GMhatKxsQop+YQYK/7e1h+i8uxI54IklqBBVCwti8U=; b=LpAoo6Qc6gzxvcEEOLPso7/t9ryONVbamq7M3cldqVwEe/tHmYGBbiJAODU5N2lBMW eov1cA222A/yyk+KJI5O2mqLec840OzVz2h1NToY1PuO5e7GIHM6o6xRT21B+YbVNYAz hkNEkdaa+1naEJZcTxOY3ID4VYnwrwQ0vlc9YgpUMFo3LIE+/0WX4F9ZKU0tow1hCTVE lyVWzA4fap/XaTzLh1kJXx1TrRBWlAjCJOOTCUOAxXirhBJKueykvFYI82wh7NlLITDX A4ityOejDBiWhb6SqmQpmdy8CWDczr9aIddQ/ZiTzVGrTqJ8ROLndvQvs+iKFzttdPJA NiEg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1735922316; x=1736527116; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8GMhatKxsQop+YQYK/7e1h+i8uxI54IklqBBVCwti8U=; b=awO6G+E6Z1Blo4o6y6PXUsybwi9m0Z+CwWCkCplIm/XlDDK/XtzS1okHO39/cJpjq6 nTddnLLQUL/IGxZmBNWQymvTkqsSUTNrCrin9X9E6iEkUDkLCTb4+FvKKW5VFsbSA9hx F2TBDgnEn7qDq/12OXneuYLBMhLWEznJsgBu1GejzKPCxk5vn0ZWjKDDZgGXtGqP/xSq UC7xv3YJWsxUcDD2jhGk0s6BnchQ/TdT7dHZo4b7fYy22zvBWrGb3p85we8dsAqYPyWE DOAcmtH/A2bKmv220fpxkbXq55p8w7/eUxprEMReDCMsMhC/Vh6EeRpO4cmqgnsoCp3Q sH5w== X-Forwarded-Encrypted: i=1; AJvYcCVD0W1al8cE4urtl4QEVqIuXd7OaQTeHHNkVK1TwAlviyoPIx3pNjDLBfjVE1pzzxVTzdF+O5F1pQ==@vger.kernel.org X-Gm-Message-State: AOJu0YxVwU+a3rPXieCxOZwhWLBYqZqv0xk6mT5BcTz+30TnKaROK/jl /+xNnfUgsy+5mA3PN9m6J1DDJiyZeyBJnT+TLZMF4MBqWfiLENCf10xC+OhFOrg= X-Gm-Gg: ASbGncv3s1SjiPSvMIqu3/kiS+2LuIj+9YY2Cqb29wADUcyF4u1Ze0MnAmze74C3VMn Is5haK2lwiaAJ0Y9+YHzUBL+rh/HOSnfeHBdS7VQWvk4KI5INl8LxvkhpAgVMIA4aTzAvnPvJTS ExXbk1qvflKcOoTZ/4pse+7l7Xerbh9lV/a4UWKAAYts7ymSX5wss2IJpsbuLHuxpP91FQ46jIl fQKXopY/ErxHxKA547GUJFv6EPlG7IIRCBiIfd2Ast8/UNVrP+klNwVeoaoioyI/cd3C7KLBeXd RSarXazRf1s= X-Google-Smtp-Source: AGHT+IHvkBYCDNtkuQoboipJHaoUL6w4sk5iBfZsbglTc7vIk6YcMpGGuJWGPm5LzFye+zIDIa3xRA== X-Received: by 2002:a17:907:2cc5:b0:aa6:8676:3b33 with SMTP id a640c23a62f3a-aac3464f929mr4112731566b.47.1735922316348; Fri, 03 Jan 2025 08:38:36 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.102]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aac0e8953b6sm1932984066b.65.2025.01.03.08.38.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Jan 2025 08:38:35 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: rafael@kernel.org, daniel.lezcano@linaro.org, rui.zhang@intel.com, lukasz.luba@arm.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, ulf.hansson@linaro.org Cc: claudiu.beznea@tuxon.dev, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, Claudiu Beznea Subject: [PATCH 4/6] thermal: renesas: rzg3s: Add thermal driver for the Renesas RZ/G3S SoC Date: Fri, 3 Jan 2025 18:38:03 +0200 Message-ID: <20250103163805.1775705-5-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250103163805.1775705-1-claudiu.beznea.uj@bp.renesas.com> References: <20250103163805.1775705-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea The Renesas RZ/G3S SoC features a Thermal Sensor Unit (TSU) that reports the junction temperature. The temperature is reported through a dedicated ADC channel. Add a driver for the Renesas RZ/G3S TSU. Signed-off-by: Claudiu Beznea --- MAINTAINERS | 7 + drivers/thermal/renesas/Kconfig | 8 + drivers/thermal/renesas/Makefile | 1 + drivers/thermal/renesas/rzg3s_thermal.c | 301 ++++++++++++++++++++++++ 4 files changed, 317 insertions(+) create mode 100644 drivers/thermal/renesas/rzg3s_thermal.c diff --git a/MAINTAINERS b/MAINTAINERS index d2ab799a0659..0b5854dc2d5d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20131,6 +20131,13 @@ S: Maintained F: Documentation/devicetree/bindings/iio/potentiometer/renesas,x9250.yaml F: drivers/iio/potentiometer/x9250.c +RENESAS RZ/G3S THERMAL SENSOR UNIT DRIVER +M: Claudiu Beznea +L: linux-pm@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/thermal/renesas,r9a08g045-tsu.yaml +F: drivers/thermal/renesas/rzg3s_thermal.c + RESET CONTROLLER FRAMEWORK M: Philipp Zabel S: Maintained diff --git a/drivers/thermal/renesas/Kconfig b/drivers/thermal/renesas/Kconfig index dcf5fc5ae08e..566478797095 100644 --- a/drivers/thermal/renesas/Kconfig +++ b/drivers/thermal/renesas/Kconfig @@ -26,3 +26,11 @@ config RZG2L_THERMAL help Enable this to plug the RZ/G2L thermal sensor driver into the Linux thermal framework. + +config RZG3S_THERMAL + tristate "Renesas RZ/G3S thermal driver" + depends on ARCH_R9A08G045 || COMPILE_TEST + depends on OF && IIO && RZG2L_ADC + help + Enable this to plug the RZ/G3S thermal sensor driver into the Linux + thermal framework. diff --git a/drivers/thermal/renesas/Makefile b/drivers/thermal/renesas/Makefile index bf9cb3cb94d6..1feb5ab78827 100644 --- a/drivers/thermal/renesas/Makefile +++ b/drivers/thermal/renesas/Makefile @@ -3,3 +3,4 @@ obj-$(CONFIG_RCAR_GEN3_THERMAL) += rcar_gen3_thermal.o obj-$(CONFIG_RCAR_THERMAL) += rcar_thermal.o obj-$(CONFIG_RZG2L_THERMAL) += rzg2l_thermal.o +obj-$(CONFIG_RZG3S_THERMAL) += rzg3s_thermal.o diff --git a/drivers/thermal/renesas/rzg3s_thermal.c b/drivers/thermal/renesas/rzg3s_thermal.c new file mode 100644 index 000000000000..6719f9ca05eb --- /dev/null +++ b/drivers/thermal/renesas/rzg3s_thermal.c @@ -0,0 +1,301 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Renesas RZ/G3S TSU Thermal Sensor Driver + * + * Copyright (C) 2024 Renesas Electronics Corporation + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../thermal_hwmon.h" + +#define TSU_SM 0x0 +#define TSU_SM_EN BIT(0) +#define TSU_SM_OE BIT(1) +#define OTPTSUTRIM_REG(n) (0x18 + (n) * 0x4) +#define OTPTSUTRIM_EN_MASK BIT(31) +#define OTPTSUTRIM_MASK GENMASK(11, 0) + +#define TSU_READ_STEPS 8 + +/* Default calibration values, if FUSE values are missing. */ +#define SW_CALIB0_VAL 1297 +#define SW_CALIB1_VAL 751 + +#define MCELSIUS(temp) ((temp) * MILLIDEGREE_PER_DEGREE) + +/** + * struct rzg3s_thermal_priv - RZ/G3S thermal private data structure + * @base: TSU base address + * @dev: device pointer + * @tz: thermal zone pointer + * @rstc: reset control + * @channel: IIO channel to read the TSU + * @mode: current device mode + * @calib0: calibration value + * @calib1: calibration value + */ +struct rzg3s_thermal_priv { + void __iomem *base; + struct device *dev; + struct thermal_zone_device *tz; + struct reset_control *rstc; + struct iio_channel *channel; + enum thermal_device_mode mode; + u16 calib0; + u16 calib1; +}; + +static int rzg3s_thermal_get_temp(struct thermal_zone_device *tz, int *temp) +{ + struct rzg3s_thermal_priv *priv = thermal_zone_device_priv(tz); + struct device *dev = priv->dev; + u32 ts_code_ave = 0; + int ret, val; + + if (priv->mode != THERMAL_DEVICE_ENABLED) + return -EAGAIN; + + ret = pm_runtime_resume_and_get(dev); + if (ret) + return ret; + + for (u8 i = 0; i < TSU_READ_STEPS; i++) { + ret = iio_read_channel_raw(priv->channel, &val); + if (ret < 0) + goto rpm_put; + + ts_code_ave += val; + /* + * According to the HW manual (section 40.4.4 Procedure for Measuring the + * Temperature) we need to wait here at leat 3us. + */ + usleep_range(5, 10); + } + + ret = 0; + ts_code_ave = DIV_ROUND_CLOSEST(ts_code_ave, TSU_READ_STEPS); + + /* + * According to the HW manual (section 40.4.4 Procedure for Measuring the Temperature) + * the computation formula is as follows: + * + * Tj = (ts_code_ave - priv->calib1) * 165 / (priv->calib0 - priv->calib1) - 40 + */ + *temp = DIV_ROUND_CLOSEST((ts_code_ave - priv->calib1) * 165, + (priv->calib0 - priv->calib1)) - 40; + + /* Report it in mili degrees Celsius and round it up to 0.5 degrees Celsius. */ + *temp = roundup(MCELSIUS(*temp), 500); + +rpm_put: + pm_runtime_mark_last_busy(dev); + pm_runtime_put_autosuspend(dev); + + return ret; +} + +static void rzg3s_thermal_set_mode(struct rzg3s_thermal_priv *priv, + enum thermal_device_mode mode) +{ + struct device *dev = priv->dev; + int ret; + + ret = pm_runtime_resume_and_get(dev); + if (ret) + return; + + if (mode == THERMAL_DEVICE_DISABLED) { + writel(0, priv->base + TSU_SM); + } else { + writel(TSU_SM_EN, priv->base + TSU_SM); + /* + * According to the HW manual (section 40.4.1 Procedure for + * Starting the TSU) we need to wait here 30us or more. + */ + usleep_range(30, 40); + + writel(TSU_SM_OE | TSU_SM_EN, priv->base + TSU_SM); + /* + * According to the HW manual (section 40.4.1 Procedure for + * Starting the TSU) we need to wait here 50us or more. + */ + usleep_range(50, 60); + } + + pm_runtime_mark_last_busy(dev); + pm_runtime_put_autosuspend(dev); +} + +static int rzg3s_thermal_change_mode(struct thermal_zone_device *tz, + enum thermal_device_mode mode) +{ + struct rzg3s_thermal_priv *priv = thermal_zone_device_priv(tz); + + if (priv->mode == mode) + return 0; + + rzg3s_thermal_set_mode(priv, mode); + priv->mode = mode; + + return 0; +} + +static const struct thermal_zone_device_ops rzg3s_tz_of_ops = { + .get_temp = rzg3s_thermal_get_temp, + .change_mode = rzg3s_thermal_change_mode, +}; + +static int rzg3s_thermal_read_calib(struct rzg3s_thermal_priv *priv) +{ + struct device *dev = priv->dev; + u32 val; + int ret; + + ret = pm_runtime_resume_and_get(dev); + if (ret) + return ret; + + val = readl(priv->base + OTPTSUTRIM_REG(0)); + if (val & OTPTSUTRIM_EN_MASK) + priv->calib0 = FIELD_GET(OTPTSUTRIM_MASK, val); + else + priv->calib0 = SW_CALIB0_VAL; + + val = readl(priv->base + OTPTSUTRIM_REG(1)); + if (val & OTPTSUTRIM_EN_MASK) + priv->calib1 = FIELD_GET(OTPTSUTRIM_MASK, val); + else + priv->calib1 = SW_CALIB1_VAL; + + pm_runtime_mark_last_busy(dev); + pm_runtime_put_autosuspend(dev); + + return 0; +} + +static int rzg3s_thermal_probe(struct platform_device *pdev) +{ + struct rzg3s_thermal_priv *priv; + struct device *dev = &pdev->dev; + int ret; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + priv->channel = devm_iio_channel_get(dev, "tsu"); + if (IS_ERR(priv->channel)) + return dev_err_probe(dev, PTR_ERR(priv->channel), "Failed to get IIO channel!\n"); + + priv->rstc = devm_reset_control_get_exclusive_deasserted(dev, NULL); + if (IS_ERR(priv->rstc)) + return dev_err_probe(dev, PTR_ERR(priv->rstc), "Failed to get reset!\n"); + + priv->dev = dev; + priv->mode = THERMAL_DEVICE_DISABLED; + platform_set_drvdata(pdev, priv); + + pm_runtime_set_autosuspend_delay(dev, 300); + pm_runtime_use_autosuspend(dev); + pm_runtime_enable(dev); + + ret = rzg3s_thermal_read_calib(priv); + if (ret) { + dev_err_probe(dev, ret, "Failed to read calibration data!\n"); + goto rpm_disable; + } + + priv->tz = thermal_of_zone_register(dev->of_node, 0, priv, &rzg3s_tz_of_ops); + if (IS_ERR(priv->tz)) { + dev_err_probe(dev, PTR_ERR(priv->tz), "Failed to register thermal zone!\n"); + goto rpm_disable; + } + + ret = thermal_add_hwmon_sysfs(priv->tz); + if (ret) { + dev_err_probe(dev, ret, "Failed to add hwmon sysfs!\n"); + goto tz_unregister; + } + + return 0; + +tz_unregister: + thermal_of_zone_unregister(priv->tz); +rpm_disable: + pm_runtime_disable(dev); + pm_runtime_dont_use_autosuspend(dev); + return ret; +} + +static void rzg3s_thermal_remove(struct platform_device *pdev) +{ + struct rzg3s_thermal_priv *priv = dev_get_drvdata(&pdev->dev); + + thermal_remove_hwmon_sysfs(priv->tz); + thermal_of_zone_unregister(priv->tz); + pm_runtime_disable(priv->dev); + pm_runtime_dont_use_autosuspend(priv->dev); +} + +static int rzg3s_thermal_suspend(struct device *dev) +{ + struct rzg3s_thermal_priv *priv = dev_get_drvdata(dev); + + rzg3s_thermal_set_mode(priv, THERMAL_DEVICE_DISABLED); + + return reset_control_assert(priv->rstc); +} + +static int rzg3s_thermal_resume(struct device *dev) +{ + struct rzg3s_thermal_priv *priv = dev_get_drvdata(dev); + int ret; + + ret = reset_control_deassert(priv->rstc); + if (ret) + return ret; + + if (priv->mode != THERMAL_DEVICE_DISABLED) + rzg3s_thermal_set_mode(priv, priv->mode); + + return 0; +} + +static const struct dev_pm_ops rzg3s_thermal_pm_ops = { + SYSTEM_SLEEP_PM_OPS(rzg3s_thermal_suspend, rzg3s_thermal_resume) +}; + +static const struct of_device_id rzg3s_thermal_dt_ids[] = { + { .compatible = "renesas,r9a08g045-tsu" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, rzg3s_thermal_dt_ids); + +static struct platform_driver rzg3s_thermal_driver = { + .driver = { + .name = "rzg3s_thermal", + .of_match_table = rzg3s_thermal_dt_ids, + .pm = pm_ptr(&rzg3s_thermal_pm_ops), + }, + .probe = rzg3s_thermal_probe, + .remove = rzg3s_thermal_remove, +}; +module_platform_driver(rzg3s_thermal_driver); + +MODULE_DESCRIPTION("Renesas RZ/G3S Thermal Sensor Unit Driver"); +MODULE_AUTHOR("Claudiu Beznea "); +MODULE_LICENSE("GPL"); From patchwork Fri Jan 3 16:38:04 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 855121 Received: from mail-ed1-f50.google.com (mail-ed1-f50.google.com [209.85.208.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 92E7D1FC7E3 for ; Fri, 3 Jan 2025 16:38:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735922323; cv=none; b=bh8gnIutxmRH/kHujwepvRZRIGQxbMb6GEN6+mFJ2hQzbDl1Jbu499yHFOAliHi2ZNMQ1AYkHgMLpx4shzdz4oyzlxT07JzW4qj4ks2zt6ffVZaYmtXBxd4uyXKMLgFfzyavwTLDeWPL0UC5Kv6DFyKuzSbyzq78dAfJlj1xaf0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735922323; c=relaxed/simple; bh=uA7zSCyT+GU3Zteq7U0sWo2VeqLEzQfO9yMYYfppUds=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=KuQY3FBaQFGQUF+6qNvRK7YGH7FqiniI+4KxPCFAfb7v2p/1EVZXtYFE2q9ICKNq5crgLlq1nBKx8NPy9nVYFMpeH4v0MsTekgwylulpQqzdaszgAbHxagy44w7ZIV/PXgzXjIgIsLI70v6Sgqe6/1Rg1SllBK7+nv0ZlPf1CQE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=nPddEcXr; arc=none smtp.client-ip=209.85.208.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="nPddEcXr" Received: by mail-ed1-f50.google.com with SMTP id 4fb4d7f45d1cf-5d8c1950da7so9590864a12.3 for ; Fri, 03 Jan 2025 08:38:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1735922320; x=1736527120; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=WzIPlmgQYvqaNwex1YHnIy7YRZOsyuGpSTntBCm6GNw=; b=nPddEcXr+DKBPwBGhd68CXns0WzpisDTshyQrivcZSVjxfTiIra7TAB2AKTecjIaT/ 6C0u/ZswMffft1jQBrbcT62GmMd6C+tBzUyna7T79zHud+v4luSKSWr/A5LCZAPcOUsP t5uc789kXPQHF24N+dKy8z6+slml5N1LK6Z1QcO1cICKW+tNfjwtI400GSOPk+aSBZuy cRtAz1UOyCX7wDmVqiOpv9IDpw42xxrmE0pllDNkwyIVO5tzw+6Mjrrd1fprFDRRFEGf 5iNMtN1w22O+Vl60PjrcOhNb0SXHjOOW8aSXvIFxf6OKruy8YNvdV+EmRisHUm6QXx5y GzBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1735922320; x=1736527120; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WzIPlmgQYvqaNwex1YHnIy7YRZOsyuGpSTntBCm6GNw=; b=CkfeQsSQHm4WOoRnamvjx3VmVP1HOCuIwO5OhZ+qX2y+8lKmaNi2oA82ggWQeFLgvW 0WjnrhWOHf11UcK0fg90gtyA/uM86f2AW9z3OUTNUhEuEDOOjSzWju7+4DKorbG4lmb0 4cbT05FwyYJqY71l8cE5Cn4ZZYBpjj5OFeaT/f2zBU4ty645reKsRTozk/Mfbs0Bn0wX d1WQO/Uc2jbtch1XRDAbGhGs35qqMa63Bc6ry0dO5zhLkJxUzzMr5Btepqvcc1J0VmDE YjKbWU3HnvRtm9bv0GpAR03LLJcwwZ1G1VTHj2V+oRGBrqNHNK4e9NszZzKgnHz5mQmf NJSg== X-Forwarded-Encrypted: i=1; AJvYcCX78mPSLU+VvRwe9z+u4UxaiVSK9D7k0e42MyMnIV1LTU/8+Oa0cAFAOzDXzZnVzZg6Nvww6KaPkA==@vger.kernel.org X-Gm-Message-State: AOJu0YxlyrDW+yAyfD6IumAkxpDhonB5jKxzVjWEnNxi8Slkie0v/tpg aZiptfuLHtZ3fbIEEXTJEMIV32/v9ejCHrpdixHF9Gpj18MD65Rx2QUB3TEQV+A= X-Gm-Gg: ASbGncv9Y814VKzVM//54lShhKDticTxL5Jz8cQqhUCJKzASr09duMGWkEJvCgYaLlz j0ICfCy2uQbFLMXTyNDj3IdJd7dmMj6qfDnhw419ly4PLtc6bjRfC1iEhzPRgflHofQ2hIpGvss RdRYeIvPItoY5DoWgqS32FpOsJtbAF2XjKfq6Y8hU1oLMfR6NMnrtctZCQeUKXRP3F8xspbnjX4 MK1ySvxqQERlVsZXev7z2bz2AQd//Ly7VDxHUPEoMOWvsVZ7QIjte8uGhu6ju7CfSfzpdWQvO+y BW3mP2mbqnw= X-Google-Smtp-Source: AGHT+IE84xLk/WtOOKb4Wwm+4qdlu+SqcMhw+gwQquj/QrYYaTzEDXr5cpwvEJHSOv4z3jx+xnmhFA== X-Received: by 2002:a17:907:724b:b0:aa6:7737:1991 with SMTP id a640c23a62f3a-aac2702ae51mr5003000966b.2.1735922318403; Fri, 03 Jan 2025 08:38:38 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.102]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aac0e8953b6sm1932984066b.65.2025.01.03.08.38.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Jan 2025 08:38:37 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: rafael@kernel.org, daniel.lezcano@linaro.org, rui.zhang@intel.com, lukasz.luba@arm.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, ulf.hansson@linaro.org Cc: claudiu.beznea@tuxon.dev, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, Claudiu Beznea Subject: [PATCH 5/6] arm64: dts: renesas: r9a08g045: Add TSU node Date: Fri, 3 Jan 2025 18:38:04 +0200 Message-ID: <20250103163805.1775705-6-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250103163805.1775705-1-claudiu.beznea.uj@bp.renesas.com> References: <20250103163805.1775705-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Add TSU node along with thermal zones and keep it enabled in the SoC DTSI. The temperature reported by the TSU can only be read through channel 8 of the ADC. Therefore, enable the ADC by default. Signed-off-by: Claudiu Beznea --- arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 43 ++++++++++++++++++- .../boot/dts/renesas/rzg3s-smarc-som.dtsi | 4 -- 2 files changed, 42 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi index a9b98db9ef95..fd74138198a8 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -205,7 +205,6 @@ adc: adc@10058000 { #address-cells = <1>; #size-cells = <0>; #io-channel-cells = <1>; - status = "disabled"; channel@0 { reg = <0>; @@ -244,6 +243,17 @@ channel@8 { }; }; + tsu: thermal@10059000 { + compatible = "renesas,r9a08g045-tsu"; + reg = <0 0x10059000 0 0x1000>; + clocks = <&cpg CPG_MOD R9A08G045_TSU_PCLK>; + resets = <&cpg R9A08G045_TSU_PRESETN>; + power-domains = <&cpg>; + #thermal-sensor-cells = <0>; + io-channels = <&adc 8>; + io-channel-names = "tsu"; + }; + vbattb: clock-controller@1005c000 { compatible = "renesas,r9a08g045-vbattb"; reg = <0 0x1005c000 0 0x1000>; @@ -690,6 +700,37 @@ timer { "hyp-virt"; }; + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsu>; + sustainable-power = <423>; + + cooling-maps { + map0 { + trip = <&target>; + cooling-device = <&cpu0 0 2>; + contribution = <1024>; + }; + }; + + trips { + sensor_crit: sensor-crit { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + + target: trip-point { + temperature = <100000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + }; + vbattb_xtal: vbattb-xtal { compatible = "fixed-clock"; #clock-cells = <0>; diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi index ef12c1c462a7..041d256d7b79 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi @@ -102,10 +102,6 @@ x3_clk: x3-clock { }; }; -&adc { - status = "okay"; -}; - #if SW_CONFIG3 == SW_ON ð0 { pinctrl-0 = <ð0_pins>; From patchwork Fri Jan 3 16:38:05 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 854975 Received: from mail-ej1-f42.google.com (mail-ej1-f42.google.com [209.85.218.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 076AB1FBCB0 for ; Fri, 3 Jan 2025 16:38:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.42 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735922324; cv=none; b=C+iKM50rh/K7UprqG3RR6a95Nh00r+yuuXFx41LImEilMP8sXrmbUSizggIsDRovjQxWYx1xPK7P9TcP7oPS+xr4c2W1les5C2/W/UEmPvD+VGRuenki+w2Bz55JOE0+1TUzFboEQFv0rXCzq+PLCxwgkcLq+FutbA79rBmB2xo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735922324; c=relaxed/simple; bh=ElJIj15I7VDEmOYeFsm2GgBst4b8C7b3V/BjoymFWVI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=gA5c/uHBEqKl1lLIbDTVXxl8ZsbYnXeMSaBkTIKvM63oxA7+mgq7qJZGawd55YY2kJlzjDRt74dMBSHlUbpmYRDx1LwLKQinfyRP6J6jcEes75E/jsrBlLEoEvwJGxOrYw6tq/jJ4weHQnK2GMbzc0vwjqGeinosTk54GhbnQeM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=dEQYtl93; arc=none smtp.client-ip=209.85.218.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="dEQYtl93" Received: by mail-ej1-f42.google.com with SMTP id a640c23a62f3a-aa67333f7d2so1782077466b.0 for ; Fri, 03 Jan 2025 08:38:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1735922320; x=1736527120; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8obrWVZsJoXmrid0pqmVf5t2hFsLjtOlv8BcTL5IH0U=; b=dEQYtl93Df3LWWZvuu5qW2QRtK6fz0b649Scup7lS23/SuQ9/KQDOgPN7ppr1aenF4 q63qwk7oxnvuPpshdbbfQBsnOPWstop+STH848gnsTIChZgs7WPuo0zdLCkMA3uStnAS Vbgr0oCnJlvnaWbGknRBenUL2jFQIYe9jkLMzq8XcmEQHpiBe9Wu0DHc/GalexKHJSrj FAFPXpjVMUaRJXki7CvVVxhjHwob84XazPeQI2ly5Tqidrm8uljlEjLdxcIXw4vrFaKu JkEjSFQtPYRZFdAA81pzamLW/j/7zFSXM5w812OzwOJ8MhCU8Fx3EgwepehiBHIyuZqt 6+cg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1735922320; x=1736527120; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8obrWVZsJoXmrid0pqmVf5t2hFsLjtOlv8BcTL5IH0U=; b=vq9dPPZjcNFiWqjCRfwBEulmdfih4cqOUiGGF/hbblfECmoOxUgZV1Ki0Nxj96LyGE jHcWrJQnjAcPtfz6xcqJpZQMfZNrPL3eIoIjlAFrHnrAAt7W7g4GorumOQZx/17agW4n 0VdOB0WoFQqH2TIKqVHg4z1DF4FEyESvKuCTL+A3hsUW8S8pm77g8EGXUGJ7T3pa7S6w +y/m60NL8lfkX43fMduLHeVitQqdWoNTVyDHpJOGXqMndSKxTNvuO6uss9ZEG5rKQa9n Ne7bD76T5nq2L4Ay//WgD70d8UF8VPnrA7v8fPvB5BbqKO8h1Ke34imxsq0pR+MHgWVu b8MQ== X-Forwarded-Encrypted: i=1; AJvYcCWDoAQNQi5CsY6BYAmvAdTbdZNRZAuyrMhpHst6luNdw+YGKdC/dvTNtBl4Tch4zG/KsLxzhBPzQw==@vger.kernel.org X-Gm-Message-State: AOJu0YzE2NPY4m3vFgGJAFS+ONdPHrATZ2ulEDDzZYXl2UslU+ZbwMqW NRC3oeLWh9JMht9b7AcMIIz728qU+lILRBVz8+pmvgwv11ua1+BdZyi+0XbkY5g= X-Gm-Gg: ASbGncvKTMuHPh86meSSmy2V56yOw9M0Sywjrr2gEUC8gvZHxnRA0d6BIUDU5d8q4jP ILwCIKZ3h0K/O6IkuOiwhwZFpUigL9btxvHUTNIMLmDwjbT9+nEkvixFFUHzURNNzIeCQLTTUwI EBNPacMz5YzQtHiUpLKe+nnCA0i+cSV5JZ8mEVkE3VunpixdFI0DhOoSgAmMjGdelm8XQkuLGmo +tjEeWQ6wvI+PE7VtL9W2tBgbIDf/EWsjItS6L41Y0xYkkww8V3UMZxHQwbY9nL9DYTb24xCk0v d5u4IoR9+CE= X-Google-Smtp-Source: AGHT+IH+DUY6nprcntI+5aClJEE8pz4wAhTYG8dCJD+t8yU/xxOBpHwSJqf9myK1PfsCCnfBeBYRqg== X-Received: by 2002:a17:907:1b96:b0:aae:83c6:c67e with SMTP id a640c23a62f3a-aae83c6c8f5mr3028524366b.55.1735922320359; Fri, 03 Jan 2025 08:38:40 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.102]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aac0e8953b6sm1932984066b.65.2025.01.03.08.38.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Jan 2025 08:38:39 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: rafael@kernel.org, daniel.lezcano@linaro.org, rui.zhang@intel.com, lukasz.luba@arm.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, ulf.hansson@linaro.org Cc: claudiu.beznea@tuxon.dev, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, Claudiu Beznea Subject: [PATCH 6/6] arm64: defconfig: Enable RZ/G3S thermal Date: Fri, 3 Jan 2025 18:38:05 +0200 Message-ID: <20250103163805.1775705-7-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250103163805.1775705-1-claudiu.beznea.uj@bp.renesas.com> References: <20250103163805.1775705-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Enable the CONFIG_RZG3S_THERMAL flag for the RZ/G3S SoC. Signed-off-by: Claudiu Beznea --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index dfa5c8d5b658..576a544b8c79 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -706,6 +706,7 @@ CONFIG_ROCKCHIP_THERMAL=m CONFIG_RCAR_THERMAL=y CONFIG_RCAR_GEN3_THERMAL=y CONFIG_RZG2L_THERMAL=y +CONFIG_RZG3S_THERMAL=m CONFIG_ARMADA_THERMAL=y CONFIG_MTK_THERMAL=m CONFIG_MTK_LVTS_THERMAL=m