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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38a1c832e53sm33389931f8f.27.2024.12.31.11.06.27 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 31 Dec 2024 11:06:27 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Helge Deller , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v4 1/6] tests: Add functional tests for HPPA machines Date: Tue, 31 Dec 2024 20:06:15 +0100 Message-ID: <20241231190620.24442-2-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241231190620.24442-1-philmd@linaro.org> References: <20241231190620.24442-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=philmd@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Add quick firmware boot tests (less than 1sec) for the B160L (32-bit) and C3700 (64-bit) HPPA machines: $ make check-functional-hppa 1/4 qemu:func-quick+func-hppa / func-hppa-empty_cpu_model OK 0.13s 1 subtests passed 2/4 qemu:func-quick+func-hppa / func-hppa-version OK 0.14s 1 subtests passed 3/4 qemu:func-quick+func-hppa / func-hppa-info_usernet OK 0.22s 1 subtests passed 4/4 qemu:func-quick+func-hppa / func-hppa-hppa_seabios OK 0.22s 2 subtests passed Suggested-by: Helge Deller Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Helge Deller Tested-by: Helge Deller --- MAINTAINERS | 1 + tests/functional/meson.build | 4 +++ tests/functional/test_hppa_seabios.py | 35 +++++++++++++++++++++++++++ 3 files changed, 40 insertions(+) create mode 100755 tests/functional/test_hppa_seabios.py diff --git a/MAINTAINERS b/MAINTAINERS index 38a290e9c2c..17c720dd2b9 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1201,6 +1201,7 @@ F: include/hw/pci-host/astro.h F: include/hw/pci-host/dino.h F: pc-bios/hppa-firmware.img F: roms/seabios-hppa/ +F: tests/functional/test_hppa_seabios.py LoongArch Machines ------------------ diff --git a/tests/functional/meson.build b/tests/functional/meson.build index 24f7f8f2f1c..71810a3aa82 100644 --- a/tests/functional/meson.build +++ b/tests/functional/meson.build @@ -104,6 +104,10 @@ tests_avr_system_thorough = [ 'avr_mega2560', ] +tests_hppa_system_quick = [ + 'hppa_seabios', +] + tests_i386_system_thorough = [ 'i386_tuxrun', ] diff --git a/tests/functional/test_hppa_seabios.py b/tests/functional/test_hppa_seabios.py new file mode 100755 index 00000000000..a44d1a3eebe --- /dev/null +++ b/tests/functional/test_hppa_seabios.py @@ -0,0 +1,35 @@ +#!/usr/bin/env python3 +# +# SeaBIOS boot test for HPPA machines +# +# Copyright (c) 2024 Linaro, Ltd +# +# SPDX-License-Identifier: GPL-2.0-or-later + +from qemu_test import QemuSystemTest +from qemu_test import wait_for_console_pattern + +class HppaSeabios(QemuSystemTest): + + timeout = 5 + MACH_BITS = {'B160L': 32, 'C3700': 64} + + def boot_seabios(self): + mach = self.machine + bits = self.MACH_BITS[mach] + self.vm.set_console() + self.vm.launch() + self.machine + wait_for_console_pattern(self, f'SeaBIOS PA-RISC {bits}-bit Firmware') + wait_for_console_pattern(self, f'Emulated machine: HP {mach} ({bits}-bit') + + def test_hppa_32(self): + self.set_machine('B160L') + self.boot_seabios() + + def test_hppa_64(self): + self.set_machine('C3700') + self.boot_seabios() + +if __name__ == '__main__': + QemuSystemTest.main() From patchwork Tue Dec 31 19:06:16 2024 Content-Type: text/plain; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38a1c848a47sm33074712f8f.62.2024.12.31.11.06.31 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 31 Dec 2024 11:06:32 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Helge Deller , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v4 2/6] target/hppa: Convert hppa_cpu_init() to ResetHold handler Date: Tue, 31 Dec 2024 20:06:16 +0100 Message-ID: <20241231190620.24442-3-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241231190620.24442-1-philmd@linaro.org> References: <20241231190620.24442-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=philmd@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Helge Deller hppa_cpu_initfn() is called once when a HPPA CPU instance is initialized, but it sets fields which should be set each time a CPU resets. Rename it as a reset handler, having it matching the ResettablePhases::hold() signature, and register it as ResettableClass handler. Since on reset the CPU registers and TLB entries are expected to be zero, add a memset() call clearing CPUHPPAState up to the &end_reset_fields marker. Signed-off-by: Helge Deller Co-developed-by: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé --- target/hppa/cpu.h | 5 +++++ target/hppa/cpu.c | 14 ++++++++++++-- 2 files changed, 17 insertions(+), 2 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 22a6510e087..c1d69c1a835 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -263,6 +263,9 @@ typedef struct CPUArchState { IntervalTreeRoot tlb_root; HPPATLBEntry tlb[HPPA_TLB_ENTRIES]; + + /* Fields up to this point are cleared by a CPU reset */ + struct {} end_reset_fields; } CPUHPPAState; /** @@ -281,6 +284,7 @@ struct ArchCPU { /** * HPPACPUClass: * @parent_realize: The parent class' realize handler. + * @parent_phases: The parent class' reset phase handlers. * * An HPPA CPU model. */ @@ -288,6 +292,7 @@ struct HPPACPUClass { CPUClass parent_class; DeviceRealize parent_realize; + ResettablePhases parent_phases; }; #include "exec/cpu-all.h" diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 47d01609557..d784bcdd602 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -193,13 +193,20 @@ static void hppa_cpu_realizefn(DeviceState *dev, Error **errp) tcg_cflags_set(cs, CF_PCREL); } -static void hppa_cpu_initfn(Object *obj) +static void hppa_cpu_reset_hold(Object *obj, ResetType type) { + HPPACPUClass *scc = HPPA_CPU_GET_CLASS(obj); CPUState *cs = CPU(obj); HPPACPU *cpu = HPPA_CPU(obj); CPUHPPAState *env = &cpu->env; + if (scc->parent_phases.hold) { + scc->parent_phases.hold(obj, type); + } cs->exception_index = -1; + + memset(env, 0, offsetof(CPUHPPAState, end_reset_fields)); + cpu_hppa_loaded_fr0(env); cpu_hppa_put_psw(env, PSW_W); } @@ -242,10 +249,14 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *data) DeviceClass *dc = DEVICE_CLASS(oc); CPUClass *cc = CPU_CLASS(oc); HPPACPUClass *acc = HPPA_CPU_CLASS(oc); + ResettableClass *rc = RESETTABLE_CLASS(oc); device_class_set_parent_realize(dc, hppa_cpu_realizefn, &acc->parent_realize); + resettable_class_set_parent_phases(rc, NULL, hppa_cpu_reset_hold, NULL, + &acc->parent_phases); + cc->class_by_name = hppa_cpu_class_by_name; cc->has_work = hppa_cpu_has_work; cc->mmu_index = hppa_cpu_mmu_index; @@ -269,7 +280,6 @@ static const TypeInfo hppa_cpu_type_infos[] = { .parent = TYPE_CPU, .instance_size = sizeof(HPPACPU), .instance_align = __alignof(HPPACPU), - .instance_init = hppa_cpu_initfn, .abstract = false, .class_size = sizeof(HPPACPUClass), .class_init = hppa_cpu_class_init, From patchwork Tue Dec 31 19:06:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 854396 Delivered-To: patch@linaro.org Received: by 2002:a5d:4888:0:b0:385:e875:8a9e with SMTP id g8csp7064883wrq; Tue, 31 Dec 2024 11:07:38 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWrSfDg+E9A/w7KRz03LSUugVqQOmfWiHLIrfMVAkyhXHcrcf4Pc2T9X7RlWgU3JJ6deRfjwA==@linaro.org X-Google-Smtp-Source: AGHT+IEfCkSjJr7063TI4DV/LfGNOA1C5LCt3cd/vl1EqqCC8ZO6liRLdn+/dxFpMrd89J4vkcEX X-Received: by 2002:a05:6122:2519:b0:516:2833:1b8d with SMTP id 71dfb90a1353d-51b75d62414mr28271216e0c.11.1735672058167; Tue, 31 Dec 2024 11:07:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1735672058; cv=none; d=google.com; s=arc-20240605; b=PJHCFpqJ1pTOjeSlcw0SibcFVbkVll/KFnNdV66wko52A/s+vbIRrjmGFcAOiR3Ylq ze2Bozb3xoQIiEIq2IbBpnl1/TTPdDlf4nK13RYK2aDzBbvizOgPtDP+1uSEM+ZFx46l GRavsk3nQa9NFxXATiJy/mUZH3vLCrt63l24RpPuC8v47N9pk4PuwMZ1AzeVhlbZLJha 4ujqypOxmgAlBRShN8T+Tbgabkj7LT8Q0YudLBnZiSZBvyC08aV60nn1tEnOcJrPevJD jWIjKd02UEZuZbCOORRZc+vD/BcjQFK4k6/GNXT0uEqKRoAC7upoU7L36uAMXOH4pcP6 2asg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=GAtXelESZqP9EpLglyIc26IsQk/mXnYos/ye7zC5LFE=; fh=Pu80oL6pqNVhcxmoTE7CG5kT5lPd7R2XHVDIETOmhNw=; b=UAXvY9YweTmb2Ja+S0+ISXmYwjg2eKIyIeQY+ls2NXvujMmn0q3fhW7GpWKNl1M+xh 9lw6ifXPLvUgushQZo7bjdbxHnmbdmMPbFGT+j03d9Tg/gBgp9+GwQ6PQL8zeXjk5tDX /K/3820wmqJ6lRPITRnVSYouxl3Xu/pja72N7k6ZMFA0a7VVsNCB2ziW+/l4e7fMcPoS S3h8Eg62ZpkhBn6wTzyumQojcvqWo1lFmIBkOYyPGjYVFf3dLUtvjV/WgQTpasEHWhyC JRYrdTKUTv0BW+mnQBuKisGzSjczwdkOa3sxbBQdaZiMqPAIljg/7DFk0lILno/mxUGc V5BQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=e6C6G1RH; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4366127c488sm395913725e9.27.2024.12.31.11.06.36 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 31 Dec 2024 11:06:36 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Helge Deller , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v4 3/6] hw/hppa: Reset vCPUs calling resettable_reset() Date: Tue, 31 Dec 2024 20:06:17 +0100 Message-ID: <20241231190620.24442-4-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241231190620.24442-1-philmd@linaro.org> References: <20241231190620.24442-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=philmd@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Helge Deller Rather than manually (and incompletely) resetting vCPUs, call resettable_reset() which will fully reset the vCPUs. Remove redundant assignations. Signed-off-by: Helge Deller Co-developed-by: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé --- hw/hppa/machine.c | 6 +++--- target/hppa/cpu.c | 1 + 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/hw/hppa/machine.c b/hw/hppa/machine.c index 65259308e2e..8230f43e41c 100644 --- a/hw/hppa/machine.c +++ b/hw/hppa/machine.c @@ -655,12 +655,12 @@ static void hppa_machine_reset(MachineState *ms, ResetType type) for (i = 0; i < smp_cpus; i++) { CPUState *cs = CPU(cpu[i]); + /* reset CPU */ + resettable_reset(OBJECT(cs), RESET_TYPE_COLD); + cpu_set_pc(cs, firmware_entry); cpu[i]->env.psw = PSW_Q; cpu[i]->env.gr[5] = CPU_HPA + i * 0x1000; - - cs->exception_index = -1; - cs->halted = 0; } /* already initialized by machine_hppa_init()? */ diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index d784bcdd602..41538d39d62 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -204,6 +204,7 @@ static void hppa_cpu_reset_hold(Object *obj, ResetType type) scc->parent_phases.hold(obj, type); } cs->exception_index = -1; + cs->halted = 0; memset(env, 0, offsetof(CPUHPPAState, end_reset_fields)); From patchwork Tue Dec 31 19:06:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 854397 Delivered-To: patch@linaro.org Received: by 2002:a5d:4888:0:b0:385:e875:8a9e with SMTP id g8csp7064995wrq; Tue, 31 Dec 2024 11:08:02 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXZIqDTmEmkBya64oMH0MhmLpD8tBz0K+0Gw6LTk0gcWd3skYi1nhj678IWHLhxtht0mTh//g==@linaro.org X-Google-Smtp-Source: AGHT+IGh3z2gbGKClkplM7ahCi6dIUzHCNqMTVA2rMee1iaPjhLnksl06kXWx4Q6wGAZvqFH2DVP X-Received: by 2002:a05:620a:470d:b0:7b1:3c0e:3289 with SMTP id af79cd13be357-7b9bacb4f01mr6893600285a.22.1735672081809; Tue, 31 Dec 2024 11:08:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1735672081; cv=none; d=google.com; s=arc-20240605; b=fvE4evxEZkBChMcUukkTTIUzZ+ozlB4F0j8emgAUZ4BRhLXyLTlxRPSMhVzUlwog7D CwT73sP7KAqGie3fhi+3e/fAk56nJx50+W7xG0LlHERuDz/Z20av8e+qfPjx9LQGVVXO l021qOWhYj9nfTZghsW/8cw7VHNpPsQWsYaZtcruLQrKDSdSur3OtN/kXyxwZoNsVi+0 fAP3Kf69OrQY07Aa//xV0djeBKomgmdkHA/8PkGQ10X/QbWn7F/Pmb467hGXQdqyccRA XyVJ/1Sy2yHyA0pf6HgtvF1TlkZ2gNi/Og0FewnqYhbwZKP3Dsq2CuTdKDq4OyKU3gAQ /Khw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=c0vE3lYtWkiDZCwAWAKMF4/xKoT2gUVX19Q6TmVZnmQ=; fh=Pu80oL6pqNVhcxmoTE7CG5kT5lPd7R2XHVDIETOmhNw=; b=Wpjxo3xJidh2RUuT9wbM/IEYu3+ykHek+vFNt/Gy4aGLdM7RV1Bm1QxU7YNtduhAmR r2XacjCZoPlb1nnyB6rsWnAKepnRk3WnpmIcmFzyklGLuezefXw4+s77FSue6PdTFPnh rj9rh/2cM/qi7yPTGxeYr6+cEXzYTZsj5PpknWNDg2tVb2I9IszKcQaatkgjLC4mrMDj v/e2ATV2cQV1/Q8OJ+gdXHcJ7b/gNG5dsCKoCJUaAgUd6rf1FIFHE03q5cC4kZslKTBI OdCzLRpJdDhwGFjtmJSxmkYyI1fPUkG7PSjtYxqLA/eDP8heNabVZ+oTQLjCfFg52vvw Q+8Q==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=l4IPgLdp; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4366127c515sm398879245e9.30.2024.12.31.11.06.41 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 31 Dec 2024 11:06:41 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Helge Deller , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v4 4/6] target/hppa: Only set PSW 'M' bit on reset Date: Tue, 31 Dec 2024 20:06:18 +0100 Message-ID: <20241231190620.24442-5-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241231190620.24442-1-philmd@linaro.org> References: <20241231190620.24442-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=philmd@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org On reset: "All PSW bits except the M bit is reset. The M bit is set." Commit 1a19da0da44 ("target/hppa: Fill in hppa_cpu_do_interrupt / hppa_cpu_exec_interrupt") inadvertently set the W bit at RESET, remove it and set the M bit. Signed-off-by: Philippe Mathieu-Daudé Acked-by: Helge Deller --- target/hppa/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 41538d39d62..dbd46842841 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -209,7 +209,7 @@ static void hppa_cpu_reset_hold(Object *obj, ResetType type) memset(env, 0, offsetof(CPUHPPAState, end_reset_fields)); cpu_hppa_loaded_fr0(env); - cpu_hppa_put_psw(env, PSW_W); + cpu_hppa_put_psw(env, PSW_M); } static ObjectClass *hppa_cpu_class_by_name(const char *cpu_model) From patchwork Tue Dec 31 19:06:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 854394 Delivered-To: patch@linaro.org Received: by 2002:a5d:4888:0:b0:385:e875:8a9e with SMTP id g8csp7064838wrq; Tue, 31 Dec 2024 11:07:31 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWxsSywe0e3Pg9p4//IN3l27sVLdzVVHoWcIlOgZ3spbK8A3lXaCRnYjb/0YxsgpEko+9VORQ==@linaro.org X-Google-Smtp-Source: AGHT+IFkwgiwWPpJsXG4Sx2dvOjmF89REVxfdBlbdOEv2xC/QWP1ZNKd67Xv0HpS1jnZi7hxgwpi X-Received: by 2002:ad4:5d69:0:b0:6d8:81cd:a0ce with SMTP id 6a1803df08f44-6dd233aab3amr670332856d6.43.1735672050706; Tue, 31 Dec 2024 11:07:30 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1735672050; cv=none; d=google.com; s=arc-20240605; b=kcvOinulyTI1voOPyAKpmgEjMN5IPx26wXCR6skhSBEwDi9BItmvzTZePRCqMHQ6CI 8PPb455zFhlASX91rpUJkDaCaBkepKU85MD7uF8V7PdDsNjOpAojCXG/BxIla5Swge3o g+pyYfVB+wppsMUknOxYHDr8gCmI4Zhg1DybOJf8VKqkh71mFTXYmwchU3dWdX8wMFN+ 9VEqIEbQsfbDupMiU4Oh1TAWiq7N2rJkxzONMoSo0cLSL/N1vlxBtq50yeuMrLiInWCe ar/npzY2tKTmqXCqA6bYFAZ+cG6fjOWvWkFx5eBHaYjmz78b/HH5cF+zc3BeaExWzYGr KUiQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=b7UfBZMFotuOZuG+02/D0eezoHBGpYOKCSHoS+es9Cw=; fh=Pu80oL6pqNVhcxmoTE7CG5kT5lPd7R2XHVDIETOmhNw=; b=dpjb9xyRNz2lKwU0+YF652eXM0uafETdoo+Jq+CEEPrt7iCESFpstCoDP120zU/yF3 cwrQq0bVcp6G3v9QtnXsG1EWweDmSdReSI6lb+ulip9ErrNF0cVuMliNUOrkwBp9F5/e yHa37U4AlfbUx68VpXa+jiOtNVGcGwvWM7D7aGu65XD+45xYLxSmv50We2ftK3KGTbp2 Ng2qboF4/zFHaQMermpNirumnbaBOq77Ulmu6kyUFbg8v7A8T1OmJJ+aTRVcpDN/NBPK C1s/ccaWbjiZwolzviw0OUSRmII5YV0CcAtQQf5R2XLdoXUQr2OMIWoGlgjuGScJhu9M dBbg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=J0TY4nxe; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43656b0145csm432054725e9.15.2024.12.31.11.06.45 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 31 Dec 2024 11:06:46 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Helge Deller , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v4 5/6] target/hppa: Set PC on vCPU reset Date: Tue, 31 Dec 2024 20:06:19 +0100 Message-ID: <20241231190620.24442-6-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241231190620.24442-1-philmd@linaro.org> References: <20241231190620.24442-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=philmd@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Helge Deller On reset: "The CPU begins fetching instructions from address 0xf0000004. This address is in PDC space." Switch vCPUs to 32-bit mode (PSW_W bit is not set) and start execution at address 0xf0000004. Signed-off-by: Helge Deller Co-developed-by: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé --- target/hppa/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index dbd46842841..7278b7ca6b5 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -205,6 +205,7 @@ static void hppa_cpu_reset_hold(Object *obj, ResetType type) } cs->exception_index = -1; cs->halted = 0; + cpu_set_pc(cs, 0xf0000004); memset(env, 0, offsetof(CPUHPPAState, end_reset_fields)); From patchwork Tue Dec 31 19:06:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 854398 Delivered-To: patch@linaro.org Received: by 2002:a5d:4888:0:b0:385:e875:8a9e with SMTP id g8csp7065029wrq; Tue, 31 Dec 2024 11:08:07 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWNwxRT6iPXQ4I91RgkdLTMeMtCZb2DqknzKEmoA9dG4TCciQJXTL0Hy2mc81cDh3cHP5dUTQ==@linaro.org X-Google-Smtp-Source: AGHT+IEpgTIHBfrF+Zz195mmtWJpGIhIZxmYahhg2mY1oU3F5jsOPOap03gPyBWBf6wnb9SE3ouj X-Received: by 2002:a05:6102:508d:b0:4af:e0d4:70df with SMTP id ada2fe7eead31-4b2cc49c342mr24542455137.27.1735672087512; Tue, 31 Dec 2024 11:08:07 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1735672087; cv=none; d=google.com; s=arc-20240605; b=hFBltNIbGptcF3UFqGs9ro5XPEcEqvyc99cMvZhOE2L8A6Mn2J9QGBDyQ6T26ZSpnI H9GNXoq2rDdEFg0n+OQ2Wg3YjO2s7TgDlTVpf10cUi/O4XMy3tuKT5J85oJwZ0F6Wpr/ CZaYQw9FT5o/wxDW4MQV5B9TZMv5QYAXlz6rNVb1nHHTRI8jPxgWM8mJwlExmVZAxKWk b+X4WjTKHsRbM2Q1xDd/k643pHBRkJ2UC8PayR0/rCwPgzAMJz3B19trhiskqnlx08Ay Z2B/ZMair9vrwJGdHZJD9BI0QpERE5+vXcMuBP8Ng4SxMveq5znAgJ8zScq+nIdhnKer TW5w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=LT79yJT21rJPtnu6Fd4xIWi2kLyEAZ71iOLyoGT2BAA=; fh=Pu80oL6pqNVhcxmoTE7CG5kT5lPd7R2XHVDIETOmhNw=; b=LW74zYShWI8QFkv14YS/J4N3Oi5EJuO/cAWsByU6Y6YCc0PywmamwjsrXZaQ0GfG1b aEPx4WMC01L0rNhFTeJNYuohd2kwot3JAt/Z85OttKohNasc2veDbepFfABk7Lyo00C9 MZhiwQMrT/Ug8ZjzIq9s44L1DBk7g9GDkMnK9ZK2OLPJigYwDlsuLKvTs4My6YVmHjKw CgjacdhWWzjkza5mb9z/7eQ3DflHW/mOO0eaBiDI5hnwXspE/bBfNHZqq/sxrcxun5OC 1FkVq9HGRxYvZ6PQG9yUmwG/8t6hiVWIjc06i9nGdrNfYlU9Rfh0J39+3kmN5Un81Ej4 SXBA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NfZFKMBM; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38a1c84722dsm33476906f8f.53.2024.12.31.11.06.50 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 31 Dec 2024 11:06:51 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Helge Deller , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v4 6/6] target/hppa: Speed up hppa_is_pa20() Date: Tue, 31 Dec 2024 20:06:20 +0100 Message-ID: <20241231190620.24442-7-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241231190620.24442-1-philmd@linaro.org> References: <20241231190620.24442-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=philmd@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Helge Deller Although the hppa_is_pa20() helper is costly due to string comparisons in object_dynamic_cast(), it is called quite often during memory lookups and at each start of a block of instruction translations. Speed hppa_is_pa20() up by calling object_dynamic_cast() only once at CPU creation and store the result in the is_pa20 of struct CPUArchState. Signed-off-by: Helge Deller Co-developed-by: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé --- target/hppa/cpu.h | 6 ++++-- target/hppa/cpu.c | 8 ++++++++ 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index c1d69c1a835..083d4f5a56a 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -266,6 +266,8 @@ typedef struct CPUArchState { /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; + + bool is_pa20; } CPUHPPAState; /** @@ -297,9 +299,9 @@ struct HPPACPUClass { #include "exec/cpu-all.h" -static inline bool hppa_is_pa20(CPUHPPAState *env) +static inline bool hppa_is_pa20(const CPUHPPAState *env) { - return object_dynamic_cast(OBJECT(env_cpu(env)), TYPE_HPPA64_CPU) != NULL; + return env->is_pa20; } static inline int HPPA_BTLB_ENTRIES(CPUHPPAState *env) diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 7278b7ca6b5..b0bc9d35e4c 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -193,6 +193,13 @@ static void hppa_cpu_realizefn(DeviceState *dev, Error **errp) tcg_cflags_set(cs, CF_PCREL); } +static void hppa_cpu_initfn(Object *obj) +{ + CPUHPPAState *env = cpu_env(CPU(obj)); + + env->is_pa20 = !!object_dynamic_cast(obj, TYPE_HPPA64_CPU); +} + static void hppa_cpu_reset_hold(Object *obj, ResetType type) { HPPACPUClass *scc = HPPA_CPU_GET_CLASS(obj); @@ -282,6 +289,7 @@ static const TypeInfo hppa_cpu_type_infos[] = { .parent = TYPE_CPU, .instance_size = sizeof(HPPACPU), .instance_align = __alignof(HPPACPU), + .instance_init = hppa_cpu_initfn, .abstract = false, .class_size = sizeof(HPPACPUClass), .class_init = hppa_cpu_class_init,