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[82.243.161.21]) by smtp.googlemail.com with ESMTPSA id 4sm2883231wmg.22.2019.12.18.09.24.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Dec 2019 09:24:26 -0800 (PST) From: Jerome Brunet To: Mark Brown , Liam Girdwood Cc: Jerome Brunet , alsa-devel@alsa-project.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org, Kevin Hilman , Alden DSouza Subject: [PATCH 1/4] ASoC: meson: axg-fifo: fix fifo threshold setup Date: Wed, 18 Dec 2019 18:24:17 +0100 Message-Id: <20191218172420.1199117-2-jbrunet@baylibre.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191218172420.1199117-1-jbrunet@baylibre.com> References: <20191218172420.1199117-1-jbrunet@baylibre.com> MIME-Version: 1.0 X-Patchwork-Bot: notify Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On TODDR sm1, the fifo threshold register field is slightly different compared to the other SoCs. This leads to the fifo A being flushed to memory every 8kB. If the period is smaller than that, several periods are pushed to memory and notified at once. This is not ideal. Fix the register field update. With this, the fifos are flushed every 128B. We could still do better, like adapt the threshold depending on the period size, but at least it consistent across the different SoC/fifos Fixes: 5ac825c3d85e ("ASoC: meson: axg-toddr: add sm1 support") Reported-by: Alden DSouza Signed-off-by: Jerome Brunet --- sound/soc/meson/axg-fifo.c | 27 +++++++++++++++++++++++++-- sound/soc/meson/axg-fifo.h | 6 ++++-- sound/soc/meson/axg-frddr.c | 24 ++++++++++++------------ sound/soc/meson/axg-toddr.c | 21 +++++++++------------ 4 files changed, 50 insertions(+), 28 deletions(-) -- 2.23.0 diff --git a/sound/soc/meson/axg-fifo.c b/sound/soc/meson/axg-fifo.c index 772eda857019..4365086c9a31 100644 --- a/sound/soc/meson/axg-fifo.c +++ b/sound/soc/meson/axg-fifo.c @@ -113,8 +113,10 @@ int axg_fifo_pcm_hw_params(struct snd_soc_component *component, { struct snd_pcm_runtime *runtime = ss->runtime; struct axg_fifo *fifo = axg_fifo_data(ss); + unsigned int burst_num, period, threshold; dma_addr_t end_ptr; - unsigned int burst_num; + + period = params_period_bytes(params); /* Setup dma memory pointers */ end_ptr = runtime->dma_addr + runtime->dma_bytes - AXG_FIFO_BURST; @@ -122,9 +124,25 @@ int axg_fifo_pcm_hw_params(struct snd_soc_component *component, regmap_write(fifo->map, FIFO_FINISH_ADDR, end_ptr); /* Setup interrupt periodicity */ - burst_num = params_period_bytes(params) / AXG_FIFO_BURST; + burst_num = period / AXG_FIFO_BURST; regmap_write(fifo->map, FIFO_INT_ADDR, burst_num); + /* + * Start the fifo request on the smallest of the following: + * - Half the fifo size + * - Half the period size + */ + threshold = min(period / 2, + (unsigned int)AXG_FIFO_MIN_DEPTH / 2); + + /* + * With the threshold in bytes, register value is: + * V = (threshold / burst) - 1 + */ + threshold /= AXG_FIFO_BURST; + regmap_field_write(fifo->field_threshold, + threshold ? threshold - 1 : 0); + /* Enable block count irq */ regmap_update_bits(fifo->map, FIFO_CTRL0, CTRL0_INT_EN(FIFO_INT_COUNT_REPEAT), @@ -347,6 +365,11 @@ int axg_fifo_probe(struct platform_device *pdev) return fifo->irq; } + fifo->field_threshold = + devm_regmap_field_alloc(dev, fifo->map, data->field_threshold); + if (IS_ERR(fifo->field_threshold)) + return PTR_ERR(fifo->field_threshold); + return devm_snd_soc_register_component(dev, data->component_drv, data->dai_drv, 1); } diff --git a/sound/soc/meson/axg-fifo.h b/sound/soc/meson/axg-fifo.h index cf928d43b558..c442195ba191 100644 --- a/sound/soc/meson/axg-fifo.h +++ b/sound/soc/meson/axg-fifo.h @@ -9,7 +9,9 @@ struct clk; struct platform_device; +struct reg_field; struct regmap; +struct regmap_field; struct reset_control; struct snd_soc_component_driver; @@ -50,8 +52,6 @@ struct snd_soc_pcm_runtime; #define CTRL1_STATUS2_SEL_MASK GENMASK(11, 8) #define CTRL1_STATUS2_SEL(x) ((x) << 8) #define STATUS2_SEL_DDR_READ 0 -#define CTRL1_THRESHOLD_MASK GENMASK(23, 16) -#define CTRL1_THRESHOLD(x) ((x) << 16) #define CTRL1_FRDDR_DEPTH_MASK GENMASK(31, 24) #define CTRL1_FRDDR_DEPTH(x) ((x) << 24) #define FIFO_START_ADDR 0x08 @@ -67,12 +67,14 @@ struct axg_fifo { struct regmap *map; struct clk *pclk; struct reset_control *arb; + struct regmap_field *field_threshold; int irq; }; struct axg_fifo_match_data { const struct snd_soc_component_driver *component_drv; struct snd_soc_dai_driver *dai_drv; + struct reg_field field_threshold; }; int axg_fifo_pcm_open(struct snd_soc_component *component, diff --git a/sound/soc/meson/axg-frddr.c b/sound/soc/meson/axg-frddr.c index 0a7d41257a38..df104303351f 100644 --- a/sound/soc/meson/axg-frddr.c +++ b/sound/soc/meson/axg-frddr.c @@ -50,7 +50,7 @@ static int axg_frddr_dai_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) { struct axg_fifo *fifo = snd_soc_dai_get_drvdata(dai); - unsigned int fifo_depth, fifo_threshold; + unsigned int fifo_depth; int ret; /* Enable pclk to access registers and clock the fifo ip */ @@ -68,11 +68,8 @@ static int axg_frddr_dai_startup(struct snd_pcm_substream *substream, * Depth and threshold are zero based. */ fifo_depth = AXG_FIFO_MIN_CNT - 1; - fifo_threshold = (AXG_FIFO_MIN_CNT / 2) - 1; - regmap_update_bits(fifo->map, FIFO_CTRL1, - CTRL1_FRDDR_DEPTH_MASK | CTRL1_THRESHOLD_MASK, - CTRL1_FRDDR_DEPTH(fifo_depth) | - CTRL1_THRESHOLD(fifo_threshold)); + regmap_update_bits(fifo->map, FIFO_CTRL1, CTRL1_FRDDR_DEPTH_MASK, + CTRL1_FRDDR_DEPTH(fifo_depth)); return 0; } @@ -158,8 +155,9 @@ static const struct snd_soc_component_driver axg_frddr_component_drv = { }; static const struct axg_fifo_match_data axg_frddr_match_data = { - .component_drv = &axg_frddr_component_drv, - .dai_drv = &axg_frddr_dai_drv + .field_threshold = REG_FIELD(FIFO_CTRL1, 16, 23), + .component_drv = &axg_frddr_component_drv, + .dai_drv = &axg_frddr_dai_drv }; static const struct snd_soc_dai_ops g12a_frddr_ops = { @@ -281,8 +279,9 @@ static const struct snd_soc_component_driver g12a_frddr_component_drv = { }; static const struct axg_fifo_match_data g12a_frddr_match_data = { - .component_drv = &g12a_frddr_component_drv, - .dai_drv = &g12a_frddr_dai_drv + .field_threshold = REG_FIELD(FIFO_CTRL1, 16, 23), + .component_drv = &g12a_frddr_component_drv, + .dai_drv = &g12a_frddr_dai_drv }; /* On SM1, the output selection in on CTRL2 */ @@ -350,8 +349,9 @@ static const struct snd_soc_component_driver sm1_frddr_component_drv = { }; static const struct axg_fifo_match_data sm1_frddr_match_data = { - .component_drv = &sm1_frddr_component_drv, - .dai_drv = &g12a_frddr_dai_drv + .field_threshold = REG_FIELD(FIFO_CTRL1, 16, 23), + .component_drv = &sm1_frddr_component_drv, + .dai_drv = &g12a_frddr_dai_drv }; static const struct of_device_id axg_frddr_of_match[] = { diff --git a/sound/soc/meson/axg-toddr.c b/sound/soc/meson/axg-toddr.c index f6023397c8fe..e711abcf8c12 100644 --- a/sound/soc/meson/axg-toddr.c +++ b/sound/soc/meson/axg-toddr.c @@ -89,7 +89,6 @@ static int axg_toddr_dai_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) { struct axg_fifo *fifo = snd_soc_dai_get_drvdata(dai); - unsigned int fifo_threshold; int ret; /* Enable pclk to access registers and clock the fifo ip */ @@ -107,11 +106,6 @@ static int axg_toddr_dai_startup(struct snd_pcm_substream *substream, /* Apply single buffer mode to the interface */ regmap_update_bits(fifo->map, FIFO_CTRL0, CTRL0_TODDR_PP_MODE, 0); - /* TODDR does not have a configurable fifo depth */ - fifo_threshold = AXG_FIFO_MIN_CNT - 1; - regmap_update_bits(fifo->map, FIFO_CTRL1, CTRL1_THRESHOLD_MASK, - CTRL1_THRESHOLD(fifo_threshold)); - return 0; } @@ -190,8 +184,9 @@ static const struct snd_soc_component_driver axg_toddr_component_drv = { }; static const struct axg_fifo_match_data axg_toddr_match_data = { - .component_drv = &axg_toddr_component_drv, - .dai_drv = &axg_toddr_dai_drv + .field_threshold = REG_FIELD(FIFO_CTRL1, 16, 23), + .component_drv = &axg_toddr_component_drv, + .dai_drv = &axg_toddr_dai_drv }; static const struct snd_soc_dai_ops g12a_toddr_ops = { @@ -228,8 +223,9 @@ static const struct snd_soc_component_driver g12a_toddr_component_drv = { }; static const struct axg_fifo_match_data g12a_toddr_match_data = { - .component_drv = &g12a_toddr_component_drv, - .dai_drv = &g12a_toddr_dai_drv + .field_threshold = REG_FIELD(FIFO_CTRL1, 16, 23), + .component_drv = &g12a_toddr_component_drv, + .dai_drv = &g12a_toddr_dai_drv }; static const char * const sm1_toddr_sel_texts[] = { @@ -297,8 +293,9 @@ static const struct snd_soc_component_driver sm1_toddr_component_drv = { }; static const struct axg_fifo_match_data sm1_toddr_match_data = { - .component_drv = &sm1_toddr_component_drv, - .dai_drv = &g12a_toddr_dai_drv + .field_threshold = REG_FIELD(FIFO_CTRL1, 12, 23), + .component_drv = &sm1_toddr_component_drv, + .dai_drv = &g12a_toddr_dai_drv }; static const struct of_device_id axg_toddr_of_match[] = { From patchwork Wed Dec 18 17:24:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 182018 Delivered-To: patch@linaro.org Received: by 2002:a92:3001:0:0:0:0:0 with SMTP id x1csp946851ile; Wed, 18 Dec 2019 09:24:34 -0800 (PST) X-Google-Smtp-Source: APXvYqxr5fEs/LlSfEh8jlTh1g4FfQqt5ezmyHM026yOk82zim/ny5MtpyC4vXWkcvoCiKULwo+z X-Received: by 2002:aca:1e13:: with SMTP id m19mr1076053oic.175.1576689874394; Wed, 18 Dec 2019 09:24:34 -0800 (PST) ARC-Seal: i=1; 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[82.243.161.21]) by smtp.googlemail.com with ESMTPSA id 4sm2883231wmg.22.2019.12.18.09.24.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Dec 2019 09:24:28 -0800 (PST) From: Jerome Brunet To: Mark Brown , Liam Girdwood Cc: Jerome Brunet , alsa-devel@alsa-project.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org, Kevin Hilman Subject: [PATCH 2/4] ASoC: meson: axg-fifo: add fifo depth to the bindings documentation Date: Wed, 18 Dec 2019 18:24:18 +0100 Message-Id: <20191218172420.1199117-3-jbrunet@baylibre.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191218172420.1199117-1-jbrunet@baylibre.com> References: <20191218172420.1199117-1-jbrunet@baylibre.com> MIME-Version: 1.0 X-Patchwork-Bot: notify Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add a new property with the depth of the fifo in bytes. This is useful since some instance of the fifo, even on the same SoC, may have different depth. The depth is useful is set some parameters of the fifo. Signed-off-by: Jerome Brunet --- Documentation/devicetree/bindings/sound/amlogic,axg-fifo.txt | 4 ++++ 1 file changed, 4 insertions(+) -- 2.23.0 diff --git a/Documentation/devicetree/bindings/sound/amlogic,axg-fifo.txt b/Documentation/devicetree/bindings/sound/amlogic,axg-fifo.txt index 3080979350a0..fa4545ed81ca 100644 --- a/Documentation/devicetree/bindings/sound/amlogic,axg-fifo.txt +++ b/Documentation/devicetree/bindings/sound/amlogic,axg-fifo.txt @@ -17,6 +17,9 @@ Required properties: * "arb" : memory ARB line (required) * "rst" : dedicated device reset line (optional) - #sound-dai-cells: must be 0. +- amlogic,fifo-depth: The size of the controller's fifo in bytes. This + is useful for determining certain configuration such + as the flush threshold of the fifo Example of FRDDR A on the A113 SoC: @@ -27,4 +30,5 @@ frddr_a: audio-controller@1c0 { interrupts = ; clocks = <&clkc_audio AUD_CLKID_FRDDR_A>; resets = <&arb AXG_ARB_FRDDR_A>; + fifo-depth = <512>; }; From patchwork Wed Dec 18 17:24:19 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 182020 Delivered-To: patch@linaro.org Received: by 2002:a92:3001:0:0:0:0:0 with SMTP id x1csp947036ile; Wed, 18 Dec 2019 09:24:42 -0800 (PST) X-Google-Smtp-Source: APXvYqzWWv3bsaqvsC4SWEqJSUEsAcbw9q5UkkUP6Vd6/NfqRrWgOn9mt2FnPnTVNhaePr93IXo7 X-Received: by 2002:a05:6830:300d:: with SMTP id a13mr3650383otn.182.1576689882727; Wed, 18 Dec 2019 09:24:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1576689882; cv=none; d=google.com; s=arc-20160816; b=fVlM+I0NHt7xplg2SAMlyGkfQOHc0ZtEsf3MRaAQtXGa8wKPrvt/AikyG+NXfeq65y 9zMsDEbzLotWmowrav/9/EUDgziFi27xKnutYT6QfvHS1vhRsnL+RmaUtsez/tiA1qLf IimcwsGi8Eq4uYQ9mLCEqWZESuydaBhExJ4X40aHxOp9FBqxn9a3bhQhiE4aI7zC1Aor dmmeBfCBJhZ0tOsus4qJHBzcPcHhK2gPJKTyHloD6qlLkAKD8HcHikABW5T5miDanfyF 0Pi/4/D7USacI1rh11gKh4FICzRtOM2cAg/Omm8jJh4zSrjEI9r+S9gHeK7uL1LORSfU 5lsA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=nI3wHpadQrFAs/JfgdrJy2gaVNas6wWVbz5bBhEZKws=; b=u+f15c6+K48Pg5G/aLHfDkfJ/k3S6B4xzhfPewFpJPdC9A2u3KMwE2bWY2c88gbkdg bfbTCcw5zD5GyP/DDY5JO0TfyPz+HlZ79yJ26VDsGHyfJ3OvR6Cr4oMOrhzhxHYSv0pZ 6+zExmzdkA7PCxi/eQcObFCbMWtBNQjfuuTiqwL1l1N6Ffcw2nt3M+HnsxpMn0AMLDzF 8GRdTrIIZUeVbxLNWx+s95wSgj8eeTXhIODBcn2aUGdKEUitLBnDCOHj+0Zz3fpSXAbI Q2fgCkhqfa0OUqt3AVL/lHNNDxbPqSDHZ4C4beY4e8TJ6ec3Qvhs9ot6YmWgrsXE+rRQ 3lXQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=bbqrbWIy; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[82.243.161.21]) by smtp.googlemail.com with ESMTPSA id 4sm2883231wmg.22.2019.12.18.09.24.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Dec 2019 09:24:30 -0800 (PST) From: Jerome Brunet To: Mark Brown , Liam Girdwood Cc: Jerome Brunet , alsa-devel@alsa-project.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org, Kevin Hilman Subject: [PATCH 3/4] ASoC: meson: axg-fifo: improve depth handling Date: Wed, 18 Dec 2019 18:24:19 +0100 Message-Id: <20191218172420.1199117-4-jbrunet@baylibre.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191218172420.1199117-1-jbrunet@baylibre.com> References: <20191218172420.1199117-1-jbrunet@baylibre.com> MIME-Version: 1.0 X-Patchwork-Bot: notify Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Let the fifo driver parse the fifo depth from DT. Eventually all DT should have this property. Until it is actually the case, default to 256 bytes if the property is missing. 256 bytes is the size of the smallest fifo on the supported SoCs. On the supported SoC, fifo A is usually bigger than the other ones. With depth known, we can improve the usage of the fifo and adapt the setup of request threshold. Signed-off-by: Jerome Brunet --- sound/soc/meson/axg-fifo.c | 19 +++++++++++++++++-- sound/soc/meson/axg-fifo.h | 1 + sound/soc/meson/axg-frddr.c | 13 ++++--------- 3 files changed, 22 insertions(+), 11 deletions(-) -- 2.23.0 diff --git a/sound/soc/meson/axg-fifo.c b/sound/soc/meson/axg-fifo.c index 4365086c9a31..c2742a02d866 100644 --- a/sound/soc/meson/axg-fifo.c +++ b/sound/soc/meson/axg-fifo.c @@ -132,8 +132,7 @@ int axg_fifo_pcm_hw_params(struct snd_soc_component *component, * - Half the fifo size * - Half the period size */ - threshold = min(period / 2, - (unsigned int)AXG_FIFO_MIN_DEPTH / 2); + threshold = min(period / 2, fifo->depth / 2); /* * With the threshold in bytes, register value is: @@ -320,6 +319,7 @@ int axg_fifo_probe(struct platform_device *pdev) const struct axg_fifo_match_data *data; struct axg_fifo *fifo; void __iomem *regs; + int ret; data = of_device_get_match_data(dev); if (!data) { @@ -370,6 +370,21 @@ int axg_fifo_probe(struct platform_device *pdev) if (IS_ERR(fifo->field_threshold)) return PTR_ERR(fifo->field_threshold); + ret = of_property_read_u32(dev->of_node, "amlogic,fifo-depth", + &fifo->depth); + if (ret) { + /* Error out for anything but a missing property */ + if (ret != -EINVAL) + return ret; + /* + * If the property is missing, it might be because of an old + * DT. In such case, assume the smallest known fifo depth + */ + fifo->depth = 256; + dev_warn(dev, "fifo depth not found, assume %u bytes\n", + fifo->depth); + } + return devm_snd_soc_register_component(dev, data->component_drv, data->dai_drv, 1); } diff --git a/sound/soc/meson/axg-fifo.h b/sound/soc/meson/axg-fifo.h index c442195ba191..521b54e98fd3 100644 --- a/sound/soc/meson/axg-fifo.h +++ b/sound/soc/meson/axg-fifo.h @@ -68,6 +68,7 @@ struct axg_fifo { struct clk *pclk; struct reset_control *arb; struct regmap_field *field_threshold; + unsigned int depth; int irq; }; diff --git a/sound/soc/meson/axg-frddr.c b/sound/soc/meson/axg-frddr.c index df104303351f..c3ae8ac30745 100644 --- a/sound/soc/meson/axg-frddr.c +++ b/sound/soc/meson/axg-frddr.c @@ -50,7 +50,7 @@ static int axg_frddr_dai_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) { struct axg_fifo *fifo = snd_soc_dai_get_drvdata(dai); - unsigned int fifo_depth; + unsigned int val; int ret; /* Enable pclk to access registers and clock the fifo ip */ @@ -61,15 +61,10 @@ static int axg_frddr_dai_startup(struct snd_pcm_substream *substream, /* Apply single buffer mode to the interface */ regmap_update_bits(fifo->map, FIFO_CTRL0, CTRL0_FRDDR_PP_MODE, 0); - /* - * TODO: We could adapt the fifo depth and the fifo threshold - * depending on the expected memory throughput and lantencies - * For now, we'll just use the same values as the vendor kernel - * Depth and threshold are zero based. - */ - fifo_depth = AXG_FIFO_MIN_CNT - 1; + /* Use all fifo depth */ + val = (fifo->depth / AXG_FIFO_BURST) - 1; regmap_update_bits(fifo->map, FIFO_CTRL1, CTRL1_FRDDR_DEPTH_MASK, - CTRL1_FRDDR_DEPTH(fifo_depth)); + CTRL1_FRDDR_DEPTH(val)); return 0; }