From patchwork Fri Dec 27 11:07:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Parthiban Nallathambi X-Patchwork-Id: 853888 Received: from omta38.uswest2.a.cloudfilter.net (omta38.uswest2.a.cloudfilter.net [35.89.44.37]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CD52B1F192B for ; Fri, 27 Dec 2024 11:08:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=35.89.44.37 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735297708; cv=none; b=EZ60FP+/0CwujgbKwdl5K5rKvZ5FlPw1oXc1huK2FV43v+V9pGN7l/AcBGIyuF1GNUgL4yZHKEHtLEbwN46bkPOKplmJTxmQGr2tHyTcjF1uKVfaub2Ls67Mf1/815wgovof/+qWRFsAKqRJhtxVdM/Ujp7Inp6buYdA2enxErA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735297708; c=relaxed/simple; bh=qHYIlw5q2Ro5I852QrjEef3P3GktuZk2GSnSTYiauwE=; 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Signed-off-by: Parthiban Nallathambi --- Documentation/devicetree/bindings/iommu/allwinner,sun50i-h6-iommu.yaml | 1 - 1 file changed, 1 deletion(-) diff --git a/Documentation/devicetree/bindings/iommu/allwinner,sun50i-h6-iommu.yaml b/Documentation/devicetree/bindings/iommu/allwinner,sun50i-h6-iommu.yaml index a8409db4a3e3..03176f68485b 100644 --- a/Documentation/devicetree/bindings/iommu/allwinner,sun50i-h6-iommu.yaml +++ b/Documentation/devicetree/bindings/iommu/allwinner,sun50i-h6-iommu.yaml @@ -42,7 +42,6 @@ required: - reg - interrupts - clocks - - resets additionalProperties: false From patchwork Fri Dec 27 11:07:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Parthiban Nallathambi X-Patchwork-Id: 853887 Received: from omta40.uswest2.a.cloudfilter.net (omta40.uswest2.a.cloudfilter.net [35.89.44.39]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BE1AF1F2387 for ; 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Mixer can be used with lcd/lvds/dsi, but shares the same GPIO bank. Signed-off-by: Parthiban Nallathambi --- .../display/allwinner,sun4i-a10-display-engine.yaml | 2 ++ .../display/allwinner,sun8i-a83t-de2-mixer.yaml | 1 + .../bindings/display/allwinner,sun8i-r40-tcon-top.yaml | 17 +++++++++++++++++ 3 files changed, 20 insertions(+) diff --git a/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-display-engine.yaml b/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-display-engine.yaml index e6088f379f70..dc47c684fcb0 100644 --- a/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-display-engine.yaml +++ b/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-display-engine.yaml @@ -64,6 +64,7 @@ properties: - allwinner,sun9i-a80-display-engine - allwinner,sun20i-d1-display-engine - allwinner,sun50i-a64-display-engine + - allwinner,sun50i-a100-display-engine - allwinner,sun50i-h6-display-engine allwinner,pipelines: @@ -96,6 +97,7 @@ if: - allwinner,sun9i-a80-display-engine - allwinner,sun20i-d1-display-engine - allwinner,sun50i-a64-display-engine + - allwinner,sun50i-a100-display-engine then: properties: diff --git a/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-de2-mixer.yaml b/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-de2-mixer.yaml index b75c1ec686ad..ebcddca2efb3 100644 --- a/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-de2-mixer.yaml +++ b/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-de2-mixer.yaml @@ -23,6 +23,7 @@ properties: - allwinner,sun20i-d1-de2-mixer-1 - allwinner,sun50i-a64-de2-mixer-0 - allwinner,sun50i-a64-de2-mixer-1 + - allwinner,sun50i-a100-de2-mixer-0 - allwinner,sun50i-h6-de3-mixer-0 reg: diff --git a/Documentation/devicetree/bindings/display/allwinner,sun8i-r40-tcon-top.yaml b/Documentation/devicetree/bindings/display/allwinner,sun8i-r40-tcon-top.yaml index 7d849c4095a3..9b14b7fb2d2f 100644 --- a/Documentation/devicetree/bindings/display/allwinner,sun8i-r40-tcon-top.yaml +++ b/Documentation/devicetree/bindings/display/allwinner,sun8i-r40-tcon-top.yaml @@ -42,6 +42,7 @@ properties: enum: - allwinner,sun8i-r40-tcon-top - allwinner,sun20i-d1-tcon-top + - allwinner,sun50i-a100-tcon-top - allwinner,sun50i-h6-tcon-top reg: @@ -179,6 +180,22 @@ allOf: - description: TCON TV0 output clock name - description: DSI output clock name + - if: + properties: + compatible: + contains: + const: allwinner,sun50i-a100-tcon-top + + then: + properties: + clocks: + items: + - description: The TCON TOP interface clock + + clock-names: + items: + - const: bus + - if: properties: compatible: From patchwork Fri Dec 27 11:07:51 2024 Content-Type: text/plain; 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Add it with fallback to v3s compatible. Signed-off-by: Parthiban Nallathambi --- .../devicetree/bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml index 3e00905b66ca..ed038967929b 100644 --- a/Documentation/devicetree/bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml +++ b/Documentation/devicetree/bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml @@ -23,6 +23,7 @@ properties: - const: allwinner,sun8i-h3-de2-clk - const: allwinner,sun8i-v3s-de2-clk - const: allwinner,sun50i-a64-de2-clk + - const: allwinner,sun50i-a100-de2-clk - const: allwinner,sun50i-h5-de2-clk - const: allwinner,sun50i-h6-de3-clk - items: @@ -31,6 +32,9 @@ properties: - items: - const: allwinner,sun20i-d1-de2-clk - const: allwinner,sun50i-h5-de2-clk + - items: + - const: allwinner,sun50i-a100-de2-clk + - const: allwinner,sun8i-v3s-de2-clk reg: maxItems: 1 From patchwork Fri Dec 27 11:07:53 2024 Content-Type: text/plain; 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All the controller shares the same GPIO D block, where LVDS controller can co-exits. Although 2 LVDS controller is available, there is no document details for the second. Add compatible for a100 lcd controller. Signed-off-by: Parthiban Nallathambi --- Documentation/devicetree/bindings/display/allwinner,sun4i-a10-tcon.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-tcon.yaml b/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-tcon.yaml index 6d8ae781c230..7ea45a0a2073 100644 --- a/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-tcon.yaml +++ b/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-tcon.yaml @@ -35,6 +35,7 @@ properties: - const: allwinner,sun9i-a80-tcon-tv - const: allwinner,sun20i-d1-tcon-lcd - const: allwinner,sun20i-d1-tcon-tv + - const: allwinner,sun50i-a100-tcon-lcd - items: - enum: From patchwork Fri Dec 27 11:07:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Parthiban Nallathambi X-Patchwork-Id: 853880 Received: from omta036.useast.a.cloudfilter.net (omta036.useast.a.cloudfilter.net [44.202.169.35]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1EF921F238A for ; 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Add its compatible (with the SoM compatible) to the sunxi board DT binding file. Signed-off-by: Parthiban Nallathambi --- Documentation/devicetree/bindings/arm/sunxi.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml index 046536d02706..eb19f8b1fe68 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -891,6 +891,12 @@ properties: - const: allwinner,sl631 - const: allwinner,sun8i-v3 + - description: Szbaijie A133 Helper board + items: + - const: szbaijie,helper-a133 + - const: szbaijie,helper-a133-core + - const: allwinner,sun50i-a133 + - description: Tanix TX1 items: - const: oranth,tanix-tx1 From patchwork Fri Dec 27 11:07:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Parthiban Nallathambi X-Patchwork-Id: 853884 Received: from omta36.uswest2.a.cloudfilter.net (omta36.uswest2.a.cloudfilter.net [35.89.44.35]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 675FE1F3D34 for ; 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Get reset control line optionally. Signed-off-by: Parthiban Nallathambi --- drivers/iommu/sun50i-iommu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iommu/sun50i-iommu.c b/drivers/iommu/sun50i-iommu.c index 8d8f11854676..2ba804d682dc 100644 --- a/drivers/iommu/sun50i-iommu.c +++ b/drivers/iommu/sun50i-iommu.c @@ -1030,7 +1030,7 @@ static int sun50i_iommu_probe(struct platform_device *pdev) goto err_free_cache; } - iommu->reset = devm_reset_control_get(&pdev->dev, NULL); + iommu->reset = devm_reset_control_get_optional(&pdev->dev, NULL); if (IS_ERR(iommu->reset)) { dev_err(&pdev->dev, "Couldn't get our reset line.\n"); ret = PTR_ERR(iommu->reset); From patchwork Fri Dec 27 11:07:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Parthiban Nallathambi X-Patchwork-Id: 853883 Received: from omta040.useast.a.cloudfilter.net (omta040.useast.a.cloudfilter.net [44.202.169.39]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 34A4F1F4263 for ; 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a=ed25519-sha256; t=1735297689; l=915; i=parthiban@linumiz.com; s=20241125; h=from:subject:message-id; bh=OF2xEirt2I4TWCuMHqY/Rfu3fQsoGOZ+4waicM8FC9g=; b=fGp7v4SGTK0k7oY1nfO7iOPyXtT+W0sH/qCeqn4yRfELAjBZ2AytoCH4bQp52XB14uVa69J0o aCEINdrh3p7DQ9sPMwGkrEx6YufICcsAuyqeNObKpd1Q/R9jiYnQtO1 X-Developer-Key: i=parthiban@linumiz.com; a=ed25519; pk=PrcMZ/nwnHbeXNFUFUS833wF3DAX4hziDHEbBp1eNb8= X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - md-in-79.webhostbox.net X-AntiAbuse: Original Domain - vger.kernel.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - linumiz.com X-BWhitelist: no X-Source-IP: 122.165.245.213 X-Source-L: No X-Exim-ID: 1tR8DP-000bEK-2q X-Source: X-Source-Args: X-Source-Dir: X-Source-Sender: ([127.0.1.1]) [122.165.245.213]:50828 X-Source-Auth: parthiban@linumiz.com X-Email-Count: 341 X-Org: HG=dishared_whb_net_legacy;ORG=directi; X-Source-Cap: bGludW1jbWM7aG9zdGdhdG9yO21kLWluLTc5LndlYmhvc3Rib3gubmV0 X-Local-Domain: yes X-CMAE-Envelope: MS4xfKI17lpsz1GTvPSpBN0rtVR/8M/tpGeMWTbSh3Lx+t7So7OQ2puo47NUx/vdJW6x2YiDIhgnPfbRCH2h04/GLcCFIRCIT7B1IXieLiPkjVGxtG30fyAr aGjMoMntA4paIHqhLo/UY8IxUO9InWaicQ8fu0Kj5dvJFC7JaquJPfmlJBHiosg/RcUNHPaHOqqqRoXL5r/4YkjpiBXVVjDLI/M= Display Engine(DE2) in Allwinner A100/A133 has one mixers and tcon. The routing for mixer0 is through tcon0 and connected to LVDS/RGB/MIPI-DSI controller. Signed-off-by: Parthiban Nallathambi --- drivers/gpu/drm/sun4i/sun4i_drv.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c b/drivers/gpu/drm/sun4i/sun4i_drv.c index 5eccf58f2e17..e012a6316bba 100644 --- a/drivers/gpu/drm/sun4i/sun4i_drv.c +++ b/drivers/gpu/drm/sun4i/sun4i_drv.c @@ -436,6 +436,7 @@ static const struct of_device_id sun4i_drv_of_table[] = { { .compatible = "allwinner,sun9i-a80-display-engine" }, { .compatible = "allwinner,sun20i-d1-display-engine" }, { .compatible = "allwinner,sun50i-a64-display-engine" }, + { .compatible = "allwinner,sun50i-a100-display-engine" }, { .compatible = "allwinner,sun50i-h6-display-engine" }, { } }; From patchwork Fri Dec 27 11:08:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Parthiban Nallathambi X-Patchwork-Id: 853882 Received: from omta38.uswest2.a.cloudfilter.net (omta38.uswest2.a.cloudfilter.net [35.89.44.37]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CA3791F2381 for ; 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Make tv0 optional by introducing another control similar to tv1 and make existing users with true/present. Signed-off-by: Parthiban Nallathambi --- drivers/gpu/drm/sun4i/sun8i_tcon_top.c | 34 ++++++++++++++++++++-------------- 1 file changed, 20 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/sun4i/sun8i_tcon_top.c b/drivers/gpu/drm/sun4i/sun8i_tcon_top.c index 8adda578c51b..bd9d0840ead7 100644 --- a/drivers/gpu/drm/sun4i/sun8i_tcon_top.c +++ b/drivers/gpu/drm/sun4i/sun8i_tcon_top.c @@ -16,6 +16,7 @@ #include "sun8i_tcon_top.h" struct sun8i_tcon_top_quirks { + bool has_tcon_tv0; bool has_tcon_tv1; bool has_dsi; }; @@ -191,10 +192,11 @@ static int sun8i_tcon_top_bind(struct device *dev, struct device *master, * to TVE clock parent. */ i = 0; - clk_data->hws[CLK_TCON_TOP_TV0] = - sun8i_tcon_top_register_gate(dev, "tcon-tv0", regs, - &tcon_top->reg_lock, - TCON_TOP_TCON_TV0_GATE, i++); + if (quirks->has_tcon_tv0) + clk_data->hws[CLK_TCON_TOP_TV0] = + sun8i_tcon_top_register_gate(dev, "tcon-tv0", regs, + &tcon_top->reg_lock, + TCON_TOP_TCON_TV0_GATE, i++); if (quirks->has_tcon_tv1) clk_data->hws[CLK_TCON_TOP_TV1] = @@ -208,16 +210,18 @@ static int sun8i_tcon_top_bind(struct device *dev, struct device *master, &tcon_top->reg_lock, TCON_TOP_TCON_DSI_GATE, i++); - for (i = 0; i < CLK_NUM; i++) - if (IS_ERR(clk_data->hws[i])) { - ret = PTR_ERR(clk_data->hws[i]); - goto err_unregister_gates; - } + if (i) { + for (i = 0; i < CLK_NUM; i++) + if (IS_ERR(clk_data->hws[i])) { + ret = PTR_ERR(clk_data->hws[i]); + goto err_unregister_gates; + } - ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get, - clk_data); - if (ret) - goto err_unregister_gates; + ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get, + clk_data); + if (ret) + goto err_unregister_gates; + } dev_set_drvdata(dev, tcon_top); @@ -266,16 +270,18 @@ static void sun8i_tcon_top_remove(struct platform_device *pdev) } static const struct sun8i_tcon_top_quirks sun8i_r40_tcon_top_quirks = { + .has_tcon_tv0 = true, .has_tcon_tv1 = true, .has_dsi = true, }; static const struct sun8i_tcon_top_quirks sun20i_d1_tcon_top_quirks = { + .has_tcon_tv0 = true, .has_dsi = true, }; static const struct sun8i_tcon_top_quirks sun50i_h6_tcon_top_quirks = { - /* Nothing special */ + .has_tcon_tv0 = true, }; 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Received: from [122.165.245.213] (port=50828 helo=[127.0.1.1]) by md-in-79.webhostbox.net with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.96.2) (envelope-from ) id 1tR8Dj-000bEK-2P; Fri, 27 Dec 2024 16:39:31 +0530 From: Parthiban Nallathambi Date: Fri, 27 Dec 2024 16:38:02 +0530 Subject: [PATCH 15/22] clk: sunxi-ng: sun8i-de2: add pll-com clock support Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241227-a133-display-support-v1-15-13b52f71fb14@linumiz.com> References: <20241227-a133-display-support-v1-0-13b52f71fb14@linumiz.com> In-Reply-To: <20241227-a133-display-support-v1-0-13b52f71fb14@linumiz.com> To: Joerg Roedel , Will Deacon , Robin Murphy , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Maxime Ripard , Maarten Lankhorst , Thomas Zimmermann , David Airlie , Simona Vetter , Michael Turquette , Stephen Boyd , Philipp Zabel , Linus Walleij , Vinod Koul , Kishon Vijay Abraham I Cc: iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-phy@lists.infradead.org, Parthiban Nallathambi X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; 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There is no documentation reference or details in DE 2.0 specification. But these changes are needed to get the display clock to work and this is inherited from the vendor BSP. Signed-off-by: Parthiban Nallathambi --- drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c index f2aa71206bc2..3e28c32050e0 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c +++ b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c @@ -241,7 +241,7 @@ static const struct sunxi_ccu_desc sun50i_h5_de2_clk_desc = { static int sunxi_de2_clk_probe(struct platform_device *pdev) { - struct clk *bus_clk, *mod_clk; + struct clk *bus_clk, *mod_clk, *pll_clk; struct reset_control *rstc; void __iomem *reg; const struct sunxi_ccu_desc *ccu_desc; @@ -265,6 +265,11 @@ static int sunxi_de2_clk_probe(struct platform_device *pdev) return dev_err_probe(&pdev->dev, PTR_ERR(mod_clk), "Couldn't get mod clk\n"); + pll_clk = devm_clk_get_optional(&pdev->dev, "pll-com"); + if (IS_ERR(pll_clk)) + return dev_err_probe(&pdev->dev, PTR_ERR(pll_clk), + "Couldn't get pll clk\n"); + rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); if (IS_ERR(rstc)) return dev_err_probe(&pdev->dev, PTR_ERR(rstc), @@ -283,12 +288,20 @@ static int sunxi_de2_clk_probe(struct platform_device *pdev) goto err_disable_bus_clk; } + if (pll_clk) { + ret = clk_prepare_enable(pll_clk); + if (ret) { + dev_err(&pdev->dev, "Couldn't enable pll clk: %d\n", ret); + goto err_disable_mod_clk; + } + } + /* The reset control needs to be asserted for the controls to work */ ret = reset_control_deassert(rstc); if (ret) { dev_err(&pdev->dev, "Couldn't deassert reset control: %d\n", ret); - goto err_disable_mod_clk; + goto err_disable_pll_clk; } ret = devm_sunxi_ccu_probe(&pdev->dev, reg, ccu_desc); @@ -299,6 +312,8 @@ static int sunxi_de2_clk_probe(struct platform_device *pdev) err_assert_reset: reset_control_assert(rstc); +err_disable_pll_clk: + clk_disable_unprepare(pll_clk); err_disable_mod_clk: clk_disable_unprepare(mod_clk); err_disable_bus_clk: