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Hence rename spi0 pins to spi4 like spi0_cs to spi4_cs etc. Signed-off-by: Manikanta Mylavarapu --- .../devicetree/bindings/pinctrl/qcom,ipq5424-tlmm.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq5424-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,ipq5424-tlmm.yaml index df284d3645c1..4e0be380caf6 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,ipq5424-tlmm.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq5424-tlmm.yaml @@ -79,7 +79,7 @@ $defs: qdss_cti_trig_out_b0, qdss_cti_trig_in_b1, qdss_cti_trig_out_b1, qdss_traceclk_a, qdss_tracectl_a, qdss_tracedata_a, qspi_clk, qspi_cs, qspi_data, resout, rx0, rx1, rx2, sdc_clk, sdc_cmd, - sdc_data, spi0_cs, spi0_clk, spi0_miso, spi0_mosi, spi1, spi10, + sdc_data, spi4_cs, spi4_clk, spi4_miso, spi4_mosi, spi1, spi10, spi11, tsens_max, uart0, uart1, wci_txd, wci_rxd, wsi_clk, wsi_data ] required: From patchwork Fri Dec 27 07:24:42 2024 Content-Type: text/plain; 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Hence we need to rename the spi0 clocks to spi4 clocks. However, renaming spi0 to spi4 will result in the following compilation error's. drivers/clk/qcom/gcc-ipq5424.c:2865:3: error: ‘GCC_QUPV3_SPI0_CLK’ undeclared here drivers/clk/qcom/gcc-ipq5424.c:2866:3: error: ‘GCC_QUPV3_SPI0_CLK_SRC’ undeclared here To add spi4 clocks without compilation error's, do not rename the spi0 clocks. Instead, duplicate the spi0 clock macros and rename them to spi4. After switching to spi4 clocks in the gcc-ipq5424 driver, remove the spi0 clock macros. Signed-off-by: Manikanta Mylavarapu --- include/dt-bindings/clock/qcom,ipq5424-gcc.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/dt-bindings/clock/qcom,ipq5424-gcc.h b/include/dt-bindings/clock/qcom,ipq5424-gcc.h index 755ce7a71c7c..5dad45a8f614 100644 --- a/include/dt-bindings/clock/qcom,ipq5424-gcc.h +++ b/include/dt-bindings/clock/qcom,ipq5424-gcc.h @@ -123,6 +123,7 @@ #define GCC_QUPV3_I2C0_CLK 113 #define GCC_QUPV3_I2C1_CLK 114 #define GCC_QUPV3_SPI0_CLK 115 +#define GCC_QUPV3_SPI4_CLK GCC_QUPV3_SPI0_CLK #define GCC_QUPV3_SPI1_CLK 116 #define GCC_QUPV3_UART0_CLK 117 #define GCC_QUPV3_UART1_CLK 118 @@ -132,6 +133,7 @@ #define GCC_QUPV3_I2C0_DIV_CLK_SRC 122 #define GCC_QUPV3_I2C1_DIV_CLK_SRC 123 #define GCC_QUPV3_SPI0_CLK_SRC 124 +#define GCC_QUPV3_SPI4_CLK_SRC GCC_QUPV3_SPI0_CLK_SRC #define GCC_QUPV3_SPI1_CLK_SRC 125 #define GCC_QUPV3_UART0_CLK_SRC 126 #define GCC_QUPV3_UART1_CLK_SRC 127 From patchwork Fri Dec 27 07:24:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Mylavarapu X-Patchwork-Id: 854035 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D0B02146593; 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Hence rename spi0 pins to spi4 like spi0_cs to spi4_cs etc. Signed-off-by: Manikanta Mylavarapu --- drivers/pinctrl/qcom/pinctrl-ipq5424.c | 32 +++++++++++++------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-ipq5424.c b/drivers/pinctrl/qcom/pinctrl-ipq5424.c index 0d610b076da3..05c45a115d7a 100644 --- a/drivers/pinctrl/qcom/pinctrl-ipq5424.c +++ b/drivers/pinctrl/qcom/pinctrl-ipq5424.c @@ -233,10 +233,10 @@ enum ipq5424_functions { msm_mux_sdc_clk, msm_mux_sdc_cmd, msm_mux_sdc_data, - msm_mux_spi0_clk, - msm_mux_spi0_cs, - msm_mux_spi0_miso, - msm_mux_spi0_mosi, + msm_mux_spi4_clk, + msm_mux_spi4_cs, + msm_mux_spi4_miso, + msm_mux_spi4_mosi, msm_mux_spi1, msm_mux_spi10, msm_mux_spi11, @@ -300,7 +300,7 @@ static const char * const qspi_clk_groups[] = { "gpio5", }; -static const char * const spi0_clk_groups[] = { +static const char * const spi4_clk_groups[] = { "gpio6", }; @@ -318,7 +318,7 @@ static const char * const qdss_tracedata_a_groups[] = { "gpio38", "gpio39", }; -static const char * const spi0_cs_groups[] = { +static const char * const spi4_cs_groups[] = { "gpio7", }; @@ -326,7 +326,7 @@ static const char * const cri_trng1_groups[] = { "gpio7", }; -static const char * const spi0_miso_groups[] = { +static const char * const spi4_miso_groups[] = { "gpio8", }; @@ -334,7 +334,7 @@ static const char * const cri_trng2_groups[] = { "gpio8", }; -static const char * const spi0_mosi_groups[] = { +static const char * const spi4_mosi_groups[] = { "gpio9", }; @@ -695,10 +695,10 @@ static const struct pinfunction ipq5424_functions[] = { MSM_PIN_FUNCTION(sdc_clk), MSM_PIN_FUNCTION(sdc_cmd), MSM_PIN_FUNCTION(sdc_data), - MSM_PIN_FUNCTION(spi0_clk), - MSM_PIN_FUNCTION(spi0_cs), - MSM_PIN_FUNCTION(spi0_miso), - MSM_PIN_FUNCTION(spi0_mosi), + MSM_PIN_FUNCTION(spi4_clk), + MSM_PIN_FUNCTION(spi4_cs), + MSM_PIN_FUNCTION(spi4_miso), + MSM_PIN_FUNCTION(spi4_mosi), MSM_PIN_FUNCTION(spi1), MSM_PIN_FUNCTION(spi10), MSM_PIN_FUNCTION(spi11), @@ -718,10 +718,10 @@ static const struct msm_pingroup ipq5424_groups[] = { PINGROUP(3, sdc_data, qspi_data, pwm2, _, _, _, _, _, _), PINGROUP(4, sdc_cmd, qspi_cs, _, _, _, _, _, _, _), PINGROUP(5, sdc_clk, qspi_clk, _, _, _, _, _, _, _), - PINGROUP(6, spi0_clk, pwm1, _, cri_trng0, qdss_tracedata_a, _, _, _, _), - PINGROUP(7, spi0_cs, pwm1, _, cri_trng1, qdss_tracedata_a, _, _, _, _), - PINGROUP(8, spi0_miso, pwm1, wci_txd, wci_rxd, _, cri_trng2, qdss_tracedata_a, _, _), - PINGROUP(9, spi0_mosi, pwm1, _, cri_trng3, qdss_tracedata_a, _, _, _, _), + PINGROUP(6, spi4_clk, pwm1, _, cri_trng0, qdss_tracedata_a, _, _, _, _), + PINGROUP(7, spi4_cs, pwm1, _, cri_trng1, qdss_tracedata_a, _, _, _, _), + PINGROUP(8, spi4_miso, pwm1, wci_txd, wci_rxd, _, cri_trng2, qdss_tracedata_a, _, _), + PINGROUP(9, spi4_mosi, pwm1, _, cri_trng3, qdss_tracedata_a, _, _, _, _), PINGROUP(10, uart0, pwm0, spi11, _, wci_txd, wci_rxd, _, qdss_tracedata_a, _), PINGROUP(11, uart0, pwm0, spi1, _, wci_txd, wci_rxd, _, qdss_tracedata_a, _), PINGROUP(12, uart0, pwm0, spi11, _, prng_rosc0, qdss_tracedata_a, _, _, _), From patchwork Fri Dec 27 07:24:44 2024 Content-Type: text/plain; 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Hence rename spi0 clocks to spi4 like GCC_QUPV3_SPI0_CLK to GCC_QUPV3_SPI4_CLK. Signed-off-by: Manikanta Mylavarapu --- drivers/clk/qcom/gcc-ipq5424.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/clk/qcom/gcc-ipq5424.c b/drivers/clk/qcom/gcc-ipq5424.c index 88a7d5b2e751..5fcf7d9ca390 100644 --- a/drivers/clk/qcom/gcc-ipq5424.c +++ b/drivers/clk/qcom/gcc-ipq5424.c @@ -531,7 +531,7 @@ static struct clk_rcg2 gcc_qupv3_i2c1_clk_src = { }, }; -static const struct freq_tbl ftbl_gcc_qupv3_spi0_clk_src[] = { +static const struct freq_tbl ftbl_gcc_qupv3_spi4_clk_src[] = { F(960000, P_XO, 10, 2, 5), F(4800000, P_XO, 5, 0, 0), F(9600000, P_XO, 2, 4, 5), @@ -543,14 +543,14 @@ static const struct freq_tbl ftbl_gcc_qupv3_spi0_clk_src[] = { { } }; -static struct clk_rcg2 gcc_qupv3_spi0_clk_src = { +static struct clk_rcg2 gcc_qupv3_spi4_clk_src = { .cmd_rcgr = 0x4004, .mnd_width = 8, .hid_width = 5, .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_spi0_clk_src, + .freq_tbl = ftbl_gcc_qupv3_spi4_clk_src, .clkr.hw.init = &(const struct clk_init_data) { - .name = "gcc_qupv3_spi0_clk_src", + .name = "gcc_qupv3_spi4_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, @@ -562,7 +562,7 @@ static struct clk_rcg2 gcc_qupv3_spi1_clk_src = { .mnd_width = 8, .hid_width = 5, .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_spi0_clk_src, + .freq_tbl = ftbl_gcc_qupv3_spi4_clk_src, .clkr.hw.init = &(const struct clk_init_data) { .name = "gcc_qupv3_spi1_clk_src", .parent_data = gcc_parent_data_0, @@ -2072,16 +2072,16 @@ static struct clk_branch gcc_qupv3_i2c1_clk = { }, }; -static struct clk_branch gcc_qupv3_spi0_clk = { +static struct clk_branch gcc_qupv3_spi4_clk = { .halt_reg = 0x4020, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x4020, .enable_mask = BIT(0), .hw.init = &(const struct clk_init_data) { - .name = "gcc_qupv3_spi0_clk", + .name = "gcc_qupv3_spi4_clk", .parent_hws = (const struct clk_hw*[]) { - &gcc_qupv3_spi0_clk_src.clkr.hw, + &gcc_qupv3_spi4_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2862,8 +2862,8 @@ static struct clk_regmap *gcc_ipq5424_clocks[] = { [GCC_QUPV3_I2C1_CLK] = &gcc_qupv3_i2c1_clk.clkr, [GCC_QUPV3_I2C1_CLK_SRC] = &gcc_qupv3_i2c1_clk_src.clkr, [GCC_QUPV3_I2C1_DIV_CLK_SRC] = &gcc_qupv3_i2c1_div_clk_src.clkr, - [GCC_QUPV3_SPI0_CLK] = &gcc_qupv3_spi0_clk.clkr, - [GCC_QUPV3_SPI0_CLK_SRC] = &gcc_qupv3_spi0_clk_src.clkr, + [GCC_QUPV3_SPI4_CLK] = &gcc_qupv3_spi4_clk.clkr, + [GCC_QUPV3_SPI4_CLK_SRC] = &gcc_qupv3_spi4_clk_src.clkr, [GCC_QUPV3_SPI1_CLK] = &gcc_qupv3_spi1_clk.clkr, [GCC_QUPV3_SPI1_CLK_SRC] = &gcc_qupv3_spi1_clk_src.clkr, [GCC_QUPV3_UART0_CLK] = &gcc_qupv3_uart0_clk.clkr, From patchwork Fri Dec 27 07:24:45 2024 Content-Type: text/plain; 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Signed-off-by: Manikanta Mylavarapu --- Changes in V3: - Replace spi0 with spi4 in all applicable places such as clocks, commit message, heading and dt node name. arch/arm64/boot/dts/qcom/ipq5424.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi index 5e219f900412..d425298d0471 100644 --- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi @@ -201,6 +201,17 @@ uart1: serial@1a84000 { clock-names = "se"; interrupts = ; }; + + spi4: spi@1a90000 { + compatible = "qcom,geni-spi"; + reg = <0 0x01a90000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_SPI4_CLK>; + clock-names = "se"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; sdhc: mmc@7804000 { From patchwork Fri Dec 27 07:24:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Mylavarapu X-Patchwork-Id: 853858 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BBBFC149C6A; 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Signed-off-by: Manikanta Mylavarapu --- Changes in V3: - Replace spi0 with spi4 in all applicable places such as tlmm pin names, commit message, heading and dt node name. arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts | 43 +++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts index d4d31026a026..1e7c7f73b21e 100644 --- a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts +++ b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts @@ -23,6 +23,36 @@ &sleep_clk { }; &tlmm { + spi4_default_state: spi4-default-state { + clk-pins { + pins = "gpio6"; + function = "spi4_clk"; + drive-strength = <8>; + bias-pull-down; + }; + + cs-pins { + pins = "gpio7"; + function = "spi4_cs"; + drive-strength = <8>; + bias-pull-up; + }; + + miso-pins { + pins = "gpio8"; + function = "spi4_miso"; + drive-strength = <8>; + bias-pull-down; + }; + + mosi-pins { + pins = "gpio9"; + function = "spi4_mosi"; + drive-strength = <8>; + bias-pull-down; + }; + }; + sdc_default_state: sdc-default-state { clk-pins { pins = "gpio5"; @@ -57,3 +87,16 @@ &xo_board { clock-frequency = <24000000>; }; +&spi4 { + pinctrl-0 = <&spi4_default_state>; + pinctrl-names = "default"; + status = "okay"; + + flash@0 { + compatible = "micron,n25q128a11", "jedec,spi-nor"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <50000000>; + }; +};