From patchwork Tue Dec 24 17:05:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 853435 Received: from relay2-d.mail.gandi.net (relay2-d.mail.gandi.net [217.70.183.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 61E53212B23; Tue, 24 Dec 2024 17:06:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.194 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735059997; cv=none; b=UlUpo4Dsxk10yrBdQdQ/LYM9gY4IVlJyUvQgL/6YZSkvw8RQ2aaIY2Nv5DEeKryVf9Mc95rMz/uxMGmiuWQ0POTItzW4BqR7LeIyezVmTMTK8stxLEPs0V0yPt2CWyHwMcIeeB4BQnNconlzYFfZNubGUDFFr43mApKe2vQ9yn4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735059997; c=relaxed/simple; bh=9ETsYmF7g+IJHujOmeEiyZwUhOSnT2HzW3N29Ssup14=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=JtlZOC+okrcCawjsDqLyi5X1qZixop0qnje2yX4x4BwMR3U9jjBmextWvX+oyH04SLUnB37Di+lFGScBKf4ORC9mYEv8GzuTd93wy3dQz7FZi70c1fZi+j8VAryg3Gfj/rxpDewaOxiQiRzceIrqYDG3MDVFie05oypLQfZuUG0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=fAPtbITE; arc=none smtp.client-ip=217.70.183.194 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="fAPtbITE" Received: by mail.gandi.net (Postfix) with ESMTPSA id D22F340003; Tue, 24 Dec 2024 17:06:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1735059988; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=yep2fpLxz2x0BrYyE5exhny4uIKamjx0bibrwjwb1p8=; b=fAPtbITEHMKbTONn3xM2tV41g/KqcuzonPT8sVvi6RHv+XQEEeYKgX8amVjzTQcB+iN+wW FYgAX+Tr2KxqzJPUHaW60TrKoiwprAUoouYzb77XRZOI0b8WO1UDvlAXfO9InWh+Z17YDp o46cqQHSiB9ZLTauwRAKuE/nFtmaujayyStAHaa1+T+RC56OTc9u3f8zZlTJVDpzSWbKFI QR1ij98JFdq179bRmfTMueDdC2zGu1lNOV0aa/2dD9RQMZidD9N4+xsP6Avjru3PHjlC1B MJBINpN/rekFyA2N34ashKqNSP+T9w6Dl8eO0pEytq15pvGnO8krxxb71b3l9w== From: Miquel Raynal Date: Tue, 24 Dec 2024 18:05:46 +0100 Subject: [PATCH v2 01/27] spi: spi-mem: Extend spi-mem operations with a per-operation maximum frequency Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241224-winbond-6-11-rc1-quad-support-v2-1-ad218dbc406f@bootlin.com> References: <20241224-winbond-6-11-rc1-quad-support-v2-0-ad218dbc406f@bootlin.com> In-Reply-To: <20241224-winbond-6-11-rc1-quad-support-v2-0-ad218dbc406f@bootlin.com> To: Mark Brown , Sanjay R Mehta , Serge Semin , Han Xu , Conor Dooley , Daire McNamara , Matthias Brugger , AngeloGioacchino Del Regno , Haibo Chen , Yogesh Gaur , Heiko Stuebner , Michal Simek , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Jacky Huang , Shan-Chun Hung , Chin-Ting Kuo , =?utf-8?q?C=C3=A9dric_Le_Goa?= =?utf-8?q?ter?= , Joel Stanley , Andrew Jeffery , Avi Fishman , Tomer Maimon , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair , Maxime Coquelin , Alexandre Torgue , Raju Rangoju Cc: Thomas Petazzoni , Steam Lin , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-mtd@lists.infradead.org, linux-aspeed@lists.ozlabs.org, openbmc@lists.ozlabs.org, linux-stm32@st-md-mailman.stormreply.com, Pratyush Yadav X-Mailer: b4 0.15-dev X-GND-Sasl: miquel.raynal@bootlin.com In the spi subsystem, the bus frequency is derived as follows: - the controller may expose a minimum and maximum operating frequency - the hardware description, through the spi peripheral properties, advise what is the maximum acceptable frequency from a device/wiring point of view. Transfers must be observed at a frequency which fits both (so in practice, the lowest maximum). Actually, this second point mixes two information and already takes the lowest frequency among: - what the spi device is capable of (what is written in the component datasheet) - what the wiring allows (electromagnetic sensibility, crossovers, terminations, antenna effect, etc). This logic works until spi devices are no longer capable of sustaining their highest frequency regardless of the operation. Spi memories are typically subject to such variation. Some devices are capable of spitting their internally stored data (essentially in read mode) at a very fast rate, typically up to 166MHz on Winbond SPI-NAND chips, using "fast" commands. However, some of the low-end operations, such as regular page read-from-cache commands, are more limited and can only be executed at 54MHz at most. This is currently a problem in the SPI-NAND subsystem. Another situation, even if not yet supported, will be with DTR commands, when the data is latched on both edges of the clock. The same chips as mentioned previously are in this case limited to 80MHz. Yet another example might be continuous reads, which, under certain circumstances, can also run at most at 104 or 120MHz. As a matter of fact, the "one frequency per chip" policy is outdated and more fine grain configuration is needed: we need to allow per-operation frequency limitations. So far, all datasheets I encountered advertise a maximum default frequency, which need to be lowered for certain specific operations. So based on the current infrastructure, we can still expect firmware (device trees in general) to continued advertising the same maximum speed which is a mix between the PCB limitations and the chip maximum capability, and expect per-operation lower frequencies when this is relevant. Add a `struct spi_mem_op` member to carry this information. Not providing this field explicitly from upper layers means that there is no further constraint and the default spi device maximum speed will be carried instead. The SPI_MEM_OP() macro is also expanded with an optional frequency argument, because virtually all operations can be subject to such a limitation, and this will allow for a smooth and discrete transition. For controller drivers which do not implement the spi-mem interface, the per-transfer speed is also set acordingly to a lower (than the maximum default) speed when relevant. Acked-by: Pratyush Yadav Signed-off-by: Miquel Raynal --- drivers/mtd/nand/spi/core.c | 2 ++ drivers/spi/spi-mem.c | 28 ++++++++++++++++++++++++++++ include/linux/spi/spi-mem.h | 12 +++++++++++- 3 files changed, 41 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index b1df7f6271616ba1e6a9718b7aea2512795505dc..94f33c8be031ac60208e22e4e3fa0d90cfae093c 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -1214,6 +1214,8 @@ spinand_select_op_variant(struct spinand_device *spinand, if (ret) break; + spi_mem_adjust_op_freq(spinand->spimem, &op); + if (!spi_mem_supports_op(spinand->spimem, &op)) break; diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c index abc6792e738c730166ef9b0aa505ce5225893938..12299ce89a1cc80495858dbbbaa822f2968bb7ab 100644 --- a/drivers/spi/spi-mem.c +++ b/drivers/spi/spi-mem.c @@ -187,6 +187,10 @@ bool spi_mem_default_supports_op(struct spi_mem *mem, return false; } + if (op->max_freq && mem->spi->controller->min_speed_hz && + op->max_freq < mem->spi->controller->min_speed_hz) + return false; + return spi_mem_check_buswidth(mem, op); } EXPORT_SYMBOL_GPL(spi_mem_default_supports_op); @@ -364,6 +368,9 @@ int spi_mem_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) u8 *tmpbuf; int ret; + /* Make sure the operation frequency is correct before going futher */ + spi_mem_adjust_op_freq(mem, (struct spi_mem_op *)op); + ret = spi_mem_check_op(op); if (ret) return ret; @@ -410,6 +417,7 @@ int spi_mem_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) xfers[xferpos].tx_buf = tmpbuf; xfers[xferpos].len = op->cmd.nbytes; xfers[xferpos].tx_nbits = op->cmd.buswidth; + xfers[xferpos].speed_hz = op->max_freq; spi_message_add_tail(&xfers[xferpos], &msg); xferpos++; totalxferlen++; @@ -424,6 +432,7 @@ int spi_mem_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) xfers[xferpos].tx_buf = tmpbuf + 1; xfers[xferpos].len = op->addr.nbytes; xfers[xferpos].tx_nbits = op->addr.buswidth; + xfers[xferpos].speed_hz = op->max_freq; spi_message_add_tail(&xfers[xferpos], &msg); xferpos++; totalxferlen += op->addr.nbytes; @@ -435,6 +444,7 @@ int spi_mem_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) xfers[xferpos].len = op->dummy.nbytes; xfers[xferpos].tx_nbits = op->dummy.buswidth; xfers[xferpos].dummy_data = 1; + xfers[xferpos].speed_hz = op->max_freq; spi_message_add_tail(&xfers[xferpos], &msg); xferpos++; totalxferlen += op->dummy.nbytes; @@ -450,6 +460,7 @@ int spi_mem_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) } xfers[xferpos].len = op->data.nbytes; + xfers[xferpos].speed_hz = op->max_freq; spi_message_add_tail(&xfers[xferpos], &msg); xferpos++; totalxferlen += op->data.nbytes; @@ -528,6 +539,23 @@ int spi_mem_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op) } EXPORT_SYMBOL_GPL(spi_mem_adjust_op_size); +/** + * spi_mem_adjust_op_freq() - Adjust the frequency of a SPI mem operation to + * match controller, PCB and chip limitations + * @mem: the SPI memory + * @op: the operation to adjust + * + * Some chips have per-op frequency limitations and must adapt the maximum + * speed. This function allows SPI mem drivers to set @op->max_freq to the + * maximum supported value. + */ +void spi_mem_adjust_op_freq(struct spi_mem *mem, struct spi_mem_op *op) +{ + if (!op->max_freq || op->max_freq > mem->spi->max_speed_hz) + op->max_freq = mem->spi->max_speed_hz; +} +EXPORT_SYMBOL_GPL(spi_mem_adjust_op_freq); + static ssize_t spi_mem_no_dirmap_read(struct spi_mem_dirmap_desc *desc, u64 offs, size_t len, void *buf) { diff --git a/include/linux/spi/spi-mem.h b/include/linux/spi/spi-mem.h index c46d2b8029be5b3cee1cb6a5dc00e3d1a0e9ced2..84ec524987921a95963235de4b6f728ef2fc5987 100644 --- a/include/linux/spi/spi-mem.h +++ b/include/linux/spi/spi-mem.h @@ -68,6 +68,9 @@ enum spi_mem_data_dir { SPI_MEM_DATA_OUT, }; +#define SPI_MEM_OP_MAX_FREQ(__freq) \ + .max_freq = __freq + /** * struct spi_mem_op - describes a SPI memory operation * @cmd.nbytes: number of opcode bytes (only 1 or 2 are valid). The opcode is @@ -97,6 +100,9 @@ enum spi_mem_data_dir { * operation does not involve transferring data * @data.buf.in: input buffer (must be DMA-able) * @data.buf.out: output buffer (must be DMA-able) + * @max_freq: frequency limitation wrt this operation. 0 means there is no + * specific constraint and the highest achievable frequency can be + * attempted. */ struct spi_mem_op { struct { @@ -135,14 +141,17 @@ struct spi_mem_op { const void *out; } buf; } data; + + unsigned int max_freq; }; -#define SPI_MEM_OP(__cmd, __addr, __dummy, __data) \ +#define SPI_MEM_OP(__cmd, __addr, __dummy, __data, ...) \ { \ .cmd = __cmd, \ .addr = __addr, \ .dummy = __dummy, \ .data = __data, \ + __VA_ARGS__ \ } /** @@ -371,6 +380,7 @@ bool spi_mem_default_supports_op(struct spi_mem *mem, #endif /* CONFIG_SPI_MEM */ int spi_mem_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op); +void spi_mem_adjust_op_freq(struct spi_mem *mem, struct spi_mem_op *op); bool spi_mem_supports_op(struct spi_mem *mem, const struct spi_mem_op *op); From patchwork Tue Dec 24 17:05:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 853434 Received: from relay2-d.mail.gandi.net (relay2-d.mail.gandi.net [217.70.183.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 10381212FB0; Tue, 24 Dec 2024 17:06:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.194 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735060006; cv=none; b=cp5W5xirn8CoZ0R1rOkDcB41DclDO1mLuE5Qedef8eGOmb4tsSHyC/yNG2WerkvSufQbjt12Ff51b7z5ezPSUl3lJtWRvOVgIxx9dLJ/szYkxyndU3SsZUu9JYfVkfGpjEH/ipBkRVVTSLlNBiP5WSQxFG171O4u9xwR7rnpI90= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735060006; c=relaxed/simple; bh=TQ8aXk2UITTF0V87m8Kpdw316O05nWgk6I0dD8XK6mM=; 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c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1735060002; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=dHPofq5XZq7az/ZH3pSbnokgc8b9g3SIFoGkVNSo6iM=; b=dCoBmN1Zsbg4xR1kd5uwqWvdqw5NRNRqTHsjVIAxvOPpWGjePVJdoiMUap/IIyk1IZgVED bpU8xzpiemf1TCGirkGDqJbA2yfArVvUS0fkMLO4/cOBw4bsSCH33Eel9/vHSHFIPYU3Fx Pskt2ss8OSIR41cfnMJ6Qii9rwsehhu7SEliVI5KQycD9YnPhxf1gvwikQPrV6zly2XPcm hmWPX0JtoOYwWlBEH791HIfeXbCLgJ661nUu0/BjwTV6ohz1wjw6bLRgUiZvVZax/J7dZK rd9ljXu6CJ1UiZTTk1CDbGn8Xb/aP4eRUm3FzlYllBkt7ne3RGqccrBfk7c9vw== From: Miquel Raynal Date: Tue, 24 Dec 2024 18:05:49 +0100 Subject: [PATCH v2 04/27] spi: amd: Drop redundant check Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241224-winbond-6-11-rc1-quad-support-v2-4-ad218dbc406f@bootlin.com> References: <20241224-winbond-6-11-rc1-quad-support-v2-0-ad218dbc406f@bootlin.com> In-Reply-To: <20241224-winbond-6-11-rc1-quad-support-v2-0-ad218dbc406f@bootlin.com> To: Mark Brown , Sanjay R Mehta , Serge Semin , Han Xu , Conor Dooley , Daire McNamara , Matthias Brugger , AngeloGioacchino Del Regno , Haibo Chen , Yogesh Gaur , Heiko Stuebner , Michal Simek , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Jacky Huang , Shan-Chun Hung , Chin-Ting Kuo , =?utf-8?q?C=C3=A9dric_Le_Goa?= =?utf-8?q?ter?= , Joel Stanley , Andrew Jeffery , Avi Fishman , Tomer Maimon , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair , Maxime Coquelin , Alexandre Torgue , Raju Rangoju Cc: Thomas Petazzoni , Steam Lin , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-mtd@lists.infradead.org, linux-aspeed@lists.ozlabs.org, openbmc@lists.ozlabs.org, linux-stm32@st-md-mailman.stormreply.com X-Mailer: b4 0.15-dev X-GND-Sasl: miquel.raynal@bootlin.com Both spi and spi-mem cores already take care of checking the minimum and maximum speed for transfers depending on the controller capabilities. There is no reason to repeat this check in controller drivers. Once this possible error condition removed from the function, it makes no longer sense to return an int. Signed-off-by: Miquel Raynal --- drivers/spi/spi-amd.c | 13 +++---------- 1 file changed, 3 insertions(+), 10 deletions(-) diff --git a/drivers/spi/spi-amd.c b/drivers/spi/spi-amd.c index 485ae1e382e3eb8f4d72ebb0fb15c51b9a118d3b..fbe795bbcf507abcbbd973b226b5db0de1584898 100644 --- a/drivers/spi/spi-amd.c +++ b/drivers/spi/spi-amd.c @@ -298,19 +298,16 @@ static const struct amd_spi_freq amd_spi_freq[] = { { AMD_SPI_MIN_HZ, F_800KHz, 0}, }; -static int amd_set_spi_freq(struct amd_spi *amd_spi, u32 speed_hz) +static void amd_set_spi_freq(struct amd_spi *amd_spi, u32 speed_hz) { unsigned int i, spd7_val, alt_spd; - if (speed_hz < AMD_SPI_MIN_HZ) - return -EINVAL; - for (i = 0; i < ARRAY_SIZE(amd_spi_freq); i++) if (speed_hz >= amd_spi_freq[i].speed_hz) break; if (amd_spi->speed_hz == amd_spi_freq[i].speed_hz) - return 0; + return; amd_spi->speed_hz = amd_spi_freq[i].speed_hz; @@ -329,8 +326,6 @@ static int amd_set_spi_freq(struct amd_spi *amd_spi, u32 speed_hz) amd_spi_setclear_reg32(amd_spi, AMD_SPI_SPEED_REG, spd7_val, AMD_SPI_SPD7_MASK); } - - return 0; } static inline int amd_spi_fifo_xfer(struct amd_spi *amd_spi, @@ -679,9 +674,7 @@ static int amd_spi_exec_mem_op(struct spi_mem *mem, amd_spi = spi_controller_get_devdata(mem->spi->controller); - ret = amd_set_spi_freq(amd_spi, op->max_freq); - if (ret) - return ret; + amd_set_spi_freq(amd_spi, op->max_freq); if (amd_spi->version == AMD_SPI_V2) amd_set_spi_addr_mode(amd_spi, op); From patchwork Tue Dec 24 17:05:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 853433 Received: from relay2-d.mail.gandi.net (relay2-d.mail.gandi.net [217.70.183.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5A90A21323B; Tue, 24 Dec 2024 17:06:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.194 ARC-Seal: i=1; a=rsa-sha256; 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spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="mjyzG3GW" Received: by mail.gandi.net (Postfix) with ESMTPSA id 7169F40002; Tue, 24 Dec 2024 17:06:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1735060011; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=GhS+zZ6UEvQnr62N11JkbnpzTV68YUYjNDNf+0QneiY=; b=mjyzG3GWELMq6c7f+8BEGOXFcDyZWw4zZFu5oZ2bXKmWLasrMO/ecJD+oTC5EHpPnh+quK /9s58HlReb6/z8C6P81U5uRXkQ/ZJaKPQTrjuCT/5lQKUh2hQHsGUUhSbHbz0u6oIDbciG /zw6CNFxXPEpc3SSOGj3alSbFeE499xV08jk+3HCwMJr8finn7su+O60xgOJj2KFY6ObfM Mb3x4z4jl8wpvnGBpRpLOJwKLFsP/QLpyr4h0RG5G1uW7kB++G9tcFYX5WEzbFWVmDjOHx HFM8urZlhjo6nG0RNMZ4fEgRUPTufSjchTwx2YIgxI17pCukEoKI0IFNCA6Bzg== From: Miquel Raynal Date: Tue, 24 Dec 2024 18:05:51 +0100 Subject: [PATCH v2 06/27] spi: cadence-qspi: Support per spi-mem operation frequency switches Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241224-winbond-6-11-rc1-quad-support-v2-6-ad218dbc406f@bootlin.com> References: <20241224-winbond-6-11-rc1-quad-support-v2-0-ad218dbc406f@bootlin.com> In-Reply-To: <20241224-winbond-6-11-rc1-quad-support-v2-0-ad218dbc406f@bootlin.com> To: Mark Brown , Sanjay R Mehta , Serge Semin , Han Xu , Conor Dooley , Daire McNamara , Matthias Brugger , AngeloGioacchino Del Regno , Haibo Chen , Yogesh Gaur , Heiko Stuebner , Michal Simek , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Jacky Huang , Shan-Chun Hung , Chin-Ting Kuo , =?utf-8?q?C=C3=A9dric_Le_Goa?= =?utf-8?q?ter?= , Joel Stanley , Andrew Jeffery , Avi Fishman , Tomer Maimon , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair , Maxime Coquelin , Alexandre Torgue , Raju Rangoju Cc: Thomas Petazzoni , Steam Lin , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-mtd@lists.infradead.org, linux-aspeed@lists.ozlabs.org, openbmc@lists.ozlabs.org, linux-stm32@st-md-mailman.stormreply.com, Tudor Ambarus X-Mailer: b4 0.15-dev X-GND-Sasl: miquel.raynal@bootlin.com Every ->exec_op() call correctly configures the spi bus speed to the maximum allowed frequency for the memory using the constant spi default parameter. Since we can now have per-operation constraints, let's use the value that comes from the spi-mem operation structure instead. In case there is no specific limitation for this operation, the default spi device value will be given anyway. The per-operation frequency capability is thus advertised to the spi-mem core. Reviewed-by: Tudor Ambarus Signed-off-by: Miquel Raynal --- drivers/spi/spi-cadence-quadspi.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c index 0b45b7b2b3ab30951d94ea2ce57dcba3a2600847..e4862163252ed35053f743c74f1175e033940b17 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -1407,7 +1407,7 @@ static int cqspi_mem_process(struct spi_mem *mem, const struct spi_mem_op *op) struct cqspi_flash_pdata *f_pdata; f_pdata = &cqspi->f_pdata[spi_get_chipselect(mem->spi, 0)]; - cqspi_configure(f_pdata, mem->spi->max_speed_hz); + cqspi_configure(f_pdata, op->max_freq); if (op->data.dir == SPI_MEM_DATA_IN && op->data.buf.in) { /* @@ -1655,6 +1655,7 @@ static const struct spi_controller_mem_ops cqspi_mem_ops = { static const struct spi_controller_mem_caps cqspi_mem_caps = { .dtr = true, + .per_op_freq = true, }; static int cqspi_setup_flash(struct cqspi_st *cqspi) From patchwork Tue Dec 24 17:05:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 853432 Received: from relay2-d.mail.gandi.net (relay2-d.mail.gandi.net [217.70.183.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BD8E22135A2; Tue, 24 Dec 2024 17:07:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.194 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735060023; cv=none; b=tSYqaZCNE78qOuaiWfmEXGc1GbsNiiaoz8bwe1NVmaF7tONG3XrugvYjg245x8zEJ5UzH39p1NHaMNiKijqrw8/Ol0i4WB0miPaUxUSU6SAGS9M0g6TrCJ4PBIdgmDu4VWPHyGRKVr4cmRzI/O/7SBPBha0fsJZgMUKzLGff+T0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735060023; c=relaxed/simple; bh=eFgMyOfxkl02m78OhThqpNpwuFeCqsIrRLmrBn7fZ74=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; 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bh=JrcFdkL7v8hevVCz++URbVmucpyX6fBOW8nqTnbI9/s=; b=kTWXaOPzzt1n8GnCYOS5frwghRr0Z8Y3UTN7TxOoJ8Baz1n++H+4bZPUQ1zsGguKewtTZa vnDdnIpGFK+Gb7t9YpYjxhWzBP1K0pa+Ps6j4BIfmJZnTZvd5n6T+TjdHxw//N0Cr6SwOp dsfRL6xiEk8Xy/g9dUzcRjirgLX/ujrzp3uQ+l7Tl+OVPt+H8fkRBywAUnvbJAU80IjTN+ nG19PCo2IOI9eoLW3VxY1rinXDX88gnXej2E7tAACk2UC0EY3Y/X6OfGyApXl1xXXWU9c9 xTHgAxgg9xIgjAsuV3Qo13B6tsVSmX3hO9hpAmhffZFCkfzdHz+GhzLv9SRWSg== From: Miquel Raynal Date: Tue, 24 Dec 2024 18:05:53 +0100 Subject: [PATCH v2 08/27] spi: fsl-qspi: Support per spi-mem operation frequency switches Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241224-winbond-6-11-rc1-quad-support-v2-8-ad218dbc406f@bootlin.com> References: <20241224-winbond-6-11-rc1-quad-support-v2-0-ad218dbc406f@bootlin.com> In-Reply-To: <20241224-winbond-6-11-rc1-quad-support-v2-0-ad218dbc406f@bootlin.com> To: Mark Brown , Sanjay R Mehta , Serge Semin , Han Xu , Conor Dooley , Daire McNamara , Matthias Brugger , AngeloGioacchino Del Regno , Haibo Chen , Yogesh Gaur , Heiko Stuebner , Michal Simek , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Jacky Huang , Shan-Chun Hung , Chin-Ting Kuo , =?utf-8?q?C=C3=A9dric_Le_Goa?= =?utf-8?q?ter?= , Joel Stanley , Andrew Jeffery , Avi Fishman , Tomer Maimon , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair , Maxime Coquelin , Alexandre Torgue , Raju Rangoju Cc: Thomas Petazzoni , Steam Lin , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-mtd@lists.infradead.org, linux-aspeed@lists.ozlabs.org, openbmc@lists.ozlabs.org, linux-stm32@st-md-mailman.stormreply.com X-Mailer: b4 0.15-dev X-GND-Sasl: miquel.raynal@bootlin.com Every ->exec_op() call correctly configures the spi bus speed to the maximum allowed frequency for the memory using the constant spi default parameter. Since we can now have per-operation constraints, let's use the value that comes from the spi-mem operation structure instead. In case there is no specific limitation for this operation, the default spi device value will be given anyway. The per-operation frequency capability is thus advertised to the spi-mem core. Cc: Han Xu Signed-off-by: Miquel Raynal --- drivers/spi/spi-fsl-qspi.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/spi/spi-fsl-qspi.c b/drivers/spi/spi-fsl-qspi.c index 9ec53bf0dda8ead27bc7a11a9bb09a08efe2ea05..355e6a39fb41896f460e2474a90b8f0b42068ff3 100644 --- a/drivers/spi/spi-fsl-qspi.c +++ b/drivers/spi/spi-fsl-qspi.c @@ -522,9 +522,10 @@ static void fsl_qspi_invalidate(struct fsl_qspi *q) qspi_writel(q, reg, q->iobase + QUADSPI_MCR); } -static void fsl_qspi_select_mem(struct fsl_qspi *q, struct spi_device *spi) +static void fsl_qspi_select_mem(struct fsl_qspi *q, struct spi_device *spi, + const struct spi_mem_op *op) { - unsigned long rate = spi->max_speed_hz; + unsigned long rate = op->max_freq; int ret; if (q->selected == spi_get_chipselect(spi, 0)) @@ -652,7 +653,7 @@ static int fsl_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) fsl_qspi_readl_poll_tout(q, base + QUADSPI_SR, (QUADSPI_SR_IP_ACC_MASK | QUADSPI_SR_AHB_ACC_MASK), 10, 1000); - fsl_qspi_select_mem(q, mem->spi); + fsl_qspi_select_mem(q, mem->spi, op); if (needs_amba_base_offset(q)) addr_offset = q->memmap_phy; @@ -839,6 +840,10 @@ static const struct spi_controller_mem_ops fsl_qspi_mem_ops = { .get_name = fsl_qspi_get_name, }; +static const struct spi_controller_mem_caps fsl_qspi_mem_caps = { + .per_op_freq = true, +}; + static int fsl_qspi_probe(struct platform_device *pdev) { struct spi_controller *ctlr; @@ -923,6 +928,7 @@ static int fsl_qspi_probe(struct platform_device *pdev) ctlr->bus_num = -1; ctlr->num_chipselect = 4; ctlr->mem_ops = &fsl_qspi_mem_ops; + ctlr->mem_caps = &fsl_qspi_mem_caps; fsl_qspi_default_setup(q); From patchwork Tue Dec 24 17:05:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 853431 Received: from relay2-d.mail.gandi.net (relay2-d.mail.gandi.net [217.70.183.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E12102135D5; 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arc=none smtp.client-ip=217.70.183.194 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="ZWKmgERF" Received: by mail.gandi.net (Postfix) with ESMTPSA id EF6EA40005; Tue, 24 Dec 2024 17:07:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1735060029; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=NPTwujdULqDMAWJvUaFFPZ6Ty000e2Bmk5z+jRzLZ3I=; b=ZWKmgERFc9lmwxxx6UvyJo+HxANoWAKFnt/84JjZx6t4upVdrlwsfWjPeuUq0FzAgyEy2V shJMU0k3uOASbarNefu0/toxF9Ps41PKa8/7p2T8WOuvxGopWz3GPQFWE8P85t2tlE94+J KtOa58aSvfYrt2wSk3EV3aLtdFGKCWiJqyBkUJnFoVjd9Q7u+p3UO7Jz45ZylJT3sLWl1w nzWNmOxyeogdCFXripvD68o2ySV+xFEEEqPwnUWpBL1Qw15mT7yDGUH9GMNQgd5QZDkQby 2X9/D8BdT4Xodu2qrCeJUPqRR/kgmoVlDw9kPD+uIFaxUrHmS9ndMaoaPEvjAg== From: Miquel Raynal Date: Tue, 24 Dec 2024 18:05:55 +0100 Subject: [PATCH v2 10/27] spi: mt65xx: Support per spi-mem operation frequency switches Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241224-winbond-6-11-rc1-quad-support-v2-10-ad218dbc406f@bootlin.com> References: <20241224-winbond-6-11-rc1-quad-support-v2-0-ad218dbc406f@bootlin.com> In-Reply-To: <20241224-winbond-6-11-rc1-quad-support-v2-0-ad218dbc406f@bootlin.com> To: Mark Brown , Sanjay R Mehta , Serge Semin , Han Xu , Conor Dooley , Daire McNamara , Matthias Brugger , AngeloGioacchino Del Regno , Haibo Chen , Yogesh Gaur , Heiko Stuebner , Michal Simek , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Jacky Huang , Shan-Chun Hung , Chin-Ting Kuo , =?utf-8?q?C=C3=A9dric_Le_Goa?= =?utf-8?q?ter?= , Joel Stanley , Andrew Jeffery , Avi Fishman , Tomer Maimon , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair , Maxime Coquelin , Alexandre Torgue , Raju Rangoju Cc: Thomas Petazzoni , Steam Lin , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-mtd@lists.infradead.org, linux-aspeed@lists.ozlabs.org, openbmc@lists.ozlabs.org, linux-stm32@st-md-mailman.stormreply.com X-Mailer: b4 0.15-dev X-GND-Sasl: miquel.raynal@bootlin.com Every ->exec_op() call correctly configures the spi bus speed to the maximum allowed frequency for the memory using the constant spi default parameter. Since we can now have per-operation constraints, let's use the value that comes from the spi-mem operation structure instead. In case there is no specific limitation for this operation, the default spi device value will be given anyway. The per-operation frequency capability is thus advertised to the spi-mem core. Cc: Matthias Brugger Signed-off-by: Miquel Raynal --- drivers/spi/spi-mt65xx.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-mt65xx.c b/drivers/spi/spi-mt65xx.c index 85f3bafc975dbc3fd95f77b8dcfc0ca9aac32f5d..197bf2dbe5de7e853ccddf2c90d8bff40202f025 100644 --- a/drivers/spi/spi-mt65xx.c +++ b/drivers/spi/spi-mt65xx.c @@ -961,7 +961,7 @@ static int mtk_spi_mem_exec_op(struct spi_mem *mem, mtk_spi_reset(mdata); mtk_spi_hw_init(mem->spi->controller, mem->spi); - mtk_spi_prepare_transfer(mem->spi->controller, mem->spi->max_speed_hz); + mtk_spi_prepare_transfer(mem->spi->controller, op->max_freq); reg_val = readl(mdata->base + SPI_CFG3_IPM_REG); /* opcode byte len */ @@ -1122,6 +1122,10 @@ static const struct spi_controller_mem_ops mtk_spi_mem_ops = { .exec_op = mtk_spi_mem_exec_op, }; +static const struct spi_controller_mem_caps mtk_spi_mem_caps = { + .per_op_freq = true, +}; + static int mtk_spi_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -1160,6 +1164,7 @@ static int mtk_spi_probe(struct platform_device *pdev) if (mdata->dev_comp->ipm_design) { mdata->dev = dev; host->mem_ops = &mtk_spi_mem_ops; + host->mem_caps = &mtk_spi_mem_caps; init_completion(&mdata->spimem_done); } From patchwork Tue Dec 24 17:05:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 853430 Received: from relay2-d.mail.gandi.net (relay2-d.mail.gandi.net [217.70.183.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D6FE82135D5; Tue, 24 Dec 2024 17:07:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.194 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735060041; cv=none; b=hk3lrasxy5I5asyijF+5mF121dYPYnkq1Ijp77FWW1aMRA9UKLStbqUc5nVJKVErNYGeLUZBOJjVRNrhF42QyG3s4ley7iosT718Z58oV0nUm00WqmIECA/yCMD/TuPqKG7yNN7y5Nf4F1tOjt3OQee0BFGaTKGnBxeHaBB1iIg= ARC-Message-Signature: i=1; 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Tue, 24 Dec 2024 17:07:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1735060038; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=fr6JNepud+tKAg7jOJTxXgDVqn2KcjPpqjlaMsDjliI=; b=CSkCFlGkm/AGyyqDWBoKC7f7WIvlY1M7GORyxbGUIKrt6+6czKidzsUbaL50gf93p9ddfS ZDqqJzVHIrU+0eS3KnqkFg1TLgu61zH9wAj7SXssYuQjZdV+Xz6PZEGNfDw37RqTWIbQ8x vSLtuog6dZuxiOd4/sEdwboRPu4qNi/P4c1X9KNUNcIBlnnrmXbI53nY8yVPe3N6oJ1srV BkxymrrotzeCoj0I7nF4KAX/dPmTd0mJ/P0jAz8/YNMUF2fhKS26pn+Cfn8tqMLznGUk3D sMdnGKR2Mf7E4llNfEReKSM6aKdGKK8Sa9GmbNuls5gBRTL8o7veelGjWtCVYw== From: Miquel Raynal Date: Tue, 24 Dec 2024 18:05:57 +0100 Subject: [PATCH v2 12/27] spi: nxp-fspi: Support per spi-mem operation frequency switches Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241224-winbond-6-11-rc1-quad-support-v2-12-ad218dbc406f@bootlin.com> References: <20241224-winbond-6-11-rc1-quad-support-v2-0-ad218dbc406f@bootlin.com> In-Reply-To: <20241224-winbond-6-11-rc1-quad-support-v2-0-ad218dbc406f@bootlin.com> To: Mark Brown , Sanjay R Mehta , Serge Semin , Han Xu , Conor Dooley , Daire McNamara , Matthias Brugger , AngeloGioacchino Del Regno , Haibo Chen , Yogesh Gaur , Heiko Stuebner , Michal Simek , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Jacky Huang , Shan-Chun Hung , Chin-Ting Kuo , =?utf-8?q?C=C3=A9dric_Le_Goa?= =?utf-8?q?ter?= , Joel Stanley , Andrew Jeffery , Avi Fishman , Tomer Maimon , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair , Maxime Coquelin , Alexandre Torgue , Raju Rangoju Cc: Thomas Petazzoni , Steam Lin , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-mtd@lists.infradead.org, linux-aspeed@lists.ozlabs.org, openbmc@lists.ozlabs.org, linux-stm32@st-md-mailman.stormreply.com X-Mailer: b4 0.15-dev X-GND-Sasl: miquel.raynal@bootlin.com Every ->exec_op() call correctly configures the spi bus speed to the maximum allowed frequency for the memory using the constant spi default parameter. Since we can now have per-operation constraints, let's use the value that comes from the spi-mem operation structure instead. In case there is no specific limitation for this operation, the default spi device value will be given anyway. The per-operation frequency capability is thus advertised to the spi-mem core. Cc: AngeloGioacchino Del Regno Signed-off-by: Miquel Raynal --- drivers/spi/spi-nxp-fspi.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/spi/spi-nxp-fspi.c b/drivers/spi/spi-nxp-fspi.c index 1161b9e5a4dce633718e22022410b5e7435bb51c..bad6b30bab0ecb90d0aaf603b6de5bc834d19de6 100644 --- a/drivers/spi/spi-nxp-fspi.c +++ b/drivers/spi/spi-nxp-fspi.c @@ -705,9 +705,10 @@ static void nxp_fspi_dll_calibration(struct nxp_fspi *f) * Value for rest of the CS FLSHxxCR0 register would be zero. * */ -static void nxp_fspi_select_mem(struct nxp_fspi *f, struct spi_device *spi) +static void nxp_fspi_select_mem(struct nxp_fspi *f, struct spi_device *spi, + const struct spi_mem_op *op) { - unsigned long rate = spi->max_speed_hz; + unsigned long rate = op->max_freq; int ret; uint64_t size_kb; @@ -931,7 +932,7 @@ static int nxp_fspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) FSPI_STS0_ARB_IDLE, 1, POLL_TOUT, true); WARN_ON(err); - nxp_fspi_select_mem(f, mem->spi); + nxp_fspi_select_mem(f, mem->spi, op); nxp_fspi_prepare_lut(f, op); /* @@ -1149,6 +1150,10 @@ static const struct spi_controller_mem_ops nxp_fspi_mem_ops = { .get_name = nxp_fspi_get_name, }; +static const struct spi_controller_mem_caps nxp_fspi_mem_caps = { + .per_op_freq = true, +}; + static int nxp_fspi_probe(struct platform_device *pdev) { struct spi_controller *ctlr; @@ -1246,6 +1251,7 @@ static int nxp_fspi_probe(struct platform_device *pdev) ctlr->bus_num = -1; ctlr->num_chipselect = NXP_FSPI_MAX_CHIPSELECT; ctlr->mem_ops = &nxp_fspi_mem_ops; + ctlr->mem_caps = &nxp_fspi_mem_caps; nxp_fspi_default_setup(f); From patchwork Tue Dec 24 17:05:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 853429 Received: from relay2-d.mail.gandi.net (relay2-d.mail.gandi.net [217.70.183.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CB681213E6B; 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Since we can now have per-operation constraints, let's use the value that comes from the spi-mem operation structure instead. In case there is no specific limitation for this operation, the default spi device value will be given anyway. The per-operation frequency capability is thus advertised to the spi-mem core. Signed-off-by: Miquel Raynal --- drivers/spi/spi-sn-f-ospi.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-sn-f-ospi.c b/drivers/spi/spi-sn-f-ospi.c index adac645732fedfe6e33a5a0979ba43d5d203bfce..6ad4b729897e3909a5e22b33aa47b812219a6ee5 100644 --- a/drivers/spi/spi-sn-f-ospi.c +++ b/drivers/spi/spi-sn-f-ospi.c @@ -335,7 +335,6 @@ static void f_ospi_config_indir_protocol(struct f_ospi *ospi, static int f_ospi_indir_prepare_op(struct f_ospi *ospi, struct spi_mem *mem, const struct spi_mem_op *op) { - struct spi_device *spi = mem->spi; u32 irq_stat_en; int ret; @@ -343,7 +342,7 @@ static int f_ospi_indir_prepare_op(struct f_ospi *ospi, struct spi_mem *mem, if (ret) return ret; - f_ospi_config_clk(ospi, spi->max_speed_hz); + f_ospi_config_clk(ospi, op->max_freq); f_ospi_config_indir_protocol(ospi, mem, op); @@ -577,6 +576,10 @@ static const struct spi_controller_mem_ops f_ospi_mem_ops = { .exec_op = f_ospi_exec_op, }; +static const struct spi_controller_mem_caps f_ospi_mem_caps = { + .per_op_freq = true, +}; + static int f_ospi_init(struct f_ospi *ospi) { int ret; @@ -614,6 +617,7 @@ static int f_ospi_probe(struct platform_device *pdev) | SPI_RX_DUAL | SPI_RX_QUAD | SPI_RX_OCTAL | SPI_MODE_0 | SPI_MODE_1 | SPI_LSB_FIRST; ctlr->mem_ops = &f_ospi_mem_ops; + ctlr->mem_caps = &f_ospi_mem_caps; ctlr->bus_num = -1; of_property_read_u32(dev->of_node, "num-cs", &num_cs); if (num_cs > OSPI_NUM_CS) { From patchwork Tue Dec 24 17:06:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 853428 Received: from relay2-d.mail.gandi.net (relay2-d.mail.gandi.net [217.70.183.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D1D35214203; Tue, 24 Dec 2024 17:07:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.194 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; 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spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="o9cmLlei" Received: by mail.gandi.net (Postfix) with ESMTPSA id 4653940002; Tue, 24 Dec 2024 17:07:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1735060058; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=nrGU5YmafXBcwzax7Dz7/fkc5aKf/Lo+6Qt8hqq78ww=; b=o9cmLlei4SVjACmnx8b9OR17EDa9MM8UqcY95EsA75X6fF5V55vjDRjx6S/m4N5rv61PMV Qg9pjzjzdnmwCj+bdQwuOGNte7wETrmUz1JOty5bUgGke0N/UaoI5+vkTHK8LVw1T1IVuz PQ1Zkmxrnc+Bmwr1g9lLsFzQ8jojwMNwizGoU1g/UAmb4oCUUwbk8++N6d5oGjFLJWrcEn 3HnOM41v0tL1h/opiKnYgNKlhdAHzmF8LniGkL7z0LekHLcYNF6+PTROTXb8l2HMCujaZC EnuGOoTh4fSBqmWqCn4QNi5iGH2SEtsVBQfOy0yAAO0hOu7vW8682g/tQCB+ig== From: Miquel Raynal Date: Tue, 24 Dec 2024 18:06:01 +0100 Subject: [PATCH v2 16/27] spi: zynq-qspi: Support per spi-mem operation frequency switches Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241224-winbond-6-11-rc1-quad-support-v2-16-ad218dbc406f@bootlin.com> References: <20241224-winbond-6-11-rc1-quad-support-v2-0-ad218dbc406f@bootlin.com> In-Reply-To: <20241224-winbond-6-11-rc1-quad-support-v2-0-ad218dbc406f@bootlin.com> To: Mark Brown , Sanjay R Mehta , Serge Semin , Han Xu , Conor Dooley , Daire McNamara , Matthias Brugger , AngeloGioacchino Del Regno , Haibo Chen , Yogesh Gaur , Heiko Stuebner , Michal Simek , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Jacky Huang , Shan-Chun Hung , Chin-Ting Kuo , =?utf-8?q?C=C3=A9dric_Le_Goa?= =?utf-8?q?ter?= , Joel Stanley , Andrew Jeffery , Avi Fishman , Tomer Maimon , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair , Maxime Coquelin , Alexandre Torgue , Raju Rangoju Cc: Thomas Petazzoni , Steam Lin , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-mtd@lists.infradead.org, linux-aspeed@lists.ozlabs.org, openbmc@lists.ozlabs.org, linux-stm32@st-md-mailman.stormreply.com X-Mailer: b4 0.15-dev X-GND-Sasl: miquel.raynal@bootlin.com Every ->exec_op() call correctly configures the spi bus speed to the maximum allowed frequency for the memory using the constant spi default parameter. Since we can now have per-operation constraints, let's use the value that comes from the spi-mem operation structure instead. In case there is no specific limitation for this operation, the default spi device value will be given anyway. The per-operation frequency capability is thus advertised to the spi-mem core. Cc: Heiko Stuebner Signed-off-by: Miquel Raynal --- drivers/spi/spi-zynq-qspi.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/spi/spi-zynq-qspi.c b/drivers/spi/spi-zynq-qspi.c index dee9c339a35e74c86fe1c768990a3f870b0a1b9d..f3cacb01e25b97892f9fbefc6e5cf43b9722ae4d 100644 --- a/drivers/spi/spi-zynq-qspi.c +++ b/drivers/spi/spi-zynq-qspi.c @@ -318,6 +318,7 @@ static void zynq_qspi_chipselect(struct spi_device *spi, bool assert) * zynq_qspi_config_op - Configure QSPI controller for specified transfer * @xqspi: Pointer to the zynq_qspi structure * @spi: Pointer to the spi_device structure + * @op: The memory operation to execute * * Sets the operational mode of QSPI controller for the next QSPI transfer and * sets the requested clock frequency. @@ -331,7 +332,8 @@ static void zynq_qspi_chipselect(struct spi_device *spi, bool assert) * controller the driver will set the highest or lowest frequency supported by * controller. */ -static int zynq_qspi_config_op(struct zynq_qspi *xqspi, struct spi_device *spi) +static int zynq_qspi_config_op(struct zynq_qspi *xqspi, struct spi_device *spi, + const struct spi_mem_op *op) { u32 config_reg, baud_rate_val = 0; @@ -346,7 +348,7 @@ static int zynq_qspi_config_op(struct zynq_qspi *xqspi, struct spi_device *spi) */ while ((baud_rate_val < ZYNQ_QSPI_CONFIG_BAUD_DIV_MAX) && (clk_get_rate(xqspi->refclk) / (2 << baud_rate_val)) > - spi->max_speed_hz) + op->max_freq) baud_rate_val++; config_reg = zynq_qspi_read(xqspi, ZYNQ_QSPI_CONFIG_OFFSET); @@ -534,7 +536,7 @@ static int zynq_qspi_exec_mem_op(struct spi_mem *mem, op->dummy.buswidth, op->data.buswidth); zynq_qspi_chipselect(mem->spi, true); - zynq_qspi_config_op(xqspi, mem->spi); + zynq_qspi_config_op(xqspi, mem->spi, op); if (op->cmd.opcode) { reinit_completion(&xqspi->data_completion); @@ -620,6 +622,10 @@ static const struct spi_controller_mem_ops zynq_qspi_mem_ops = { .exec_op = zynq_qspi_exec_mem_op, }; +static const struct spi_controller_mem_caps zynq_qspi_mem_caps = { + .per_op_freq = true, +}; + /** * zynq_qspi_probe - Probe method for the QSPI driver * @pdev: Pointer to the platform_device structure @@ -706,6 +712,7 @@ static int zynq_qspi_probe(struct platform_device *pdev) ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | SPI_TX_DUAL | SPI_TX_QUAD; ctlr->mem_ops = &zynq_qspi_mem_ops; + ctlr->mem_caps = &zynq_qspi_mem_caps; ctlr->setup = zynq_qspi_setup_op; ctlr->max_speed_hz = clk_get_rate(xqspi->refclk) / 2; ctlr->dev.of_node = np; From patchwork Tue Dec 24 17:06:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 853427 Received: from relay2-d.mail.gandi.net (relay2-d.mail.gandi.net [217.70.183.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 84AFD214229; Tue, 24 Dec 2024 17:07:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.194 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735060070; cv=none; b=eOENgl7IN0MKBM6hjlHm5/JIjxRh0cw2Rxq1Wnrxd5Box1tKenZ2A6qniqNsuvM5hbzqC9DodagZLDb1+kLM2sDkISZnO+G9rCJ0ZUEASOPzbF905PM9GkR1UyiZNuoYbJJ7lQgG1Aqn+I+hPdGIGEicxDOL0Q9Qfq7WTp8GhxI= ARC-Message-Signature: i=1; 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Tue, 24 Dec 2024 17:07:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1735060067; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=EpRU8Ni8GjnsQQyxRFEa2zYtIybiX1a/U99sUmUB8ik=; b=hpz+wZ9Xf8dFstk/m+YyNBOA1jU16WXt02YuZEB13we+5AlHozMgcgGEt7XH7QAEBKrt4x pdQv7bfGYC8qZKodCkYH2txGARNmwJ6GlCQSVbJtyIeV77++Sflj0z5mJRvEWXOAqFAj0S AlnkwnsFo08U2zyXnpc83ybVzOrrdRzAC09kJseKDFdJCb94rzJpqgvRIOE59peLIaG/Bc GkH11Oo+GM/gd8rOV0W+cbrCPLb44BGEr8k3icqi3IqhevGe9ICRVjcqrlaHoAviIHFPtT 7ptIjZcrtfR2ssUUlTyzEgJ5LL8zTQWWIaqzQvXH6aTYV2OSptcNulufYIvReA== From: Miquel Raynal Date: Tue, 24 Dec 2024 18:06:03 +0100 Subject: [PATCH v2 18/27] spi: spi-mem: Reorder spi-mem macro assignments Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241224-winbond-6-11-rc1-quad-support-v2-18-ad218dbc406f@bootlin.com> References: <20241224-winbond-6-11-rc1-quad-support-v2-0-ad218dbc406f@bootlin.com> In-Reply-To: <20241224-winbond-6-11-rc1-quad-support-v2-0-ad218dbc406f@bootlin.com> To: Mark Brown , Sanjay R Mehta , Serge Semin , Han Xu , Conor Dooley , Daire McNamara , Matthias Brugger , AngeloGioacchino Del Regno , Haibo Chen , Yogesh Gaur , Heiko Stuebner , Michal Simek , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Jacky Huang , Shan-Chun Hung , Chin-Ting Kuo , =?utf-8?q?C=C3=A9dric_Le_Goa?= =?utf-8?q?ter?= , Joel Stanley , Andrew Jeffery , Avi Fishman , Tomer Maimon , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair , Maxime Coquelin , Alexandre Torgue , Raju Rangoju Cc: Thomas Petazzoni , Steam Lin , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-mtd@lists.infradead.org, linux-aspeed@lists.ozlabs.org, openbmc@lists.ozlabs.org, linux-stm32@st-md-mailman.stormreply.com X-Mailer: b4 0.15-dev X-GND-Sasl: miquel.raynal@bootlin.com Follow the order in which all the `struct spi_mem_op` members are defined. This is purely aesthetics, there is no functional change. Signed-off-by: Miquel Raynal --- include/linux/spi/spi-mem.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/include/linux/spi/spi-mem.h b/include/linux/spi/spi-mem.h index c7a7719c264846ad9fce613ba96d9284ad7893e7..ca6ea01c40f85095ac2730cb424cfb21d7daa700 100644 --- a/include/linux/spi/spi-mem.h +++ b/include/linux/spi/spi-mem.h @@ -15,16 +15,16 @@ #define SPI_MEM_OP_CMD(__opcode, __buswidth) \ { \ + .nbytes = 1, \ .buswidth = __buswidth, \ .opcode = __opcode, \ - .nbytes = 1, \ } #define SPI_MEM_OP_ADDR(__nbytes, __val, __buswidth) \ { \ .nbytes = __nbytes, \ - .val = __val, \ .buswidth = __buswidth, \ + .val = __val, \ } #define SPI_MEM_OP_NO_ADDR { } @@ -39,18 +39,18 @@ #define SPI_MEM_OP_DATA_IN(__nbytes, __buf, __buswidth) \ { \ + .buswidth = __buswidth, \ .dir = SPI_MEM_DATA_IN, \ .nbytes = __nbytes, \ .buf.in = __buf, \ - .buswidth = __buswidth, \ } #define SPI_MEM_OP_DATA_OUT(__nbytes, __buf, __buswidth) \ { \ + .buswidth = __buswidth, \ .dir = SPI_MEM_DATA_OUT, \ .nbytes = __nbytes, \ .buf.out = __buf, \ - .buswidth = __buswidth, \ } #define SPI_MEM_OP_NO_DATA { } From patchwork Tue Dec 24 17:06:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 853426 Received: from relay2-d.mail.gandi.net (relay2-d.mail.gandi.net [217.70.183.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 12AFA2144BC; Tue, 24 Dec 2024 17:07:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.194 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735060080; cv=none; b=oOrX6OiN7BiBYGbPtuHDlJu5tcNBNh+XphXDDH6DmGPFTb2rGw+bbJQslY7VAE0galN+raA7ENup2CFjBFK+7O6AMR968VuDvD/5EFfM90JBgtsD9GHy+VMqFY3OagQM2WFkiV31/djYTs3c2G1vAixBM8AN8aqBCk7uCOk7a/w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735060080; c=relaxed/simple; bh=W1aAkAWZPMCLJ3WbD/0dMBdUSq6fmF7MOdurXGYmIHA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; 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bh=VzPEJXwTtX4trhn4jiSXKCMpEB5Y/gw2NHlQipYlhDw=; b=EzF2TBztddoKYRFhcVtq8rq/rg+jTFBz9rODvimhcXvHvXfu+GHbgH0M07v8SJOsvYkb5/ azHgKUXYrRaGpvifsZI/6x52aHsGWwNyT3bBorvLjJrSGX+Dsg//+fzBoMtIoWdRgUDA2t niAwU/bCugZRReTXZ19Wuhe61iFT3y0yiAFN/WcAGNDBCFaO2/2Pk+darLR5Z64w/KmNVx e1TGhyebkHmosHM9EPv+G9yigrrNL0KS+gw4Pt/gmCZffAOn1Hdv1qzSi5IwDL2Kznh4wS Bii8S97vU8+7vHFR4RxslHDM/VaNj4Nf2jWo9AnN/auRec87X1NVVjynykdIpA== From: Miquel Raynal Date: Tue, 24 Dec 2024 18:06:05 +0100 Subject: [PATCH v2 20/27] spi: spi-mem: Estimate the time taken by operations Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241224-winbond-6-11-rc1-quad-support-v2-20-ad218dbc406f@bootlin.com> References: <20241224-winbond-6-11-rc1-quad-support-v2-0-ad218dbc406f@bootlin.com> In-Reply-To: <20241224-winbond-6-11-rc1-quad-support-v2-0-ad218dbc406f@bootlin.com> To: Mark Brown , Sanjay R Mehta , Serge Semin , Han Xu , Conor Dooley , Daire McNamara , Matthias Brugger , AngeloGioacchino Del Regno , Haibo Chen , Yogesh Gaur , Heiko Stuebner , Michal Simek , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Jacky Huang , Shan-Chun Hung , Chin-Ting Kuo , =?utf-8?q?C=C3=A9dric_Le_Goa?= =?utf-8?q?ter?= , Joel Stanley , Andrew Jeffery , Avi Fishman , Tomer Maimon , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair , Maxime Coquelin , Alexandre Torgue , Raju Rangoju Cc: Thomas Petazzoni , Steam Lin , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-mtd@lists.infradead.org, linux-aspeed@lists.ozlabs.org, openbmc@lists.ozlabs.org, linux-stm32@st-md-mailman.stormreply.com X-Mailer: b4 0.15-dev X-GND-Sasl: miquel.raynal@bootlin.com In the SPI-NAND layer, we currently make list of operation variants from the fastest one to the slowest and there is a bit of logic in the core to go over them and pick the first one that is supported by the controller, ie. the fastest one among the supported ops. This kind of logic only works if all operations run at the same frequency, but as soon as we introduce per operation max frequencies it is not longer as obvious which operation will be faster, especially since it also depends on the PCB/controller frequency limitation. One way to make this choice more clever is to go over all the variants and for each of them derive an indicator which will help derive the theoretical best. In this case, we derive a theoretical duration for the entire operation and we take the smallest one. Add a helper that parses the spi-mem operation and returns this value. Signed-off-by: Miquel Raynal --- drivers/spi/spi-mem.c | 30 ++++++++++++++++++++++++++++++ include/linux/spi/spi-mem.h | 1 + 2 files changed, 31 insertions(+) diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c index 96374afd0193ca2cf4f50004f66c36dce32894e8..a9f0f47f4759b0e1ce22348e713a3b42cfb8ea9c 100644 --- a/drivers/spi/spi-mem.c +++ b/drivers/spi/spi-mem.c @@ -562,6 +562,36 @@ void spi_mem_adjust_op_freq(struct spi_mem *mem, struct spi_mem_op *op) } EXPORT_SYMBOL_GPL(spi_mem_adjust_op_freq); +/** + * spi_mem_calc_op_duration() - Derives the theoretical length (in ns) of an + * operation. This helps finding the best variant + * among a list of possible choices. + * @op: the operation to benchmark + * + * Some chips have per-op frequency limitations, PCBs usually have their own + * limitations as well, and controllers can support dual, quad or even octal + * modes, sometimes in DTR. All these combinations make it impossible to + * statically list the best combination for all situations. If we want something + * accurate, all these combinations should be rated (eg. with a time estimate) + * and the best pick should be taken based on these calculations. + * + * Returns a ns estimate for the time this op would take. + */ +u64 spi_mem_calc_op_duration(struct spi_mem_op *op) +{ + u64 ncycles = 0; + u32 ns_per_cycles; + + ns_per_cycles = 1000000000 / op->max_freq; + ncycles += ((op->cmd.nbytes * 8) / op->cmd.buswidth) / (op->cmd.dtr ? 2 : 1); + ncycles += ((op->addr.nbytes * 8) / op->addr.buswidth) / (op->addr.dtr ? 2 : 1); + ncycles += ((op->dummy.nbytes * 8) / op->dummy.buswidth) / (op->dummy.dtr ? 2 : 1); + ncycles += ((op->data.nbytes * 8) / op->data.buswidth) / (op->data.dtr ? 2 : 1); + + return ncycles * ns_per_cycles; +} +EXPORT_SYMBOL_GPL(spi_mem_calc_op_duration); + static ssize_t spi_mem_no_dirmap_read(struct spi_mem_dirmap_desc *desc, u64 offs, size_t len, void *buf) { diff --git a/include/linux/spi/spi-mem.h b/include/linux/spi/spi-mem.h index 306c05dd13789017da2c5339cddc031f03302bb9..82390712794c5a4dcef1319c19d74b77b6e1e724 100644 --- a/include/linux/spi/spi-mem.h +++ b/include/linux/spi/spi-mem.h @@ -424,6 +424,7 @@ bool spi_mem_default_supports_op(struct spi_mem *mem, int spi_mem_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op); void spi_mem_adjust_op_freq(struct spi_mem *mem, struct spi_mem_op *op); +u64 spi_mem_calc_op_duration(struct spi_mem *mem, struct spi_mem_op *op); bool spi_mem_supports_op(struct spi_mem *mem, const struct spi_mem_op *op); From patchwork Tue Dec 24 17:06:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 853425 Received: from relay2-d.mail.gandi.net (relay2-d.mail.gandi.net [217.70.183.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 88938212D6B; Tue, 24 Dec 2024 17:08:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.194 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735060088; cv=none; b=WWBURMvkuAYYMfmNLrG2dICdQcVUZFYIrfYqD61VRtPRVhU1X/gVFDnWFsTkfEtn6PYUlxeJgjod1mR6rI8J9YFJYFDyOddZ3XLNNdmfsx+2oxiosJtjqLtxBSm414+xac9A+l7360FitEB5viEQ7PAhCBaBu3Y8uDwgOFtazGk= ARC-Message-Signature: i=1; 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Tue, 24 Dec 2024 17:08:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1735060085; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=+4OsasNx8lhobCm5ORTBJQ6wBy7WkLnmvrsNMBWmSJ4=; b=Bzx8EfmHiwZa5evAKhuHzFGByKQK+6zDdGV+b5AUFTMeWY2TvOSxI9RxY04NNOg+9i2uJ7 7QLwCGd8mJLoUXAZX1/Ko87uyYIcHxsJ4vqdqC3if3qLJJtkj8XPuVgaXkfHoX8RM/1UhL IPJNcKey+8qBTIiX4QsGhLnSsjquwzQWVKflqEvt5uqVGFzEr6tYvaNpzusa+yCRa5Lq16 YkJemgbFsUbxTmsm2TycV+PjQg1qd5iFJ0zKFZbjXLF9+XAwfKmms0K6y8ANtEiX9Ygx/F JNh5x3zy0dTkP8BKZLED4xrBcEVn2WHVqQLm0liqHOIahWU7xZ4PKxeSxzyLWw== From: Miquel Raynal Date: Tue, 24 Dec 2024 18:06:07 +0100 Subject: [PATCH v2 22/27] mtd: spinand: Add an optional frequency to read from cache macros Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241224-winbond-6-11-rc1-quad-support-v2-22-ad218dbc406f@bootlin.com> References: <20241224-winbond-6-11-rc1-quad-support-v2-0-ad218dbc406f@bootlin.com> In-Reply-To: <20241224-winbond-6-11-rc1-quad-support-v2-0-ad218dbc406f@bootlin.com> To: Mark Brown , Sanjay R Mehta , Serge Semin , Han Xu , Conor Dooley , Daire McNamara , Matthias Brugger , AngeloGioacchino Del Regno , Haibo Chen , Yogesh Gaur , Heiko Stuebner , Michal Simek , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Jacky Huang , Shan-Chun Hung , Chin-Ting Kuo , =?utf-8?q?C=C3=A9dric_Le_Goa?= =?utf-8?q?ter?= , Joel Stanley , Andrew Jeffery , Avi Fishman , Tomer Maimon , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair , Maxime Coquelin , Alexandre Torgue , Raju Rangoju Cc: Thomas Petazzoni , Steam Lin , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-mtd@lists.infradead.org, linux-aspeed@lists.ozlabs.org, openbmc@lists.ozlabs.org, linux-stm32@st-md-mailman.stormreply.com X-Mailer: b4 0.15-dev X-GND-Sasl: miquel.raynal@bootlin.com While the SPINAND_PAGE_READ_FROM_CACHE_FAST_OP macro is supposed to be able to run at the flash highest supported frequency, it is not the case of the regular read from cache, which may be limited in terms of maximum frequency. Add an optional argument to this macro, which will be used to set the maximum frequency, if any. Signed-off-by: Miquel Raynal --- include/linux/mtd/spinand.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h index 63c89307c86524143913660c66ec4fe4375904f8..1948e654b8aacb3d4b774a00939e8e8198f53da7 100644 --- a/include/linux/mtd/spinand.h +++ b/include/linux/mtd/spinand.h @@ -62,11 +62,12 @@ SPI_MEM_OP_NO_DUMMY, \ SPI_MEM_OP_NO_DATA) -#define SPINAND_PAGE_READ_FROM_CACHE_OP(addr, ndummy, buf, len) \ +#define SPINAND_PAGE_READ_FROM_CACHE_OP(addr, ndummy, buf, len, ...) \ SPI_MEM_OP(SPI_MEM_OP_CMD(0x03, 1), \ SPI_MEM_OP_ADDR(2, addr, 1), \ SPI_MEM_OP_DUMMY(ndummy, 1), \ - SPI_MEM_OP_DATA_IN(len, buf, 1)) + SPI_MEM_OP_DATA_IN(len, buf, 1), \ + __VA_OPT__(SPI_MEM_OP_MAX_FREQ(__VA_ARGS__))) #define SPINAND_PAGE_READ_FROM_CACHE_FAST_OP(addr, ndummy, buf, len) \ SPI_MEM_OP(SPI_MEM_OP_CMD(0x0b, 1), \ From patchwork Tue Dec 24 17:06:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 853424 Received: from relay2-d.mail.gandi.net (relay2-d.mail.gandi.net [217.70.183.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7AB3D214802; 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arc=none smtp.client-ip=217.70.183.194 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="NWeSscwS" Received: by mail.gandi.net (Postfix) with ESMTPSA id 990F240004; Tue, 24 Dec 2024 17:08:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1735060094; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=eSDAGRiX5uW2hASEynfGv8MA56J5pas3+2b3+3jgoTI=; b=NWeSscwSHEiYDed758p0Sz7XLYoEmgcCUuMG2FxPUiP+UjMSiZa4CUEYTHJ81jbA99oCbK pU6KGwB8IU0mhnIAF9uLp46iZ/AyGA/1u4sS0VhvK0B0WTgbseJ86J5S0WU0gugJXlRmxV 2Tix99EFRBVeDdcTNWk1bQrBF/Xj4JgoxMn2P/B1x9W+0leLiRjfSq1Zag7rwcSMoCbgV/ mprDs8N1a8v2MubogrOEhBzP1HPe8Dd3yaM6IBYd1DpifyEJhUpoxaS0Jt7MqYuJskjY+X IIpVOJrU1O/YsOFzilsjoxVjbs3/Ff0lwoEPD3Gl+LPluVfhNH/HOVV5WLW5/Q== From: Miquel Raynal Date: Tue, 24 Dec 2024 18:06:09 +0100 Subject: [PATCH v2 24/27] mtd: spinand: Add support for read DTR operations Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241224-winbond-6-11-rc1-quad-support-v2-24-ad218dbc406f@bootlin.com> References: <20241224-winbond-6-11-rc1-quad-support-v2-0-ad218dbc406f@bootlin.com> In-Reply-To: <20241224-winbond-6-11-rc1-quad-support-v2-0-ad218dbc406f@bootlin.com> To: Mark Brown , Sanjay R Mehta , Serge Semin , Han Xu , Conor Dooley , Daire McNamara , Matthias Brugger , AngeloGioacchino Del Regno , Haibo Chen , Yogesh Gaur , Heiko Stuebner , Michal Simek , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Jacky Huang , Shan-Chun Hung , Chin-Ting Kuo , =?utf-8?q?C=C3=A9dric_Le_Goa?= =?utf-8?q?ter?= , Joel Stanley , Andrew Jeffery , Avi Fishman , Tomer Maimon , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair , Maxime Coquelin , Alexandre Torgue , Raju Rangoju Cc: Thomas Petazzoni , Steam Lin , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-mtd@lists.infradead.org, linux-aspeed@lists.ozlabs.org, openbmc@lists.ozlabs.org, linux-stm32@st-md-mailman.stormreply.com X-Mailer: b4 0.15-dev X-GND-Sasl: miquel.raynal@bootlin.com Advanced SPI-NAND chips are capable of reading data much faster by leveraging DTR support. This support extends to dual and quad configurations. Create macros defining all possible read from cache DTR variants: - SPINAND_PAGE_READ_FROM_CACHE_DTR_OP - SPINAND_PAGE_READ_FROM_CACHE_X2_DTR_OP - SPINAND_PAGE_READ_FROM_CACHE_X4_DTR_OP - SPINAND_PAGE_READ_FROM_CACHE_DUALIO_DTR_OP - SPINAND_PAGE_READ_FROM_CACHE_QUADIO_DTR_OP Signed-off-by: Miquel Raynal --- include/linux/mtd/spinand.h | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h index 1948e654b8aacb3d4b774a00939e8e8198f53da7..eeabf4a17c578405550fcc1ed1653f9ef09b5ff6 100644 --- a/include/linux/mtd/spinand.h +++ b/include/linux/mtd/spinand.h @@ -87,6 +87,13 @@ SPI_MEM_OP_DUMMY(ndummy, 1), \ SPI_MEM_OP_DATA_IN(len, buf, 1)) +#define SPINAND_PAGE_READ_FROM_CACHE_DTR_OP(addr, ndummy, buf, len, freq) \ + SPI_MEM_OP(SPI_MEM_OP_CMD(0x0d, 1), \ + SPI_MEM_DTR_OP_ADDR(2, addr, 1), \ + SPI_MEM_DTR_OP_DUMMY(ndummy, 1), \ + SPI_MEM_DTR_OP_DATA_IN(len, buf, 1), \ + SPI_MEM_OP_MAX_FREQ(freq)) + #define SPINAND_PAGE_READ_FROM_CACHE_X2_OP(addr, ndummy, buf, len) \ SPI_MEM_OP(SPI_MEM_OP_CMD(0x3b, 1), \ SPI_MEM_OP_ADDR(2, addr, 1), \ @@ -99,6 +106,13 @@ SPI_MEM_OP_DUMMY(ndummy, 1), \ SPI_MEM_OP_DATA_IN(len, buf, 2)) +#define SPINAND_PAGE_READ_FROM_CACHE_X2_DTR_OP(addr, ndummy, buf, len, freq) \ + SPI_MEM_OP(SPI_MEM_OP_CMD(0x3d, 1), \ + SPI_MEM_DTR_OP_ADDR(2, addr, 1), \ + SPI_MEM_DTR_OP_DUMMY(ndummy, 1), \ + SPI_MEM_DTR_OP_DATA_IN(len, buf, 2), \ + SPI_MEM_OP_MAX_FREQ(freq)) + #define SPINAND_PAGE_READ_FROM_CACHE_X4_OP(addr, ndummy, buf, len) \ SPI_MEM_OP(SPI_MEM_OP_CMD(0x6b, 1), \ SPI_MEM_OP_ADDR(2, addr, 1), \ @@ -111,6 +125,13 @@ SPI_MEM_OP_DUMMY(ndummy, 1), \ SPI_MEM_OP_DATA_IN(len, buf, 4)) +#define SPINAND_PAGE_READ_FROM_CACHE_X4_DTR_OP(addr, ndummy, buf, len, freq) \ + SPI_MEM_OP(SPI_MEM_OP_CMD(0x6d, 1), \ + SPI_MEM_DTR_OP_ADDR(2, addr, 1), \ + SPI_MEM_DTR_OP_DUMMY(ndummy, 1), \ + SPI_MEM_DTR_OP_DATA_IN(len, buf, 4), \ + SPI_MEM_OP_MAX_FREQ(freq)) + #define SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(addr, ndummy, buf, len) \ SPI_MEM_OP(SPI_MEM_OP_CMD(0xbb, 1), \ SPI_MEM_OP_ADDR(2, addr, 2), \ @@ -123,6 +144,13 @@ SPI_MEM_OP_DUMMY(ndummy, 2), \ SPI_MEM_OP_DATA_IN(len, buf, 2)) +#define SPINAND_PAGE_READ_FROM_CACHE_DUALIO_DTR_OP(addr, ndummy, buf, len, freq) \ + SPI_MEM_OP(SPI_MEM_OP_CMD(0xbd, 1), \ + SPI_MEM_DTR_OP_ADDR(2, addr, 2), \ + SPI_MEM_DTR_OP_DUMMY(ndummy, 2), \ + SPI_MEM_DTR_OP_DATA_IN(len, buf, 2), \ + SPI_MEM_OP_MAX_FREQ(freq)) + #define SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(addr, ndummy, buf, len) \ SPI_MEM_OP(SPI_MEM_OP_CMD(0xeb, 1), \ SPI_MEM_OP_ADDR(2, addr, 4), \ @@ -135,6 +163,13 @@ SPI_MEM_OP_DUMMY(ndummy, 4), \ SPI_MEM_OP_DATA_IN(len, buf, 4)) +#define SPINAND_PAGE_READ_FROM_CACHE_QUADIO_DTR_OP(addr, ndummy, buf, len, freq) \ + SPI_MEM_OP(SPI_MEM_OP_CMD(0xed, 1), \ + SPI_MEM_DTR_OP_ADDR(2, addr, 4), \ + SPI_MEM_DTR_OP_DUMMY(ndummy, 4), \ + SPI_MEM_DTR_OP_DATA_IN(len, buf, 4), \ + SPI_MEM_OP_MAX_FREQ(freq)) + #define SPINAND_PROG_EXEC_OP(addr) \ SPI_MEM_OP(SPI_MEM_OP_CMD(0x10, 1), \ SPI_MEM_OP_ADDR(3, addr, 1), \ From patchwork Tue Dec 24 17:06:11 2024 Content-Type: text/plain; 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bh=+afwOEQnbaba+LXNGTuAYGtAsSXdRwU1zxfezGFUpKo=; b=d0I+Ib/8YxcbnQcn2sSQWaONcDnUHh95Y9JAP+oVs5WXmg2Uy0E5rDGRGpBGrDUJEyXQon VxhiFm+4tYji9gfM7q8vOOnXLtn+IvHFMGbNkB7dzoEczXAsiFUlyn4zrnLALlp1Ce0Jlu Hw9d4UR7pSwa/0gyR+riIqoOgQyQXFb5tRp2R2K3Xa3yjB3oZK0MekHyBcKnbdzkQy9sNJ E0XAxwcMD6aGjkrFFhK74YZt8QwlIhwb0Z1w6mNo9dmz4p4dEnC5gJB/4Cle4brwrReQAN TCisk9Cu9cEY8OTBN0HgMsbouJ6mBlOzAoR85kwDXQ5vlT5VbKdRcGLUnqSGcA== From: Miquel Raynal Date: Tue, 24 Dec 2024 18:06:11 +0100 Subject: [PATCH v2 26/27] mtd: spinand: winbond: Add comment about naming Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241224-winbond-6-11-rc1-quad-support-v2-26-ad218dbc406f@bootlin.com> References: <20241224-winbond-6-11-rc1-quad-support-v2-0-ad218dbc406f@bootlin.com> In-Reply-To: <20241224-winbond-6-11-rc1-quad-support-v2-0-ad218dbc406f@bootlin.com> To: Mark Brown , Sanjay R Mehta , Serge Semin , Han Xu , Conor Dooley , Daire McNamara , Matthias Brugger , AngeloGioacchino Del Regno , Haibo Chen , Yogesh Gaur , Heiko Stuebner , Michal Simek , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Jacky Huang , Shan-Chun Hung , Chin-Ting Kuo , =?utf-8?q?C=C3=A9dric_Le_Goa?= =?utf-8?q?ter?= , Joel Stanley , Andrew Jeffery , Avi Fishman , Tomer Maimon , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair , Maxime Coquelin , Alexandre Torgue , Raju Rangoju Cc: Thomas Petazzoni , Steam Lin , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-mtd@lists.infradead.org, linux-aspeed@lists.ozlabs.org, openbmc@lists.ozlabs.org, linux-stm32@st-md-mailman.stormreply.com X-Mailer: b4 0.15-dev X-GND-Sasl: miquel.raynal@bootlin.com Make the link between the core macros and the datasheet. Signed-off-by: Miquel Raynal --- drivers/mtd/nand/spi/winbond.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/mtd/nand/spi/winbond.c b/drivers/mtd/nand/spi/winbond.c index 97517d495e57a6e9e616ed7e66b4a8e9fc1fe62a..51972ba0f193c7b27ece0296c1590ddfed0ac813 100644 --- a/drivers/mtd/nand/spi/winbond.c +++ b/drivers/mtd/nand/spi/winbond.c @@ -18,6 +18,11 @@ #define W25N04KV_STATUS_ECC_5_8_BITFLIPS (3 << 4) +/* + * "X2" in the core is equivalent to "dual output" in the datasheets, + * "X4" in the core is equivalent to "quad output" in the datasheets. + */ + static SPINAND_OP_VARIANTS(read_cache_dtr_variants, SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0), SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),