From patchwork Fri Dec 20 21:36:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sohil Mehta X-Patchwork-Id: 852500 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F0128157A48; Fri, 20 Dec 2024 21:39:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734730758; cv=none; b=J4HYl/OwVd5IxRiaP3LUfziJDj1ePd/8jOsC7/W3O5a2GG7jOU7bTXHX/G0Wl+a6Qvp/MEOCQXubepIzharDoWdiayu4YoYnM6TeZnGBFn7wJLUbt+76J294z1beh8zc23HzeG1ub5PrUH8eaMxttz0173nXJoTaSBNsfpo+XEQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734730758; c=relaxed/simple; bh=WGLszqkcK4qS7XxdeQwaV9JLA+JQQF8TjunUmB8Arzk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=hfNJ+kJrq3fEwsbRDoSeuqxLap2tZIl4w76u3vbKvP6tWNvzckuMf++8EYicwsQjk6xZMQLl5QY7F1D5uNc4lOGywlL78qHONvQDbBcFbJrFjA9ACnbkyBoKDF8qL9aEJfbvbKEbvJDLV39bGlMxkWHyvBdWQTBKMYjM+JTc2og= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=QnIaGu5V; arc=none smtp.client-ip=198.175.65.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="QnIaGu5V" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1734730757; x=1766266757; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=WGLszqkcK4qS7XxdeQwaV9JLA+JQQF8TjunUmB8Arzk=; b=QnIaGu5VrJHl8Fr7spuz2bIMVgllyN6qvLPazvhzVkid/X0+7Ymmgnao vMSH22z7yDbp3YZWEBnbndWQbpd8LKvyHtHDIn2NwtRJdLjSnx4Qhp3GJ ynsLzhrFv+2O3wyjA4PoejSYQKtff0NfCXovdu0+d/pba1ATbBAdfdUVS NdOKnfAFduU3HJR1xeOPaTcPZtfKDZX/XeCwtVml8oSfZ5I1FJMhCNy69 gk9Sga+5ZjIl1sMZXzLILRk6XlsM4b9a1PpO5VEFqWRGDs50RyEcowGHk 78/QoAi+iOMETOiUJEC+aMIHxJyuSEswP8WiLMZXF/yUNIA/DGX4cnoMZ A==; X-CSE-ConnectionGUID: QYQxpPyrT+CHS+mVIbks2Q== X-CSE-MsgGUID: WRoyM0OfTg+EJA3GhdPK4w== X-IronPort-AV: E=McAfee;i="6700,10204,11292"; a="39070617" X-IronPort-AV: E=Sophos;i="6.12,251,1728975600"; d="scan'208";a="39070617" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Dec 2024 13:39:15 -0800 X-CSE-ConnectionGUID: /tMvC+22Rb+rT6uaVbKJBQ== X-CSE-MsgGUID: vrXDA1jARrSxFxpmx5mnvw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="103223826" Received: from sohilmeh.sc.intel.com ([172.25.103.65]) by fmviesa005.fm.intel.com with ESMTP; 20 Dec 2024 13:39:14 -0800 From: Sohil Mehta To: x86@kernel.org, Dave Hansen , Tony Luck Cc: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , Thomas Gleixner , Borislav Petkov , "H . Peter Anvin" , "Rafael J . Wysocki" , Len Brown , Andy Lutomirski , Viresh Kumar , Fenghua Yu , Jean Delvare , Guenter Roeck , Sohil Mehta , Zhang Rui , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org, linux-pm@vger.kernel.org, linux-hwmon@vger.kernel.org Subject: [RFC PATCH 01/15] x86/apic: Fix 32-bit APIC initialization for extended Intel families Date: Fri, 20 Dec 2024 21:36:56 +0000 Message-ID: <20241220213711.1892696-2-sohil.mehta@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241220213711.1892696-1-sohil.mehta@intel.com> References: <20241220213711.1892696-1-sohil.mehta@intel.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 detect_init_APIC() limits the APIC detection to families 6 and 15. Extend the check to family numbers beyond 15. Also, convert it to a VFM check to make it simpler. Signed-off-by: Sohil Mehta Acked-by: Dave Hansen --- arch/x86/kernel/apic/apic.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c index c5fb28e6451a..13dac8f78213 100644 --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -2014,8 +2014,8 @@ static bool __init detect_init_APIC(void) case X86_VENDOR_HYGON: break; case X86_VENDOR_INTEL: - if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || - (boot_cpu_data.x86 == 5 && boot_cpu_has(X86_FEATURE_APIC))) + if ((boot_cpu_data.x86 == 5 && boot_cpu_has(X86_FEATURE_APIC)) || + boot_cpu_data.x86_vfm >= INTEL_PENTIUM_PRO) break; goto no_apic; default: From patchwork Fri Dec 20 21:36:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sohil Mehta X-Patchwork-Id: 852770 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 706802210C0; Fri, 20 Dec 2024 21:39:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734730759; cv=none; b=RXbXpYP3pVxhQ3ai+SwDNwiLDdshAHvFFreVPVZGz/9xcdW5YR0f3ZiHxySuCTHeEPsKv1nYmiL8DKEaNacCYNs51PQnz/5Dn5lvbv3qM1bMY0FEQ0la4+OK/WEguJKu4pjKl3t2PzY8gg4djLlcJC4fh3605REZIx7+5hawbZQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734730759; c=relaxed/simple; bh=mCrZEKcq0bU/X4Zpv9YkufkdbaRSoGmsrcDiM/WKDGo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=BrVO28dXZSQW/rXOcDYdFA3o838R+7z62IbQsMRiLaUfWogKNRL+BdS4qBOkh4IMu7NkPd9VvHbdz2+WbUblGAkdIXX6allg6fbnbtE+VsAmUKjRH/w2T+m6HIMTfBVYO+Y6ORtxm8y4lKB4Gep44tWTqRZx+PFdDlao1hr5ExE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=beJ3aNfK; arc=none smtp.client-ip=198.175.65.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="beJ3aNfK" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1734730758; x=1766266758; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=mCrZEKcq0bU/X4Zpv9YkufkdbaRSoGmsrcDiM/WKDGo=; b=beJ3aNfK0xIUsuKmrb9A3uDUx5i2nuQl+7KBg+/k0xBDRug0PV68z+m8 xxHwFrRsgVv0Edz3UHL3WsyScgcgWzVwanT6MKOeQRMkN8Fe6E7XuiQqG lsaeBR+WxyxVNGhZRsFCWmTpmKOF5kQAmXPnECCjIndZnMonjPoK0LF3S 6lD30CpIT+Lf296sRDQgEcc3ztP6aYABQVlyhVHmrHOpW+sAUvSE+p7fr pYItFszWSth9/R+xu2GVuxkrbTJgRSIf+vQzi99YDfZuEnRPrAkX1NlNv wFqv3AQnIVmNlMR6HbPs+16cXKFE4eAmvyWGAt2qklLVuRNS3i6pQ9AN1 Q==; X-CSE-ConnectionGUID: EPOm5H3GSly2myUMI152jQ== X-CSE-MsgGUID: mdMl1OHITECa/g7tSqUSnA== X-IronPort-AV: E=McAfee;i="6700,10204,11292"; a="39070629" X-IronPort-AV: E=Sophos;i="6.12,251,1728975600"; d="scan'208";a="39070629" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Dec 2024 13:39:15 -0800 X-CSE-ConnectionGUID: ogqVXgK+Qa6uo5r7INgAzw== X-CSE-MsgGUID: M2zFWnTuTlS402OPAjjQjw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="103223832" Received: from sohilmeh.sc.intel.com ([172.25.103.65]) by fmviesa005.fm.intel.com with ESMTP; 20 Dec 2024 13:39:14 -0800 From: Sohil Mehta To: x86@kernel.org, Dave Hansen , Tony Luck Cc: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , Thomas Gleixner , Borislav Petkov , "H . Peter Anvin" , "Rafael J . Wysocki" , Len Brown , Andy Lutomirski , Viresh Kumar , Fenghua Yu , Jean Delvare , Guenter Roeck , Sohil Mehta , Zhang Rui , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org, linux-pm@vger.kernel.org, linux-hwmon@vger.kernel.org Subject: [RFC PATCH 02/15] x86/apic: Fix smp init delay for extended Intel families Date: Fri, 20 Dec 2024 21:36:57 +0000 Message-ID: <20241220213711.1892696-3-sohil.mehta@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241220213711.1892696-1-sohil.mehta@intel.com> References: <20241220213711.1892696-1-sohil.mehta@intel.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The MP specification version 1.4 references the i486 and early Pentium processors in family 5. However, all processors starting with family 6 likely do not need the 10 msec INIT delay. The omission of the Pentium 4s (family 15) seems like an oversight in the original check. With some risk, choose a simpler check and extend the quirk to all recent and upcoming Intel processors. While at it, fix the command line parameter comment to match with the actual name. Signed-off-by: Sohil Mehta --- arch/x86/kernel/smpboot.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c index b5a8f0891135..6c98e9178963 100644 --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -668,7 +668,7 @@ static void impress_friends(void) * But that slows boot and resume on modern processors, which include * many cores and don't require that delay. * - * Cmdline "init_cpu_udelay=" is available to over-ride this delay. + * Cmdline "cpu_init_udelay=" is available to override this delay. * Modern processor families are quirked to remove the delay entirely. */ #define UDELAY_10MS_DEFAULT 10000 @@ -690,9 +690,9 @@ static void __init smp_quirk_init_udelay(void) return; /* if modern processor, use no delay */ - if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) || - ((boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) && (boot_cpu_data.x86 >= 0x18)) || - ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) { + if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && boot_cpu_data.x86_vfm >= INTEL_PENTIUM_PRO) || + (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON && boot_cpu_data.x86 >= 0x18) || + (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && boot_cpu_data.x86 >= 0xF)) { init_udelay = 0; return; } From patchwork Fri Dec 20 21:36:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sohil Mehta X-Patchwork-Id: 852499 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 96220225A57; Fri, 20 Dec 2024 21:39:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734730760; cv=none; b=fNHSX2DJi1tuxaKMSCSmlAWUCelTxGFUfGvd8K/ujRSHpqnfZqcdZzXMfx3f1KBEu7rcMcop4PU83s1VK8WY0Gb4CZCxrDmz+1x7OP1Ls/ULy/GLt8S9XqerKon2SiJh7iJhZq1OsO6O6kvQEnOZ/NT0WSqMKqGyaKY9zWsbap8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734730760; c=relaxed/simple; bh=zlu3Ip1J4PfGkdJP4zJ6MYrEEsH5WCqwL0qdutLDhUo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=EbjJ8RjoSEv3Eb8rbgnV1FSnYnjs2z2x7QCpu4jker/UM1DeTuQ6C7WTwUk5pI+9lxIa5pD10uoSo9iZ7NpZCtEGa2KvL8a7Dr/jPWZSpPhxcCHNHx2b7xTGemOC2EujUEsWH36t2GZYVwCqe5biCpvCl726+Bv8KaPGwPy92iA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=che1XCwC; arc=none smtp.client-ip=198.175.65.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="che1XCwC" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1734730758; x=1766266758; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=zlu3Ip1J4PfGkdJP4zJ6MYrEEsH5WCqwL0qdutLDhUo=; b=che1XCwC6MvyYphi+H1F0Y70UYHsdqgrcNr9UT/AdprCduXQadH0r0jo b0pCeiGCNP6p/TOlYmOXF9J3W2GnmMry5OIeV6mtrQ7nAsd6ZnEMB0+JF SweoObGh9JUJQaNmTi5RsKn/wNLcsrSyi+p/4btpHuLqwV/kDR7ybMz73 HRcu1pD0JL5guLMEE3aS6+zbKaSJC/1SlcVv3wxb4Vhjr/m+4J/qPPcuD 0TImydIdO74P5szgB5V2h+nGBRJVY5C1rcAS+QX7dMnQCtd80L2Xwtt7Y uHb2cn5/FGu2ikmxzA0u2x9Ok2iwZIrU80kLVafEBuEHqnvzgIEZwtU7C w==; X-CSE-ConnectionGUID: /EX6ApY2RmW09pwsHqbFXA== X-CSE-MsgGUID: Gv4umYfqRKynrJmp0PP9bw== X-IronPort-AV: E=McAfee;i="6700,10204,11292"; a="39070641" X-IronPort-AV: E=Sophos;i="6.12,251,1728975600"; d="scan'208";a="39070641" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Dec 2024 13:39:16 -0800 X-CSE-ConnectionGUID: dovdIZ7DRoqSmQdYZHY7vw== X-CSE-MsgGUID: w44AezdmQPOCd8GqUYY73w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="103223835" Received: from sohilmeh.sc.intel.com ([172.25.103.65]) by fmviesa005.fm.intel.com with ESMTP; 20 Dec 2024 13:39:15 -0800 From: Sohil Mehta To: x86@kernel.org, Dave Hansen , Tony Luck Cc: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , Thomas Gleixner , Borislav Petkov , "H . Peter Anvin" , "Rafael J . Wysocki" , Len Brown , Andy Lutomirski , Viresh Kumar , Fenghua Yu , Jean Delvare , Guenter Roeck , Sohil Mehta , Zhang Rui , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org, linux-pm@vger.kernel.org, linux-hwmon@vger.kernel.org Subject: [RFC PATCH 03/15] x86/cpu/intel: Fix init_intel() checks for extended family numbers Date: Fri, 20 Dec 2024 21:36:58 +0000 Message-ID: <20241220213711.1892696-4-sohil.mehta@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241220213711.1892696-1-sohil.mehta@intel.com> References: <20241220213711.1892696-1-sohil.mehta@intel.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X86_FEATURE_REP_GOOD is only set for family 6 processors. Extend the check to family numbers beyond 15. It is uncertain whether the Pentium 4s (family 15) should set the feature flag as well. Commit 185f3b9da24c ("x86: make intel.c have 64-bit support code") that originally set X86_FEATURE_REP_GOOD also set the x86_cache_alignment preference for family 15 processors. The omission of the family 15 seems intentional. Also, the 32-bit user copy alignment preference is only set for family 6 and 15 processors. Extend the preference to family numbers beyond 15. Signed-off-by: Sohil Mehta --- arch/x86/kernel/cpu/intel.c | 19 ++++++------------- 1 file changed, 6 insertions(+), 13 deletions(-) diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index 8ded9f859a3a..f44b2e618fb3 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -449,23 +449,16 @@ static void intel_workarounds(struct cpuinfo_x86 *c) (c->x86_stepping < 0x6 || c->x86_stepping == 0xb)) set_cpu_bug(c, X86_BUG_11AP); - #ifdef CONFIG_X86_INTEL_USERCOPY /* * Set up the preferred alignment for movsl bulk memory moves + * Family 4 - 486: untested + * Family 5 - Pentium: untested + * Family 6 - PII/PIII only like movsl with 8-byte alignment + * Family 15 - P4 is OK down to 8-byte alignment */ - switch (c->x86) { - case 4: /* 486: untested */ - break; - case 5: /* Old Pentia: untested */ - break; - case 6: /* PII/PIII only like movsl with 8-byte alignment */ - movsl_mask.mask = 7; - break; - case 15: /* P4 is OK down to 8-byte alignment */ + if (c->x86_vfm >= INTEL_PENTIUM_PRO) movsl_mask.mask = 7; - break; - } #endif intel_smp_check(c); @@ -563,7 +556,7 @@ static void init_intel(struct cpuinfo_x86 *c) #ifdef CONFIG_X86_64 if (c->x86 == 15) c->x86_cache_alignment = c->x86_clflush_size * 2; - if (c->x86 == 6) + if (c->x86 == 6 || c->x86 > 15) set_cpu_cap(c, X86_FEATURE_REP_GOOD); #else /* From patchwork Fri Dec 20 21:36:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sohil Mehta X-Patchwork-Id: 852769 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9625322687C; Fri, 20 Dec 2024 21:39:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734730760; cv=none; b=ITZKiH1dkc1Wz1Uix21Ulh/jrMY4lvnHme4rjP+ZrN6mBfdMWZkBjq18hFEXNCsbYlrrQqR2IqyDmetj9N2nanL6W2XOv5jHzl3hZoOmGV5wP4qnHFaOZc4LGsoNzIMqDlr1fChMz4oJ3erNfrXlsBCColEvtcAN8JkzNJ/jnYs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734730760; c=relaxed/simple; bh=2gP+CtCrc5rkz2Pvmazx/u1oV3mo36Q6cxwLGcuRBdY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ThomjsgHZ4dvxYug8eAsCegcqMueQhKqwItrcwZUSMUurGbB/dnT8i0seqEhu8HaawdYGZFwSsBqOlQNnHrqxC7cCvy0JuzYuGyM+kEryAbGCWrS/DhSAhflo2Uvi3vvhb5wT2SpeVVB4c45ryEwOXqfGyFS8dcAAtP4jE+RLPI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=RJOMpupn; arc=none smtp.client-ip=198.175.65.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="RJOMpupn" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1734730759; x=1766266759; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=2gP+CtCrc5rkz2Pvmazx/u1oV3mo36Q6cxwLGcuRBdY=; b=RJOMpupnvjYzQNkOSesviR4Q70w/ENCWkGjwuNkRXSw0YG9+X3OA4vvK WCQkK92Ury+iwrwULk/wRhstInR3S3eZk9t6ZmJQdAeYVavqymXYUR7P3 MUhmIfW/7iZtAE372tn/Y/YuoFdxKKjOr29H3eeHKq4qCbMdPBTrdGw8V sgKDe0HaExtqlqlLl7MfHT3qDuMPyNVOxA/aTQDW1LK2omjsU1m22/qhQ S/eB0+Z6veRj4ScsujvGneiOaZpKvqx+D+b1h4gG9WPMceUNdURLFFPaZ 5KL4Ok+/BJyP2/42nqSKtPgDmWjc0Zs8vZ2a5Em8ArB+3E9D2mDd5oN2F g==; X-CSE-ConnectionGUID: h8Io7ZpiSxO5nxL6rG8KpQ== X-CSE-MsgGUID: KKhG7lGxSP+a44zw33qSRg== X-IronPort-AV: E=McAfee;i="6700,10204,11292"; a="39070654" X-IronPort-AV: E=Sophos;i="6.12,251,1728975600"; d="scan'208";a="39070654" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Dec 2024 13:39:16 -0800 X-CSE-ConnectionGUID: z1wT93DdRuafVZNCbYP0Ig== X-CSE-MsgGUID: G3ak4Tt9TOq/u2dy0GsdVg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="103223838" Received: from sohilmeh.sc.intel.com ([172.25.103.65]) by fmviesa005.fm.intel.com with ESMTP; 20 Dec 2024 13:39:15 -0800 From: Sohil Mehta To: x86@kernel.org, Dave Hansen , Tony Luck Cc: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , Thomas Gleixner , Borislav Petkov , "H . Peter Anvin" , "Rafael J . Wysocki" , Len Brown , Andy Lutomirski , Viresh Kumar , Fenghua Yu , Jean Delvare , Guenter Roeck , Sohil Mehta , Zhang Rui , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org, linux-pm@vger.kernel.org, linux-hwmon@vger.kernel.org Subject: [RFC PATCH 04/15] cpufreq: Fix the efficient idle check for Intel extended families Date: Fri, 20 Dec 2024 21:36:59 +0000 Message-ID: <20241220213711.1892696-5-sohil.mehta@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241220213711.1892696-1-sohil.mehta@intel.com> References: <20241220213711.1892696-1-sohil.mehta@intel.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 should_io_be_busy() only considers certain family 6 CPUs as having efficient idling. However, Arjan (the original author) says that choice was due to the lack of testing done on the old systems. He suggests to consider all Intel processors as having efficient idle. Extend the check to all processors starting with family 6. Signed-off-by: Sohil Mehta --- drivers/cpufreq/cpufreq_ondemand.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/cpufreq/cpufreq_ondemand.c b/drivers/cpufreq/cpufreq_ondemand.c index a7c38b8b3e78..dfafb161f1c4 100644 --- a/drivers/cpufreq/cpufreq_ondemand.c +++ b/drivers/cpufreq/cpufreq_ondemand.c @@ -15,6 +15,10 @@ #include #include +#ifdef CONFIG_X86 +#include +#endif + #include "cpufreq_ondemand.h" /* On-demand governor macros */ @@ -32,8 +36,7 @@ static unsigned int default_powersave_bias; /* * Not all CPUs want IO time to be accounted as busy; this depends on how * efficient idling at a higher frequency/voltage is. - * Pavel Machek says this is not so for various generations of AMD and old - * Intel systems. + * Pavel Machek says this is not so for various generations of AMD. * Mike Chan (android.com) claims this is also not true for ARM. * Because of this, whitelist specific known (series) of CPUs by default, and * leave all others up to the user. @@ -42,11 +45,11 @@ static int should_io_be_busy(void) { #if defined(CONFIG_X86) /* - * For Intel, Core 2 (model 15) and later have an efficient idle. + * Starting with Family 6 consider all Intel CPUs to have an + * efficient idle. */ if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && - boot_cpu_data.x86 == 6 && - boot_cpu_data.x86_model >= 15) + boot_cpu_data.x86_vfm >= INTEL_PENTIUM_PRO) return 1; #endif return 0; From patchwork Fri Dec 20 21:37:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sohil Mehta X-Patchwork-Id: 852498 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6AC23227B8B; Fri, 20 Dec 2024 21:39:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734730761; cv=none; b=SZR4Ad5hWPM/h5AwmFe02n2/radMp+J/iAoJhKAQw6WGMzDrXBAn40kCXj2VqjXT9EeErNmhP3jvOJ6AuFNM0mpyFuczftXEX2O05PYtjRUPqSUBPVxQmbnt1qXvGTKsV3gJW6kLGxz2fnGDImBdxelxED4nnr7p+sYGbX3bpu8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734730761; c=relaxed/simple; bh=RigSsP0koHKo+ynGNOr65xWILzziWrY3/A9JCpL5ADo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=mSR5LaeTRouuNqJyGC02KpgFjpnKt8pAknBNW0kjBr7YLUGrL+DTt6H3KVK3UpD0e6KAPO5AXdOBSEt/d9mAT4eLB1Qd0455aUx8QKrsen1kfe8hZQthDQncodGpBY3J5qUTxRZ+m3TUpB0qq7pmoHrHRlALW0MxRdvLQlOlGB4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=TfJJVL0q; arc=none smtp.client-ip=198.175.65.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="TfJJVL0q" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1734730760; x=1766266760; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=RigSsP0koHKo+ynGNOr65xWILzziWrY3/A9JCpL5ADo=; b=TfJJVL0q9EaOmessQtHeRqvcRoZxvjSClRJG4Amo1DjNz/02hbo6xOkB zxsjo54CgJJ/HTJd8EwZHenFxNiQYKYo8RrdnZ8qAIG+QQm6RPAogvKEs MLCC5n10t6izeXL4RFpVW9SRdkcrc7E8V9JMFIzrzh8dk8fSgK5aG8qr/ YV46cvgMtVq6j3wN/wVLsWgC92qofyj4KuCyHXlEAZAYQ/N8thG8Fi1WP hVoKKh19XT8pIYSD0jBMl6YWse1tkXjp0hO0wGr/tkSIRO3ZYHmFmH0su vSFxXXMRarQIWEzt7jqMS2ovFmoCL8HLhKl63BX7UwHFwIdYsToqCn7Sl Q==; X-CSE-ConnectionGUID: 2knWKvOmRL2WL/7iqfrQMA== X-CSE-MsgGUID: Nn6B5KuSSzqpNkPBtX/k9A== X-IronPort-AV: E=McAfee;i="6700,10204,11292"; a="39070675" X-IronPort-AV: E=Sophos;i="6.12,251,1728975600"; d="scan'208";a="39070675" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Dec 2024 13:39:17 -0800 X-CSE-ConnectionGUID: PBznrhb5Qh2lUv/z1yIlCA== X-CSE-MsgGUID: gfYDJXLvQYeCdMHnJRJLng== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="103223841" Received: from sohilmeh.sc.intel.com ([172.25.103.65]) by fmviesa005.fm.intel.com with ESMTP; 20 Dec 2024 13:39:15 -0800 From: Sohil Mehta To: x86@kernel.org, Dave Hansen , Tony Luck Cc: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , Thomas Gleixner , Borislav Petkov , "H . Peter Anvin" , "Rafael J . Wysocki" , Len Brown , Andy Lutomirski , Viresh Kumar , Fenghua Yu , Jean Delvare , Guenter Roeck , Sohil Mehta , Zhang Rui , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org, linux-pm@vger.kernel.org, linux-hwmon@vger.kernel.org Subject: [RFC PATCH 05/15] hwmon: Fix Intel family checks to include extended family numbers Date: Fri, 20 Dec 2024 21:37:00 +0000 Message-ID: <20241220213711.1892696-6-sohil.mehta@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241220213711.1892696-1-sohil.mehta@intel.com> References: <20241220213711.1892696-1-sohil.mehta@intel.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The current Intel family-model checks in the coretemp driver seem to implicitly assume family 6. Extend the checks to include the extended family numbers beyond 15 as well. Also, add explicit checks for family 6 in places where it is assumed implicitly. x86_model checks seem inconsistent and scattered throughout the driver. Consolidating and converting them to VFM ones would be a useful addition in future. Signed-off-by: Sohil Mehta Acked-by: Guenter Roeck --- drivers/hwmon/coretemp.c | 26 ++++++++++++++++++-------- 1 file changed, 18 insertions(+), 8 deletions(-) diff --git a/drivers/hwmon/coretemp.c b/drivers/hwmon/coretemp.c index 1b9203b20d70..1aa67a2b5f18 100644 --- a/drivers/hwmon/coretemp.c +++ b/drivers/hwmon/coretemp.c @@ -185,6 +185,13 @@ static int adjust_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *dev) return tjmax_table[i].tjmax; } + /* + * Return without adjustment if the Family isn't 6. + * The rest of the function assumes Family 6. + */ + if (c->x86 != 6) + return tjmax; + for (i = 0; i < ARRAY_SIZE(tjmax_model_table); i++) { const struct tjmax_model *tm = &tjmax_model_table[i]; if (c->x86_model == tm->model && @@ -260,14 +267,17 @@ static int adjust_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *dev) static bool cpu_has_tjmax(struct cpuinfo_x86 *c) { + u8 family = c->x86; u8 model = c->x86_model; - return model > 0xe && - model != 0x1c && - model != 0x26 && - model != 0x27 && - model != 0x35 && - model != 0x36; + return family > 15 || + (family == 6 && + model > 0xe && + model != 0x1c && + model != 0x26 && + model != 0x27 && + model != 0x35 && + model != 0x36); } static int get_tjmax(struct temp_data *tdata, struct device *dev) @@ -460,7 +470,7 @@ static int chk_ucode_version(unsigned int cpu) * Readings might stop update when processor visited too deep sleep, * fixed for stepping D0 (6EC). */ - if (c->x86_model == 0xe && c->x86_stepping < 0xc && c->microcode < 0x39) { + if (c->x86 == 6 && c->x86_model == 0xe && c->x86_stepping < 0xc && c->microcode < 0x39) { pr_err("Errata AE18 not fixed, update BIOS or microcode of the CPU!\n"); return -ENODEV; } @@ -580,7 +590,7 @@ static int create_core_data(struct platform_device *pdev, unsigned int cpu, * MSR_IA32_TEMPERATURE_TARGET register. Atoms don't have the register * at all. */ - if (c->x86_model > 0xe && c->x86_model != 0x1c) + if (c->x86 > 15 || (c->x86 == 6 && c->x86_model > 0xe && c->x86_model != 0x1c)) if (get_ttarget(tdata, &pdev->dev) >= 0) tdata->attr_size++; From patchwork Fri Dec 20 21:37:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sohil Mehta X-Patchwork-Id: 852497 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 588A42288D0; Fri, 20 Dec 2024 21:39:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734730762; cv=none; b=YutwSDm6h1xfvmsBjostNyFC28TNMNhTFX9Dw7UjAKK7293UrWGZf2ruUyokaeJMPE/sH5RxxZN9HOh8bv9zT3R9k48IEspzEHZezVpc1oppqVkDRPbVpgEIWaq7/yKrZA6itv+vrMNQNYxy81c9ClcqmqlzdZ9niy3VCsSjowo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734730762; c=relaxed/simple; bh=mBOSa7vDktow9RtpDWMVAM+JsLjZGeJOv/UXCTAQnh8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=WLmbFoZ6Q4K2XLtBNK+mB4hOqklSEnW75YyCd2cxJib8o1XhlCHVTgI9I8vyabHPKEbkftiUZlGNFon9W94gZk+NnVzJcZIn0A/M9l49XGsRMVLWsC51oEx+ikVvOp3BcdTz5KBeLmt+0R4adt29MlI0Uzz3eao5cV9pi8SgCTU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=WZp59ZRD; arc=none smtp.client-ip=198.175.65.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="WZp59ZRD" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1734730761; x=1766266761; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=mBOSa7vDktow9RtpDWMVAM+JsLjZGeJOv/UXCTAQnh8=; b=WZp59ZRDAWTQyYhBYGemsPH/QSR74X/I7377lHiR945Sl7Ct4PJTNWdn OpDDjkrAc9GjbZNyXTrGIAPYxHYTP4xrSVpOfxKxsGXzqycrCXQKIrDWK Tk3dPO+ZwuDkzBGp3gyxHA+O74g0pJVtFheP3SfnfzZ7c05d5CngSuaV8 U4SKwT7GH4lDCAO8pK72ozdBNsgXe3R730DnOYfM3B2M1A5679IE1pAJ/ 923Fwhzl/+o/YOCeipdwAFzOdzXHL5kwCV47wBBHrxyxdr//uz9SEopXE fEQ4vttuTWVWyLlDwVpFm82OVYt7YAWeVLOEoCTIC48UIOj5PTv/nz69W Q==; X-CSE-ConnectionGUID: DPJAckaOSB6GAB8iZROAQQ== X-CSE-MsgGUID: 85V2fY6/Tby6ErtMU8GSqg== X-IronPort-AV: E=McAfee;i="6700,10204,11292"; a="39070678" X-IronPort-AV: E=Sophos;i="6.12,251,1728975600"; d="scan'208";a="39070678" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Dec 2024 13:39:17 -0800 X-CSE-ConnectionGUID: j7vMtVUiQe+fZBGZnTTYqQ== X-CSE-MsgGUID: oYZyDvjSRK2xHeqVxAOFuQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="103223844" Received: from sohilmeh.sc.intel.com ([172.25.103.65]) by fmviesa005.fm.intel.com with ESMTP; 20 Dec 2024 13:39:16 -0800 From: Sohil Mehta To: x86@kernel.org, Dave Hansen , Tony Luck Cc: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , Thomas Gleixner , Borislav Petkov , "H . Peter Anvin" , "Rafael J . Wysocki" , Len Brown , Andy Lutomirski , Viresh Kumar , Fenghua Yu , Jean Delvare , Guenter Roeck , Sohil Mehta , Zhang Rui , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org, linux-pm@vger.kernel.org, linux-hwmon@vger.kernel.org Subject: [RFC PATCH 06/15] x86/microcode: Update the Intel processor flag scan check Date: Fri, 20 Dec 2024 21:37:01 +0000 Message-ID: <20241220213711.1892696-7-sohil.mehta@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241220213711.1892696-1-sohil.mehta@intel.com> References: <20241220213711.1892696-1-sohil.mehta@intel.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The check whether to read IA32_PLATFORM_ID MSR is misleading. It doesn't seem to consider family while comparing the model number. This works because init_intel_microcode() bails out if the processor family is less than 6. It is better to update the current check to specifically include family 6. Ideally, a VFM check would make it more readable. But, there isn't a macro to derive VFM from sig. Signed-off-by: Sohil Mehta --- arch/x86/kernel/cpu/microcode/intel.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/microcode/intel.c index f3d534807d91..734819a12d5f 100644 --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -74,7 +74,8 @@ void intel_collect_cpu_info(struct cpu_signature *sig) sig->pf = 0; sig->rev = intel_get_microcode_revision(); - if (x86_model(sig->sig) >= 5 || x86_family(sig->sig) > 6) { + /* TODO: Simplify this using a VFM check? */ + if ((x86_family(sig->sig) == 6 && x86_model(sig->sig) >= 5) || x86_family(sig->sig) > 6) { unsigned int val[2]; /* get processor flags from MSR 0x17 */ From patchwork Fri Dec 20 21:37:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sohil Mehta X-Patchwork-Id: 852768 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 23E62228380; Fri, 20 Dec 2024 21:39:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734730761; cv=none; b=Fif3sh1W3K1NzNeJRfZV5SFnblzXl0h8kI6oid1R5EryAhWnX1eZScxwYNpCSsaF7kHCooVpGwar6bd1+Gv50etixaINg5Qs9EKCf3ajfr6xbhqTGIDMOp+aZlYnAHRzbQVi9qqugC4mGog+Xm9daaSUMqnmCKlmFx04kINu8/k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734730761; c=relaxed/simple; bh=w5yxFrFjNk2rOvxvNr3CKSLfp4P0JFH0fW/f7AsjuWk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=cBlw2vDz7iGgyzB+OIoJ27/az5Ul+Oj/AiPZzhvusLCXFBGscqlhVa9c1kGHGrX+iD/FZE6a7ODqHr50gFsb9F0J+Rk3fMRlhX27lRQwNUVH8CjYoIUu15m4AgouTnHJ4h0CqAr3afeSFjMAqpk14Vla014PnN6wgVeIkgxWquk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=OQr9/+Qv; arc=none smtp.client-ip=198.175.65.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="OQr9/+Qv" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1734730760; x=1766266760; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=w5yxFrFjNk2rOvxvNr3CKSLfp4P0JFH0fW/f7AsjuWk=; b=OQr9/+Qvgw3JDdIS2lmdkQyNX0EaOz7Ua3Qo15KXMLhPK9lhDkXjeJeF JQ7AmvAV3wyGtB894wQtvCX1EJlrtJVBS9Rk23+y3242Wz7bKPtUzOYAX CvUfDVt6oRO7LE33jgwOpLCtIAkI3z6QU1hvyPns00jEJduVtJBkwS6s8 QdSRc6/KtKHerUOiKp3jd+KMmPpGpc5VR+7y5E4JnsXpNA5mtXebCV5Tc RIgZG4Oim2t4Lx0DNP0WXxiz9eDFl4iD4NSZQ3SVbHudlWWyyamuBs/li Rp9VEYQABYZSzR1UmhnC/Lg6ollRQTuBQQXa7GsW6OPAhTdeXJ2uOGQCO A==; X-CSE-ConnectionGUID: qIoCiHMbRZOPfqGS8BTPaw== X-CSE-MsgGUID: B3Z3aUNkQOOaK2sfAhE44w== X-IronPort-AV: E=McAfee;i="6700,10204,11292"; a="39070699" X-IronPort-AV: E=Sophos;i="6.12,251,1728975600"; d="scan'208";a="39070699" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Dec 2024 13:39:17 -0800 X-CSE-ConnectionGUID: +7AvRxIXRzK5RubY0g8fEQ== X-CSE-MsgGUID: 5/NJpDxeTAWD4dS0s729CA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="103223847" Received: from sohilmeh.sc.intel.com ([172.25.103.65]) by fmviesa005.fm.intel.com with ESMTP; 20 Dec 2024 13:39:16 -0800 From: Sohil Mehta To: x86@kernel.org, Dave Hansen , Tony Luck Cc: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , Thomas Gleixner , Borislav Petkov , "H . Peter Anvin" , "Rafael J . Wysocki" , Len Brown , Andy Lutomirski , Viresh Kumar , Fenghua Yu , Jean Delvare , Guenter Roeck , Sohil Mehta , Zhang Rui , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org, linux-pm@vger.kernel.org, linux-hwmon@vger.kernel.org Subject: [RFC PATCH 07/15] x86/mtrr: Modify a x86_model check to an Intel VFM check Date: Fri, 20 Dec 2024 21:37:02 +0000 Message-ID: <20241220213711.1892696-8-sohil.mehta@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241220213711.1892696-1-sohil.mehta@intel.com> References: <20241220213711.1892696-1-sohil.mehta@intel.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Get rid of one of the last few Intel x86_model checks in arch/x86. Signed-off-by: Sohil Mehta --- arch/x86/kernel/cpu/mtrr/generic.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/cpu/mtrr/generic.c b/arch/x86/kernel/cpu/mtrr/generic.c index 7b29ebda024f..36f5dbd2f482 100644 --- a/arch/x86/kernel/cpu/mtrr/generic.c +++ b/arch/x86/kernel/cpu/mtrr/generic.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -1025,8 +1026,7 @@ int generic_validate_add_page(unsigned long base, unsigned long size, * For Intel PPro stepping <= 7 * must be 4 MiB aligned and not touch 0x70000000 -> 0x7003FFFF */ - if (mtrr_if == &generic_mtrr_ops && boot_cpu_data.x86 == 6 && - boot_cpu_data.x86_model == 1 && + if (mtrr_if == &generic_mtrr_ops && boot_cpu_data.x86_vfm == INTEL_PENTIUM_PRO && boot_cpu_data.x86_stepping <= 7) { if (base & ((1 << (22 - PAGE_SHIFT)) - 1)) { pr_warn("mtrr: base(0x%lx000) is not 4 MiB aligned\n", base); From patchwork Fri Dec 20 21:37:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sohil Mehta X-Patchwork-Id: 852767 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6B3CF229130; Fri, 20 Dec 2024 21:39:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734730763; cv=none; b=rLsTxzb8B3ZAxgza79Xz1yTrdeQf0dKafgn7Yd34nyqp6PRY7ErFhsv+rTCbIVlz9yePJXCE+W1H6EFxAFo2OI+ASNIiPCYejPbJ+zZO+M/9iqjmBv3/MS7XNE8MHYgH5qMprmaTPpyWj5gR+vP8Hyy+i441tzprKj0EJInNugc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734730763; c=relaxed/simple; bh=khcbHN+6/uEv0zea4Ln5lsuwyhVArEvDUPEFThN18B0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=EsUf3bPckbBVlRsyOryH0zNeez9NZU69rol4aT2RQch8CFPC4UcJthZDkcUan1a36AAZsfZX9WBF6fUzxslC9A9aBx6QeR6AR0nCPu97sXj9ViOxx70qqD+LHrDaSepPPCtyoE9GhCLePArrsjdHn9qe9AL1RsMmisslAlmt32s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Yw/lTK6w; arc=none smtp.client-ip=198.175.65.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Yw/lTK6w" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1734730762; x=1766266762; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=khcbHN+6/uEv0zea4Ln5lsuwyhVArEvDUPEFThN18B0=; b=Yw/lTK6wQeOBcTnxpLi7jtElnDtFfKZ5gGoFL2OtDAPJ5+LD8KLEuT4L ChuwgsgxPO22jDrYXdFnAv/x4obh6cHVsu6q+i1/cLVpZT+FKFMT8Hjcb qQZzu4xJTFfpdQZ5jTR4oVYf35gW552dN0fTb82neuhR15Dflv+ZLujIo wLsiNiLrjk+pkHGoZwhMEkSqKytbKYBWwblu8QUv3kMpFXLZ1BS0Qw4IU xdZgR8SEbpi6b4+GJYroMOwUwj78/emwv3aF0K+VJku3ZYkOSlCJVwSGW qEEr/bnzNf4obzve/T0BzV/eWIJghFq37A8arejjRv9cLoAezpbFWtGNY Q==; X-CSE-ConnectionGUID: 670lzGn0Ro2sTBLnwheH8Q== X-CSE-MsgGUID: gB+bBP4xTRGaiz5XqMVPNg== X-IronPort-AV: E=McAfee;i="6700,10204,11292"; a="39070701" X-IronPort-AV: E=Sophos;i="6.12,251,1728975600"; d="scan'208";a="39070701" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Dec 2024 13:39:17 -0800 X-CSE-ConnectionGUID: 5VroBSZYTgqwRrTN7cx7yQ== X-CSE-MsgGUID: GbSPoW/XRVSuVJcmu/w4LA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="103223850" Received: from sohilmeh.sc.intel.com ([172.25.103.65]) by fmviesa005.fm.intel.com with ESMTP; 20 Dec 2024 13:39:16 -0800 From: Sohil Mehta To: x86@kernel.org, Dave Hansen , Tony Luck Cc: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , Thomas Gleixner , Borislav Petkov , "H . Peter Anvin" , "Rafael J . Wysocki" , Len Brown , Andy Lutomirski , Viresh Kumar , Fenghua Yu , Jean Delvare , Guenter Roeck , Sohil Mehta , Zhang Rui , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org, linux-pm@vger.kernel.org, linux-hwmon@vger.kernel.org Subject: [RFC PATCH 08/15] x86/cpu/intel: Replace early family 6 checks with VFM ones Date: Fri, 20 Dec 2024 21:37:03 +0000 Message-ID: <20241220213711.1892696-9-sohil.mehta@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241220213711.1892696-1-sohil.mehta@intel.com> References: <20241220213711.1892696-1-sohil.mehta@intel.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Introduce names for some old pentium models and replace with VFM based checks. Signed-off-by: Sohil Mehta --- arch/x86/include/asm/intel-family.h | 3 +++ arch/x86/kernel/cpu/intel.c | 13 ++++++------- 2 files changed, 9 insertions(+), 7 deletions(-) diff --git a/arch/x86/include/asm/intel-family.h b/arch/x86/include/asm/intel-family.h index 6d7b04ffc5fd..41278093bcd4 100644 --- a/arch/x86/include/asm/intel-family.h +++ b/arch/x86/include/asm/intel-family.h @@ -46,6 +46,9 @@ #define INTEL_ANY IFM(X86_FAMILY_ANY, X86_MODEL_ANY) #define INTEL_PENTIUM_PRO IFM(6, 0x01) +#define INTEL_PENTIUM_II_KLAMATH IFM(6, 0x03) +#define INTEL_PENTIUM_III_TUALATIN IFM(6, 0x0B) +#define INTEL_PENTIUM_M_DOTHAN IFM(6, 0x0D) #define INTEL_CORE_YONAH IFM(6, 0x0E) diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index f44b2e618fb3..cde8f45ccd57 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -195,7 +195,7 @@ void intel_unlock_cpuid_leafs(struct cpuinfo_x86 *c) if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) return; - if (c->x86 < 6 || (c->x86 == 6 && c->x86_model < 0xd)) + if (c->x86_vfm < INTEL_PENTIUM_M_DOTHAN) return; /* @@ -301,7 +301,7 @@ static void early_init_intel(struct cpuinfo_x86 *c) * If fast string is not enabled in IA32_MISC_ENABLE for any reason, * clear the fast string and enhanced fast string CPU capabilities. */ - if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) { + if (c->x86_vfm >= INTEL_PENTIUM_M_DOTHAN) { rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable); if (!(misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING)) { pr_info("Disabled fast string operations\n"); @@ -350,9 +350,7 @@ static void bsp_init_intel(struct cpuinfo_x86 *c) int ppro_with_ram_bug(void) { /* Uses data from early_cpu_detect now */ - if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && - boot_cpu_data.x86 == 6 && - boot_cpu_data.x86_model == 1 && + if (boot_cpu_data.x86_vfm == INTEL_PENTIUM_PRO && boot_cpu_data.x86_stepping < 8) { pr_info("Pentium Pro with Errata#50 detected. Taking evasive action.\n"); return 1; @@ -413,7 +411,8 @@ static void intel_workarounds(struct cpuinfo_x86 *c) * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until * model 3 mask 3 */ - if ((c->x86<<8 | c->x86_model<<4 | c->x86_stepping) < 0x633) + if ((c->x86_vfm == INTEL_PENTIUM_II_KLAMATH && c->x86_stepping < 3) || + c->x86_vfm < INTEL_PENTIUM_II_KLAMATH) clear_cpu_cap(c, X86_FEATURE_SEP); /* @@ -620,7 +619,7 @@ static unsigned int intel_size_cache(struct cpuinfo_x86 *c, unsigned int size) * to determine which, so we use a boottime override * for the 512kb model, and assume 256 otherwise. */ - if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0)) + if (c->x86_vfm == INTEL_PENTIUM_III_TUALATIN && size == 0) size = 256; /* From patchwork Fri Dec 20 21:37:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sohil Mehta X-Patchwork-Id: 852496 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F1CDE229666; Fri, 20 Dec 2024 21:39:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734730763; cv=none; b=WIuxLHGTpyEAfNd5Bi1/njt8W8b2XQ9reovyJ79hxNLr2ZuivYdsMiDw++Me37Vp4+H+Ek8IgAyHoUYzwzbWt9TDTDfI+R3XSIfPEZDjJqe/9YqzWN8ANu3oLeXBrlcxMUbuwQVBsVcBktl5hT3dd68g9VZd2WTQn8vYb/lgrkk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734730763; c=relaxed/simple; bh=O4ncBifRTq9YBhwAqZ5RW1n+vh570dNEbVhOk1ZSBJw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=N5pMk70WUQj2DsyaD6CIoXyQMZaG79pnJQsqDuCGXGRCz7+Y1ma8MY7nQaj2quk4O2HYGKeF9pyBYd3qVOfJwwt2g9iN8E7xNVuUnkSP2/3xCZcVU6dbPNFTKE4V/kQM2j0sw5SK9p1ZkjdP13t239WZ0BbeRphuebjISc3ADuc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=CsLfLkAa; arc=none smtp.client-ip=198.175.65.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="CsLfLkAa" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1734730762; x=1766266762; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=O4ncBifRTq9YBhwAqZ5RW1n+vh570dNEbVhOk1ZSBJw=; b=CsLfLkAaDAADh0VprZQPtof4KuTsLHECDjiQbfHkBeH7lHDm7ClOmrm4 HS+JmQ8rG8n5JR0dIhv9KUsxJ838GMrhOt+LWlCGyM63aNYmBCigNQqT0 KOlpLTZ7Ky8d5O8HmUzmlURnADp4Gtn2HhpGcEL5ZM+V3DPc+dW+9aBvk 0k3Lka7PkVpGWrGns8KbNrLO+nRkyt+glLh4g1b9jHt6ke8eoqR/MnmpE D5k0dbos5t6CL7IVUdKL419TmM5m45iasn6NNNbuzWo5HDoKLprXU7yoD zk+wtvyNrW9TkYJctvVPpgbRLtgeELro/l0fq4x8VEhm27YzoyQZDKFn4 A==; X-CSE-ConnectionGUID: 81DmAPlCSb6Edh3JRDVrjg== X-CSE-MsgGUID: EpAjN+TNSMaJHbqcwO81+w== X-IronPort-AV: E=McAfee;i="6700,10204,11292"; a="39070724" X-IronPort-AV: E=Sophos;i="6.12,251,1728975600"; d="scan'208";a="39070724" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Dec 2024 13:39:18 -0800 X-CSE-ConnectionGUID: WRYG0StfRiiG+cO98DSeDA== X-CSE-MsgGUID: uRlwZ5epSAySRexzZPD09w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="103223853" Received: from sohilmeh.sc.intel.com ([172.25.103.65]) by fmviesa005.fm.intel.com with ESMTP; 20 Dec 2024 13:39:17 -0800 From: Sohil Mehta To: x86@kernel.org, Dave Hansen , Tony Luck Cc: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , Thomas Gleixner , Borislav Petkov , "H . Peter Anvin" , "Rafael J . Wysocki" , Len Brown , Andy Lutomirski , Viresh Kumar , Fenghua Yu , Jean Delvare , Guenter Roeck , Sohil Mehta , Zhang Rui , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org, linux-pm@vger.kernel.org, linux-hwmon@vger.kernel.org Subject: [RFC PATCH 09/15] x86/cpu/intel: Replace family 15 checks with VFM ones Date: Fri, 20 Dec 2024 21:37:04 +0000 Message-ID: <20241220213711.1892696-10-sohil.mehta@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241220213711.1892696-1-sohil.mehta@intel.com> References: <20241220213711.1892696-1-sohil.mehta@intel.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Introduce names for some old pentium 4 models and replace with VFM based checks. Signed-off-by: Sohil Mehta --- arch/x86/include/asm/intel-family.h | 4 ++++ arch/x86/kernel/cpu/intel.c | 6 +++--- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/arch/x86/include/asm/intel-family.h b/arch/x86/include/asm/intel-family.h index 41278093bcd4..79cfd42c849f 100644 --- a/arch/x86/include/asm/intel-family.h +++ b/arch/x86/include/asm/intel-family.h @@ -182,6 +182,10 @@ /* Family 5 */ #define INTEL_QUARK_X1000 IFM(5, 0x09) /* Quark X1000 SoC */ +/* Family 15 */ +#define INTEL_P4_WILLAMETTE IFM(15, 0x01) /* Also Xeon Foster */ +#define INTEL_P4_PRESCOTT IFM(15, 0x03) + /* Family 19 */ #define INTEL_PANTHERCOVE_X IFM(19, 0x01) /* Diamond Rapids */ diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index cde8f45ccd57..26221f38db70 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -256,8 +256,8 @@ static void early_init_intel(struct cpuinfo_x86 *c) #endif /* CPUID workaround for 0F33/0F34 CPU */ - if (c->x86 == 0xF && c->x86_model == 0x3 - && (c->x86_stepping == 0x3 || c->x86_stepping == 0x4)) + if (c->x86_vfm == INTEL_P4_PRESCOTT && + (c->x86_stepping == 0x3 || c->x86_stepping == 0x4)) c->x86_phys_bits = 36; /* @@ -430,7 +430,7 @@ static void intel_workarounds(struct cpuinfo_x86 *c) * P4 Xeon erratum 037 workaround. * Hardware prefetcher may cause stale data to be loaded into the cache. */ - if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_stepping == 1)) { + if (c->x86_vfm == INTEL_P4_WILLAMETTE && c->x86_stepping == 1) { if (msr_set_bit(MSR_IA32_MISC_ENABLE, MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) > 0) { pr_info("CPU: C0 stepping P4 Xeon detected.\n"); From patchwork Fri Dec 20 21:37:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sohil Mehta X-Patchwork-Id: 852766 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2CEA322967E; Fri, 20 Dec 2024 21:39:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734730764; cv=none; b=CX/dAL1i67Lc8nqwRd1qiRPMyDMH1NR/EJntjdo1dHq31uJfX8rOoHYCR1oOEowBa6fd6TtRvS7X4ulQqmT8sMToX+0fjHCTNQYu4h+yUjMG4zo4+P70UfkXNWwSYA++Nx2/wIKndgDgFQB2/vtNVxjDonBWKDftj/EIPHsi0zc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734730764; c=relaxed/simple; bh=aRVoNC6xFppjLAQNekbF747ddhqNf7rFuzG74RxiCzY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=IbiGI9v68ZX7HJ7G5vc9ZyLtTeHi//M0Dm+uQFTKc+TikMOdQR3bSQKhaoxJPx/MmYs9AGxU0odrBq9Z0xfAQmSb8t32qTZnZrtM6mU2tVBHEiSSGW40OFSbz+1fsyo+87pYV9sU1rRcmJDY/IDTRR30R/xc77CBUBcEpvp0QTY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=lS19NCqK; arc=none smtp.client-ip=198.175.65.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="lS19NCqK" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1734730763; x=1766266763; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=aRVoNC6xFppjLAQNekbF747ddhqNf7rFuzG74RxiCzY=; b=lS19NCqKt/vh4lp/rFnR1BQTk3q95+KqKenh8A5fA0VNX/pNxITd6vSM nANp3rgo3VnNBi3EE1BxEXN3qMsu5U+9BmmDRigIcL29qVs8kaUlhXGz2 UGOhhW/1DcdBk5m+Qb9KS1oaFaN4KInkzDSyIKgGBQ6p2ChTMKLuL01IX +eaNWGDX1QuTgzzHJsSVehHOibZ3NpUuifgeCSEHJccXwAj47MZB4ELCx j9OnIb9Uq0BsI2Ac5iIXoA2hTh1yTNwKI6xToxomrQjePWsslzJTGhoqp Y1P57k3UYKVq6ZOgERyjS30MOkEnfyMKFYyYnJ/6N9Ysf+XEjRJAZSxLh Q==; X-CSE-ConnectionGUID: Kr+OVlLHRpSNRPY7YlOiAw== X-CSE-MsgGUID: GWoLIEnqQtOiZA93xHbTKw== X-IronPort-AV: E=McAfee;i="6700,10204,11292"; a="39070735" X-IronPort-AV: E=Sophos;i="6.12,251,1728975600"; d="scan'208";a="39070735" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Dec 2024 13:39:18 -0800 X-CSE-ConnectionGUID: WFmrtmXiQvavyC5yeTWcoQ== X-CSE-MsgGUID: 5Pg55BtcS/2yUi1o3T+wMw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="103223856" Received: from sohilmeh.sc.intel.com ([172.25.103.65]) by fmviesa005.fm.intel.com with ESMTP; 20 Dec 2024 13:39:17 -0800 From: Sohil Mehta To: x86@kernel.org, Dave Hansen , Tony Luck Cc: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , Thomas Gleixner , Borislav Petkov , "H . Peter Anvin" , "Rafael J . Wysocki" , Len Brown , Andy Lutomirski , Viresh Kumar , Fenghua Yu , Jean Delvare , Guenter Roeck , Sohil Mehta , Zhang Rui , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org, linux-pm@vger.kernel.org, linux-hwmon@vger.kernel.org Subject: [RFC PATCH 10/15] x86/cpu/intel: Replace family 5 model checks with VFM ones Date: Fri, 20 Dec 2024 21:37:05 +0000 Message-ID: <20241220213711.1892696-11-sohil.mehta@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241220213711.1892696-1-sohil.mehta@intel.com> References: <20241220213711.1892696-1-sohil.mehta@intel.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Introduce names for some family 5 models and convert VFM based checks. Signed-off-by: Sohil Mehta --- arch/x86/include/asm/intel-family.h | 3 +++ arch/x86/kernel/cpu/intel.c | 11 +++++------ 2 files changed, 8 insertions(+), 6 deletions(-) diff --git a/arch/x86/include/asm/intel-family.h b/arch/x86/include/asm/intel-family.h index 79cfd42c849f..025d091be98e 100644 --- a/arch/x86/include/asm/intel-family.h +++ b/arch/x86/include/asm/intel-family.h @@ -180,6 +180,9 @@ #define INTEL_XEON_PHI_KNM IFM(6, 0x85) /* Knights Mill */ /* Family 5 */ +#define INTEL_FAM5_START IFM(5, 0x00) /* Notational marker, also P5 A-step */ +#define INTEL_PENTIUM_75 IFM(5, 0x02) /* P54C - Need a better name */ +#define INTEL_PENTIUM_MMX IFM(5, 0x04) /* P55C */ #define INTEL_QUARK_X1000 IFM(5, 0x09) /* Quark X1000 SoC */ /* Family 15 */ diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index 26221f38db70..26962a602e86 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -367,9 +367,8 @@ static void intel_smp_check(struct cpuinfo_x86 *c) /* * Mask B, Pentium, but not Pentium MMX */ - if (c->x86 == 5 && - c->x86_stepping >= 1 && c->x86_stepping <= 4 && - c->x86_model <= 3) { + if (c->x86_vfm >= INTEL_FAM5_START && c->x86_vfm < INTEL_PENTIUM_MMX && + c->x86_stepping >= 1 && c->x86_stepping <= 4) { /* * Remember we have B step Pentia with bugs */ @@ -396,7 +395,7 @@ static void intel_workarounds(struct cpuinfo_x86 *c) * The Quark is also family 5, but does not have the same bug. */ clear_cpu_bug(c, X86_BUG_F00F); - if (c->x86 == 5 && c->x86_model < 9) { + if (c->x86_vfm >= INTEL_FAM5_START && c->x86_vfm < INTEL_QUARK_X1000) { static int f00f_workaround_enabled; set_cpu_bug(c, X86_BUG_F00F); @@ -444,7 +443,7 @@ static void intel_workarounds(struct cpuinfo_x86 *c) * integrated APIC (see 11AP erratum in "Pentium Processor * Specification Update"). */ - if (boot_cpu_has(X86_FEATURE_APIC) && (c->x86<<8 | c->x86_model<<4) == 0x520 && + if (boot_cpu_has(X86_FEATURE_APIC) && c->x86_vfm == INTEL_PENTIUM_75 && (c->x86_stepping < 0x6 || c->x86_stepping == 0xb)) set_cpu_bug(c, X86_BUG_11AP); @@ -626,7 +625,7 @@ static unsigned int intel_size_cache(struct cpuinfo_x86 *c, unsigned int size) * Intel Quark SoC X1000 contains a 4-way set associative * 16K cache with a 16 byte cache line and 256 lines per tag */ - if ((c->x86 == 5) && (c->x86_model == 9)) + if (c->x86_vfm == INTEL_QUARK_X1000) size = 16; return size; } From patchwork Fri Dec 20 21:37:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sohil Mehta X-Patchwork-Id: 852495 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 76D2D22A1E6; Fri, 20 Dec 2024 21:39:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734730765; cv=none; b=T/NghVusGwiuRPaRE9aF+m7VbqdUX0bJkrADq3FhsNK4I+doGt8zSG7xVAwRYSDumTaJ7zMyVE190nbog/SPXIcRqO8xHNMnoKhZ9TlGzTuJu90iWbfgoUy6aYQCKyrfu8jPiwjhtF9u9kRf3cHbPfzCdUOR0y7EpA5xDo0dSBc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734730765; c=relaxed/simple; bh=nskDi7vWKmYmbEC/bVsVOpL6GgLNfPD5bwlSaoQJlAk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ANTJGjpxziJEpOPrQ0nGdw2QX71mxBqLzyjYahilsXkpb6sajrEIeGXOIU/MRray/m3UAY8i9k02pnvPboMUJOlDQQ3DNhremi+xDfCAGb/cE0g2gwZkDv9riFh+78VKZJ0V450UmD2QfWmXiX3EWH+d1a7lryCZOnr1OpgIq7M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=nJsfoUIi; arc=none smtp.client-ip=198.175.65.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="nJsfoUIi" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1734730764; x=1766266764; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=nskDi7vWKmYmbEC/bVsVOpL6GgLNfPD5bwlSaoQJlAk=; b=nJsfoUIiP6fIgeeoj8ayj8PHDKinqSbKsCuz6avURX3Vi8dZFYiosDi6 EHcAJjzhDaGP48nndD3fV0wWFlGpdb4jEKguqznmcyMMZj/THhtaDB2hS CngWQx6yteeu02hGJu+O5DqpJL2ZYN6H64BHRnL1Q2aaaCPNbEEP0YVYR m8qRIWDj2sG+ZRSWB1TZHYaTZBUa9TulxSkpM1mVOffftGHPSLgpbgsTl VvAB92ZhmjTMTgzcsJXG5FjC5VlcYbs1FeQt2MqfrdYl9AoOIPtZ/bdr2 s6GBaZmdEjIBc1zY1p6/7kkJN8P0ff644hg9Wk2DopiN5JjlgsYolha5V g==; X-CSE-ConnectionGUID: Bsr/BlzJSz+EdSUJfCYfFQ== X-CSE-MsgGUID: FLnJxrlWSQek4keCOGDl1A== X-IronPort-AV: E=McAfee;i="6700,10204,11292"; a="39070747" X-IronPort-AV: E=Sophos;i="6.12,251,1728975600"; d="scan'208";a="39070747" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Dec 2024 13:39:19 -0800 X-CSE-ConnectionGUID: Y+pEd0TdQgy9J/VxtRPOfA== X-CSE-MsgGUID: aAIm8e3IShiCRH6xfhcFRw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="103223859" Received: from sohilmeh.sc.intel.com ([172.25.103.65]) by fmviesa005.fm.intel.com with ESMTP; 20 Dec 2024 13:39:17 -0800 From: Sohil Mehta To: x86@kernel.org, Dave Hansen , Tony Luck Cc: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , Thomas Gleixner , Borislav Petkov , "H . Peter Anvin" , "Rafael J . Wysocki" , Len Brown , Andy Lutomirski , Viresh Kumar , Fenghua Yu , Jean Delvare , Guenter Roeck , Sohil Mehta , Zhang Rui , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org, linux-pm@vger.kernel.org, linux-hwmon@vger.kernel.org Subject: [RFC PATCH 11/15] x86/pat: Replace Intel model checks with VFM ones Date: Fri, 20 Dec 2024 21:37:06 +0000 Message-ID: <20241220213711.1892696-12-sohil.mehta@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241220213711.1892696-1-sohil.mehta@intel.com> References: <20241220213711.1892696-1-sohil.mehta@intel.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Introduce markers and names for some family 6 and family 15 models and replace with VFM based checks. Signed-off-by: Sohil Mehta --- arch/x86/include/asm/intel-family.h | 2 ++ arch/x86/mm/pat/memtype.c | 7 ++++--- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/x86/include/asm/intel-family.h b/arch/x86/include/asm/intel-family.h index 025d091be98e..76a184361930 100644 --- a/arch/x86/include/asm/intel-family.h +++ b/arch/x86/include/asm/intel-family.h @@ -186,8 +186,10 @@ #define INTEL_QUARK_X1000 IFM(5, 0x09) /* Quark X1000 SoC */ /* Family 15 */ +#define INTEL_FAM15_START IFM(15, 0x00) /* Notational marker */ #define INTEL_P4_WILLAMETTE IFM(15, 0x01) /* Also Xeon Foster */ #define INTEL_P4_PRESCOTT IFM(15, 0x03) +#define INTEL_P4_CEDARMILL IFM(15, 0x06) /* Also Xeon Dempsey */ /* Family 19 */ #define INTEL_PANTHERCOVE_X IFM(19, 0x01) /* Diamond Rapids */ diff --git a/arch/x86/mm/pat/memtype.c b/arch/x86/mm/pat/memtype.c index feb8cc6a12bf..e6d7dc608b77 100644 --- a/arch/x86/mm/pat/memtype.c +++ b/arch/x86/mm/pat/memtype.c @@ -43,6 +43,7 @@ #include #include +#include #include #include #include @@ -290,9 +291,9 @@ void __init pat_bp_init(void) return; } - if ((c->x86_vendor == X86_VENDOR_INTEL) && - (((c->x86 == 0x6) && (c->x86_model <= 0xd)) || - ((c->x86 == 0xf) && (c->x86_model <= 0x6)))) { + if (c->x86_vendor == X86_VENDOR_INTEL && + ((c->x86_vfm >= INTEL_PENTIUM_PRO && c->x86_vfm <= INTEL_PENTIUM_M_DOTHAN) || + (c->x86_vfm > INTEL_FAM15_START && c->x86_vfm <= INTEL_P4_CEDARMILL))) { /* * PAT support with the lower four entries. Intel Pentium 2, * 3, M, and 4 are affected by PAT errata, which makes the From patchwork Fri Dec 20 21:37:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sohil Mehta X-Patchwork-Id: 852765 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F07BE22A807; Fri, 20 Dec 2024 21:39:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734730766; cv=none; b=SH+Hev3CCKUyOnsas6yxkFqPRb27mwg3K6kIfNFfoa/x7aqrksvGxERgVA/lNWTRqXBESQtu1RhW809l9YuqoxBvGhxUoTk6UGt96YrrGvKxHSTd2t5vJL5o7wnImY7I+MMNpbGnwdPk6ODiJDLqgi/wZv5yepNVgragF8ZgusI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734730766; c=relaxed/simple; bh=sdXp+h2ETwRXHxEyxIcdZXZlBP+plqq6x2FmUGbFHmk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Q/2LNUabbKxIVwEY8rMQpGM5vp7BnZjgBTEczzfPFR5OFgVsx6hC/tFs0T6wd0Fx0OOZzJXOclofNV0ukUXpno9wdTds+oYEaPiYsqZKfdqM433a77xzFw/gd0zNWmtrnP0VF6RnskzgJnJmpiWkKEU91ykaGt1ccMSHNv+8Rq4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Skci+Ity; arc=none smtp.client-ip=198.175.65.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Skci+Ity" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1734730764; x=1766266764; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=sdXp+h2ETwRXHxEyxIcdZXZlBP+plqq6x2FmUGbFHmk=; b=Skci+Ityj10dV3dLb8ZdAIezjHZhQC1u7bx3MYASi7os5nmxpDaLEc0u p3ugPqOS9HU1zt0Rs0abxiM3FQrG0NBgaNR1EYa5dJ6Qozbre/OZXbSCL o6AOKdPyqxgnZBUA2Dmq4p0KAg5u8QneLlpmfw2UYtUPillejg613IY0K h01f1S9izaltOkG8/dSeLMcajWVzt340EKrISSJIOdRUcREqvGaPDw+d4 8g2fvEy7HacOfbUCwfYVEr4Ew/iyp7lDeHN4miopQBWkRg7J7e6ohAlPv Oq+Di6Z3O8z4LuUm6wYcItsdags7wOamLutZaGz5X7IwAv+d3QlL1E3FG Q==; X-CSE-ConnectionGUID: 2THhP3R7Q6KfBIC0FDBwPw== X-CSE-MsgGUID: T+tPAE6oTZGchIojl8Vn6w== X-IronPort-AV: E=McAfee;i="6700,10204,11292"; a="39070757" X-IronPort-AV: E=Sophos;i="6.12,251,1728975600"; d="scan'208";a="39070757" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Dec 2024 13:39:19 -0800 X-CSE-ConnectionGUID: jEjo24QQQdiyh7CqRDStfg== X-CSE-MsgGUID: 5AqDAvbSRcqkKR211zb04A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="103223863" Received: from sohilmeh.sc.intel.com ([172.25.103.65]) by fmviesa005.fm.intel.com with ESMTP; 20 Dec 2024 13:39:18 -0800 From: Sohil Mehta To: x86@kernel.org, Dave Hansen , Tony Luck Cc: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , Thomas Gleixner , Borislav Petkov , "H . Peter Anvin" , "Rafael J . Wysocki" , Len Brown , Andy Lutomirski , Viresh Kumar , Fenghua Yu , Jean Delvare , Guenter Roeck , Sohil Mehta , Zhang Rui , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org, linux-pm@vger.kernel.org, linux-hwmon@vger.kernel.org Subject: [RFC PATCH 12/15] x86/acpi/cstate: Improve Intel family model checks Date: Fri, 20 Dec 2024 21:37:07 +0000 Message-ID: <20241220213711.1892696-13-sohil.mehta@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241220213711.1892696-1-sohil.mehta@intel.com> References: <20241220213711.1892696-1-sohil.mehta@intel.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Update the Intel family checks to consistently use Family 15 instead of Family 0xF. Also, get rid of one of last usages of x86_model by using the new VFM checks. Update the incorrect comment since the check has changed since the initial commit ee1ca48fae7e ("ACPI: Disable ARB_DISABLE on platforms where it is not needed"). commit 3e2ada5867b7 ("ACPI: fix Compaq Evo N800c (Pentium 4m) boot hang regression") removed the P4s and commit 03a05ed11529 ("ACPI: Use the ARB_DISABLE for the CPU which model id is less than 0x0f.") got rid of CORE_YONAH. Signed-off-by: Sohil Mehta --- arch/x86/include/asm/intel-family.h | 3 +++ arch/x86/kernel/acpi/cstate.c | 8 ++++---- 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/arch/x86/include/asm/intel-family.h b/arch/x86/include/asm/intel-family.h index 76a184361930..73e458440fcb 100644 --- a/arch/x86/include/asm/intel-family.h +++ b/arch/x86/include/asm/intel-family.h @@ -179,6 +179,9 @@ #define INTEL_XEON_PHI_KNL IFM(6, 0x57) /* Knights Landing */ #define INTEL_XEON_PHI_KNM IFM(6, 0x85) /* Knights Mill */ +/* Notational marker denoting the last Family 6 model */ +#define INTEL_FAM6_LAST IFM(6, 0xFF) + /* Family 5 */ #define INTEL_FAM5_START IFM(5, 0x00) /* Notational marker, also P5 A-step */ #define INTEL_PENTIUM_75 IFM(5, 0x02) /* P54C - Need a better name */ diff --git a/arch/x86/kernel/acpi/cstate.c b/arch/x86/kernel/acpi/cstate.c index f3ffd0a3a012..6d87d1ebe89b 100644 --- a/arch/x86/kernel/acpi/cstate.c +++ b/arch/x86/kernel/acpi/cstate.c @@ -13,6 +13,7 @@ #include #include +#include #include #include @@ -46,12 +47,11 @@ void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flags, /* * On all recent Intel platforms, ARB_DISABLE is a nop. * So, set bm_control to zero to indicate that ARB_DISABLE - * is not required while entering C3 type state on - * P4, Core and beyond CPUs + * is not required while entering C3 type state. */ if (c->x86_vendor == X86_VENDOR_INTEL && - (c->x86 > 0xf || (c->x86 == 6 && c->x86_model >= 0x0f))) - flags->bm_control = 0; + (c->x86 > 15 || (c->x86_vfm >= INTEL_CORE2_MEROM && c->x86_vfm <= INTEL_FAM6_LAST))) + flags->bm_control = 0; if (c->x86_vendor == X86_VENDOR_CENTAUR) { if (c->x86 > 6 || (c->x86 == 6 && c->x86_model == 0x0f && From patchwork Fri Dec 20 21:37:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sohil Mehta X-Patchwork-Id: 852494 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3D9D4225A57; Fri, 20 Dec 2024 21:39:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734730766; cv=none; b=HCTU81hqOf+Cti/zjdAANprjHxRMcObHI8yUOY06wAK71nh8m1GhyfypofmhENNGJ1/kW8IOcA4pj9qt2LU+AbPf7IE5cVht597JTCBz0C1OKEf8ZtvUOcYOkL5RsqbETbQ065BWTdvN68yc/iJlSqYktsj5aj1BlmZ/HNRvC9k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734730766; c=relaxed/simple; bh=lJi86SDL3jP0QQKtxfp4RUv5GIs6fNzg9Bs4+TE8C9k=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=jvTGtjQDaXqee7+lm3qu/6ZmPRA+5MwpeVYdZlo5fP/87KO4pc11zxkxDNQLt9tSYu03dhLZH75i4BN9ub+SI7pKclpnJXyL97qqlxohw4feMJFM2hvhN49AOMYmxgE4WRV9cTUUjz/YtZcd4dE7fN3LzmdndQ2vA+7KkE3YwQw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=B0oetdcH; arc=none smtp.client-ip=198.175.65.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="B0oetdcH" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1734730765; x=1766266765; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=lJi86SDL3jP0QQKtxfp4RUv5GIs6fNzg9Bs4+TE8C9k=; b=B0oetdcHmzcMGB31t25AtsQnXB9RoP1azrBnX+c/lPIjdDjhlYlQ2rd5 V2x3Hs/OjeGeC9ahg2oM4hGrp2duEWa3bMTo36phxbpctugFlI9SBFEfM rZfrTULmxfgnakuyZKTT3fwiqntUB9mGnV3OdmQKF1BI+rv64O9zntjgO Bbd2Q2l5AiFryzzi7Cjcp1HZ+Q6qqsi+9veehcMCLkTXHDDyywQYwxEHy hJoMP1+JQgDFcmmkrs08Dx+YH1xNZkTBnG9RUTdTb6Oibcxk1RAgt37Y/ BHC17I4gtmVFcIGK7N6GVVTJiFdUy/2aehX9e4CoN+mpUoRhYi5EZV/6S Q==; X-CSE-ConnectionGUID: AGwseDzfRr2B3vIIDSijCQ== X-CSE-MsgGUID: q8aGsFQZRIuquBC3EAt6QQ== X-IronPort-AV: E=McAfee;i="6700,10204,11292"; a="39070769" X-IronPort-AV: E=Sophos;i="6.12,251,1728975600"; d="scan'208";a="39070769" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Dec 2024 13:39:19 -0800 X-CSE-ConnectionGUID: 6FliDagGSaCMJTHqIqm2SA== X-CSE-MsgGUID: qQmQK1VHSF6HWdYzB5TIkA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="103223866" Received: from sohilmeh.sc.intel.com ([172.25.103.65]) by fmviesa005.fm.intel.com with ESMTP; 20 Dec 2024 13:39:18 -0800 From: Sohil Mehta To: x86@kernel.org, Dave Hansen , Tony Luck Cc: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , Thomas Gleixner , Borislav Petkov , "H . Peter Anvin" , "Rafael J . Wysocki" , Len Brown , Andy Lutomirski , Viresh Kumar , Fenghua Yu , Jean Delvare , Guenter Roeck , Sohil Mehta , Zhang Rui , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org, linux-pm@vger.kernel.org, linux-hwmon@vger.kernel.org Subject: [RFC PATCH 13/15] x86/cpu/intel: Bound the non-architectural constant_tsc model checks Date: Fri, 20 Dec 2024 21:37:08 +0000 Message-ID: <20241220213711.1892696-14-sohil.mehta@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241220213711.1892696-1-sohil.mehta@intel.com> References: <20241220213711.1892696-1-sohil.mehta@intel.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Constant TSC has been architectural on Intel CPUs for a while. Supported CPUs use the architectural Invariant TSC bit in CPUID.80000007. A family model check is not required for such CPUs. Prevent unnecessary confusion but restricting the checks and moving it closer to the architectural check. Invariant TSC was likely introduced around the Nehalam timeframe on the Xeon side and Saltwell timeframe on the Atom side. (Needs confirmation) Due to interspersed model numbers use an Ivybridge model number check to be safe. Signed-off-by: Sohil Mehta --- arch/x86/kernel/cpu/intel.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index 26962a602e86..d37ef3a72234 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -210,10 +210,6 @@ static void early_init_intel(struct cpuinfo_x86 *c) { u64 misc_enable; - if ((c->x86 == 0xf && c->x86_model >= 0x03) || - (c->x86 == 0x6 && c->x86_model >= 0x0e)) - set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); - if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64)) c->microcode = intel_get_microcode_revision(); @@ -272,6 +268,11 @@ static void early_init_intel(struct cpuinfo_x86 *c) set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); } + /* Some older CPUs have invariant TSC but may not report it architecturally via 8000_0007 */ + if ((c->x86_vfm >= INTEL_P4_PRESCOTT && c->x86_vfm <= INTEL_P4_WILLAMETTE) || + (c->x86_vfm >= INTEL_CORE_YONAH && c->x86_vfm <= INTEL_IVYBRIDGE)) + set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); + /* Penwell and Cloverview have the TSC which doesn't sleep on S3 */ switch (c->x86_vfm) { case INTEL_ATOM_SALTWELL_MID: From patchwork Fri Dec 20 21:37:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sohil Mehta X-Patchwork-Id: 852493 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9E6BD22B8B0; Fri, 20 Dec 2024 21:39:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734730767; cv=none; b=FP0D1tY4EOOd4a/mcJ6Ga2pR1vDBNGqhp157/mGfpPXhB1QlDqtPoUIsaliibCZEnig3Bfl34+g0a13TwYn9/MmpAATrIr4/BMNV+FLy/WXZcu6SBchLB0z8OKim7Ux0bppq79pry4LjK1+BNa17gDpWT6hHJPHryw9efyaPImw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734730767; c=relaxed/simple; bh=IY7m0pnKYc6827kwQJ/ud1WEARNr4WSixtaPdx1SIcw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=dv3mntVI+pWKS87YGDTc9JeDXxmb8Wilao0QqaQiSnIDGpZj+kPyc0n+VP2hujNrCwkus1+O+4/e6CaIFILLayt4wWF1Eo/5D0+X49epA24evwGFGiSveGVyYtnlxJl9/pj2mb/BrTdbIIv3aW7t8VA4Zu71/uLXbuR0V9QpgKA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=fB5rg8Tu; arc=none smtp.client-ip=198.175.65.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="fB5rg8Tu" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1734730766; x=1766266766; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=IY7m0pnKYc6827kwQJ/ud1WEARNr4WSixtaPdx1SIcw=; b=fB5rg8Tuiwx7OHLjfYy3b2TBeHmATaVccBYlk8SLZ69u74grseCsWNnV d4UJYr1GZW504o6nnCjKH7HQ6asOQjzcJ9hQOjxbhD8g9kiI3g9h2QcOv Y/qvAg1Gm5ZnE3dmQMdZFUpNxQtZdjRVHgOi4Gq0FKiT33SQzX0iTVqnb dnAT7kOXuBeTCfXUBzVLAsG8qZuMQBXbfnPdg4nvHVPxW05nOXBb19CnY c8WBZ3aPt7GLiDA8HwmVDMtl+KEB/AbNkEtxf7M1mTi8MMjT4t/+oiiMu gfNDY4mTbAYNlLQ6r3V3Uom9E0qPu6RjlGlhsqjU4KYCbfOSVXFESyIhV Q==; X-CSE-ConnectionGUID: BJa2STe8SsegExI0dYY1fA== X-CSE-MsgGUID: V3sEdgYrSLGWYtZet2ZnIA== X-IronPort-AV: E=McAfee;i="6700,10204,11292"; a="39070780" X-IronPort-AV: E=Sophos;i="6.12,251,1728975600"; d="scan'208";a="39070780" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Dec 2024 13:39:20 -0800 X-CSE-ConnectionGUID: 7aXvm4FOS3aLBLKlNQfO5w== X-CSE-MsgGUID: yJSFAI3+RuGqA8CR4R0AaA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="103223869" Received: from sohilmeh.sc.intel.com ([172.25.103.65]) by fmviesa005.fm.intel.com with ESMTP; 20 Dec 2024 13:39:19 -0800 From: Sohil Mehta To: x86@kernel.org, Dave Hansen , Tony Luck Cc: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , Thomas Gleixner , Borislav Petkov , "H . Peter Anvin" , "Rafael J . Wysocki" , Len Brown , Andy Lutomirski , Viresh Kumar , Fenghua Yu , Jean Delvare , Guenter Roeck , Sohil Mehta , Zhang Rui , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org, linux-pm@vger.kernel.org, linux-hwmon@vger.kernel.org Subject: [RFC PATCH 14/15] perf/x86: Simplify p6_pmu_init() Date: Fri, 20 Dec 2024 21:37:09 +0000 Message-ID: <20241220213711.1892696-15-sohil.mehta@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241220213711.1892696-1-sohil.mehta@intel.com> References: <20241220213711.1892696-1-sohil.mehta@intel.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 A switch case is unnecessary when only a single case matters. Also, the gaps in the case numbers are due to no CPU with those model numbers being released. Avoid the switch case and combine the cases into simpler VFM checks. Also, this gets rid of one last few Intel x86_model comparisons. No functional change intended. Signed-off-by: Sohil Mehta --- arch/x86/events/intel/p6.c | 28 +++++++--------------------- 1 file changed, 7 insertions(+), 21 deletions(-) diff --git a/arch/x86/events/intel/p6.c b/arch/x86/events/intel/p6.c index a6cffb4f4ef5..37e3beb6d633 100644 --- a/arch/x86/events/intel/p6.c +++ b/arch/x86/events/intel/p6.c @@ -2,6 +2,8 @@ #include #include +#include + #include "../perf_event.h" /* @@ -244,35 +246,19 @@ static __init void p6_pmu_rdpmc_quirk(void) } } +/* Only called for Family 6 CPUs without X86_FEATURE_ARCH_PERFMON */ __init int p6_pmu_init(void) { x86_pmu = p6_pmu; - switch (boot_cpu_data.x86_model) { - case 1: /* Pentium Pro */ - x86_add_quirk(p6_pmu_rdpmc_quirk); - break; - - case 3: /* Pentium II - Klamath */ - case 5: /* Pentium II - Deschutes */ - case 6: /* Pentium II - Mendocino */ - break; - - case 7: /* Pentium III - Katmai */ - case 8: /* Pentium III - Coppermine */ - case 10: /* Pentium III Xeon */ - case 11: /* Pentium III - Tualatin */ - break; - - case 9: /* Pentium M - Banias */ - case 13: /* Pentium M - Dothan */ - break; - - default: + if (boot_cpu_data.x86_vfm >= INTEL_CORE_YONAH) { pr_cont("unsupported p6 CPU model %d ", boot_cpu_data.x86_model); return -ENODEV; } + if (boot_cpu_data.x86_vfm == INTEL_PENTIUM_PRO) + x86_add_quirk(p6_pmu_rdpmc_quirk); + memcpy(hw_cache_event_ids, p6_hw_cache_event_ids, sizeof(hw_cache_event_ids)); From patchwork Fri Dec 20 21:37:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sohil Mehta X-Patchwork-Id: 852764 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1F5EB22B8D9; Fri, 20 Dec 2024 21:39:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734730767; cv=none; b=Tt5EsMo0/gn8qAGDqqfUihMd0QGHvoO44Ok6ohKVQ4pXV0KEpllhn9KsHcWbKnOFafmjiNyivZ/CMZEK4op1JUMH5Zte0FBsEk4iVSajx4y1Zke1l5Y/73Lz+jcgjb/6bJmnWZ5LpwIppj5gIvaXkemIarL2PO0F9rkd5tuDfJ4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734730767; c=relaxed/simple; bh=P7ru4qx+MPgk/Pvi5QoK/6DMjTyTZM1LsOislTZ21R4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=RCDEf5/cqWomf7iK9yPPjsMZtSb6LejC3t5KIC6TgOyplYy4+P3BzSBqmiQDu9XM9Nl7La2+OGriDJlVzveLw6z7+FKBcUkOy+jaKw8aUfEbJfljOzPiB8HdkMqgVPCP0DjecWjCyTf6IWZ6yWYJ+D1ZBXEtx7t+ICsZw5Uvag4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=SVB9Ms6+; arc=none smtp.client-ip=198.175.65.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="SVB9Ms6+" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1734730766; x=1766266766; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=P7ru4qx+MPgk/Pvi5QoK/6DMjTyTZM1LsOislTZ21R4=; b=SVB9Ms6+Bej9Svvy00zudQmAobfUDyczXmXBayot1ZgFOR03lkpMyyXC 6YUmwlHFEaLySnc295IjpHftvXqajEA/JUK6ra5EPGDOOXb9V/E/jUUm3 WAE/CFGw6bcdCv//bpG2iv+FluadQ0+qLe6OPPBb8lUcZFlgJKKige8EP JgeWbgW6YDs3PMiYgDV3GsWuqyHkXa74FtH9/eN32zqpf5xvARX/vM7WE obI8G5XXurjkxt4l2gdImGBGsH/pnei8cPUWp2HDKcNjihPksHOWboJRz SnVNQz7ziPmRiNKVSZ0W87W2eEWET+bUInEhAgKXiOHtq/na2z/ZtxLcK Q==; X-CSE-ConnectionGUID: RhLX0b/IQeuLunz/Fl8icw== X-CSE-MsgGUID: qKGr4nkyTtStz7m6M8XcGA== X-IronPort-AV: E=McAfee;i="6700,10204,11292"; a="39070794" X-IronPort-AV: E=Sophos;i="6.12,251,1728975600"; d="scan'208";a="39070794" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Dec 2024 13:39:20 -0800 X-CSE-ConnectionGUID: Vyab51gZQfeIHUm1FYygxw== X-CSE-MsgGUID: JmFcIO4bQDaV0caz/Pe/lg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="103223872" Received: from sohilmeh.sc.intel.com ([172.25.103.65]) by fmviesa005.fm.intel.com with ESMTP; 20 Dec 2024 13:39:19 -0800 From: Sohil Mehta To: x86@kernel.org, Dave Hansen , Tony Luck Cc: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , Thomas Gleixner , Borislav Petkov , "H . Peter Anvin" , "Rafael J . Wysocki" , Len Brown , Andy Lutomirski , Viresh Kumar , Fenghua Yu , Jean Delvare , Guenter Roeck , Sohil Mehta , Zhang Rui , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org, linux-pm@vger.kernel.org, linux-hwmon@vger.kernel.org Subject: [RFC PATCH 15/15] perf/x86/p4: Replace Pentium 4 model checks with VFM ones Date: Fri, 20 Dec 2024 21:37:10 +0000 Message-ID: <20241220213711.1892696-16-sohil.mehta@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241220213711.1892696-1-sohil.mehta@intel.com> References: <20241220213711.1892696-1-sohil.mehta@intel.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Introduce names for some old pentium 4 models and replace with VFM based checks. Signed-off-by: Sohil Mehta --- arch/x86/events/intel/p4.c | 7 ++++--- arch/x86/include/asm/intel-family.h | 1 + 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/x86/events/intel/p4.c b/arch/x86/events/intel/p4.c index 844bc4fc4724..fb726c6fc6e7 100644 --- a/arch/x86/events/intel/p4.c +++ b/arch/x86/events/intel/p4.c @@ -10,6 +10,7 @@ #include #include +#include #include #include @@ -732,9 +733,9 @@ static bool p4_event_match_cpu_model(unsigned int event_idx) { /* INSTR_COMPLETED event only exist for model 3, 4, 6 (Prescott) */ if (event_idx == P4_EVENT_INSTR_COMPLETED) { - if (boot_cpu_data.x86_model != 3 && - boot_cpu_data.x86_model != 4 && - boot_cpu_data.x86_model != 6) + if (boot_cpu_data.x86_vfm != INTEL_P4_PRESCOTT && + boot_cpu_data.x86_vfm != INTEL_P4_PRESCOTT_2M && + boot_cpu_data.x86_vfm != INTEL_P4_CEDARMILL) return false; } diff --git a/arch/x86/include/asm/intel-family.h b/arch/x86/include/asm/intel-family.h index 73e458440fcb..77840c0b0df3 100644 --- a/arch/x86/include/asm/intel-family.h +++ b/arch/x86/include/asm/intel-family.h @@ -192,6 +192,7 @@ #define INTEL_FAM15_START IFM(15, 0x00) /* Notational marker */ #define INTEL_P4_WILLAMETTE IFM(15, 0x01) /* Also Xeon Foster */ #define INTEL_P4_PRESCOTT IFM(15, 0x03) +#define INTEL_P4_PRESCOTT_2M IFM(15, 0x04) #define INTEL_P4_CEDARMILL IFM(15, 0x06) /* Also Xeon Dempsey */ /* Family 19 */