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Tue, 17 Dec 2024 16:34:18 -0800 (PST) Received: from prasmi.Home ([2a06:5906:61b:2d00:ca61:1d3a:8af0:1c5a]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43656b3b287sm2365625e9.29.2024.12.17.16.34.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Dec 2024 16:34:17 -0800 (PST) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Wim Van Sebroeck , Guenter Roeck , Magnus Damm , Wolfram Sang Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-watchdog@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH 1/6] dt-bindings: clock: rzv2h-cpg: Add syscon compatible for CPG block Date: Wed, 18 Dec 2024 00:34:09 +0000 Message-ID: <20241218003414.490498-2-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241218003414.490498-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20241218003414.490498-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-watchdog@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar The CPG block in the RZ/V2H(P) and RZ/G3E SoCs includes Error Reset Registers (CPG_ERROR_RSTm). A system reset is triggered in response to error interrupt factors, and the corresponding bit is set in the CPG_ERROR_RSTm register. These registers can be utilized by various IP blocks as needed. For example, specific bits in these registers indicate resets caused by events such as underflow or overflow of the watchdog timer. This functionality allows the watchdog driver to determine whether the current boot resulted from a `Power-on Reset` or a `Watchdog Reset`. Add the syscon-compatible property to the RZ/V2H(P) and RZ/G3E CPG block, allowing drivers to interact with the CPG_ERROR_RSTm registers as required. Signed-off-by: Lad Prabhakar --- .../devicetree/bindings/clock/renesas,rzv2h-cpg.yaml | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml b/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml index c3fe76abd549..f42d79e73e70 100644 --- a/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml +++ b/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml @@ -17,9 +17,11 @@ description: properties: compatible: - enum: - - renesas,r9a09g047-cpg # RZ/G3E - - renesas,r9a09g057-cpg # RZ/V2H + items: + - enum: + - renesas,r9a09g047-cpg # RZ/G3E + - renesas,r9a09g057-cpg # RZ/V2H + - const: syscon reg: maxItems: 1 @@ -73,7 +75,7 @@ additionalProperties: false examples: - | clock-controller@10420000 { - compatible = "renesas,r9a09g057-cpg"; + compatible = "renesas,r9a09g057-cpg", "syscon"; reg = <0x10420000 0x10000>; clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>; clock-names = "audio_extal", "rtxin", "qextal"; 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Tue, 17 Dec 2024 16:34:19 -0800 (PST) Received: from prasmi.Home ([2a06:5906:61b:2d00:ca61:1d3a:8af0:1c5a]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43656b3b287sm2365625e9.29.2024.12.17.16.34.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Dec 2024 16:34:18 -0800 (PST) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Wim Van Sebroeck , Guenter Roeck , Magnus Damm , Wolfram Sang Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-watchdog@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH 2/6] arm64: dts: renesas: r9a09g047: Add `syscon` compatible for CPG node Date: Wed, 18 Dec 2024 00:34:10 +0000 Message-ID: <20241218003414.490498-3-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241218003414.490498-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20241218003414.490498-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-watchdog@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar Add `syscon` compatible for CPG node to allow the IP blocks to interact with the CPG registers as needed. Signed-off-by: Lad Prabhakar --- arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi index 7a422e9ad29e..f4e865b534a3 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi @@ -132,7 +132,7 @@ soc: soc { ranges; cpg: clock-controller@10420000 { - compatible = "renesas,r9a09g047-cpg"; + compatible = "renesas,r9a09g047-cpg", "syscon"; reg = <0 0x10420000 0 0x10000>; clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>; clock-names = "audio_extal", "rtxin", "qextal"; From patchwork Wed Dec 18 00:34:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lad, Prabhakar" X-Patchwork-Id: 852001 Received: from mail-wr1-f46.google.com (mail-wr1-f46.google.com [209.85.221.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6F78C22F11; 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Tue, 17 Dec 2024 16:34:20 -0800 (PST) Received: from prasmi.Home ([2a06:5906:61b:2d00:ca61:1d3a:8af0:1c5a]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43656b3b287sm2365625e9.29.2024.12.17.16.34.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Dec 2024 16:34:20 -0800 (PST) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Wim Van Sebroeck , Guenter Roeck , Magnus Damm , Wolfram Sang Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-watchdog@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH 3/6] arm64: dts: renesas: r9a09g057: Add `syscon` compatible for CPG node Date: Wed, 18 Dec 2024 00:34:11 +0000 Message-ID: <20241218003414.490498-4-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241218003414.490498-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20241218003414.490498-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-watchdog@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar Add `syscon` compatible for CPG node to allow the IP blocks to interact with the CPG registers as needed. Signed-off-by: Lad Prabhakar --- arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi index e39da64a32e9..69de6c302b17 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi @@ -243,7 +243,7 @@ pinctrl: pinctrl@10410000 { }; cpg: clock-controller@10420000 { - compatible = "renesas,r9a09g057-cpg"; + compatible = "renesas,r9a09g057-cpg", "syscon"; reg = <0 0x10420000 0 0x10000>; clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>; clock-names = "audio_extal", "rtxin", "qextal"; From patchwork Wed Dec 18 00:34:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lad, Prabhakar" X-Patchwork-Id: 852326 Received: from mail-wm1-f52.google.com (mail-wm1-f52.google.com [209.85.128.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 890343B796; 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Tue, 17 Dec 2024 16:34:22 -0800 (PST) Received: from prasmi.Home ([2a06:5906:61b:2d00:ca61:1d3a:8af0:1c5a]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43656b3b287sm2365625e9.29.2024.12.17.16.34.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Dec 2024 16:34:21 -0800 (PST) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Wim Van Sebroeck , Guenter Roeck , Magnus Damm , Wolfram Sang Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-watchdog@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH 4/6] dt-bindings: watchdog: renesas: Document `renesas,r9a09g057-syscon-wdt-errorrst` property Date: Wed, 18 Dec 2024 00:34:12 +0000 Message-ID: <20241218003414.490498-5-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241218003414.490498-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20241218003414.490498-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-watchdog@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar The RZ/V2H(P) CPG block includes Error Reset Registers (CPG_ERROR_RSTm). A system reset is triggered in response to error interrupt factors, and the corresponding bit is set in the CPG_ERROR_RSTm register. These registers can be utilized by various IP blocks as needed. In the event of a watchdog overflow or underflow, a system reset is issued, and the CPG_ERROR_RST2[0/1/2/3] bits are set depending on the watchdog in use: CM33 = 0, CA55 = 1, CR8_0 = 2, CR8_1 = 3. For the watchdog driver to determine and report the current boot status, it needs to read the CPG_ERROR_RST2[0/1/2/3]bits and provide this information to the user upon request. To facilitate this operation, add `renesas,r9a09g057-syscon-wdt-errorrst` property to the WDT node, which maps to the `syscon` CPG node, enabling retrieval of the necessary information. For example: wdt1: watchdog@14400000 { compatible = "renesas,r9a09g057-wdt"; renesas,r9a09g057-syscon-wdt-errorrst = <&cpg 0xb40 1>; ... }; The `renesas,r9a09g057-syscon-wdt-errorrst` property consists of three cells: 1. The first cell is a phandle to the CPG node. 2. The second cell specifies the offset of the CPG_ERROR_RSTm register within the SYSCON. 3. The third cell indicates the specific bit within the CPG_ERROR_RSTm register. Signed-off-by: Lad Prabhakar --- .../bindings/watchdog/renesas,wdt.yaml | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/Documentation/devicetree/bindings/watchdog/renesas,wdt.yaml b/Documentation/devicetree/bindings/watchdog/renesas,wdt.yaml index 29ada89fdcdc..8d29f5f1be7e 100644 --- a/Documentation/devicetree/bindings/watchdog/renesas,wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/renesas,wdt.yaml @@ -112,6 +112,19 @@ properties: timeout-sec: true + renesas,r9a09g057-syscon-wdt-errorrst: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + The first cell is a phandle to the SYSCON entry required to obtain + the current boot status. The second cell specifies the CPG_ERROR_RSTm + register offset within the SYSCON, and the third cell indicates the + bit within the CPG_ERROR_RSTm register. + items: + - items: + - description: Phandle to the CPG node + - description: The CPG_ERROR_RSTm register offset + - description: The bit within CPG_ERROR_RSTm register of interest + required: - compatible - reg @@ -182,7 +195,11 @@ allOf: properties: interrupts: false interrupt-names: false + required: + - renesas,r9a09g057-syscon-wdt-errorrst else: + properties: + renesas,r9a09g057-syscon-wdt-errorrst: false required: - interrupts From patchwork Wed Dec 18 00:34:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lad, Prabhakar" X-Patchwork-Id: 852000 Received: from mail-wm1-f53.google.com (mail-wm1-f53.google.com [209.85.128.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 17DFC84D29; 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Tue, 17 Dec 2024 16:34:24 -0800 (PST) Received: from prasmi.Home ([2a06:5906:61b:2d00:ca61:1d3a:8af0:1c5a]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43656b3b287sm2365625e9.29.2024.12.17.16.34.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Dec 2024 16:34:23 -0800 (PST) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Wim Van Sebroeck , Guenter Roeck , Magnus Damm , Wolfram Sang Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-watchdog@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH 5/6] watchdog: rzv2h_wdt: Add support to retrieve the bootstatus information Date: Wed, 18 Dec 2024 00:34:13 +0000 Message-ID: <20241218003414.490498-6-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241218003414.490498-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20241218003414.490498-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-watchdog@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar On the RZ/V2H(P) SoC we can determine if the current boot is due to `Power-on-Reset` or due to the `Watchdog`. The information used to determine this is present on the CPG block. The CPG_ERROR_RSTm(m = 2 - 8) registers are set in response to an error interrupt causing an reset. CPG_ERROR_RST2[ERROR_RST0/1/2] is set if there was an underflow/overflow on WDT1 causing an error interrupt. To fetch this information from CPG block `syscon` is used and bootstatus field in the watchdog device is updated based on the CPG_ERROR_RST2[ERROR_RST0/1/2] bit. Upon consumig CPG_ERROR_RST2[ERROR_RST0/1/2] bit we clear it. Signed-off-by: Lad Prabhakar --- drivers/watchdog/rzv2h_wdt.c | 48 +++++++++++++++++++++++++++++++++++- 1 file changed, 47 insertions(+), 1 deletion(-) diff --git a/drivers/watchdog/rzv2h_wdt.c b/drivers/watchdog/rzv2h_wdt.c index 8defd0241213..5ba5965ac170 100644 --- a/drivers/watchdog/rzv2h_wdt.c +++ b/drivers/watchdog/rzv2h_wdt.c @@ -4,14 +4,17 @@ * * Copyright (C) 2024 Renesas Electronics Corporation. */ +#include #include #include #include #include +#include #include #include #include #include +#include #include #include #include @@ -40,6 +43,9 @@ #define WDT_DEFAULT_TIMEOUT 60U +#define CPG_ERROR_RST2(x) BIT(x) +#define CPG_ERROR_RST2_WEN(x) BIT((x) + 16) + static bool nowayout = WATCHDOG_NOWAYOUT; module_param(nowayout, bool, 0); MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" @@ -139,6 +145,11 @@ static const struct watchdog_info rzv2h_wdt_ident = { .identity = "Renesas RZ/V2H WDT Watchdog", }; +static const struct watchdog_info rzv2h_wdt_ident_card_reset = { + .options = WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_CARDRESET, + .identity = "Renesas RZ/V2H WDT Watchdog", +}; + static int rzv2h_wdt_restart(struct watchdog_device *wdev, unsigned long action, void *data) { @@ -206,9 +217,40 @@ static const struct watchdog_ops rzv2h_wdt_ops = { static int rzv2h_wdt_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; struct rzv2h_wdt_priv *priv; + unsigned int bootstatus = 0; + bool cardreset = false; + struct regmap *syscon; int ret; + /* Do not error out to maintain old DT compatibility */ + syscon = syscon_regmap_lookup_by_phandle(np, "renesas,r9a09g057-syscon-wdt-errorrst"); + if (!IS_ERR(syscon)) { + struct of_phandle_args args; + u32 reg; + + ret = of_parse_phandle_with_fixed_args(np, "renesas,r9a09g057-syscon-wdt-errorrst", + 2, 0, &args); + if (ret) + return ret; + + ret = regmap_read(syscon, args.args[0], ®); + if (ret) + return -EINVAL; + + if (reg & CPG_ERROR_RST2(args.args[1])) { + ret = regmap_write(syscon, args.args[0], + CPG_ERROR_RST2(args.args[1]) | + CPG_ERROR_RST2_WEN(args.args[1])); + if (ret) + return -EINVAL; + } + cardreset = true; + bootstatus = reg & CPG_ERROR_RST2(args.args[1]) ? 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Tue, 17 Dec 2024 16:34:26 -0800 (PST) Received: from prasmi.Home ([2a06:5906:61b:2d00:ca61:1d3a:8af0:1c5a]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43656b3b287sm2365625e9.29.2024.12.17.16.34.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Dec 2024 16:34:25 -0800 (PST) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Wim Van Sebroeck , Guenter Roeck , Magnus Damm , Wolfram Sang Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-watchdog@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH 6/6] arm64: dts: renesas: r9a09g057: Add `renesas,r9a09g057-syscon-wdt-errorrst` property to WDT node Date: Wed, 18 Dec 2024 00:34:14 +0000 Message-ID: <20241218003414.490498-7-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241218003414.490498-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20241218003414.490498-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-watchdog@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar Add `renesas,r9a09g057-syscon-wdt-errorrst` property to WDT node, to determine whether the current boot resulted from a `Power-on Reset` or a `Watchdog Reset`. Signed-off-by: Lad Prabhakar --- arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi index 69de6c302b17..44ec54569ce1 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi @@ -445,6 +445,7 @@ wdt0: watchdog@11c00400 { clock-names = "pclk", "oscclk"; resets = <&cpg 0x75>; power-domains = <&cpg>; + renesas,r9a09g057-syscon-wdt-errorrst = <&cpg 0xb40 0>; status = "disabled"; }; @@ -455,6 +456,7 @@ wdt1: watchdog@14400000 { clock-names = "pclk", "oscclk"; resets = <&cpg 0x76>; power-domains = <&cpg>; + renesas,r9a09g057-syscon-wdt-errorrst = <&cpg 0xb40 1>; status = "disabled"; }; @@ -465,6 +467,7 @@ wdt2: watchdog@13000000 { clock-names = "pclk", "oscclk"; resets = <&cpg 0x77>; power-domains = <&cpg>; + renesas,r9a09g057-syscon-wdt-errorrst = <&cpg 0xb40 2>; status = "disabled"; }; @@ -475,6 +478,7 @@ wdt3: watchdog@13000400 { clock-names = "pclk", "oscclk"; resets = <&cpg 0x78>; power-domains = <&cpg>; + renesas,r9a09g057-syscon-wdt-errorrst = <&cpg 0xb40 3>; status = "disabled"; };