From patchwork Mon Dec 16 19:39:33 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grygorii Strashko X-Patchwork-Id: 181795 Delivered-To: patch@linaro.org Received: by 2002:a92:3001:0:0:0:0:0 with SMTP id x1csp4762732ile; Mon, 16 Dec 2019 11:39:46 -0800 (PST) X-Google-Smtp-Source: APXvYqx+eVb2o4uOk8xTmm0rH2/voBWII2nL8ay+qJKcAfjpRADrktmXVSJo0Wvq8vTzQSLBLu4b X-Received: by 2002:a05:6830:1141:: with SMTP id x1mr34117669otq.120.1576525186004; Mon, 16 Dec 2019 11:39:46 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1576525186; cv=none; d=google.com; s=arc-20160816; b=p+dy/lg4f568l/l6hLQxFvvNbTSVWCdatC1X91gMfeFzr0rpnz0NIlT47c2fxPahL6 ZIMVY4LL93JLHHGzpGnJa0+zX5sYqD0YlcXYl6XLNeURrOdLAutzJpxyoh5EWMS+ZtXf zSrNfxEgN00N8Pju3KECN9bnZaulQflUc1C1Rol4PxDCbBCesibJ8vUNFvSab/eUPuPO cGTmcZR6Y5KAulJXg6iLKC3i4Wdp/aqGIQYJIut0NWHXsEFBhdZD6oB6LSq3KmDOM4p5 V1Lz20u+LPbQt3ucMODzcX0dUagZYgsVHrBrWAxgHyDyQtYqi6FI4SmUNCuzl1gjlC82 Ewxg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:message-id:date:subject:cc :to:from:dkim-signature; bh=fHFISX76d/3z4kvmaSh9/CggfzKg2UKNa0Wi+T6T+LE=; b=EjJIsIGmj5ah3sscIJZeYJ4Xusa8878b3NbDrpqp+cc55uOY11CsPfAyrsghxG6+RT mJtIGuPCtPkNcqclltb1m70clwVS1mWBp81XlQUjqTXICe1xosi/t2yCHDNZL7uEaP6E h69mgBpACHOha96ITx6RjoLUQuQlDgBFeuEjVv8d4IM8vReI/um5QycOxCr2SLQfbV63 q3NR4sKXZTHzDpIOvN6zvNFkPJLXlzsQxG9K4lov4raIBdFCix4vLSYn6ad189UI9ySB fh73pb6dh6VUaAgUGCPhV0bVWJ77eHmwsEc1a4XMUl5D0DeN6Z2YfO7FFiu2mPlFG0iy 3/bw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=c2Jxp9TU; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id s2si11147398otd.190.2019.12.16.11.39.45; Mon, 16 Dec 2019 11:39:45 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=c2Jxp9TU; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727183AbfLPTjp (ORCPT + 8 others); Mon, 16 Dec 2019 14:39:45 -0500 Received: from fllv0015.ext.ti.com ([198.47.19.141]:42590 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726426AbfLPTjp (ORCPT ); Mon, 16 Dec 2019 14:39:45 -0500 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id xBGJdf7K115290; Mon, 16 Dec 2019 13:39:41 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1576525181; bh=fHFISX76d/3z4kvmaSh9/CggfzKg2UKNa0Wi+T6T+LE=; h=From:To:CC:Subject:Date; b=c2Jxp9TUyPztonyCfugucKgSH+bxacOmuLLylD9+qvHrSbqPRVnCJYBznMEqg0c/H Tz6BGSx/gBnipalFhQ/DMCfZSxhirFKM5/Je97W2/+IT4Tv/iWZHq+6AIfUGoN1hEK 05HN7pRnNhYBISxD76rYxFni7C+cj7ruygr/UZJI= Received: from DLEE102.ent.ti.com (dlee102.ent.ti.com [157.170.170.32]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id xBGJdfNs086758 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 16 Dec 2019 13:39:41 -0600 Received: from DLEE106.ent.ti.com (157.170.170.36) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Mon, 16 Dec 2019 13:39:40 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Mon, 16 Dec 2019 13:39:40 -0600 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id xBGJddHv084050; Mon, 16 Dec 2019 13:39:40 -0600 From: Grygorii Strashko To: Tero Kristo , Nishanth Menon , Rob Herring , CC: Sekhar Nori , , , Grygorii Strashko Subject: [PATCH] arm64: dts: ti: k3-am65-mcu: add system control module node Date: Mon, 16 Dec 2019 21:39:33 +0200 Message-ID: <20191216193933.31429-1-grygorii.strashko@ti.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The MCU System control module support is added to the device tree to allow drivers to access to their System control module registers. Signed-off-by: Grygorii Strashko --- arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi | 8 ++++++++ arch/arm64/boot/dts/ti/k3-am65.dtsi | 2 ++ 2 files changed, 10 insertions(+) -- 2.17.1 diff --git a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi index 27fc73f94cf9..3f76c2120b95 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi @@ -6,6 +6,14 @@ */ &cbass_mcu { + mcu_conf: scm_conf@40f00000 { + compatible = "syscon", "simple-mfd"; + reg = <0x0 0x40f00000 0x0 0x20000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x40f00000 0x20000>; + }; + mcu_uart0: serial@40a00000 { compatible = "ti,am654-uart"; reg = <0x00 0x40a00000 0x00 0x100>; diff --git a/arch/arm64/boot/dts/ti/k3-am65.dtsi b/arch/arm64/boot/dts/ti/k3-am65.dtsi index 6dfccd5d56c8..0923e71f663a 100644 --- a/arch/arm64/boot/dts/ti/k3-am65.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65.dtsi @@ -74,6 +74,7 @@ /* MCUSS Range */ <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>, + <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */ <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>, @@ -88,6 +89,7 @@ #size-cells = <2>; ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/ <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>, /* First peripheral window */ + <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */ <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */ <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */ <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>, /* MCU SRAM */