From patchwork Mon Dec 16 09:57:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 181647 Delivered-To: patch@linaro.org Received: by 2002:a92:3001:0:0:0:0:0 with SMTP id x1csp4091209ile; Mon, 16 Dec 2019 01:56:12 -0800 (PST) X-Google-Smtp-Source: APXvYqx0/A289gwOails3QBxgA44AjNsDyZOJjPc1OCEUQBvoZ7v1n84J/x56oCytoR2ZRsDm+j9 X-Received: by 2002:a9d:7f16:: with SMTP id j22mr11579800otq.256.1576490172898; Mon, 16 Dec 2019 01:56:12 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1576490172; cv=none; d=google.com; s=arc-20160816; b=OdCPG/dN+zQh0kjIU0i4Gsbwn6FXGA1e616AMG8w9FbFiDeM8KqxV76ON8q/cHg4ka vLeLd7etc6MwUIaCtYPBPwXESNl6JFO7JXNtxPsklWvNDSGDSI+9RBI2mThjnj1ihDIH EVg29lStH6sccpDvr0FzXAglQeCYtrVdlRxkEGefTN4BUpY4HQuDiA7gXuLHUCq/khhF g7fqs/jZiW3VjWWd4/zOb+vgUhuwz5/Sc2Vlbc/AmV8YTe5WrngdkxZozN16QaqZVVeq 2q1iqB0TafaWDoxLZ00z0j56k9zYlNRbIbrBTY8UFea2Hm7PhtjTdpcB92Gm9C9ABfws j0Pg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=VhJSSgKonMP8J+UZxJu16JLCrKr2Kl8xqPLRdnV/E1E=; b=M4EViW6TGF3ksbxMYEoGTFbjtS5EkWQAdR6sZpjLk1EXjtYGEG1o8+/jJv7JivpyC7 EsJfBKSw8IkXFhg9AWWOFpFvK+qnLP0NGmrtMariQRoDITUzLatKMx6fQ+5vNJQXVnZ+ YiYtpogYqdAW9vyLN2of3TWJdKIny/4MAh6Iy/QGp/NP57Hn5AgghmTL5p8//HX50nJZ vTtGA1K4KqIKzbY2RMYG7poaCnGtzeRUdRhc+bWCaha3LEPFJze94wSsalywhVBPMbpD VDZ24liILtoMtNKLhBW727mTO/LCKTlU0eZFQ5ifirdSO62YgYrGJoTfhrNS/tKQA5G/ tvTQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=s7Uj9JcN; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id n137si10155669oig.127.2019.12.16.01.56.12; Mon, 16 Dec 2019 01:56:12 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=s7Uj9JcN; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727189AbfLPJ4L (ORCPT + 27 others); Mon, 16 Dec 2019 04:56:11 -0500 Received: from lelv0143.ext.ti.com ([198.47.23.248]:58734 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727170AbfLPJ4I (ORCPT ); Mon, 16 Dec 2019 04:56:08 -0500 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id xBG9u3LF106027; Mon, 16 Dec 2019 03:56:03 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1576490164; bh=VhJSSgKonMP8J+UZxJu16JLCrKr2Kl8xqPLRdnV/E1E=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=s7Uj9JcN+ZvQ/erGMxSB7Xb91kJBeW0uhi0jCKddmsvtHZ4RL2tK1x5hZNIHmjyYG 5U/oI0e95BTaibvR0yJfN8cS03SS8WRvQK1B+kZfi4d4WQpSI92EozJO7BxuSLaeSW KVCkMEa0AW4pXxBn/xl3MNoT0zbERn4JMXiv92zY= Received: from DFLE113.ent.ti.com (dfle113.ent.ti.com [10.64.6.34]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id xBG9u30U124709 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 16 Dec 2019 03:56:03 -0600 Received: from DFLE109.ent.ti.com (10.64.6.30) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Mon, 16 Dec 2019 03:56:02 -0600 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Mon, 16 Dec 2019 03:56:02 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id xBG9tsJL084408; Mon, 16 Dec 2019 03:56:00 -0600 From: Kishon Vijay Abraham I To: Rob Herring , Anil Varughese , Roger Quadros , Jyri Sarha CC: , Kishon Vijay Abraham I , , Subject: [PATCH v4 02/14] phy: cadence: Sierra: Make "phy_clk" and "sierra_apb" optional resources Date: Mon, 16 Dec 2019 15:27:00 +0530 Message-ID: <20191216095712.13266-3-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191216095712.13266-1-kishon@ti.com> References: <20191216095712.13266-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Certain platforms like TI J721E using Cadence Sierra Serdes doesn't provide explicit phy_clk and reset (APB reset) control. Make them optional here. Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/cadence/phy-cadence-sierra.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.17.1 diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c index de10402f2931..bed68c25682f 100644 --- a/drivers/phy/cadence/phy-cadence-sierra.c +++ b/drivers/phy/cadence/phy-cadence-sierra.c @@ -193,7 +193,7 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev) platform_set_drvdata(pdev, sp); - sp->clk = devm_clk_get(dev, "phy_clk"); + sp->clk = devm_clk_get_optional(dev, "phy_clk"); if (IS_ERR(sp->clk)) { dev_err(dev, "failed to get clock phy_clk\n"); return PTR_ERR(sp->clk); @@ -205,7 +205,7 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev) return PTR_ERR(sp->phy_rst); } - sp->apb_rst = devm_reset_control_get(dev, "sierra_apb"); + sp->apb_rst = devm_reset_control_get_optional(dev, "sierra_apb"); if (IS_ERR(sp->apb_rst)) { dev_err(dev, "failed to get apb reset\n"); return PTR_ERR(sp->apb_rst); From patchwork Mon Dec 16 09:57:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 181648 Delivered-To: patch@linaro.org Received: by 2002:a92:3001:0:0:0:0:0 with SMTP id x1csp4091234ile; Mon, 16 Dec 2019 01:56:14 -0800 (PST) X-Google-Smtp-Source: APXvYqzDBT1ekxmBxvugRZ2mNQfruF+p8TpM81Pf2jFLyJD4cqXfeZBeQ6GnakQ/LNmSxoTSjZvV X-Received: by 2002:a05:6830:1d1:: with SMTP id r17mr32846029ota.151.1576490174722; Mon, 16 Dec 2019 01:56:14 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1576490174; cv=none; d=google.com; s=arc-20160816; b=KUVoFDH/sMoq1bSVgyIoANONg63+jNXAEX9TAABm1Dret5Tt50vH3jHUiCiAeYFs8M 9ip+zf3c4w7V6fBLdJ9Hsgvl0xOrNwibSilsqLdavJF9XrYUyKw6glYHa8EbS+L9nw8o 6BuSD3XYda6CI0qHBfSgsL5miN3oesv/TTKwZ4YyshTZM4ou2wXl5VEN9XeZPLuguEF3 ObLFra6L74yXAVHmt8p+CbLlF+fEHQbaOnpQ1T7QduGhgw8AVLQdjcyCPFhc5GcR97xX QE+4NkIziiVjSMP4DDtbsReJ+hc42Mv2ezapypsnXL5xcenGqX1lfYaPlRngx2hOfWck /HHA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=avI91FBELJT9quIZJP1Cy+zKUk4/9Oroz+ODXwWi4lU=; b=kztSMMhxmDwcUFaUQDy272Nj3+jlmQVIaVEXeaWJMkwol1BZGOpoE1kQhteffpifQM IN9z5fBSX8QoDPRifiGcOCdvjnuGRe/oMkqz/HCiO38WdHY5CxC3v7kKPOwVE9HSRzb4 qBESonhwuIbzsifAxiv32zc5qhouoLY5CUcHm8SsO3JxZa5Cd72tN5dajyLNI+Uy2Ys0 0sYDUfgjeYnVHun7VImUXnUeZTQ2fYKhSA2Cp/XDeoBbfUOgNMoP8GLaK/DS9ZDycH4i KtGDw34SXmuWXZAGN8vCNfdAu4Wk3SiyYMi8XC4lisSZI3aQ9A+LOwWmn/ZSvUX8Bfmo vPtw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=PfDQvo+B; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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This is in perparation for adding SERDES_16G support present in TI's J721E SoC. Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/cadence/phy-cadence-sierra.c | 291 ++++++++++++++++++----- 1 file changed, 237 insertions(+), 54 deletions(-) -- 2.17.1 diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c index bed68c25682f..c60809f615af 100644 --- a/drivers/phy/cadence/phy-cadence-sierra.c +++ b/drivers/phy/cadence/phy-cadence-sierra.c @@ -22,49 +22,63 @@ #include /* PHY register offsets */ -#define SIERRA_PHY_PLL_CFG (0xc00e << 2) -#define SIERRA_DET_STANDEC_A (0x4000 << 2) -#define SIERRA_DET_STANDEC_B (0x4001 << 2) -#define SIERRA_DET_STANDEC_C (0x4002 << 2) -#define SIERRA_DET_STANDEC_D (0x4003 << 2) -#define SIERRA_DET_STANDEC_E (0x4004 << 2) -#define SIERRA_PSM_LANECAL (0x4008 << 2) -#define SIERRA_PSM_DIAG (0x4015 << 2) -#define SIERRA_PSC_TX_A0 (0x4028 << 2) -#define SIERRA_PSC_TX_A1 (0x4029 << 2) -#define SIERRA_PSC_TX_A2 (0x402A << 2) -#define SIERRA_PSC_TX_A3 (0x402B << 2) -#define SIERRA_PSC_RX_A0 (0x4030 << 2) -#define SIERRA_PSC_RX_A1 (0x4031 << 2) -#define SIERRA_PSC_RX_A2 (0x4032 << 2) -#define SIERRA_PSC_RX_A3 (0x4033 << 2) -#define SIERRA_PLLCTRL_SUBRATE (0x403A << 2) -#define SIERRA_PLLCTRL_GEN_D (0x403E << 2) -#define SIERRA_DRVCTRL_ATTEN (0x406A << 2) -#define SIERRA_CLKPATHCTRL_TMR (0x4081 << 2) -#define SIERRA_RX_CREQ_FLTR_A_MODE1 (0x4087 << 2) -#define SIERRA_RX_CREQ_FLTR_A_MODE0 (0x4088 << 2) -#define SIERRA_CREQ_CCLKDET_MODE01 (0x408E << 2) -#define SIERRA_RX_CTLE_MAINTENANCE (0x4091 << 2) -#define SIERRA_CREQ_FSMCLK_SEL (0x4092 << 2) -#define SIERRA_CTLELUT_CTRL (0x4098 << 2) -#define SIERRA_DFE_ECMP_RATESEL (0x40C0 << 2) -#define SIERRA_DFE_SMP_RATESEL (0x40C1 << 2) -#define SIERRA_DEQ_VGATUNE_CTRL (0x40E1 << 2) -#define SIERRA_TMRVAL_MODE3 (0x416E << 2) -#define SIERRA_TMRVAL_MODE2 (0x416F << 2) -#define SIERRA_TMRVAL_MODE1 (0x4170 << 2) -#define SIERRA_TMRVAL_MODE0 (0x4171 << 2) -#define SIERRA_PICNT_MODE1 (0x4174 << 2) -#define SIERRA_CPI_OUTBUF_RATESEL (0x417C << 2) -#define SIERRA_LFPSFILT_NS (0x418A << 2) -#define SIERRA_LFPSFILT_RD (0x418B << 2) -#define SIERRA_LFPSFILT_MP (0x418C << 2) -#define SIERRA_SDFILT_H2L_A (0x4191 << 2) +#define SIERRA_COMMON_CDB_OFFSET 0x0 +#define SIERRA_MACRO_ID_REG 0x0 + +#define SIERRA_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \ + ((0x4000 << (block_offset)) + \ + (((ln) << 9) << (reg_offset))) +#define SIERRA_DET_STANDEC_A 0x000 +#define SIERRA_DET_STANDEC_B 0x001 +#define SIERRA_DET_STANDEC_C 0x002 +#define SIERRA_DET_STANDEC_D 0x003 +#define SIERRA_DET_STANDEC_E 0x004 +#define SIERRA_PSM_LANECAL 0x008 +#define SIERRA_PSM_DIAG 0x015 +#define SIERRA_PSC_TX_A0 0x028 +#define SIERRA_PSC_TX_A1 0x029 +#define SIERRA_PSC_TX_A2 0x02A +#define SIERRA_PSC_TX_A3 0x02B +#define SIERRA_PSC_RX_A0 0x030 +#define SIERRA_PSC_RX_A1 0x031 +#define SIERRA_PSC_RX_A2 0x032 +#define SIERRA_PSC_RX_A3 0x033 +#define SIERRA_PLLCTRL_SUBRATE 0x03A +#define SIERRA_PLLCTRL_GEN_D 0x03E +#define SIERRA_DRVCTRL_ATTEN 0x06A +#define SIERRA_CLKPATHCTRL_TMR 0x081 +#define SIERRA_RX_CREQ_FLTR_A_MODE1 0x087 +#define SIERRA_RX_CREQ_FLTR_A_MODE0 0x088 +#define SIERRA_CREQ_CCLKDET_MODE01 0x08E +#define SIERRA_RX_CTLE_MAINTENANCE 0x091 +#define SIERRA_CREQ_FSMCLK_SEL 0x092 +#define SIERRA_CTLELUT_CTRL 0x098 +#define SIERRA_DFE_ECMP_RATESEL 0x0C0 +#define SIERRA_DFE_SMP_RATESEL 0x0C1 +#define SIERRA_DEQ_VGATUNE_CTRL 0x0E1 +#define SIERRA_TMRVAL_MODE3 0x16E +#define SIERRA_TMRVAL_MODE2 0x16F +#define SIERRA_TMRVAL_MODE1 0x170 +#define SIERRA_TMRVAL_MODE0 0x171 +#define SIERRA_PICNT_MODE1 0x174 +#define SIERRA_CPI_OUTBUF_RATESEL 0x17C +#define SIERRA_LFPSFILT_NS 0x18A +#define SIERRA_LFPSFILT_RD 0x18B +#define SIERRA_LFPSFILT_MP 0x18C +#define SIERRA_SDFILT_H2L_A 0x191 + +#define SIERRA_PHY_CONFIG_CTRL_OFFSET(block_offset) \ + (0xc000 << (block_offset)) +#define SIERRA_PHY_PLL_CFG 0xe #define SIERRA_MACRO_ID 0x00007364 #define SIERRA_MAX_LANES 4 +static const struct reg_field macro_id_type = + REG_FIELD(SIERRA_MACRO_ID_REG, 0, 15); +static const struct reg_field phy_pll_cfg_1 = + REG_FIELD(SIERRA_PHY_PLL_CFG, 1, 1); + struct cdns_sierra_inst { struct phy *phy; u32 phy_type; @@ -80,28 +94,93 @@ struct cdns_reg_pairs { struct cdns_sierra_data { u32 id_value; + u8 block_offset_shift; + u8 reg_offset_shift; u32 pcie_regs; u32 usb_regs; struct cdns_reg_pairs *pcie_vals; struct cdns_reg_pairs *usb_vals; }; -struct cdns_sierra_phy { +struct cdns_regmap_cdb_context { struct device *dev; void __iomem *base; + u8 reg_offset_shift; +}; + +struct cdns_sierra_phy { + struct device *dev; + struct regmap *regmap; struct cdns_sierra_data *init_data; struct cdns_sierra_inst phys[SIERRA_MAX_LANES]; struct reset_control *phy_rst; struct reset_control *apb_rst; + struct regmap *regmap_lane_cdb[SIERRA_MAX_LANES]; + struct regmap *regmap_phy_config_ctrl; + struct regmap *regmap_common_cdb; + struct regmap_field *macro_id_type; + struct regmap_field *phy_pll_cfg_1; struct clk *clk; int nsubnodes; bool autoconf; }; +static int cdns_regmap_write(void *context, unsigned int reg, unsigned int val) +{ + struct cdns_regmap_cdb_context *ctx = context; + u32 offset = reg << ctx->reg_offset_shift; + + writew(val, ctx->base + offset); + + return 0; +} + +static int cdns_regmap_read(void *context, unsigned int reg, unsigned int *val) +{ + struct cdns_regmap_cdb_context *ctx = context; + u32 offset = reg << ctx->reg_offset_shift; + + *val = readw(ctx->base + offset); + return 0; +} + +#define SIERRA_LANE_CDB_REGMAP_CONF(n) \ +{ \ + .name = "sierra_lane" n "_cdb", \ + .reg_stride = 1, \ + .fast_io = true, \ + .reg_write = cdns_regmap_write, \ + .reg_read = cdns_regmap_read, \ +} + +static struct regmap_config cdns_sierra_lane_cdb_config[] = { + SIERRA_LANE_CDB_REGMAP_CONF("0"), + SIERRA_LANE_CDB_REGMAP_CONF("1"), + SIERRA_LANE_CDB_REGMAP_CONF("2"), + SIERRA_LANE_CDB_REGMAP_CONF("3"), +}; + +static struct regmap_config cdns_sierra_common_cdb_config = { + .name = "sierra_common_cdb", + .reg_stride = 1, + .fast_io = true, + .reg_write = cdns_regmap_write, + .reg_read = cdns_regmap_read, +}; + +static struct regmap_config cdns_sierra_phy_config_ctrl_config = { + .name = "sierra_phy_config_ctrl", + .reg_stride = 1, + .fast_io = true, + .reg_write = cdns_regmap_write, + .reg_read = cdns_regmap_read, +}; + static void cdns_sierra_phy_init(struct phy *gphy) { struct cdns_sierra_inst *ins = phy_get_drvdata(gphy); struct cdns_sierra_phy *phy = dev_get_drvdata(gphy->dev.parent); + struct regmap *regmap = phy->regmap; int i, j; struct cdns_reg_pairs *vals; u32 num_regs; @@ -115,10 +194,12 @@ static void cdns_sierra_phy_init(struct phy *gphy) } else { return; } - for (i = 0; i < ins->num_lanes; i++) - for (j = 0; j < num_regs ; j++) - writel(vals[j].val, phy->base + - vals[j].off + (i + ins->mlane) * 0x800); + for (i = 0; i < ins->num_lanes; i++) { + for (j = 0; j < num_regs ; j++) { + regmap = phy->regmap_lane_cdb[i + ins->mlane]; + regmap_write(regmap, vals[j].off, vals[j].val); + } + } } static int cdns_sierra_phy_on(struct phy *gphy) @@ -159,37 +240,136 @@ static int cdns_sierra_get_optional(struct cdns_sierra_inst *inst, static const struct of_device_id cdns_sierra_id_table[]; +static struct regmap *cdns_regmap_init(struct device *dev, void __iomem *base, + u32 block_offset, u8 reg_offset_shift, + const struct regmap_config *config) +{ + struct cdns_regmap_cdb_context *ctx; + + ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); + if (!ctx) + return ERR_PTR(-ENOMEM); + + ctx->dev = dev; + ctx->base = base + block_offset; + ctx->reg_offset_shift = reg_offset_shift; + + return devm_regmap_init(dev, NULL, ctx, config); +} + +static int cdns_regfield_init(struct cdns_sierra_phy *sp) +{ + struct device *dev = sp->dev; + struct regmap_field *field; + struct regmap *regmap; + + regmap = sp->regmap_common_cdb; + field = devm_regmap_field_alloc(dev, regmap, macro_id_type); + if (IS_ERR(field)) { + dev_err(dev, "MACRO_ID_TYPE reg field init failed\n"); + return PTR_ERR(field); + } + sp->macro_id_type = field; + + regmap = sp->regmap_phy_config_ctrl; + field = devm_regmap_field_alloc(dev, regmap, phy_pll_cfg_1); + if (IS_ERR(field)) { + dev_err(dev, "PHY_PLL_CFG_1 reg field init failed\n"); + return PTR_ERR(field); + } + sp->phy_pll_cfg_1 = field; + + return 0; +} + +static int cdns_regmap_init_blocks(struct cdns_sierra_phy *sp, + void __iomem *base, u8 block_offset_shift, + u8 reg_offset_shift) +{ + struct device *dev = sp->dev; + struct regmap *regmap; + u32 block_offset; + int i; + + for (i = 0; i < SIERRA_MAX_LANES; i++) { + block_offset = SIERRA_LANE_CDB_OFFSET(i, block_offset_shift, + reg_offset_shift); + regmap = cdns_regmap_init(dev, base, block_offset, + reg_offset_shift, + &cdns_sierra_lane_cdb_config[i]); + if (IS_ERR(regmap)) { + dev_err(dev, "Failed to init lane CDB regmap\n"); + return PTR_ERR(regmap); + } + sp->regmap_lane_cdb[i] = regmap; + } + + regmap = cdns_regmap_init(dev, base, SIERRA_COMMON_CDB_OFFSET, + reg_offset_shift, + &cdns_sierra_common_cdb_config); + if (IS_ERR(regmap)) { + dev_err(dev, "Failed to init common CDB regmap\n"); + return PTR_ERR(regmap); + } + sp->regmap_common_cdb = regmap; + + block_offset = SIERRA_PHY_CONFIG_CTRL_OFFSET(block_offset_shift); + regmap = cdns_regmap_init(dev, base, block_offset, reg_offset_shift, + &cdns_sierra_phy_config_ctrl_config); + if (IS_ERR(regmap)) { + dev_err(dev, "Failed to init PHY config and control regmap\n"); + return PTR_ERR(regmap); + } + sp->regmap_phy_config_ctrl = regmap; + + return 0; +} + static int cdns_sierra_phy_probe(struct platform_device *pdev) { struct cdns_sierra_phy *sp; struct phy_provider *phy_provider; struct device *dev = &pdev->dev; const struct of_device_id *match; + struct cdns_sierra_data *data; + unsigned int id_value; struct resource *res; int i, ret, node = 0; + void __iomem *base; struct device_node *dn = dev->of_node, *child; if (of_get_child_count(dn) == 0) return -ENODEV; + /* Get init data for this PHY */ + match = of_match_device(cdns_sierra_id_table, dev); + if (!match) + return -EINVAL; + + data = (struct cdns_sierra_data *)match->data; + sp = devm_kzalloc(dev, sizeof(*sp), GFP_KERNEL); if (!sp) return -ENOMEM; dev_set_drvdata(dev, sp); sp->dev = dev; + sp->init_data = data; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - sp->base = devm_ioremap_resource(dev, res); - if (IS_ERR(sp->base)) { + base = devm_ioremap_resource(dev, res); + if (IS_ERR(base)) { dev_err(dev, "missing \"reg\"\n"); - return PTR_ERR(sp->base); + return PTR_ERR(base); } - /* Get init data for this PHY */ - match = of_match_device(cdns_sierra_id_table, dev); - if (!match) - return -EINVAL; - sp->init_data = (struct cdns_sierra_data *)match->data; + ret = cdns_regmap_init_blocks(sp, base, data->block_offset_shift, + data->reg_offset_shift); + if (ret) + return ret; + + ret = cdns_regfield_init(sp); + if (ret) + return ret; platform_set_drvdata(pdev, sp); @@ -219,7 +399,8 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev) reset_control_deassert(sp->apb_rst); /* Check that PHY is present */ - if (sp->init_data->id_value != readl(sp->base)) { + regmap_field_read(sp->macro_id_type, &id_value); + if (sp->init_data->id_value != id_value) { ret = -EINVAL; goto clk_disable; } @@ -267,7 +448,7 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev) /* If more than one subnode, configure the PHY as multilink */ if (!sp->autoconf && sp->nsubnodes > 1) - writel(2, sp->base + SIERRA_PHY_PLL_CFG); + regmap_field_write(sp->phy_pll_cfg_1, 0x1); pm_runtime_enable(dev); phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); @@ -364,6 +545,8 @@ static struct cdns_reg_pairs cdns_pcie_regs[] = { static const struct cdns_sierra_data cdns_map_sierra = { SIERRA_MACRO_ID, + 0x2, + 0x2, ARRAY_SIZE(cdns_pcie_regs), ARRAY_SIZE(cdns_usb_regs), cdns_pcie_regs, From patchwork Mon Dec 16 09:57:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 181650 Delivered-To: patch@linaro.org Received: by 2002:a92:3001:0:0:0:0:0 with SMTP id x1csp4091339ile; Mon, 16 Dec 2019 01:56:23 -0800 (PST) X-Google-Smtp-Source: APXvYqwI1JwjDs8FcnzDjG01lEd5kVQRjX8OJ+knF/tJ1B06kV8c4XuxwDlkck7iNafjnz0QP38g X-Received: by 2002:a05:6830:2157:: with SMTP id r23mr31856188otd.143.1576490183438; Mon, 16 Dec 2019 01:56:23 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1576490183; cv=none; d=google.com; s=arc-20160816; b=VsEmtynEjPhWTeFIkALmQwgw2yiJmMtaQj0xmkTDLNhFNH845zaull+7+5K5xw+o9d 1mvjhyb7JG8Pcsswov9sZYAepSA3l+qBdF6iGCzLulYdtQZIAN5ujyeoca9PHJyqKMZJ IGqOLRLa3oPTXymnbKSmP/RBewcNIU14Tn7TGGCCuyM0rFqXBmF2qLu8vg4vnF0HY62Y cqQ4ytIHA90gg5y1w79e+joBA0//dvP/woLtpRnBDtxx9rldyYDWcoH2653D532WH6Bi Xtov1CpAjvOA1AI6fQr7AT57bC53ql4ZN9pgoPcv0hbO2DsdsBkD8nEOwIVPRnyiNfT+ 29WA== ARC-Message-Signature: i=1; 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Mon, 16 Dec 2019 03:56:11 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id xBG9tsJO084408; Mon, 16 Dec 2019 03:56:08 -0600 From: Kishon Vijay Abraham I To: Rob Herring , Anil Varughese , Roger Quadros , Jyri Sarha CC: , Kishon Vijay Abraham I , , Subject: [PATCH v4 05/14] phy: cadence: Sierra: Make cdns_sierra_phy_init() as phy_ops Date: Mon, 16 Dec 2019 15:27:03 +0530 Message-ID: <20191216095712.13266-6-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191216095712.13266-1-kishon@ti.com> References: <20191216095712.13266-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Instead of invoking cdns_sierra_phy_init() from probe, add it in phy_ops so that it's initialized when the PHY consumer invokes phy_init() Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/cadence/phy-cadence-sierra.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) -- 2.17.1 diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c index d3b0dac2db77..bc2ae260359c 100644 --- a/drivers/phy/cadence/phy-cadence-sierra.c +++ b/drivers/phy/cadence/phy-cadence-sierra.c @@ -176,7 +176,7 @@ static struct regmap_config cdns_sierra_phy_config_ctrl_config = { .reg_read = cdns_regmap_read, }; -static void cdns_sierra_phy_init(struct phy *gphy) +static int cdns_sierra_phy_init(struct phy *gphy) { struct cdns_sierra_inst *ins = phy_get_drvdata(gphy); struct cdns_sierra_phy *phy = dev_get_drvdata(gphy->dev.parent); @@ -185,6 +185,10 @@ static void cdns_sierra_phy_init(struct phy *gphy) struct cdns_reg_pairs *vals; u32 num_regs; + /* Initialise the PHY registers, unless auto configured */ + if (phy->autoconf) + return 0; + if (ins->phy_type == PHY_TYPE_PCIE) { num_regs = phy->init_data->pcie_regs; vals = phy->init_data->pcie_vals; @@ -192,7 +196,7 @@ static void cdns_sierra_phy_init(struct phy *gphy) num_regs = phy->init_data->usb_regs; vals = phy->init_data->usb_vals; } else { - return; + return -EINVAL; } for (i = 0; i < ins->num_lanes; i++) { for (j = 0; j < num_regs ; j++) { @@ -200,6 +204,8 @@ static void cdns_sierra_phy_init(struct phy *gphy) regmap_write(regmap, vals[j].off, vals[j].val); } } + + return 0; } static int cdns_sierra_phy_on(struct phy *gphy) @@ -218,6 +224,7 @@ static int cdns_sierra_phy_off(struct phy *gphy) } static const struct phy_ops ops = { + .init = cdns_sierra_phy_init, .power_on = cdns_sierra_phy_on, .power_off = cdns_sierra_phy_off, .owner = THIS_MODULE, @@ -438,10 +445,6 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev) sp->phys[node].phy = gphy; phy_set_drvdata(gphy, &sp->phys[node]); - /* Initialise the PHY registers, unless auto configured */ - if (!sp->autoconf) - cdns_sierra_phy_init(gphy); - node++; } sp->nsubnodes = node; From patchwork Mon Dec 16 09:57:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 181651 Delivered-To: patch@linaro.org Received: by 2002:a92:3001:0:0:0:0:0 with SMTP id x1csp4091382ile; Mon, 16 Dec 2019 01:56:26 -0800 (PST) X-Google-Smtp-Source: APXvYqz6odAFJdNGmtSOAFdpmGxDqIss1NdJjTN3CCP0R6pcekbzTyPf/tIBC3lP9fH1KVfN/wgy X-Received: by 2002:a05:6830:1599:: with SMTP id i25mr30336920otr.205.1576490186652; Mon, 16 Dec 2019 01:56:26 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1576490186; cv=none; d=google.com; s=arc-20160816; b=xl3cuay8l0BxMM6RYsQ3xFXYUakXIC0hzkGzZxKHRrPGV30+Buq6ZgD+jcQ7SqNbCU XHy0xK7HDjRgsvs72ou5SFshMK7Ig2ytGpledj2nJ36pnZ8JrIb+cDNF6VwxSQIhpnE2 LvhLbZSj6HR3RwcTA8UdONMM/gVvTI3842zkPvTO4cgp6LyD2XvKFzKoK63JQuDaT0cl MAYz+eiph1quKopIEOlJYwGir8tDQTsHCfUmzfJduNgLTQyw9cRxw6zRqrV02fSOBHHt JVhDKtFGs/bFGjJA3WMYBvKYmDCwt1tZDjARfCLv3kt3MDwqxNOXP4Q9N35A2A93SFU7 zWhQ== ARC-Message-Signature: i=1; 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[209.132.180.67]) by mx.google.com with ESMTP id q26si9734870oij.38.2019.12.16.01.56.26; Mon, 16 Dec 2019 01:56:26 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=hGgFG2xx; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727311AbfLPJ4Z (ORCPT + 27 others); Mon, 16 Dec 2019 04:56:25 -0500 Received: from lelv0142.ext.ti.com ([198.47.23.249]:36500 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727261AbfLPJ4W (ORCPT ); Mon, 16 Dec 2019 04:56:22 -0500 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id xBG9uE39056765; Mon, 16 Dec 2019 03:56:14 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1576490174; bh=jhwu9vb8HP8nAIfykGv+pt0vdo/1Nu+RVLPQfa9+g5k=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=hGgFG2xxApG2qi1VT886GXFoWiFmA5SiVxjLdE/1N5FFFfF3cjFHtvlWl2SC7slWD JG9M+2pC6r+sjv0rP/L3FEyENiKPlxib/NG7rXdhKQjMJN7UtuJeDSB/tMeEt5zVIb RvNl4erroGanRZbU1tvGDCpmpvRd72OObyftl7fk= Received: from DLEE113.ent.ti.com (dlee113.ent.ti.com [157.170.170.24]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTP id xBG9uEc3038130; Mon, 16 Dec 2019 03:56:14 -0600 Received: from DLEE112.ent.ti.com (157.170.170.23) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Mon, 16 Dec 2019 03:56:14 -0600 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Mon, 16 Dec 2019 03:56:14 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id xBG9tsJP084408; Mon, 16 Dec 2019 03:56:11 -0600 From: Kishon Vijay Abraham I To: Rob Herring , Anil Varughese , Roger Quadros , Jyri Sarha CC: , Kishon Vijay Abraham I , , Subject: [PATCH v4 06/14] phy: cadence: Sierra: Modify register macro names to be in sync with Sierra user guide Date: Mon, 16 Dec 2019 15:27:04 +0530 Message-ID: <20191216095712.13266-7-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191216095712.13266-1-kishon@ti.com> References: <20191216095712.13266-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org No functional change. Modify register offset macro names to be in sync with Sierra user guide. Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/cadence/phy-cadence-sierra.c | 167 ++++++++++++----------- 1 file changed, 84 insertions(+), 83 deletions(-) -- 2.17.1 diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c index bc2ae260359c..d490e1641cf9 100644 --- a/drivers/phy/cadence/phy-cadence-sierra.c +++ b/drivers/phy/cadence/phy-cadence-sierra.c @@ -22,57 +22,58 @@ #include /* PHY register offsets */ -#define SIERRA_COMMON_CDB_OFFSET 0x0 -#define SIERRA_MACRO_ID_REG 0x0 +#define SIERRA_COMMON_CDB_OFFSET 0x0 +#define SIERRA_MACRO_ID_REG 0x0 #define SIERRA_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \ ((0x4000 << (block_offset)) + \ (((ln) << 9) << (reg_offset))) -#define SIERRA_DET_STANDEC_A 0x000 -#define SIERRA_DET_STANDEC_B 0x001 -#define SIERRA_DET_STANDEC_C 0x002 -#define SIERRA_DET_STANDEC_D 0x003 -#define SIERRA_DET_STANDEC_E 0x004 -#define SIERRA_PSM_LANECAL 0x008 -#define SIERRA_PSM_DIAG 0x015 -#define SIERRA_PSC_TX_A0 0x028 -#define SIERRA_PSC_TX_A1 0x029 -#define SIERRA_PSC_TX_A2 0x02A -#define SIERRA_PSC_TX_A3 0x02B -#define SIERRA_PSC_RX_A0 0x030 -#define SIERRA_PSC_RX_A1 0x031 -#define SIERRA_PSC_RX_A2 0x032 -#define SIERRA_PSC_RX_A3 0x033 -#define SIERRA_PLLCTRL_SUBRATE 0x03A -#define SIERRA_PLLCTRL_GEN_D 0x03E -#define SIERRA_DRVCTRL_ATTEN 0x06A -#define SIERRA_CLKPATHCTRL_TMR 0x081 -#define SIERRA_RX_CREQ_FLTR_A_MODE1 0x087 -#define SIERRA_RX_CREQ_FLTR_A_MODE0 0x088 -#define SIERRA_CREQ_CCLKDET_MODE01 0x08E -#define SIERRA_RX_CTLE_MAINTENANCE 0x091 -#define SIERRA_CREQ_FSMCLK_SEL 0x092 -#define SIERRA_CTLELUT_CTRL 0x098 -#define SIERRA_DFE_ECMP_RATESEL 0x0C0 -#define SIERRA_DFE_SMP_RATESEL 0x0C1 -#define SIERRA_DEQ_VGATUNE_CTRL 0x0E1 -#define SIERRA_TMRVAL_MODE3 0x16E -#define SIERRA_TMRVAL_MODE2 0x16F -#define SIERRA_TMRVAL_MODE1 0x170 -#define SIERRA_TMRVAL_MODE0 0x171 -#define SIERRA_PICNT_MODE1 0x174 -#define SIERRA_CPI_OUTBUF_RATESEL 0x17C -#define SIERRA_LFPSFILT_NS 0x18A -#define SIERRA_LFPSFILT_RD 0x18B -#define SIERRA_LFPSFILT_MP 0x18C -#define SIERRA_SDFILT_H2L_A 0x191 + +#define SIERRA_DET_STANDEC_A_PREG 0x000 +#define SIERRA_DET_STANDEC_B_PREG 0x001 +#define SIERRA_DET_STANDEC_C_PREG 0x002 +#define SIERRA_DET_STANDEC_D_PREG 0x003 +#define SIERRA_DET_STANDEC_E_PREG 0x004 +#define SIERRA_PSM_LANECAL_PREG 0x008 +#define SIERRA_PSM_DIAG_PREG 0x015 +#define SIERRA_PSC_TX_A0_PREG 0x028 +#define SIERRA_PSC_TX_A1_PREG 0x029 +#define SIERRA_PSC_TX_A2_PREG 0x02A +#define SIERRA_PSC_TX_A3_PREG 0x02B +#define SIERRA_PSC_RX_A0_PREG 0x030 +#define SIERRA_PSC_RX_A1_PREG 0x031 +#define SIERRA_PSC_RX_A2_PREG 0x032 +#define SIERRA_PSC_RX_A3_PREG 0x033 +#define SIERRA_PLLCTRL_SUBRATE_PREG 0x03A +#define SIERRA_PLLCTRL_GEN_D_PREG 0x03E +#define SIERRA_DRVCTRL_ATTEN_PREG 0x06A +#define SIERRA_CLKPATHCTRL_TMR_PREG 0x081 +#define SIERRA_RX_CREQ_FLTR_A_MODE1_PREG 0x087 +#define SIERRA_RX_CREQ_FLTR_A_MODE0_PREG 0x088 +#define SIERRA_CREQ_CCLKDET_MODE01_PREG 0x08E +#define SIERRA_RX_CTLE_MAINTENANCE_PREG 0x091 +#define SIERRA_CREQ_FSMCLK_SEL_PREG 0x092 +#define SIERRA_CTLELUT_CTRL_PREG 0x098 +#define SIERRA_DFE_ECMP_RATESEL_PREG 0x0C0 +#define SIERRA_DFE_SMP_RATESEL_PREG 0x0C1 +#define SIERRA_DEQ_VGATUNE_CTRL_PREG 0x0E1 +#define SIERRA_TMRVAL_MODE3_PREG 0x16E +#define SIERRA_TMRVAL_MODE2_PREG 0x16F +#define SIERRA_TMRVAL_MODE1_PREG 0x170 +#define SIERRA_TMRVAL_MODE0_PREG 0x171 +#define SIERRA_PICNT_MODE1_PREG 0x174 +#define SIERRA_CPI_OUTBUF_RATESEL_PREG 0x17C +#define SIERRA_LFPSFILT_NS_PREG 0x18A +#define SIERRA_LFPSFILT_RD_PREG 0x18B +#define SIERRA_LFPSFILT_MP_PREG 0x18C +#define SIERRA_SDFILT_H2L_A_PREG 0x191 #define SIERRA_PHY_CONFIG_CTRL_OFFSET(block_offset) \ (0xc000 << (block_offset)) -#define SIERRA_PHY_PLL_CFG 0xe +#define SIERRA_PHY_PLL_CFG 0xe -#define SIERRA_MACRO_ID 0x00007364 -#define SIERRA_MAX_LANES 4 +#define SIERRA_MACRO_ID 0x00007364 +#define SIERRA_MAX_LANES 4 static const struct reg_field macro_id_type = REG_FIELD(SIERRA_MACRO_ID_REG, 0, 15); @@ -496,42 +497,42 @@ static struct cdns_reg_pairs cdns_usb_regs[] = { * These values are specific to this specific hardware * configuration. */ - {0xFE0A, SIERRA_DET_STANDEC_A}, - {0x000F, SIERRA_DET_STANDEC_B}, - {0x55A5, SIERRA_DET_STANDEC_C}, - {0x69AD, SIERRA_DET_STANDEC_D}, - {0x0241, SIERRA_DET_STANDEC_E}, - {0x0110, SIERRA_PSM_LANECAL}, - {0xCF00, SIERRA_PSM_DIAG}, - {0x001F, SIERRA_PSC_TX_A0}, - {0x0007, SIERRA_PSC_TX_A1}, - {0x0003, SIERRA_PSC_TX_A2}, - {0x0003, SIERRA_PSC_TX_A3}, - {0x0FFF, SIERRA_PSC_RX_A0}, - {0x0003, SIERRA_PSC_RX_A1}, - {0x0003, SIERRA_PSC_RX_A2}, - {0x0001, SIERRA_PSC_RX_A3}, - {0x0001, SIERRA_PLLCTRL_SUBRATE}, - {0x0406, SIERRA_PLLCTRL_GEN_D}, - {0x0000, SIERRA_DRVCTRL_ATTEN}, - {0x823E, SIERRA_CLKPATHCTRL_TMR}, - {0x078F, SIERRA_RX_CREQ_FLTR_A_MODE1}, - {0x078F, SIERRA_RX_CREQ_FLTR_A_MODE0}, - {0x7B3C, SIERRA_CREQ_CCLKDET_MODE01}, - {0x023C, SIERRA_RX_CTLE_MAINTENANCE}, - {0x3232, SIERRA_CREQ_FSMCLK_SEL}, - {0x8452, SIERRA_CTLELUT_CTRL}, - {0x4121, SIERRA_DFE_ECMP_RATESEL}, - {0x4121, SIERRA_DFE_SMP_RATESEL}, - {0x9999, SIERRA_DEQ_VGATUNE_CTRL}, - {0x0330, SIERRA_TMRVAL_MODE0}, - {0x01FF, SIERRA_PICNT_MODE1}, - {0x0009, SIERRA_CPI_OUTBUF_RATESEL}, - {0x000F, SIERRA_LFPSFILT_NS}, - {0x0009, SIERRA_LFPSFILT_RD}, - {0x0001, SIERRA_LFPSFILT_MP}, - {0x8013, SIERRA_SDFILT_H2L_A}, - {0x0400, SIERRA_TMRVAL_MODE1}, + {0xFE0A, SIERRA_DET_STANDEC_A_PREG}, + {0x000F, SIERRA_DET_STANDEC_B_PREG}, + {0x55A5, SIERRA_DET_STANDEC_C_PREG}, + {0x69AD, SIERRA_DET_STANDEC_D_PREG}, + {0x0241, SIERRA_DET_STANDEC_E_PREG}, + {0x0110, SIERRA_PSM_LANECAL_PREG}, + {0xCF00, SIERRA_PSM_DIAG_PREG}, + {0x001F, SIERRA_PSC_TX_A0_PREG}, + {0x0007, SIERRA_PSC_TX_A1_PREG}, + {0x0003, SIERRA_PSC_TX_A2_PREG}, + {0x0003, SIERRA_PSC_TX_A3_PREG}, + {0x0FFF, SIERRA_PSC_RX_A0_PREG}, + {0x0003, SIERRA_PSC_RX_A1_PREG}, + {0x0003, SIERRA_PSC_RX_A2_PREG}, + {0x0001, SIERRA_PSC_RX_A3_PREG}, + {0x0001, SIERRA_PLLCTRL_SUBRATE_PREG}, + {0x0406, SIERRA_PLLCTRL_GEN_D_PREG}, + {0x0000, SIERRA_DRVCTRL_ATTEN_PREG}, + {0x823E, SIERRA_CLKPATHCTRL_TMR_PREG}, + {0x078F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG}, + {0x078F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG}, + {0x7B3C, SIERRA_CREQ_CCLKDET_MODE01_PREG}, + {0x023C, SIERRA_RX_CTLE_MAINTENANCE_PREG}, + {0x3232, SIERRA_CREQ_FSMCLK_SEL_PREG}, + {0x8452, SIERRA_CTLELUT_CTRL_PREG}, + {0x4121, SIERRA_DFE_ECMP_RATESEL_PREG}, + {0x4121, SIERRA_DFE_SMP_RATESEL_PREG}, + {0x9999, SIERRA_DEQ_VGATUNE_CTRL_PREG}, + {0x0330, SIERRA_TMRVAL_MODE0_PREG}, + {0x01FF, SIERRA_PICNT_MODE1_PREG}, + {0x0009, SIERRA_CPI_OUTBUF_RATESEL_PREG}, + {0x000F, SIERRA_LFPSFILT_NS_PREG}, + {0x0009, SIERRA_LFPSFILT_RD_PREG}, + {0x0001, SIERRA_LFPSFILT_MP_PREG}, + {0x8013, SIERRA_SDFILT_H2L_A_PREG}, + {0x0400, SIERRA_TMRVAL_MODE1_PREG}, }; static struct cdns_reg_pairs cdns_pcie_regs[] = { @@ -540,10 +541,10 @@ static struct cdns_reg_pairs cdns_pcie_regs[] = { * These values are specific to this specific hardware * configuration. */ - {0x891f, SIERRA_DET_STANDEC_D}, - {0x0053, SIERRA_DET_STANDEC_E}, - {0x0400, SIERRA_TMRVAL_MODE2}, - {0x0200, SIERRA_TMRVAL_MODE3}, + {0x891f, SIERRA_DET_STANDEC_D_PREG}, + {0x0053, SIERRA_DET_STANDEC_E_PREG}, + {0x0400, SIERRA_TMRVAL_MODE2_PREG}, + {0x0200, SIERRA_TMRVAL_MODE3_PREG}, }; static const struct cdns_sierra_data cdns_map_sierra = { From patchwork Mon Dec 16 09:57:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 181657 Delivered-To: patch@linaro.org Received: by 2002:a92:3001:0:0:0:0:0 with SMTP id x1csp4091615ile; Mon, 16 Dec 2019 01:56:44 -0800 (PST) X-Google-Smtp-Source: APXvYqzUJFMll1iNbkZ02r4B+bjWkbsxWAxL/GxgC2WDWxlZEqMm+d5IBNC0ZUw1MC0r9fPdIMQ1 X-Received: by 2002:a9d:7147:: with SMTP id y7mr29823933otj.353.1576490204134; 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[209.132.180.67]) by mx.google.com with ESMTP id p2si13699008otc.62.2019.12.16.01.56.43; Mon, 16 Dec 2019 01:56:44 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="XrD5/KYc"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727415AbfLPJ4n (ORCPT + 27 others); Mon, 16 Dec 2019 04:56:43 -0500 Received: from lelv0143.ext.ti.com ([198.47.23.248]:58834 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727333AbfLPJ4l (ORCPT ); Mon, 16 Dec 2019 04:56:41 -0500 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id xBG9uSwc106137; Mon, 16 Dec 2019 03:56:28 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1576490188; bh=hOJHDmL6AFhdHJjk4PXU1SdyLIBqNQCFUPS9hn289rg=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=XrD5/KYc7fdQd9L1OvUsxoi7uX5JF+Zq0yu2PBvXqL19r9I54e5FWU3LPCcqWVfOB 3nji6WHd8N6detzrLV4YI+udsXsowZMbFmUEMco6FZFtSuQak1UTGSkshWhSg8dDK3 kJG8+Y0UlX6u+JlyvQpqBUt4iHJxMENJRKy9iEKE= Received: from DLEE113.ent.ti.com (dlee113.ent.ti.com [157.170.170.24]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTP id xBG9uS4W038405; Mon, 16 Dec 2019 03:56:28 -0600 Received: from DLEE106.ent.ti.com (157.170.170.36) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Mon, 16 Dec 2019 03:56:28 -0600 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Mon, 16 Dec 2019 03:56:28 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id xBG9tsJU084408; Mon, 16 Dec 2019 03:56:25 -0600 From: Kishon Vijay Abraham I To: Rob Herring , Anil Varughese , Roger Quadros , Jyri Sarha CC: , Kishon Vijay Abraham I , , Subject: [PATCH v4 11/14] phy: cadence: Sierra: Set cmn_refclk_dig_div/cmn_refclk1_dig_div frequency to 25MHz Date: Mon, 16 Dec 2019 15:27:09 +0530 Message-ID: <20191216095712.13266-12-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191216095712.13266-1-kishon@ti.com> References: <20191216095712.13266-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Set cmn_refclk_dig_div/cmn_refclk1_dig_div frequency to 25MHz as specified in "Common Module Clock Configurations" of the Cadence Sierra 16FFC Multi-Protocol PHY PMA Specification. It is set to 25MHz since the only user of Cadence Sierra SERDES, TI J721E SoC provides input clock frequency of 100MHz. For other frequencies, cmn_refclk_dig_div/cmn_refclk1_dig_div should be configured based on the "Common Module Clock Configurations". Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/cadence/phy-cadence-sierra.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) -- 2.17.1 diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c index 665a6dbc7816..82466d0e9b38 100644 --- a/drivers/phy/cadence/phy-cadence-sierra.c +++ b/drivers/phy/cadence/phy-cadence-sierra.c @@ -198,6 +198,8 @@ struct cdns_sierra_phy { struct regmap_field *phy_pll_cfg_1; struct regmap_field *pllctrl_lock[SIERRA_MAX_LANES]; struct clk *clk; + struct clk *cmn_refclk_dig_div; + struct clk *cmn_refclk1_dig_div; int nsubnodes; u32 num_lanes; bool autoconf; @@ -279,6 +281,8 @@ static int cdns_sierra_phy_init(struct phy *gphy) if (phy->autoconf) return 0; + clk_set_rate(phy->cmn_refclk_dig_div, 25000000); + clk_set_rate(phy->cmn_refclk1_dig_div, 25000000); if (ins->phy_type == PHY_TYPE_PCIE) { num_cmn_regs = phy->init_data->pcie_cmn_regs; num_ln_regs = phy->init_data->pcie_ln_regs; @@ -468,6 +472,7 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev) struct resource *res; int i, ret, node = 0; void __iomem *base; + struct clk *clk; struct device_node *dn = dev->of_node, *child; if (of_get_child_count(dn) == 0) @@ -523,6 +528,22 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev) return PTR_ERR(sp->apb_rst); } + clk = devm_clk_get_optional(dev, "cmn_refclk_dig_div"); + if (IS_ERR(clk)) { + dev_err(dev, "cmn_refclk_dig_div clock not found\n"); + ret = PTR_ERR(clk); + return ret; + } + sp->cmn_refclk_dig_div = clk; + + clk = devm_clk_get_optional(dev, "cmn_refclk1_dig_div"); + if (IS_ERR(clk)) { + dev_err(dev, "cmn_refclk1_dig_div clock not found\n"); + ret = PTR_ERR(clk); + return ret; + } + sp->cmn_refclk1_dig_div = clk; + ret = clk_prepare_enable(sp->clk); if (ret) return ret; From patchwork Mon Dec 16 09:57:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 181658 Delivered-To: patch@linaro.org Received: by 2002:a92:3001:0:0:0:0:0 with SMTP id x1csp4091653ile; Mon, 16 Dec 2019 01:56:48 -0800 (PST) X-Google-Smtp-Source: APXvYqyBSAPEibAInZYROSTN8vFdy0YAUOMFaK784rjoQtTVIQkQT0Oo7kHn30wkx2OC2tUs8nv2 X-Received: by 2002:a05:6830:2110:: with SMTP id i16mr30148334otc.337.1576490208015; Mon, 16 Dec 2019 01:56:48 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1576490208; cv=none; d=google.com; s=arc-20160816; b=keoYXwY2RwXhwcC7ZjOzmCoPuKuE9BsOdzSYb5s8230qYleOg6pYOtdGwvU7BKbpoj wO86xr6j2G5kXJjEfTeZyqxe60wA3BXHy/M9mf0uPDQkWjKOzL6iGo53yVgwSygGb2Wd q2zDmI9bgvymLp+zYOCRXyMnDYto95Scn2MsgairXtO/hygmjPoP8fOlNaARt1dYR+yW 6zL4XlDMKCrQKIzxqSRmulFf1vluqQwaMef+fY+C0QqwksKRtVMLoXzUc7FSH7ytqbEO KUr/ZkRNCtYF3eF3QdyKqZ1gn/gGNEaswpw9FyNWdve1diLSUlb0Y8M26sLB1/ijB9sz xwsA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=HnvQVBmnp47FnJbchzKE+jfH8rWFeTqVgl7/AlfabmE=; b=gI5FLKxC8W8pS3kSLA56XVnKsGhosnDYCmbOUQJvDfFQ64gre6LVNFJG5n3eJGJNzE vIEJ++GoYU/numvdfXbpKrzmkVZ1nHLqxSGGKZNv04T1aAdu6DiuQz3I2ajXsd7NYG9n COaKgH9cb5FNqT/cgnWtRspQvdR3Di21glrOAv9Dtz7peaGgba5Ga9NJ9dj2JzJvO6vM ZaXOTh9JWOPsjps/1Enl2CUkRww3VriyZJ9WiN9WJgLz8Do2hzmQsAfrhl6Uk4GyH+Lp 74foL9AC6cSm7RqfYzH7ZTxCrqLSRT1gU2bFen+3O/Yx+P6C0QRJl9JxDbk3wLuTcvku g7vw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=kmr3hKE0; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id t28si10202264otr.16.2019.12.16.01.56.47; Mon, 16 Dec 2019 01:56:48 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=kmr3hKE0; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727443AbfLPJ4q (ORCPT + 27 others); Mon, 16 Dec 2019 04:56:46 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:36400 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727426AbfLPJ4o (ORCPT ); Mon, 16 Dec 2019 04:56:44 -0500 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id xBG9uVDa129936; Mon, 16 Dec 2019 03:56:31 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1576490191; bh=HnvQVBmnp47FnJbchzKE+jfH8rWFeTqVgl7/AlfabmE=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=kmr3hKE0R27FjGau+nVOg+fS7q0Xg8r4yGUeCBTvQiml7/JszRaGiZ+I63/IY8FoL SasKO9DJYOatYC+avVngk9o6IiHom1W40Q8QxsTuKsTxrrQF6IRTblTpsAiiQR2DJJ cuSBPJRwOSRs81naaIZu5RJv751zsexwyb7G4zz0= Received: from DFLE114.ent.ti.com (dfle114.ent.ti.com [10.64.6.35]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTP id xBG9uVWu038426; Mon, 16 Dec 2019 03:56:31 -0600 Received: from DFLE113.ent.ti.com (10.64.6.34) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Mon, 16 Dec 2019 03:56:31 -0600 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Mon, 16 Dec 2019 03:56:31 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id xBG9tsJV084408; Mon, 16 Dec 2019 03:56:28 -0600 From: Kishon Vijay Abraham I To: Rob Herring , Anil Varughese , Roger Quadros , Jyri Sarha CC: , Kishon Vijay Abraham I , , Subject: [PATCH v4 12/14] phy: cadence: Sierra: Use correct dev pointer in cdns_sierra_phy_remove() Date: Mon, 16 Dec 2019 15:27:10 +0530 Message-ID: <20191216095712.13266-13-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191216095712.13266-1-kishon@ti.com> References: <20191216095712.13266-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org commit 44d30d622821d3b ("phy: cadence: Add driver for Sierra PHY"), incorrectly used parent device pointer to get driver data. Fix it here. Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/cadence/phy-cadence-sierra.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.17.1 diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c index 82466d0e9b38..eb87f1a0a596 100644 --- a/drivers/phy/cadence/phy-cadence-sierra.c +++ b/drivers/phy/cadence/phy-cadence-sierra.c @@ -625,7 +625,7 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev) static int cdns_sierra_phy_remove(struct platform_device *pdev) { - struct cdns_sierra_phy *phy = dev_get_drvdata(pdev->dev.parent); + struct cdns_sierra_phy *phy = platform_get_drvdata(pdev); int i; reset_control_assert(phy->phy_rst); From patchwork Mon Dec 16 09:57:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 181659 Delivered-To: patch@linaro.org Received: by 2002:a92:3001:0:0:0:0:0 with SMTP id x1csp4091709ile; Mon, 16 Dec 2019 01:56:53 -0800 (PST) X-Google-Smtp-Source: APXvYqwiA4hwrJdCN4XYF6vDWLccwtTCf8VfqG8wxEHNxVGZtxrmwzkaTImdsAaP794Bt2C0HFM5 X-Received: by 2002:a9d:6b12:: with SMTP id g18mr30214067otp.211.1576490212839; Mon, 16 Dec 2019 01:56:52 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1576490212; cv=none; d=google.com; s=arc-20160816; b=wbhWmBW8IE8cDywZZ5db34JkyrpiCv3pDew86fDz19Am4M2qra7y7LpOCn4r3FGaZF A5aSYkujiHm9kktMH0L70/xMNUVGjIok/dJVSMJaPbCGwJEU0jGqa4VZHUQLfch5/B8n AO19XCzd4lIwktGSNlDjg6KDUF6NG3JV5Z2aWWCvUa/KQAkmKLaVivieC8sd/Eutxvlo v5gNAZ2rovKJamCv9gNgJ2/eekR4VkOaILwWycUfmLrmw8RqsM0QPBnXm7oNdMx75YUy nw1GjVVdfzvAE3O56pgQ+bQpJ6YUKLXDWVDGLcnCrQF3m7uN1zzqEMaaW3pCGqMzUKSI 2IGg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=4jIKZsaBuZUbtBOGR/rHsj4US7wGWPl5B8GqRdXFiiU=; b=Izc7eWeRyO94yjWOFV5sSKWzhUpOVSJXIrb/pGiea9tKw3cjuvjr+DDavvu9SqZwT5 r2iocpO6Gg5o+X9pqNMpKOnG+aw8lmvDlTnpah97Ds1J+3k+jLGIXGc38bTzEEgxpy4F +o7Lnl9Wwc3lWWjkBwpjqYdW2X5c5UCob2X0FHve3Xq1pVm/BvpS7taejQ1yWHNTb/wy SFAY9CfETUcRnvbmeOKbNcEMT2nGaC65MYTa7Ht4AYl/vvAllVqPT5gnQSA3e5Wv1XyV LwpLpFtGz701HuUNEOChlsvtf/oc7MOQHKi8i1A7RMNkFnvXKiTCkTO926xmVDeqcVZQ Fq4A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=fLjPzpRm; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 5si10880375oih.274.2019.12.16.01.56.52; Mon, 16 Dec 2019 01:56:52 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=fLjPzpRm; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727460AbfLPJ4v (ORCPT + 27 others); Mon, 16 Dec 2019 04:56:51 -0500 Received: from fllv0015.ext.ti.com ([198.47.19.141]:55276 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727070AbfLPJ4u (ORCPT ); Mon, 16 Dec 2019 04:56:50 -0500 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id xBG9ubWJ038288; Mon, 16 Dec 2019 03:56:37 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1576490197; bh=4jIKZsaBuZUbtBOGR/rHsj4US7wGWPl5B8GqRdXFiiU=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=fLjPzpRm/76p+LHjKDKLwzZiEgv+7QQFiIKB6wluQ/LixIl8vkXPF3T5Edpi2m/7y bHAKg6mrTdkoE4gwVAEL6woS0Qt2S59lXg4Vi0IPv5StKfqf5oAlQtOa2Pg6Xk/XsX JcQ6mBX9r0YzEqAf5DI5e46aZc1/mnhfAWGpoGko= Received: from DFLE114.ent.ti.com (dfle114.ent.ti.com [10.64.6.35]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTP id xBG9ubT0038481; Mon, 16 Dec 2019 03:56:37 -0600 Received: from DFLE104.ent.ti.com (10.64.6.25) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Mon, 16 Dec 2019 03:56:36 -0600 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Mon, 16 Dec 2019 03:56:36 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id xBG9tsJX084408; Mon, 16 Dec 2019 03:56:34 -0600 From: Kishon Vijay Abraham I To: Rob Herring , Anil Varughese , Roger Quadros , Jyri Sarha CC: , Kishon Vijay Abraham I , , Subject: [PATCH v4 14/14] phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC Date: Mon, 16 Dec 2019 15:27:12 +0530 Message-ID: <20191216095712.13266-15-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191216095712.13266-1-kishon@ti.com> References: <20191216095712.13266-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add support for WIZ module present in TI's J721E SoC. WIZ is a SERDES wrapper used to configure some of the input signals to the SERDES. It is used with both Sierra(16G) and Torrent(10G) SERDES. This driver configures three clock selects (pll0, pll1, dig), two divider clocks and supports resets for each of the lanes. [jsarha@ti.com: Add support for Torrent(10G) SERDES wrapper] Signed-off-by: Jyri Sarha Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/ti/Kconfig | 15 + drivers/phy/ti/Makefile | 1 + drivers/phy/ti/phy-j721e-wiz.c | 898 +++++++++++++++++++++++++++++++++ 3 files changed, 914 insertions(+) create mode 100644 drivers/phy/ti/phy-j721e-wiz.c -- 2.17.1 diff --git a/drivers/phy/ti/Kconfig b/drivers/phy/ti/Kconfig index 174888609779..50f6b829cad0 100644 --- a/drivers/phy/ti/Kconfig +++ b/drivers/phy/ti/Kconfig @@ -33,6 +33,21 @@ config PHY_AM654_SERDES This option enables support for TI AM654 SerDes PHY used for PCIe. +config PHY_J721E_WIZ + tristate "TI J721E WIZ (SERDES Wrapper) support" + depends on OF && ARCH_K3 || COMPILE_TEST + depends on COMMON_CLK + select GENERIC_PHY + select MULTIPLEXER + select REGMAP_MMIO + select MUX_MMIO + help + This option enables support for WIZ module present in TI's J721E + SoC. WIZ is a serdes wrapper used to configure some of the input + signals to the SERDES (Sierra/Torrent). This driver configures + three clock selects (pll0, pll1, dig) and resets for each of the + lanes. + config OMAP_CONTROL_PHY tristate "OMAP CONTROL PHY Driver" depends on ARCH_OMAP2PLUS || COMPILE_TEST diff --git a/drivers/phy/ti/Makefile b/drivers/phy/ti/Makefile index bff901eb0ecc..dcba2571c9bd 100644 --- a/drivers/phy/ti/Makefile +++ b/drivers/phy/ti/Makefile @@ -8,3 +8,4 @@ obj-$(CONFIG_PHY_TUSB1210) += phy-tusb1210.o obj-$(CONFIG_TWL4030_USB) += phy-twl4030-usb.o obj-$(CONFIG_PHY_AM654_SERDES) += phy-am654-serdes.o obj-$(CONFIG_PHY_TI_GMII_SEL) += phy-gmii-sel.o +obj-$(CONFIG_PHY_J721E_WIZ) += phy-j721e-wiz.o diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c new file mode 100644 index 000000000000..b86ebdd68302 --- /dev/null +++ b/drivers/phy/ti/phy-j721e-wiz.c @@ -0,0 +1,898 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * Wrapper driver for SERDES used in J721E + * + * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ + * Author: Kishon Vijay Abraham I + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define WIZ_SERDES_CTRL 0x404 +#define WIZ_SERDES_TOP_CTRL 0x408 +#define WIZ_SERDES_RST 0x40c +#define WIZ_LANECTL(n) (0x480 + (0x40 * (n))) + +#define WIZ_MAX_LANES 4 +#define WIZ_MUX_NUM_CLOCKS 3 +#define WIZ_DIV_NUM_CLOCKS_16G 2 +#define WIZ_DIV_NUM_CLOCKS_10G 1 + +enum wiz_lane_standard_mode { + LANE_MODE_GEN1, + LANE_MODE_GEN2, + LANE_MODE_GEN3, + LANE_MODE_GEN4, +}; + +enum wiz_refclk_mux_sel { + PLL0_REFCLK, + PLL1_REFCLK, + REFCLK_DIG, +}; + +enum wiz_refclk_div_sel { + CMN_REFCLK_DIG_DIV, + CMN_REFCLK1_DIG_DIV, +}; + +static const struct reg_field por_en = REG_FIELD(WIZ_SERDES_CTRL, 31, 31); +static const struct reg_field phy_reset_n = REG_FIELD(WIZ_SERDES_RST, 31, 31); +static const struct reg_field pll1_refclk_mux_sel = + REG_FIELD(WIZ_SERDES_RST, 29, 29); +static const struct reg_field pll0_refclk_mux_sel = + REG_FIELD(WIZ_SERDES_RST, 28, 28); +static const struct reg_field refclk_dig_sel_16g = + REG_FIELD(WIZ_SERDES_RST, 24, 25); +static const struct reg_field refclk_dig_sel_10g = + REG_FIELD(WIZ_SERDES_RST, 24, 24); +static const struct reg_field pma_cmn_refclk_int_mode = + REG_FIELD(WIZ_SERDES_TOP_CTRL, 28, 29); +static const struct reg_field pma_cmn_refclk_mode = + REG_FIELD(WIZ_SERDES_TOP_CTRL, 30, 31); +static const struct reg_field pma_cmn_refclk_dig_div = + REG_FIELD(WIZ_SERDES_TOP_CTRL, 26, 27); +static const struct reg_field pma_cmn_refclk1_dig_div = + REG_FIELD(WIZ_SERDES_TOP_CTRL, 24, 25); + +static const struct reg_field p_enable[WIZ_MAX_LANES] = { + REG_FIELD(WIZ_LANECTL(0), 30, 31), + REG_FIELD(WIZ_LANECTL(1), 30, 31), + REG_FIELD(WIZ_LANECTL(2), 30, 31), + REG_FIELD(WIZ_LANECTL(3), 30, 31), +}; + +static const struct reg_field p_align[WIZ_MAX_LANES] = { + REG_FIELD(WIZ_LANECTL(0), 29, 29), + REG_FIELD(WIZ_LANECTL(1), 29, 29), + REG_FIELD(WIZ_LANECTL(2), 29, 29), + REG_FIELD(WIZ_LANECTL(3), 29, 29), +}; + +static const struct reg_field p_raw_auto_start[WIZ_MAX_LANES] = { + REG_FIELD(WIZ_LANECTL(0), 28, 28), + REG_FIELD(WIZ_LANECTL(1), 28, 28), + REG_FIELD(WIZ_LANECTL(2), 28, 28), + REG_FIELD(WIZ_LANECTL(3), 28, 28), +}; + +static const struct reg_field p_standard_mode[WIZ_MAX_LANES] = { + REG_FIELD(WIZ_LANECTL(0), 24, 25), + REG_FIELD(WIZ_LANECTL(1), 24, 25), + REG_FIELD(WIZ_LANECTL(2), 24, 25), + REG_FIELD(WIZ_LANECTL(3), 24, 25), +}; + +struct wiz_clk_mux { + struct clk_hw hw; + struct regmap_field *field; + u32 *table; + struct clk_init_data clk_data; +}; + +#define to_wiz_clk_mux(_hw) container_of(_hw, struct wiz_clk_mux, hw) + +struct wiz_clk_divider { + struct clk_hw hw; + struct regmap_field *field; + struct clk_div_table *table; + struct clk_init_data clk_data; +}; + +#define to_wiz_clk_div(_hw) container_of(_hw, struct wiz_clk_divider, hw) + +struct wiz_clk_mux_sel { + struct regmap_field *field; + u32 table[4]; + const char *node_name; +}; + +struct wiz_clk_div_sel { + struct regmap_field *field; + struct clk_div_table *table; + const char *node_name; +}; + +static struct wiz_clk_mux_sel clk_mux_sel_16g[] = { + { + /* + * Mux value to be configured for each of the input clocks + * in the order populated in device tree + */ + .table = { 1, 0 }, + .node_name = "pll0-refclk", + }, + { + .table = { 1, 0 }, + .node_name = "pll1-refclk", + }, + { + .table = { 1, 3, 0, 2 }, + .node_name = "refclk-dig", + }, +}; + +static struct wiz_clk_mux_sel clk_mux_sel_10g[] = { + { + /* + * Mux value to be configured for each of the input clocks + * in the order populated in device tree + */ + .table = { 1, 0 }, + .node_name = "pll0-refclk", + }, + { + .table = { 1, 0 }, + .node_name = "pll1-refclk", + }, + { + .table = { 1, 0 }, + .node_name = "refclk-dig", + }, +}; + +static struct clk_div_table clk_div_table[] = { + { .val = 0, .div = 1, }, + { .val = 1, .div = 2, }, + { .val = 2, .div = 4, }, + { .val = 3, .div = 8, }, +}; + +static struct wiz_clk_div_sel clk_div_sel[] = { + { + .table = clk_div_table, + .node_name = "cmn-refclk-dig-div", + }, + { + .table = clk_div_table, + .node_name = "cmn-refclk1-dig-div", + }, +}; + +enum wiz_type { + J721E_WIZ_16G, + J721E_WIZ_10G, +}; + +struct wiz { + struct regmap *regmap; + enum wiz_type type; + struct wiz_clk_mux_sel *clk_mux_sel; + struct wiz_clk_div_sel *clk_div_sel; + unsigned int clk_div_sel_num; + struct regmap_field *por_en; + struct regmap_field *phy_reset_n; + struct regmap_field *p_enable[WIZ_MAX_LANES]; + struct regmap_field *p_align[WIZ_MAX_LANES]; + struct regmap_field *p_raw_auto_start[WIZ_MAX_LANES]; + struct regmap_field *p_standard_mode[WIZ_MAX_LANES]; + struct regmap_field *pma_cmn_refclk_int_mode; + struct regmap_field *pma_cmn_refclk_mode; + struct regmap_field *pma_cmn_refclk_dig_div; + struct regmap_field *pma_cmn_refclk1_dig_div; + + struct device *dev; + u32 num_lanes; + struct platform_device *serdes_pdev; + struct reset_controller_dev wiz_phy_reset_dev; +}; + +static int wiz_reset(struct wiz *wiz) +{ + int ret; + + ret = regmap_field_write(wiz->por_en, 0x1); + if (ret) + return ret; + + mdelay(1); + + ret = regmap_field_write(wiz->por_en, 0x0); + if (ret) + return ret; + + return 0; +} + +static int wiz_mode_select(struct wiz *wiz) +{ + u32 num_lanes = wiz->num_lanes; + int ret; + int i; + + for (i = 0; i < num_lanes; i++) { + ret = regmap_field_write(wiz->p_standard_mode[i], + LANE_MODE_GEN4); + if (ret) + return ret; + } + + return 0; +} + +static int wiz_init_raw_interface(struct wiz *wiz, bool enable) +{ + u32 num_lanes = wiz->num_lanes; + int i; + int ret; + + for (i = 0; i < num_lanes; i++) { + ret = regmap_field_write(wiz->p_align[i], enable); + if (ret) + return ret; + + ret = regmap_field_write(wiz->p_raw_auto_start[i], enable); + if (ret) + return ret; + } + + return 0; +} + +static int wiz_init(struct wiz *wiz) +{ + struct device *dev = wiz->dev; + int ret; + + ret = wiz_reset(wiz); + if (ret) { + dev_err(dev, "WIZ reset failed\n"); + return ret; + } + + ret = wiz_mode_select(wiz); + if (ret) { + dev_err(dev, "WIZ mode select failed\n"); + return ret; + } + + ret = wiz_init_raw_interface(wiz, true); + if (ret) { + dev_err(dev, "WIZ interface initialization failed\n"); + return ret; + } + + return 0; +} + +static int wiz_regfield_init(struct wiz *wiz) +{ + struct wiz_clk_mux_sel *clk_mux_sel; + struct wiz_clk_div_sel *clk_div_sel; + struct regmap *regmap = wiz->regmap; + int num_lanes = wiz->num_lanes; + struct device *dev = wiz->dev; + int i; + + wiz->por_en = devm_regmap_field_alloc(dev, regmap, por_en); + if (IS_ERR(wiz->por_en)) { + dev_err(dev, "POR_EN reg field init failed\n"); + return PTR_ERR(wiz->por_en); + } + + wiz->phy_reset_n = devm_regmap_field_alloc(dev, regmap, + phy_reset_n); + if (IS_ERR(wiz->phy_reset_n)) { + dev_err(dev, "PHY_RESET_N reg field init failed\n"); + return PTR_ERR(wiz->phy_reset_n); + } + + wiz->pma_cmn_refclk_int_mode = + devm_regmap_field_alloc(dev, regmap, pma_cmn_refclk_int_mode); + if (IS_ERR(wiz->pma_cmn_refclk_int_mode)) { + dev_err(dev, "PMA_CMN_REFCLK_INT_MODE reg field init failed\n"); + return PTR_ERR(wiz->pma_cmn_refclk_int_mode); + } + + wiz->pma_cmn_refclk_mode = + devm_regmap_field_alloc(dev, regmap, pma_cmn_refclk_mode); + if (IS_ERR(wiz->pma_cmn_refclk_mode)) { + dev_err(dev, "PMA_CMN_REFCLK_MODE reg field init failed\n"); + return PTR_ERR(wiz->pma_cmn_refclk_mode); + } + + clk_div_sel = &wiz->clk_div_sel[CMN_REFCLK_DIG_DIV]; + clk_div_sel->field = devm_regmap_field_alloc(dev, regmap, + pma_cmn_refclk_dig_div); + if (IS_ERR(clk_div_sel->field)) { + dev_err(dev, "PMA_CMN_REFCLK_DIG_DIV reg field init failed\n"); + return PTR_ERR(clk_div_sel->field); + } + + if (wiz->type == J721E_WIZ_16G) { + clk_div_sel = &wiz->clk_div_sel[CMN_REFCLK1_DIG_DIV]; + clk_div_sel->field = + devm_regmap_field_alloc(dev, regmap, + pma_cmn_refclk1_dig_div); + if (IS_ERR(clk_div_sel->field)) { + dev_err(dev, "PMA_CMN_REFCLK1_DIG_DIV reg field init failed\n"); + return PTR_ERR(clk_div_sel->field); + } + } + + clk_mux_sel = &wiz->clk_mux_sel[PLL0_REFCLK]; + clk_mux_sel->field = devm_regmap_field_alloc(dev, regmap, + pll0_refclk_mux_sel); + if (IS_ERR(clk_mux_sel->field)) { + dev_err(dev, "PLL0_REFCLK_SEL reg field init failed\n"); + return PTR_ERR(clk_mux_sel->field); + } + + clk_mux_sel = &wiz->clk_mux_sel[PLL1_REFCLK]; + clk_mux_sel->field = devm_regmap_field_alloc(dev, regmap, + pll1_refclk_mux_sel); + if (IS_ERR(clk_mux_sel->field)) { + dev_err(dev, "PLL1_REFCLK_SEL reg field init failed\n"); + return PTR_ERR(clk_mux_sel->field); + } + + clk_mux_sel = &wiz->clk_mux_sel[REFCLK_DIG]; + if (wiz->type == J721E_WIZ_10G) + clk_mux_sel->field = + devm_regmap_field_alloc(dev, regmap, + refclk_dig_sel_10g); + else + clk_mux_sel->field = + devm_regmap_field_alloc(dev, regmap, + refclk_dig_sel_16g); + + if (IS_ERR(clk_mux_sel->field)) { + dev_err(dev, "REFCLK_DIG_SEL reg field init failed\n"); + return PTR_ERR(clk_mux_sel->field); + } + + for (i = 0; i < num_lanes; i++) { + wiz->p_enable[i] = devm_regmap_field_alloc(dev, regmap, + p_enable[i]); + if (IS_ERR(wiz->p_enable[i])) { + dev_err(dev, "P%d_ENABLE reg field init failed\n", i); + return PTR_ERR(wiz->p_enable[i]); + } + + wiz->p_align[i] = devm_regmap_field_alloc(dev, regmap, + p_align[i]); + if (IS_ERR(wiz->p_align[i])) { + dev_err(dev, "P%d_ALIGN reg field init failed\n", i); + return PTR_ERR(wiz->p_align[i]); + } + + wiz->p_raw_auto_start[i] = + devm_regmap_field_alloc(dev, regmap, p_raw_auto_start[i]); + if (IS_ERR(wiz->p_raw_auto_start[i])) { + dev_err(dev, "P%d_RAW_AUTO_START reg field init fail\n", + i); + return PTR_ERR(wiz->p_raw_auto_start[i]); + } + + wiz->p_standard_mode[i] = + devm_regmap_field_alloc(dev, regmap, p_standard_mode[i]); + if (IS_ERR(wiz->p_standard_mode[i])) { + dev_err(dev, "P%d_STANDARD_MODE reg field init fail\n", + i); + return PTR_ERR(wiz->p_standard_mode[i]); + } + } + + return 0; +} + +static u8 wiz_clk_mux_get_parent(struct clk_hw *hw) +{ + struct wiz_clk_mux *mux = to_wiz_clk_mux(hw); + struct regmap_field *field = mux->field; + unsigned int val; + + regmap_field_read(field, &val); + return clk_mux_val_to_index(hw, mux->table, 0, val); +} + +static int wiz_clk_mux_set_parent(struct clk_hw *hw, u8 index) +{ + struct wiz_clk_mux *mux = to_wiz_clk_mux(hw); + struct regmap_field *field = mux->field; + int val; + + val = mux->table[index]; + return regmap_field_write(field, val); +} + +static const struct clk_ops wiz_clk_mux_ops = { + .set_parent = wiz_clk_mux_set_parent, + .get_parent = wiz_clk_mux_get_parent, +}; + +static int wiz_mux_clk_register(struct wiz *wiz, struct device_node *node, + struct regmap_field *field, u32 *table) +{ + struct device *dev = wiz->dev; + struct clk_init_data *init; + const char **parent_names; + unsigned int num_parents; + struct wiz_clk_mux *mux; + char clk_name[100]; + struct clk *clk; + int ret; + + mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL); + if (!mux) + return -ENOMEM; + + num_parents = of_clk_get_parent_count(node); + if (num_parents < 2) { + dev_err(dev, "SERDES clock must have parents\n"); + return -EINVAL; + } + + parent_names = devm_kzalloc(dev, (sizeof(char *) * num_parents), + GFP_KERNEL); + if (!parent_names) + return -ENOMEM; + + of_clk_parent_fill(node, parent_names, num_parents); + + snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev), + node->name); + + init = &mux->clk_data; + + init->ops = &wiz_clk_mux_ops; + init->flags = CLK_SET_RATE_NO_REPARENT; + init->parent_names = parent_names; + init->num_parents = num_parents; + init->name = clk_name; + + mux->field = field; + mux->table = table; + mux->hw.init = init; + + clk = devm_clk_register(dev, &mux->hw); + if (IS_ERR(clk)) + return PTR_ERR(clk); + + ret = of_clk_add_provider(node, of_clk_src_simple_get, clk); + if (ret) + dev_err(dev, "Failed to add clock provider: %s\n", clk_name); + + return ret; +} + +static unsigned long wiz_clk_div_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct wiz_clk_divider *div = to_wiz_clk_div(hw); + struct regmap_field *field = div->field; + int val; + + regmap_field_read(field, &val); + + return divider_recalc_rate(hw, parent_rate, val, div->table, 0x0, 2); +} + +static long wiz_clk_div_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *prate) +{ + struct wiz_clk_divider *div = to_wiz_clk_div(hw); + + return divider_round_rate(hw, rate, prate, div->table, 2, 0x0); +} + +static int wiz_clk_div_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct wiz_clk_divider *div = to_wiz_clk_div(hw); + struct regmap_field *field = div->field; + int val; + + val = divider_get_val(rate, parent_rate, div->table, 2, 0x0); + if (val < 0) + return val; + + return regmap_field_write(field, val); +} + +static const struct clk_ops wiz_clk_div_ops = { + .recalc_rate = wiz_clk_div_recalc_rate, + .round_rate = wiz_clk_div_round_rate, + .set_rate = wiz_clk_div_set_rate, +}; + +static int wiz_div_clk_register(struct wiz *wiz, struct device_node *node, + struct regmap_field *field, + struct clk_div_table *table) +{ + struct device *dev = wiz->dev; + struct wiz_clk_divider *div; + struct clk_init_data *init; + const char **parent_names; + char clk_name[100]; + struct clk *clk; + int ret; + + div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL); + if (!div) + return -ENOMEM; + + snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev), + node->name); + + parent_names = devm_kzalloc(dev, sizeof(char *), GFP_KERNEL); + if (!parent_names) + return -ENOMEM; + + of_clk_parent_fill(node, parent_names, 1); + + init = &div->clk_data; + + init->ops = &wiz_clk_div_ops; + init->flags = 0; + init->parent_names = parent_names; + init->num_parents = 1; + init->name = clk_name; + + div->field = field; + div->table = table; + div->hw.init = init; + + clk = devm_clk_register(dev, &div->hw); + if (IS_ERR(clk)) + return PTR_ERR(clk); + + ret = of_clk_add_provider(node, of_clk_src_simple_get, clk); + if (ret) + dev_err(dev, "Failed to add clock provider: %s\n", clk_name); + + return ret; +} + +static void wiz_clock_cleanup(struct wiz *wiz, struct device_node *node) +{ + struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel; + struct device_node *clk_node; + int i; + + for (i = 0; i < WIZ_MUX_NUM_CLOCKS; i++) { + clk_node = of_get_child_by_name(node, clk_mux_sel[i].node_name); + of_clk_del_provider(clk_node); + of_node_put(clk_node); + } +} + +static int wiz_clock_init(struct wiz *wiz, struct device_node *node) +{ + struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel; + struct device *dev = wiz->dev; + struct device_node *clk_node; + const char *node_name; + unsigned long rate; + struct clk *clk; + int ret; + int i; + + clk = devm_clk_get(dev, "core_ref_clk"); + if (IS_ERR(clk)) { + dev_err(dev, "core_ref_clk clock not found\n"); + ret = PTR_ERR(clk); + return ret; + } + + rate = clk_get_rate(clk); + if (rate >= 100000000) + regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x1); + else + regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x3); + + clk = devm_clk_get(dev, "ext_ref_clk"); + if (IS_ERR(clk)) { + dev_err(dev, "ext_ref_clk clock not found\n"); + ret = PTR_ERR(clk); + return ret; + } + + rate = clk_get_rate(clk); + if (rate >= 100000000) + regmap_field_write(wiz->pma_cmn_refclk_mode, 0x0); + else + regmap_field_write(wiz->pma_cmn_refclk_mode, 0x2); + + for (i = 0; i < WIZ_MUX_NUM_CLOCKS; i++) { + node_name = clk_mux_sel[i].node_name; + clk_node = of_get_child_by_name(node, node_name); + if (!clk_node) { + dev_err(dev, "Unable to get %s node\n", node_name); + ret = -EINVAL; + goto err; + } + + ret = wiz_mux_clk_register(wiz, clk_node, clk_mux_sel[i].field, + clk_mux_sel[i].table); + if (ret) { + dev_err(dev, "Failed to register %s clock\n", + node_name); + of_node_put(clk_node); + goto err; + } + + of_node_put(clk_node); + } + + for (i = 0; i < wiz->clk_div_sel_num; i++) { + node_name = clk_div_sel[i].node_name; + clk_node = of_get_child_by_name(node, node_name); + if (!clk_node) { + dev_err(dev, "Unable to get %s node\n", node_name); + ret = -EINVAL; + goto err; + } + + ret = wiz_div_clk_register(wiz, clk_node, clk_div_sel[i].field, + clk_div_sel[i].table); + if (ret) { + dev_err(dev, "Failed to register %s clock\n", + node_name); + of_node_put(clk_node); + goto err; + } + + of_node_put(clk_node); + } + + return 0; +err: + wiz_clock_cleanup(wiz, node); + + return ret; +} + +static int wiz_phy_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct device *dev = rcdev->dev; + struct wiz *wiz = dev_get_drvdata(dev); + int ret = 0; + + if (id == 0) { + ret = regmap_field_write(wiz->phy_reset_n, false); + return ret; + } + + ret = regmap_field_write(wiz->p_enable[id - 1], false); + return ret; +} + +static int wiz_phy_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct device *dev = rcdev->dev; + struct wiz *wiz = dev_get_drvdata(dev); + int ret; + + if (id == 0) { + ret = regmap_field_write(wiz->phy_reset_n, true); + return ret; + } + + ret = regmap_field_write(wiz->p_enable[id - 1], true); + return ret; +} + +static const struct reset_control_ops wiz_phy_reset_ops = { + .assert = wiz_phy_reset_assert, + .deassert = wiz_phy_reset_deassert, +}; + +static struct regmap_config wiz_regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + .fast_io = true, +}; + +static const struct of_device_id wiz_id_table[] = { + { + .compatible = "ti,j721e-wiz-16g", .data = (void *)J721E_WIZ_16G + }, + { + .compatible = "ti,j721e-wiz-10g", .data = (void *)J721E_WIZ_10G + }, + {} +}; +MODULE_DEVICE_TABLE(of, wiz_id_table); + +static int wiz_probe(struct platform_device *pdev) +{ + struct reset_controller_dev *phy_reset_dev; + struct device *dev = &pdev->dev; + struct device_node *node = dev->of_node; + struct platform_device *serdes_pdev; + struct device_node *child_node; + struct regmap *regmap; + struct resource res; + void __iomem *base; + struct wiz *wiz; + u32 num_lanes; + int ret; + + wiz = devm_kzalloc(dev, sizeof(*wiz), GFP_KERNEL); + if (!wiz) + return -ENOMEM; + + wiz->type = (enum wiz_type)of_device_get_match_data(dev); + + child_node = of_get_child_by_name(node, "serdes"); + if (!child_node) { + dev_err(dev, "Failed to get SERDES child DT node\n"); + return -ENODEV; + } + + ret = of_address_to_resource(child_node, 0, &res); + if (ret) { + dev_err(dev, "Failed to get memory resource\n"); + goto err_addr_to_resource; + } + + base = devm_ioremap(dev, res.start, resource_size(&res)); + if (IS_ERR(base)) + goto err_addr_to_resource; + + regmap = devm_regmap_init_mmio(dev, base, &wiz_regmap_config); + if (IS_ERR(regmap)) { + dev_err(dev, "Failed to initialize regmap\n"); + ret = PTR_ERR(regmap); + goto err_addr_to_resource; + } + + ret = of_property_read_u32(node, "num-lanes", &num_lanes); + if (ret) { + dev_err(dev, "Failed to read num-lanes property\n"); + goto err_addr_to_resource; + } + + if (num_lanes > WIZ_MAX_LANES) { + dev_err(dev, "Cannot support %d lanes\n", num_lanes); + goto err_addr_to_resource; + } + + wiz->dev = dev; + wiz->regmap = regmap; + wiz->num_lanes = num_lanes; + if (wiz->type == J721E_WIZ_10G) + wiz->clk_mux_sel = clk_mux_sel_10g; + else + wiz->clk_mux_sel = clk_mux_sel_16g; + + wiz->clk_div_sel = clk_div_sel; + + if (wiz->type == J721E_WIZ_10G) + wiz->clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G; + else + wiz->clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_16G; + + platform_set_drvdata(pdev, wiz); + + ret = wiz_regfield_init(wiz); + if (ret) { + dev_err(dev, "Failed to initialize regfields\n"); + goto err_addr_to_resource; + } + + phy_reset_dev = &wiz->wiz_phy_reset_dev; + phy_reset_dev->dev = dev; + phy_reset_dev->ops = &wiz_phy_reset_ops, + phy_reset_dev->owner = THIS_MODULE, + phy_reset_dev->of_node = node; + /* Reset for each of the lane and one for the entire SERDES */ + phy_reset_dev->nr_resets = num_lanes + 1; + + ret = devm_reset_controller_register(dev, phy_reset_dev); + if (ret < 0) { + dev_warn(dev, "Failed to register reset controller\n"); + goto err_addr_to_resource; + } + + pm_runtime_enable(dev); + ret = pm_runtime_get_sync(dev); + if (ret < 0) { + dev_err(dev, "pm_runtime_get_sync failed\n"); + goto err_get_sync; + } + + ret = wiz_clock_init(wiz, node); + if (ret < 0) { + dev_warn(dev, "Failed to initialize clocks\n"); + goto err_get_sync; + } + + serdes_pdev = of_platform_device_create(child_node, NULL, dev); + if (!serdes_pdev) { + dev_WARN(dev, "Unable to create SERDES platform device\n"); + goto err_pdev_create; + } + wiz->serdes_pdev = serdes_pdev; + + ret = wiz_init(wiz); + if (ret) { + dev_err(dev, "WIZ initialization failed\n"); + goto err_wiz_init; + } + + of_node_put(child_node); + return 0; + +err_wiz_init: + of_platform_device_destroy(&serdes_pdev->dev, NULL); + +err_pdev_create: + wiz_clock_cleanup(wiz, node); + +err_get_sync: + pm_runtime_put(dev); + pm_runtime_disable(dev); + +err_addr_to_resource: + of_node_put(child_node); + + return ret; +} + +static int wiz_remove(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *node = dev->of_node; + struct platform_device *serdes_pdev; + struct wiz *wiz; + + wiz = dev_get_drvdata(dev); + serdes_pdev = wiz->serdes_pdev; + + of_platform_device_destroy(&serdes_pdev->dev, NULL); + wiz_clock_cleanup(wiz, node); + pm_runtime_put(dev); + pm_runtime_disable(dev); + + return 0; +} + +static struct platform_driver wiz_driver = { + .probe = wiz_probe, + .remove = wiz_remove, + .driver = { + .name = "wiz", + .of_match_table = wiz_id_table, + }, +}; +module_platform_driver(wiz_driver); + +MODULE_AUTHOR("Texas Instruments Inc."); +MODULE_DESCRIPTION("TI J721E WIZ driver"); +MODULE_LICENSE("GPL v2");