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[187.189.51.143]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-29e3ae09f25sm2684018fac.49.2024.12.03.12.39.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Dec 2024 12:39:51 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org Subject: [PATCH 01/11] target/arm: Copy entire float_status in is_ebf Date: Tue, 3 Dec 2024 14:39:38 -0600 Message-ID: <20241203203949.483774-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241203203949.483774-1-richard.henderson@linaro.org> References: <20241203203949.483774-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::230; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x230.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Now that float_status has a bunch of fp parameters, it is easier to copy an existing structure than create one from scratch. Begin by copying the structure that corresponds to the FPSR and make only the adjustments required for BFloat16 semantics. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell --- target/arm/tcg/vec_helper.c | 20 +++++++------------- 1 file changed, 7 insertions(+), 13 deletions(-) diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c index e825d501a2..ad6f26545a 100644 --- a/target/arm/tcg/vec_helper.c +++ b/target/arm/tcg/vec_helper.c @@ -2813,25 +2813,19 @@ bool is_ebf(CPUARMState *env, float_status *statusp, float_status *oddstatusp) * no effect on AArch32 instructions. */ bool ebf = is_a64(env) && env->vfp.fpcr & FPCR_EBF; - *statusp = (float_status){ - .tininess_before_rounding = float_tininess_before_rounding, - .float_rounding_mode = float_round_to_odd_inf, - .flush_to_zero = true, - .flush_inputs_to_zero = true, - .default_nan_mode = true, - }; + + *statusp = env->vfp.fp_status; + set_default_nan_mode(true, statusp); if (ebf) { - float_status *fpst = &env->vfp.fp_status; - set_flush_to_zero(get_flush_to_zero(fpst), statusp); - set_flush_inputs_to_zero(get_flush_inputs_to_zero(fpst), statusp); - set_float_rounding_mode(get_float_rounding_mode(fpst), statusp); - /* EBF=1 needs to do a step with round-to-odd semantics */ *oddstatusp = *statusp; set_float_rounding_mode(float_round_to_odd, oddstatusp); + } else { + set_flush_to_zero(true, statusp); + set_flush_inputs_to_zero(true, statusp); + set_float_rounding_mode(float_round_to_odd_inf, statusp); } - return ebf; } From patchwork Tue Dec 3 20:39:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 846983 Delivered-To: patch@linaro.org Received: by 2002:a5d:44cd:0:b0:385:e875:8a9e with SMTP id z13csp715466wrr; Tue, 3 Dec 2024 12:42:24 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXAiKuukwONeJmcYd1obWiDofGE18oTQqJJF9OGX1kuSf6KRQxvjXs1LBm44jFpxE7YDQxkZg==@linaro.org X-Google-Smtp-Source: AGHT+IGUjEt1gcwu8L31wXLUnGMkiWRzUO7uwggslvyy+eGd3nBVLrsdt+6iqjz3i6XKdZGlOGIu X-Received: by 2002:a05:6214:c82:b0:6cb:d4e6:2507 with SMTP id 6a1803df08f44-6d8b738ae51mr61865926d6.22.1733258544215; Tue, 03 Dec 2024 12:42:24 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733258544; cv=none; d=google.com; s=arc-20240605; b=fXFZZYYM9s1WbfeocQbLTEv3FAn9sLGNpnVubcEId3q7fH7dWMN6nWPqkLrDbzxjpg QoUI6FFDjnHOKarfbwTqSYkskeT3Mw2RN7cVSwpLYVlEEmxkqcfFNc/+j24YFKy27SeX pQtG2tXaV36twwj1a9AFYBgllwmAgUhSxsu1otDmroIPtswJZuRHlLkyV68H2S70zZRj f6m/boE6etuBOLl+bQDZF2u9ojuatISnNFb1nCjDj3wRlMQYmXaDeG0L2+PgzxHrqcLT 0xFq4FhQfbkVbYjkdqMCr1qhqCjcYWi2TLivhR4f8fUdw778mXrFPvxrPKEd/BffxpZv 9+Yg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=65/XNqGZ6VyYj6rTQSJdOtQFVcZddgAeG+CbEFdXJAI=; fh=UQCixiNfr28ZOrfhmxiGPA65dFhly8CmRsnoYC6xI9k=; b=LeBOixtFL27EaAUrvk+Q8MemIsk1nUyLk+818QHsASEbBJp9QH7gI7AJyYrtkCledx R74ZlIJxtZ1KTV3FMJkrwAISU/7tlJyGQgawMebRZw8Hz9+4NnpzHpMypOclGDyE2l6o zXyAE5EkTlOSEYBkK5XgEoOTujuLjxeL7PQz0Iij9dS8RwW/ydRojm/0PGE8oHsgXxG7 OCefaGINOX5Mq/DTyXD0GGM50TwfFEWULZPYl1zX/A0OegVMqX/3bcBvBrcOsRBN84te PgTuUB9ObNBfJaKZk4+EGho+VfpdvxLBkaeQdG92YoHjOA7JYBXaj+1qp57AxhbPquhF aU2A==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Kix3gkYb; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[187.189.51.143]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-29e3ae09f25sm2684018fac.49.2024.12.03.12.39.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Dec 2024 12:39:52 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org Subject: [PATCH 02/11] softfloat: Inline pickNaNMulAdd Date: Tue, 3 Dec 2024 14:39:39 -0600 Message-ID: <20241203203949.483774-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241203203949.483774-1-richard.henderson@linaro.org> References: <20241203203949.483774-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2001:4860:4864:20::2e; envelope-from=richard.henderson@linaro.org; helo=mail-oa1-x2e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Inline pickNaNMulAdd into its only caller. This makes one assert redundant with the immediately preceding IF. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- fpu/softfloat-parts.c.inc | 35 +++++++++++++++++++++- fpu/softfloat-specialize.c.inc | 54 ---------------------------------- 2 files changed, 34 insertions(+), 55 deletions(-) diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index 655b7d9da5..f5c6b21fee 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -80,8 +80,41 @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, if (s->default_nan_mode) { which = 3; + } else if (infzero) { + /* + * Inf * 0 + NaN -- some implementations return the + * default NaN here, and some return the input NaN. + */ + switch (s->float_infzeronan_rule) { + case float_infzeronan_dnan_never: + which = 2; + break; + case float_infzeronan_dnan_always: + which = 3; + break; + case float_infzeronan_dnan_if_qnan: + which = is_qnan(c->cls) ? 3 : 2; + break; + default: + g_assert_not_reached(); + } } else { - which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, have_snan, s); + FloatClass cls[3] = { a->cls, b->cls, c->cls }; + Float3NaNPropRule rule = s->float_3nan_prop_rule; + + assert(rule != float_3nan_prop_none); + if (have_snan && (rule & R_3NAN_SNAN_MASK)) { + /* We have at least one SNaN input and should prefer it */ + do { + which = rule & R_3NAN_1ST_MASK; + rule >>= R_3NAN_1ST_LENGTH; + } while (!is_snan(cls[which])); + } else { + do { + which = rule & R_3NAN_1ST_MASK; + rule >>= R_3NAN_1ST_LENGTH; + } while (!is_nan(cls[which])); + } } if (which == 3) { diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index e075c47889..f26458eaa3 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -448,60 +448,6 @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls, } } -/*---------------------------------------------------------------------------- -| Select which NaN to propagate for a three-input operation. -| For the moment we assume that no CPU needs the 'larger significand' -| information. -| Return values : 0 : a; 1 : b; 2 : c; 3 : default-NaN -*----------------------------------------------------------------------------*/ -static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, - bool infzero, bool have_snan, float_status *status) -{ - FloatClass cls[3] = { a_cls, b_cls, c_cls }; - Float3NaNPropRule rule = status->float_3nan_prop_rule; - int which; - - /* - * We guarantee not to require the target to tell us how to - * pick a NaN if we're always returning the default NaN. - * But if we're not in default-NaN mode then the target must - * specify. - */ - assert(!status->default_nan_mode); - - if (infzero) { - /* - * Inf * 0 + NaN -- some implementations return the default NaN here, - * and some return the input NaN. - */ - switch (status->float_infzeronan_rule) { - case float_infzeronan_dnan_never: - return 2; - case float_infzeronan_dnan_always: - return 3; - case float_infzeronan_dnan_if_qnan: - return is_qnan(c_cls) ? 3 : 2; - default: - g_assert_not_reached(); - } - } - - assert(rule != float_3nan_prop_none); - if (have_snan && (rule & R_3NAN_SNAN_MASK)) { - /* We have at least one SNaN input and should prefer it */ - do { - which = rule & R_3NAN_1ST_MASK; - rule >>= R_3NAN_1ST_LENGTH; - } while (!is_snan(cls[which])); - } else { - do { - which = rule & R_3NAN_1ST_MASK; - rule >>= R_3NAN_1ST_LENGTH; - } while (!is_nan(cls[which])); - } - return which; -} - /*---------------------------------------------------------------------------- | Returns 1 if the double-precision floating-point value `a' is a quiet | NaN; otherwise returns 0. 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[187.189.51.143]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-29e3ae09f25sm2684018fac.49.2024.12.03.12.39.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Dec 2024 12:39:53 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org Subject: [PATCH 03/11] softfloat: Use goto for default nan case in pick_nan_muladd Date: Tue, 3 Dec 2024 14:39:40 -0600 Message-ID: <20241203203949.483774-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241203203949.483774-1-richard.henderson@linaro.org> References: <20241203203949.483774-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2001:4860:4864:20::2b; envelope-from=richard.henderson@linaro.org; helo=mail-oa1-x2b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Remove "3" as a special case for which and simply branch to return the desired value. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- fpu/softfloat-parts.c.inc | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index f5c6b21fee..6423e12406 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -79,7 +79,7 @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, } if (s->default_nan_mode) { - which = 3; + goto default_nan; } else if (infzero) { /* * Inf * 0 + NaN -- some implementations return the @@ -87,17 +87,18 @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, */ switch (s->float_infzeronan_rule) { case float_infzeronan_dnan_never: - which = 2; break; case float_infzeronan_dnan_always: - which = 3; - break; + goto default_nan; case float_infzeronan_dnan_if_qnan: - which = is_qnan(c->cls) ? 3 : 2; + if (is_qnan(c->cls)) { + goto default_nan; + } break; default: g_assert_not_reached(); } + which = 2; } else { FloatClass cls[3] = { a->cls, b->cls, c->cls }; Float3NaNPropRule rule = s->float_3nan_prop_rule; @@ -117,11 +118,6 @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, } } - if (which == 3) { - parts_default_nan(a, s); - return a; - } - switch (which) { case 0: break; @@ -138,6 +134,10 @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, parts_silence_nan(a, s); } return a; + + default_nan: + parts_default_nan(a, s); + return a; } /* From patchwork Tue Dec 3 20:39:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 846982 Delivered-To: patch@linaro.org Received: by 2002:a5d:44cd:0:b0:385:e875:8a9e with SMTP id z13csp715453wrr; Tue, 3 Dec 2024 12:42:20 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXoRejoFsBs0wUNLYkqmW3PfdBfUlN6Z6poOfyo7TF2ljJ3171Z/saOSL0FBoHft/3vGTx/lg==@linaro.org X-Google-Smtp-Source: AGHT+IGz4YSTh19BNcLuv49x0viY+gjxTfoOaqD+QHbHc3l/KLcpfO7k+bHIOSwStDwvOIPHcmJ/ X-Received: by 2002:a05:6359:45a4:b0:1ca:9dcc:e6b8 with SMTP id e5c5f4694b2df-1caeaaa518emr428944055d.10.1733258540113; Tue, 03 Dec 2024 12:42:20 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733258540; cv=none; d=google.com; s=arc-20240605; b=Dd4/7mCig9cDVxxNPcHaw2qnRZL2saDClNUkv16DqFvHdtuGdozGv2JBwVVvSCwilA 2wDsXS1CG6sKn7D39JGk+IFxPRdG+0aw5y2PgKHs0JFD+kLDQd4rClq5FT5Q0yAqgJmy j4VfbPlVp3AvNlV+8Zm6zmk1EVoAbKrAvdBNVKlBdArQTGhLi2BoHClQKzTCPeDvQvkD eVgQLmGpciDFKvdGSFYHN6skY/NuDbwIgRfWlw8u48/8jEtadh27ziv1aq0CEunNCnHW AG16Xw9imk5ptwGwEcilusbP2E33Ajkj31YTBAMF9LQyq6smRUIVfi+rvnF4UFj8C9a/ GfRA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=HxoUNyLc0dEDDQUspYmsgb0BaeY/3JixWBMZpMBDUos=; fh=UQCixiNfr28ZOrfhmxiGPA65dFhly8CmRsnoYC6xI9k=; b=OZEPzCLcmcL1PmutHBeRVg7ZmWZuMEP/Viv+528dgoIPpVtUu1Az8se1raUWth/Qcq brZ10fp98UfKVdbMsNWtIEcNDF6EhcaS8ea8DKyQHTocPq8W6xbztFXMTU6QwpQyenYg ym7a0RqBVLfF5bYDb4xM9L/TrVcuaZM2qwK/0YH4qM8cHsXDuoiuPIZ1rvLSr43WyMDQ tAs7Vl0FL6b6276WjE4erSgFWpJzwvGjoGqqP5T+++leyQupHpGjD6o3NSF2jWebbqf4 RpiAzYBHUDfp679N5us8eEJGrnvD1Oaw1U8soZBlem2DwNntw1PXd7+FxYBzQp1ug11E UTCg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="p/drL0Th"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[187.189.51.143]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-29e3ae09f25sm2684018fac.49.2024.12.03.12.39.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Dec 2024 12:39:54 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org Subject: [PATCH 04/11] softfloat: Remove which from parts_pick_nan_muladd Date: Tue, 3 Dec 2024 14:39:41 -0600 Message-ID: <20241203203949.483774-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241203203949.483774-1-richard.henderson@linaro.org> References: <20241203203949.483774-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2001:4860:4864:20::2d; envelope-from=richard.henderson@linaro.org; helo=mail-oa1-x2d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Assign the pointer return value to 'a' directly, rather than going through an intermediary index. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- fpu/softfloat-parts.c.inc | 32 ++++++++++---------------------- 1 file changed, 10 insertions(+), 22 deletions(-) diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index 6423e12406..77f16ac158 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -65,9 +65,9 @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, FloatPartsN *c, float_status *s, int ab_mask, int abc_mask) { - int which; bool infzero = (ab_mask == float_cmask_infzero); bool have_snan = (abc_mask & float_cmask_snan); + FloatPartsN *ret; if (unlikely(have_snan)) { float_raise(float_flag_invalid | float_flag_invalid_snan, s); @@ -98,42 +98,30 @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, default: g_assert_not_reached(); } - which = 2; + ret = c; } else { - FloatClass cls[3] = { a->cls, b->cls, c->cls }; + FloatPartsN *val[3] = { a, b, c }; Float3NaNPropRule rule = s->float_3nan_prop_rule; assert(rule != float_3nan_prop_none); if (have_snan && (rule & R_3NAN_SNAN_MASK)) { /* We have at least one SNaN input and should prefer it */ do { - which = rule & R_3NAN_1ST_MASK; + ret = val[rule & R_3NAN_1ST_MASK]; rule >>= R_3NAN_1ST_LENGTH; - } while (!is_snan(cls[which])); + } while (!is_snan(ret->cls)); } else { do { - which = rule & R_3NAN_1ST_MASK; + ret = val[rule & R_3NAN_1ST_MASK]; rule >>= R_3NAN_1ST_LENGTH; - } while (!is_nan(cls[which])); + } while (!is_nan(ret->cls)); } } - switch (which) { - case 0: - break; - case 1: - a = b; - break; - case 2: - a = c; - break; - default: - g_assert_not_reached(); + if (is_snan(ret->cls)) { + parts_silence_nan(ret, s); } - if (is_snan(a->cls)) { - parts_silence_nan(a, s); - } - return a; + return ret; default_nan: parts_default_nan(a, s); From patchwork Tue Dec 3 20:39:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 846981 Delivered-To: patch@linaro.org Received: by 2002:a5d:44cd:0:b0:385:e875:8a9e with SMTP id z13csp715451wrr; Tue, 3 Dec 2024 12:42:20 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWQ9HfVBIZ1tAllezkusdQknM93PZK1ITW1anTZVPZLw56DSkTmAMbq30toVaNSZY7exbFMVQ==@linaro.org X-Google-Smtp-Source: AGHT+IFgFvHT4lt3qEMr05QtEZelE0lnMsnvU+IMcj9iHCFj6TGT0QDP50JNnd5fBosDQQEVXxtu X-Received: by 2002:ad4:596c:0:b0:6d8:b594:c590 with SMTP id 6a1803df08f44-6d8b72e08cemr52777106d6.6.1733258539852; Tue, 03 Dec 2024 12:42:19 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733258539; cv=none; d=google.com; s=arc-20240605; b=MWxdnUauWUzIuMT7Bw5wWRz6BCrN1xY18V1+uR5h35S3wwH821gDmAMwQfpudJTpzI DvAH42UZKAue4umzbuvxqUAQcBklc5Y+f2XHxiiXaHkn9J2C7MyJLbKAWMbqzr6Kyvyo JmLtxDru9YP8NkA8MXaYAKiRmSePBKUAAkJJdcOhtjytf93amYmem6T7gjISTKdbtZCF oVXImIV5PKY6kfh+qGyAddbyNiCbrMTg5uMuaXvPYO4S8hVvQR0pIqbnajoFm3g6MTwF uuRf2/d6wgVcf6XO2UB8BDo6u9/iYo6VR2z9/akjmVcql+dT1DCxkyc9DNmccSyMCcsF LcdQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=VtJU01uIPGdmdncl+3eL+uuul8VbLmsEdgS8yMmO9ow=; fh=UQCixiNfr28ZOrfhmxiGPA65dFhly8CmRsnoYC6xI9k=; b=LSq8qOo4zJv+jZiMQnmP7DVil+2RvVua/ie+PM0k2qJvEpgErlLLz/uQjZ8aX2pBBC QN5caVkxU+VgchhnPuSahDVYh8XqvvUiB8TOVtF4o9jrNAqHVEdfr3ztT92pgsVH7SfD a06CNcG0Q+1P5MRps7BH2+6S29CVNIL5NSF38G8vfQBaSA4arMVqn3aL5FBTC5D9uFPf i8GaHxG2wTVQTfNSwLIP0Hr8IQcMZ5tN51PdsYv0jwEUZSMwPnE8l6F1+n75Y73rJsjh bhfYrWTBVV1Z6cdT3olRwchf1z6wRyB7Ufe4NBF1YSt+VXYXc3MHuEDYml+0ZLvUqy7Z bdcg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=VbhBZIMA; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[187.189.51.143]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-29e3ae09f25sm2684018fac.49.2024.12.03.12.39.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Dec 2024 12:39:55 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org Subject: [PATCH 05/11] softfloat: Pad array size in pick_nan_muladd Date: Tue, 3 Dec 2024 14:39:42 -0600 Message-ID: <20241203203949.483774-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241203203949.483774-1-richard.henderson@linaro.org> References: <20241203203949.483774-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2001:4860:4864:20::31; envelope-from=richard.henderson@linaro.org; helo=mail-oa1-x31.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org While all indices into val[] should be in [0-2], the mask applied is two bits. To help static analysis see there is no possibility of read beyond the end of the array, pad the array to 4 entries, with the final being (implicitly) NULL. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- fpu/softfloat-parts.c.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index 77f16ac158..06cfc6abb5 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -100,7 +100,7 @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, } ret = c; } else { - FloatPartsN *val[3] = { a, b, c }; + FloatPartsN *val[R_3NAN_1ST_MASK + 1] = { a, b, c }; Float3NaNPropRule rule = s->float_3nan_prop_rule; assert(rule != float_3nan_prop_none); From patchwork Tue Dec 3 20:39:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 846979 Delivered-To: patch@linaro.org Received: by 2002:a5d:44cd:0:b0:385:e875:8a9e with SMTP id z13csp715356wrr; Tue, 3 Dec 2024 12:42:01 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVLJE/ZIis6Lt7+SfrKgJbrk45P5Uo3ZqnhVTfZW2q6gR18e0zue2NMnxfIICrd4rLfNk2a+w==@linaro.org X-Google-Smtp-Source: AGHT+IEsJcYd4kLBhC60KmNwY1LpHWdpjAufOQWyJ/uCBb4YH1bsdsGW9vmcJfAVTcnG/8cz9YMO X-Received: by 2002:a05:622a:252:b0:45f:788:b1b1 with SMTP id d75a77b69052e-4670c0b884fmr42489931cf.25.1733258520679; Tue, 03 Dec 2024 12:42:00 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733258520; cv=none; d=google.com; s=arc-20240605; b=EcP4kt3zk7R7B9AFn1CpEGHCfH+47WAk+J8J7/LbTju3AGdJEVQMG0QlFD/lDRCSgi o6Mxmm9Q4wlV/nS9UeGvp8audTJluWP/JcflyHIWnsXScg9my/Mg5Dt5MyPpfMgIKVkc vi8BZfzw6dwraBcQ+lCtxq8d4H79Dkw7P6U3TS2p0OVKyhXbdhj5gCKo17eddEdKqqbi eQoz0jfFGtZKsWyBybkwDtI3nl0QUr0Ty2xNu8y+kcdDKQwBq6HehGR8SFOxonM92mZ4 ZNGpGUhEr5QegalyjqMuLanff7v+e80q6GVXSsTKepR4/9eKC5wzbcwjQCnaWr6Dnn3o ACbg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=O/WrKqelHnCbtbsQVD2Xt769eF5XVcZugiQlkdqiXsE=; fh=UQCixiNfr28ZOrfhmxiGPA65dFhly8CmRsnoYC6xI9k=; b=XHAwZpEAnbyMgVEGBLW/I/KrOw7YNgWPqgtJGsgdNi31dorvu+F8LYMn674u6gflqA 2ynwLuiL6nQZdjRszYvY8lkrsYW7NX+9GGxRV6FflDfNnw1yhxE5kG4oiYF/kjGQ6Rx3 wsdy4aX3hdpxBB2nDPmWWY+PnDNT2NKwO5yvk8A73NJkwcfbDvbyywvq92hg0JT0PLLC 4sIKg++uz1zIxuAmJXnAV9xtZbHwVmdmFlXlFzFh8PmeqX0RLagLK4V5Bhtws2p53Hew F8eNvdaDYn/Kz7gQ2JBr0TnHm/uNLM2Peu517EDIIuI+2N5aPiLPsszgUlO+GW00sLKT ZZEQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WuoUtc+k; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[187.189.51.143]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-29e3ae09f25sm2684018fac.49.2024.12.03.12.39.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Dec 2024 12:39:56 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org Subject: [PATCH 06/11] softfloat: Move propagateFloatx80NaN to softfloat.c Date: Tue, 3 Dec 2024 14:39:43 -0600 Message-ID: <20241203203949.483774-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241203203949.483774-1-richard.henderson@linaro.org> References: <20241203203949.483774-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2001:4860:4864:20::2e; envelope-from=richard.henderson@linaro.org; helo=mail-oa1-x2e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This function is part of the public interface and is not "specialized" to any target in any way. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- fpu/softfloat.c | 52 ++++++++++++++++++++++++++++++++++ fpu/softfloat-specialize.c.inc | 52 ---------------------------------- 2 files changed, 52 insertions(+), 52 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 027a8e576d..6ba1cfd32a 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -4920,6 +4920,58 @@ void normalizeFloatx80Subnormal(uint64_t aSig, int32_t *zExpPtr, *zExpPtr = 1 - shiftCount; } +/*---------------------------------------------------------------------------- +| Takes two extended double-precision floating-point values `a' and `b', one +| of which is a NaN, and returns the appropriate NaN result. If either `a' or +| `b' is a signaling NaN, the invalid exception is raised. +*----------------------------------------------------------------------------*/ + +floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status) +{ + bool aIsLargerSignificand; + FloatClass a_cls, b_cls; + + /* This is not complete, but is good enough for pickNaN. */ + a_cls = (!floatx80_is_any_nan(a) + ? float_class_normal + : floatx80_is_signaling_nan(a, status) + ? float_class_snan + : float_class_qnan); + b_cls = (!floatx80_is_any_nan(b) + ? float_class_normal + : floatx80_is_signaling_nan(b, status) + ? float_class_snan + : float_class_qnan); + + if (is_snan(a_cls) || is_snan(b_cls)) { + float_raise(float_flag_invalid, status); + } + + if (status->default_nan_mode) { + return floatx80_default_nan(status); + } + + if (a.low < b.low) { + aIsLargerSignificand = 0; + } else if (b.low < a.low) { + aIsLargerSignificand = 1; + } else { + aIsLargerSignificand = (a.high < b.high) ? 1 : 0; + } + + if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) { + if (is_snan(b_cls)) { + return floatx80_silence_nan(b, status); + } + return b; + } else { + if (is_snan(a_cls)) { + return floatx80_silence_nan(a, status); + } + return a; + } +} + /*---------------------------------------------------------------------------- | Takes an abstract floating-point value having sign `zSign', exponent `zExp', | and extended significand formed by the concatenation of `zSig0' and `zSig1', diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index f26458eaa3..f7a320f6ff 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -551,58 +551,6 @@ floatx80 floatx80_silence_nan(floatx80 a, float_status *status) return a; } -/*---------------------------------------------------------------------------- -| Takes two extended double-precision floating-point values `a' and `b', one -| of which is a NaN, and returns the appropriate NaN result. If either `a' or -| `b' is a signaling NaN, the invalid exception is raised. -*----------------------------------------------------------------------------*/ - -floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status) -{ - bool aIsLargerSignificand; - FloatClass a_cls, b_cls; - - /* This is not complete, but is good enough for pickNaN. */ - a_cls = (!floatx80_is_any_nan(a) - ? float_class_normal - : floatx80_is_signaling_nan(a, status) - ? float_class_snan - : float_class_qnan); - b_cls = (!floatx80_is_any_nan(b) - ? float_class_normal - : floatx80_is_signaling_nan(b, status) - ? float_class_snan - : float_class_qnan); - - if (is_snan(a_cls) || is_snan(b_cls)) { - float_raise(float_flag_invalid, status); - } - - if (status->default_nan_mode) { - return floatx80_default_nan(status); - } - - if (a.low < b.low) { - aIsLargerSignificand = 0; - } else if (b.low < a.low) { - aIsLargerSignificand = 1; - } else { - aIsLargerSignificand = (a.high < b.high) ? 1 : 0; - } - - if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) { - if (is_snan(b_cls)) { - return floatx80_silence_nan(b, status); - } - return b; - } else { - if (is_snan(a_cls)) { - return floatx80_silence_nan(a, status); - } - return a; - } -} - /*---------------------------------------------------------------------------- | Returns 1 if the quadruple-precision floating-point value `a' is a quiet | NaN; otherwise returns 0. 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[187.189.51.143]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-29e3ae09f25sm2684018fac.49.2024.12.03.12.39.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Dec 2024 12:39:57 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org Subject: [PATCH 07/11] softfloat: Use parts_pick_nan in propagateFloatx80NaN Date: Tue, 3 Dec 2024 14:39:44 -0600 Message-ID: <20241203203949.483774-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241203203949.483774-1-richard.henderson@linaro.org> References: <20241203203949.483774-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2001:4860:4864:20::2a; envelope-from=richard.henderson@linaro.org; helo=mail-oa1-x2a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Unpacking and repacking the parts may be slightly more work than we did before, but we get to reuse more code. For a code path handling exceptional values, this is an improvement. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- fpu/softfloat.c | 43 +++++-------------------------------------- 1 file changed, 5 insertions(+), 38 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 6ba1cfd32a..8de8d5f342 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -4928,48 +4928,15 @@ void normalizeFloatx80Subnormal(uint64_t aSig, int32_t *zExpPtr, floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status) { - bool aIsLargerSignificand; - FloatClass a_cls, b_cls; + FloatParts128 pa, pb, *pr; - /* This is not complete, but is good enough for pickNaN. */ - a_cls = (!floatx80_is_any_nan(a) - ? float_class_normal - : floatx80_is_signaling_nan(a, status) - ? float_class_snan - : float_class_qnan); - b_cls = (!floatx80_is_any_nan(b) - ? float_class_normal - : floatx80_is_signaling_nan(b, status) - ? float_class_snan - : float_class_qnan); - - if (is_snan(a_cls) || is_snan(b_cls)) { - float_raise(float_flag_invalid, status); - } - - if (status->default_nan_mode) { + if (!floatx80_unpack_canonical(&pa, a, status) || + !floatx80_unpack_canonical(&pb, b, status)) { return floatx80_default_nan(status); } - if (a.low < b.low) { - aIsLargerSignificand = 0; - } else if (b.low < a.low) { - aIsLargerSignificand = 1; - } else { - aIsLargerSignificand = (a.high < b.high) ? 1 : 0; - } - - if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) { - if (is_snan(b_cls)) { - return floatx80_silence_nan(b, status); - } - return b; - } else { - if (is_snan(a_cls)) { - return floatx80_silence_nan(a, status); - } - return a; - } + pr = parts_pick_nan(&pa, &pb, status); + return floatx80_round_pack_canonical(pr, status); } /*---------------------------------------------------------------------------- From patchwork Tue Dec 3 20:39:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 846973 Delivered-To: patch@linaro.org Received: by 2002:a5d:44cd:0:b0:385:e875:8a9e with SMTP id z13csp714926wrr; Tue, 3 Dec 2024 12:40:48 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWPae0cRmZ/gtGoC+eskpfbSn94EgBj7eLlG3fwLVmCpaYAa/mdRR/N8W5XacbMn19zBWbjqw==@linaro.org X-Google-Smtp-Source: AGHT+IFPyfHkf/85JOzJ/fa9+s2GNlpXQjgIcaZK6wzVcCMSzcroxhsROMTHlAVWaMn9AnGs9ys5 X-Received: by 2002:a05:622a:6203:b0:466:afb6:6602 with SMTP id d75a77b69052e-46717cdfafcmr31274681cf.49.1733258448036; Tue, 03 Dec 2024 12:40:48 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733258448; cv=none; d=google.com; s=arc-20240605; b=TvjcL+efo2oINoF18eI1e3xVTQSzovHmpN/4MfsRCFTxHVOkV0PAnHlmyyQ5x+fj+q QNPG/kJ+SjIfydB7KeL91q0Q6RAoi8zsPPcjK/QY539ZVy8BNnEvR40wKa9dxYQeypce 7yAPSIliCT1Y3wBeUWirlDkJyuHREBhfITvNwr4WmQLqF81mwZqJNxLbjVQcuKmEW6/4 rtvLMkSoAnosnoKrwYAL39W0LfY/AwhC4xnVpgijMcvNKDMr7TNCn9M7XshUVgqxyb0e xpbuP39vgGsoF2XUCoYDU9vP15mp8jh6D3u3d6gX09N0d4no7crtxp7Eblu4HOwBYUvk UFdA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=vE9Xl02UsRFXlQRaYTkoaksxQH+Xcw8LkQwIo9WLMj4=; fh=UQCixiNfr28ZOrfhmxiGPA65dFhly8CmRsnoYC6xI9k=; b=QVHpwILTbPS5+X2ZoxO0LOnyC0v87RvQK4Q4GtAeogBcqeB2FxFn6bQaBv0cfJpCGs rJiVqJMpUJ22FuYLg4KgCqX1JkNGhnUAox+DCErY5ATQK6MjHPUaAGdp9q3k+cNoom1U jZfvP9HdqXc7t1v+Ileipm5ByC6JAHiomQay3KBDF0P/4e/C+MVxfFQ/Ke89vO/misNC y0imwZe3l67pBvDyQehatfH3V9sJrNNmZDoQ1D5DmwZzCUSIi2SOqoy8qyNedqnDA1tw tnN89rVu/8zBvcTYbg8+6AgPysZnrs7TrrP/yL+OSkRM9Aw97j0hLgLRgP1Ibfsf1S7i BRaw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Aqdk3YRo; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[187.189.51.143]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-29e3ae09f25sm2684018fac.49.2024.12.03.12.39.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Dec 2024 12:39:58 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org Subject: [PATCH 08/11] softfloat: Inline pickNaN Date: Tue, 3 Dec 2024 14:39:45 -0600 Message-ID: <20241203203949.483774-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241203203949.483774-1-richard.henderson@linaro.org> References: <20241203203949.483774-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::22b; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x22b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Inline pickNaN into its only caller. This makes one assert redundant with the immediately preceding IF. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- fpu/softfloat-parts.c.inc | 82 +++++++++++++++++++++++++---- fpu/softfloat-specialize.c.inc | 96 ---------------------------------- 2 files changed, 73 insertions(+), 105 deletions(-) diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index 06cfc6abb5..de51097dcf 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -39,24 +39,88 @@ static void partsN(return_nan)(FloatPartsN *a, float_status *s) static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b, float_status *s) { + int cmp, which; + if (is_snan(a->cls) || is_snan(b->cls)) { float_raise(float_flag_invalid | float_flag_invalid_snan, s); } if (s->default_nan_mode) { parts_default_nan(a, s); - } else { - int cmp = frac_cmp(a, b); - if (cmp == 0) { - cmp = a->sign < b->sign; - } + return a; + } - if (pickNaN(a->cls, b->cls, cmp > 0, s)) { - a = b; - } + cmp = frac_cmp(a, b); + if (cmp == 0) { + cmp = a->sign < b->sign; + } + + switch (s->float_2nan_prop_rule) { + case float_2nan_prop_s_ab: if (is_snan(a->cls)) { - parts_silence_nan(a, s); + which = 0; + } else if (is_snan(b->cls)) { + which = 1; + } else if (is_qnan(a->cls)) { + which = 0; + } else { + which = 1; } + break; + case float_2nan_prop_s_ba: + if (is_snan(b->cls)) { + which = 1; + } else if (is_snan(a->cls)) { + which = 0; + } else if (is_qnan(b->cls)) { + which = 1; + } else { + which = 0; + } + break; + case float_2nan_prop_ab: + which = is_nan(a->cls) ? 0 : 1; + break; + case float_2nan_prop_ba: + which = is_nan(b->cls) ? 1 : 0; + break; + case float_2nan_prop_x87: + /* + * This implements x87 NaN propagation rules: + * SNaN + QNaN => return the QNaN + * two SNaNs => return the one with the larger significand, silenced + * two QNaNs => return the one with the larger significand + * SNaN and a non-NaN => return the SNaN, silenced + * QNaN and a non-NaN => return the QNaN + * + * If we get down to comparing significands and they are the same, + * return the NaN with the positive sign bit (if any). + */ + if (is_snan(a->cls)) { + if (is_snan(b->cls)) { + which = cmp > 0 ? 0 : 1; + } else { + which = is_qnan(b->cls) ? 1 : 0; + } + } else if (is_qnan(a->cls)) { + if (is_snan(b->cls) || !is_qnan(b->cls)) { + which = 0; + } else { + which = cmp > 0 ? 0 : 1; + } + } else { + which = 1; + } + break; + default: + g_assert_not_reached(); + } + + if (which) { + a = b; + } + if (is_snan(a->cls)) { + parts_silence_nan(a, s); } return a; } diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index f7a320f6ff..cbbbab52ba 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -352,102 +352,6 @@ bool float32_is_signaling_nan(float32 a_, float_status *status) } } -/*---------------------------------------------------------------------------- -| Select which NaN to propagate for a two-input operation. -| IEEE754 doesn't specify all the details of this, so the -| algorithm is target-specific. -| The routine is passed various bits of information about the -| two NaNs and should return 0 to select NaN a and 1 for NaN b. -| Note that signalling NaNs are always squashed to quiet NaNs -| by the caller, by calling floatXX_silence_nan() before -| returning them. -| -| aIsLargerSignificand is only valid if both a and b are NaNs -| of some kind, and is true if a has the larger significand, -| or if both a and b have the same significand but a is -| positive but b is negative. It is only needed for the x87 -| tie-break rule. -*----------------------------------------------------------------------------*/ - -static int pickNaN(FloatClass a_cls, FloatClass b_cls, - bool aIsLargerSignificand, float_status *status) -{ - /* - * We guarantee not to require the target to tell us how to - * pick a NaN if we're always returning the default NaN. - * But if we're not in default-NaN mode then the target must - * specify via set_float_2nan_prop_rule(). - */ - assert(!status->default_nan_mode); - - switch (status->float_2nan_prop_rule) { - case float_2nan_prop_s_ab: - if (is_snan(a_cls)) { - return 0; - } else if (is_snan(b_cls)) { - return 1; - } else if (is_qnan(a_cls)) { - return 0; - } else { - return 1; - } - break; - case float_2nan_prop_s_ba: - if (is_snan(b_cls)) { - return 1; - } else if (is_snan(a_cls)) { - return 0; - } else if (is_qnan(b_cls)) { - return 1; - } else { - return 0; - } - break; - case float_2nan_prop_ab: - if (is_nan(a_cls)) { - return 0; - } else { - return 1; - } - break; - case float_2nan_prop_ba: - if (is_nan(b_cls)) { - return 1; - } else { - return 0; - } - break; - case float_2nan_prop_x87: - /* - * This implements x87 NaN propagation rules: - * SNaN + QNaN => return the QNaN - * two SNaNs => return the one with the larger significand, silenced - * two QNaNs => return the one with the larger significand - * SNaN and a non-NaN => return the SNaN, silenced - * QNaN and a non-NaN => return the QNaN - * - * If we get down to comparing significands and they are the same, - * return the NaN with the positive sign bit (if any). - */ - if (is_snan(a_cls)) { - if (is_snan(b_cls)) { - return aIsLargerSignificand ? 0 : 1; - } - return is_qnan(b_cls) ? 1 : 0; - } else if (is_qnan(a_cls)) { - if (is_snan(b_cls) || !is_qnan(b_cls)) { - return 0; - } else { - return aIsLargerSignificand ? 0 : 1; - } - } else { - return 1; - } - default: - g_assert_not_reached(); - } -} - /*---------------------------------------------------------------------------- | Returns 1 if the double-precision floating-point value `a' is a quiet | NaN; otherwise returns 0. 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[187.189.51.143]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-29e3ae09f25sm2684018fac.49.2024.12.03.12.39.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Dec 2024 12:39:59 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org Subject: [PATCH 09/11] softfloat: Share code between parts_pick_nan cases Date: Tue, 3 Dec 2024 14:39:46 -0600 Message-ID: <20241203203949.483774-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241203203949.483774-1-richard.henderson@linaro.org> References: <20241203203949.483774-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::229; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x229.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Remember if there was an SNaN, and use that to simplify float_2nan_prop_s_{ab,ba} to only the snan component. Then, fall through to the corresponding float_2nan_prop_{ab,ba} case to handle any remaining nans, which must be quiet. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- fpu/softfloat-parts.c.inc | 32 ++++++++++++-------------------- 1 file changed, 12 insertions(+), 20 deletions(-) diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index de51097dcf..099f1c48ef 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -39,10 +39,12 @@ static void partsN(return_nan)(FloatPartsN *a, float_status *s) static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b, float_status *s) { + bool have_snan = false; int cmp, which; if (is_snan(a->cls) || is_snan(b->cls)) { float_raise(float_flag_invalid | float_flag_invalid_snan, s); + have_snan = true; } if (s->default_nan_mode) { @@ -57,30 +59,20 @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b, switch (s->float_2nan_prop_rule) { case float_2nan_prop_s_ab: - if (is_snan(a->cls)) { - which = 0; - } else if (is_snan(b->cls)) { - which = 1; - } else if (is_qnan(a->cls)) { - which = 0; - } else { - which = 1; + if (have_snan) { + which = is_snan(a->cls) ? 0 : 1; + break; } - break; - case float_2nan_prop_s_ba: - if (is_snan(b->cls)) { - which = 1; - } else if (is_snan(a->cls)) { - which = 0; - } else if (is_qnan(b->cls)) { - which = 1; - } else { - which = 0; - } - break; + /* fall through */ case float_2nan_prop_ab: which = is_nan(a->cls) ? 0 : 1; break; + case float_2nan_prop_s_ba: + if (have_snan) { + which = is_snan(b->cls) ? 1 : 0; + break; + } + /* fall through */ case float_2nan_prop_ba: which = is_nan(b->cls) ? 1 : 0; break; From patchwork Tue Dec 3 20:39:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 846978 Delivered-To: patch@linaro.org Received: by 2002:a5d:44cd:0:b0:385:e875:8a9e with SMTP id z13csp715268wrr; Tue, 3 Dec 2024 12:41:45 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWm4eNZnYE59krzbXixzvJRCkIOMMa2yDpn+i/kM5/k08Aclj+qFuWhGFjRjJN1XyrcQuRd4w==@linaro.org X-Google-Smtp-Source: AGHT+IGzGHNjcIfETph+2he2ljJkQMZFeluCKSgZhcL3hMM2qz6sCPPx66sCfnFXAKCxw4qHQBl+ X-Received: by 2002:a05:620a:28d4:b0:7b6:6d9f:c91f with SMTP id af79cd13be357-7b6a620a22dmr473499785a.61.1733258504994; Tue, 03 Dec 2024 12:41:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733258504; cv=none; d=google.com; s=arc-20240605; b=EkYBUfrMWOrvnYRsLJXE0PEInM7Soj2W9gq8dhBa9pd9v0hkufJ98FZekKQuuCfgfm QLo+EqHCc/ouAAfMxQtfbFSInp7KNhH4czQl5uYmBM0Q7qv7zprxSSsgUZjFK/RI/tyM x2c38ftoLbrggh94TS+y6KML6v2AeVpQ5j/aEmzwzvlPKDF3UrgE19hwnsvaGWmMCIhu AdWAoVtF8yId52RbqyDJ88PqYjVHUs1dUwLxK9aLdjpa5oueDVQs13TxtIgxp5Alm2fV jKPG7xyFVBFz3MjN2ZYNZDSEmTJJ8gOTmRxa2oTg5TBXyYpudcuHx8AoEykfXIpJqak1 jQ9A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=9CTXOrxugfzuYrJxFKkXFLZxqqX/88/ScAMxLj979U8=; fh=UQCixiNfr28ZOrfhmxiGPA65dFhly8CmRsnoYC6xI9k=; b=jEcm/zp4B6rC79ehBP983Dsb2wYixy1liQwUoaBS64WwCbt/si71lY9iP3NQHO1gRf jGzaKzf+5yS26DvIgjy0rMs8u4NyBbHGX5qQG4/cPkqMCqZyvcflK1lJxb0f9v5G9ngs snrfLUM+9Gz2jDJsqAcHIQ1jHfU8QREmJp91G2iKMza1rCMB3Ba4M+1Rlt36lbctr5oi xRq52YdPyP2Qa+nJyiebV5VX5a8lCCvHfrmGkKvhbkd5MU/CgUSVUCN3DEYBxQuukx+6 lWxzZbTfvJB8cmDVjB3fvXuBsL0v76Mt+qSg+Hj0JFFVVWMo1W6AO4nIRkAIArIzLdF3 SHzg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="X4/LBCLm"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[187.189.51.143]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-29e3ae09f25sm2684018fac.49.2024.12.03.12.40.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Dec 2024 12:40:00 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org Subject: [PATCH 10/11] softfloat: Sink frac_cmp in parts_pick_nan until needed Date: Tue, 3 Dec 2024 14:39:47 -0600 Message-ID: <20241203203949.483774-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241203203949.483774-1-richard.henderson@linaro.org> References: <20241203203949.483774-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2001:4860:4864:20::2f; envelope-from=richard.henderson@linaro.org; helo=mail-oa1-x2f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Move the fractional comparison to the end of the float_2nan_prop_x87 case. This is not required for any other 2nan propagation rule. Reorganize the x87 case itself to break out of the switch when the fractional comparison is not required. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- fpu/softfloat-parts.c.inc | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index 099f1c48ef..9a2287095c 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -52,11 +52,6 @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b, return a; } - cmp = frac_cmp(a, b); - if (cmp == 0) { - cmp = a->sign < b->sign; - } - switch (s->float_2nan_prop_rule) { case float_2nan_prop_s_ab: if (have_snan) { @@ -89,20 +84,24 @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b, * return the NaN with the positive sign bit (if any). */ if (is_snan(a->cls)) { - if (is_snan(b->cls)) { - which = cmp > 0 ? 0 : 1; - } else { + if (!is_snan(b->cls)) { which = is_qnan(b->cls) ? 1 : 0; + break; } } else if (is_qnan(a->cls)) { if (is_snan(b->cls) || !is_qnan(b->cls)) { which = 0; - } else { - which = cmp > 0 ? 0 : 1; + break; } } else { which = 1; + break; } + cmp = frac_cmp(a, b); + if (cmp == 0) { + cmp = a->sign < b->sign; + } + which = cmp > 0 ? 0 : 1; break; default: g_assert_not_reached(); From patchwork Tue Dec 3 20:39:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 846977 Delivered-To: patch@linaro.org Received: by 2002:a5d:44cd:0:b0:385:e875:8a9e with SMTP id z13csp715126wrr; Tue, 3 Dec 2024 12:41:24 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCV7TzbwOoODSiHAS8er6aW9wJUM84HEdC7DvcF/u5PVPah9fBUqJYeDDGkhK1dVivGBg34mXg==@linaro.org X-Google-Smtp-Source: AGHT+IGjvLXl8KYkdieQefGFKDJuipastLXb71z38jBxCvOt2phgcY4htfOWPzk+HPCV1w72uV3T X-Received: by 2002:a05:6214:5007:b0:6d4:1d7e:bc72 with SMTP id 6a1803df08f44-6d8b927a3b1mr62749146d6.12.1733258484097; Tue, 03 Dec 2024 12:41:24 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733258484; cv=none; d=google.com; s=arc-20240605; b=jtvBDNyC1ALiN2d7LXXUizELK312/YFuOx+Yg99sCJzSD/NSAFLp5AKskVzh101T9d 7xE0lIAQ/MIfdF+KzVHTxQzcEAhj7KlWyPtASTEtRS/969x2T+pLx2F3XmUpC7ucG4LE ZyITmxNcMfcvHIjru5wqLEoxA7v8kdAjRzymwXGUQwNIfNqwTgrpTIwRuTgsRD/jJEKt BXRj6vdL3tuB9jLn6yLi4/7z+p/mBZCTK8TFB1P5ZuNlB4KUhfFxK/8OGhSfHT86z/rc hz94g+IxVigo0p4WwedbOXBc4eBj/I+P9o/0+DgfIG1O2VTARDHytez8VbV6bSN8scjF PZLw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=xxwQYUCgdJ75izA3vVBTRu+vsh+0fdcxFYY32CHBmJU=; fh=UQCixiNfr28ZOrfhmxiGPA65dFhly8CmRsnoYC6xI9k=; b=PB7Dpg8IhLeuvejBeFma/DgqdC2x/iqSVLlt02Vsej1zwREG+8SV7bIcBgj677auJK DFvtoLaTPlwrZGPNSOMmCrLrCjmBVddeTqmoOUvpayki7sRNBF6cDAX5CxWZ7kGUTUkz vQnyv9EnhB1ACbqnqE5FVmKtOL3XIDv9I4wnz77aXt3FG6EEWGttRD/w+jeOkrN+zCaO 3N3FukwRGqs8THFz72m7wxgbB6SClqFGPL6mQQVVR8Miuc9PWxu5C59wTtNKIfn3d4h6 mWH/6XjeGOsOCh6BDHveAGka1/CkGP+dtxThqk7KHkfCdKHxvLVS3aA4N83IFSzI8UZ5 pyJQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=M13DV7xs; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[187.189.51.143]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-29e3ae09f25sm2684018fac.49.2024.12.03.12.40.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Dec 2024 12:40:01 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org Subject: [PATCH 11/11] softfloat: Replace WHICH with RET in parts_pick_nan Date: Tue, 3 Dec 2024 14:39:48 -0600 Message-ID: <20241203203949.483774-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241203203949.483774-1-richard.henderson@linaro.org> References: <20241203203949.483774-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2001:4860:4864:20::32; envelope-from=richard.henderson@linaro.org; helo=mail-oa1-x32.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Replace the "index" selecting between A and B with a result variable of the proper type. This improves clarity within the function. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- fpu/softfloat-parts.c.inc | 28 +++++++++++++--------------- 1 file changed, 13 insertions(+), 15 deletions(-) diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index 9a2287095c..e51c9827d9 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -40,7 +40,8 @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b, float_status *s) { bool have_snan = false; - int cmp, which; + FloatPartsN *ret; + int cmp; if (is_snan(a->cls) || is_snan(b->cls)) { float_raise(float_flag_invalid | float_flag_invalid_snan, s); @@ -55,21 +56,21 @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b, switch (s->float_2nan_prop_rule) { case float_2nan_prop_s_ab: if (have_snan) { - which = is_snan(a->cls) ? 0 : 1; + ret = is_snan(a->cls) ? a : b; break; } /* fall through */ case float_2nan_prop_ab: - which = is_nan(a->cls) ? 0 : 1; + ret = is_nan(a->cls) ? a : b; break; case float_2nan_prop_s_ba: if (have_snan) { - which = is_snan(b->cls) ? 1 : 0; + ret = is_snan(b->cls) ? b : a; break; } /* fall through */ case float_2nan_prop_ba: - which = is_nan(b->cls) ? 1 : 0; + ret = is_nan(b->cls) ? b : a; break; case float_2nan_prop_x87: /* @@ -85,35 +86,32 @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b, */ if (is_snan(a->cls)) { if (!is_snan(b->cls)) { - which = is_qnan(b->cls) ? 1 : 0; + ret = is_qnan(b->cls) ? b : a; break; } } else if (is_qnan(a->cls)) { if (is_snan(b->cls) || !is_qnan(b->cls)) { - which = 0; + ret = a; break; } } else { - which = 1; + ret = b; break; } cmp = frac_cmp(a, b); if (cmp == 0) { cmp = a->sign < b->sign; } - which = cmp > 0 ? 0 : 1; + ret = cmp > 0 ? a : b; break; default: g_assert_not_reached(); } - if (which) { - a = b; + if (is_snan(ret->cls)) { + parts_silence_nan(ret, s); } - if (is_snan(a->cls)) { - parts_silence_nan(a, s); - } - return a; + return ret; } static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,