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Mon, 2 Dec 2024 20:42:35 GMT Received: from abhinavk-linux1.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 2 Dec 2024 12:42:34 -0800 From: Abhinav Kumar Date: Mon, 2 Dec 2024 12:41:58 -0800 Subject: [PATCH 1/3] drm/msm/dp: account for widebus in msm_dp_catalog_panel_tpg_enable() Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20241202-tpg-v1-1-0fd6b518b914@quicinc.com> References: <20241202-tpg-v1-0-0fd6b518b914@quicinc.com> In-Reply-To: <20241202-tpg-v1-0-0fd6b518b914@quicinc.com> To: Rob Clark , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , "Simona Vetter" , Stephen Boyd , Kuogee Hsieh CC: , , , , "Jessica Zhang" , Abhinav Kumar X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1733172154; l=1329; i=quic_abhinavk@quicinc.com; s=20240509; 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Fixes: 757a2f36ab09 ("drm/msm/dp: enable widebus feature for display port") Signed-off-by: Abhinav Kumar --- drivers/gpu/drm/msm/dp/dp_catalog.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c b/drivers/gpu/drm/msm/dp/dp_catalog.c index b4c8856fb25d..05c8e1996f60 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.c +++ b/drivers/gpu/drm/msm/dp/dp_catalog.c @@ -1011,9 +1011,21 @@ void msm_dp_catalog_panel_tpg_enable(struct msm_dp_catalog *msm_dp_catalog, u32 v_sync_width; u32 hsync_ctl; u32 display_hctl; + u32 h_sync_width; + u32 h_front_porch; + u32 h_back_porch; + u32 h_active; + + h_active = drm_mode->hdisplay; + h_back_porch = drm_mode->htotal - drm_mode->hsync_end; + h_sync_width = drm_mode->htotal - (drm_mode->hsync_start + h_back_porch); + h_front_porch = drm_mode->hsync_start - drm_mode->hdisplay; + + if (msm_dp_catalog->wide_bus_en) + h_active /= 2; /* TPG config parameters*/ - hsync_period = drm_mode->htotal; + hsync_period = h_sync_width + h_back_porch + h_active + h_front_porch; vsync_period = drm_mode->vtotal; display_v_start = ((drm_mode->vtotal - drm_mode->vsync_start) * From patchwork Mon Dec 2 20:41:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abhinav Kumar X-Patchwork-Id: 847048 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2A59A1DEFC5; Mon, 2 Dec 2024 20:42:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733172166; cv=none; b=rmPQJJCKzkF2uETQ5OsVJUDlATtI1xsN9RCkvoCrE+HrhwgVDjYvAeVbWIOYXdmjmJleIUl6cxPq1eg4ehAmVQeZ+X7EKd5LYu7uQCKU8Pkh3DRuEHTZoi7UwdIzQ+LnZBmktvNp1HvEf8xZQBYUzo/VipNFm5TpsebWDKosabo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; 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Mon, 2 Dec 2024 20:42:35 GMT Received: from abhinavk-linux1.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 2 Dec 2024 12:42:35 -0800 From: Abhinav Kumar Date: Mon, 2 Dec 2024 12:41:59 -0800 Subject: [PATCH 2/3] drm/msm/dp: do not touch the MMSS_DP_INTF_CONFIG for tpg Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20241202-tpg-v1-2-0fd6b518b914@quicinc.com> References: <20241202-tpg-v1-0-0fd6b518b914@quicinc.com> In-Reply-To: <20241202-tpg-v1-0-0fd6b518b914@quicinc.com> To: Rob Clark , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , "Simona Vetter" , Stephen Boyd , Kuogee Hsieh CC: , , , , "Jessica Zhang" , Abhinav Kumar X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1733172154; l=1252; i=quic_abhinavk@quicinc.com; s=20240509; h=from:subject:message-id; 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Keeping the same behavior intact, drop the clearing of MMSS_DP_INTF_CONFIG from the msm_dp_catalog_panel_tpg_enable() API. Fixes: 757a2f36ab09 ("drm/msm/dp: enable widebus feature for display port") Signed-off-by: Abhinav Kumar --- drivers/gpu/drm/msm/dp/dp_catalog.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c b/drivers/gpu/drm/msm/dp/dp_catalog.c index 05c8e1996f60..36d3f3d248ca 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.c +++ b/drivers/gpu/drm/msm/dp/dp_catalog.c @@ -1048,7 +1048,6 @@ void msm_dp_catalog_panel_tpg_enable(struct msm_dp_catalog *msm_dp_catalog, display_hctl = (hsync_end_x << 16) | hsync_start_x; - msm_dp_write_p0(catalog, MMSS_DP_INTF_CONFIG, 0x0); msm_dp_write_p0(catalog, MMSS_DP_INTF_HSYNC_CTL, hsync_ctl); msm_dp_write_p0(catalog, MMSS_DP_INTF_VSYNC_PERIOD_F0, vsync_period * hsync_period); From patchwork Mon Dec 2 20:42:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abhinav Kumar X-Patchwork-Id: 846688 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2CEA71DEFC6; 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Mon, 02 Dec 2024 20:42:36 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4B2Kga9i029657 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 2 Dec 2024 20:42:36 GMT Received: from abhinavk-linux1.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 2 Dec 2024 12:42:35 -0800 From: Abhinav Kumar Date: Mon, 2 Dec 2024 12:42:00 -0800 Subject: [PATCH 3/3] drm/msm/dp: add a debugfs node for using tpg Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20241202-tpg-v1-3-0fd6b518b914@quicinc.com> References: <20241202-tpg-v1-0-0fd6b518b914@quicinc.com> In-Reply-To: <20241202-tpg-v1-0-0fd6b518b914@quicinc.com> To: Rob Clark , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , "Simona Vetter" , Stephen Boyd , Kuogee Hsieh CC: , , , , "Jessica Zhang" , Abhinav Kumar X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1733172154; l=3055; i=quic_abhinavk@quicinc.com; s=20240509; h=from:subject:message-id; bh=8xU8eZvxuxJZRudg+03NMMrCYKY67CgFbv6HcpsX0CA=; b=4/ROjG1S7kkiQW2W6xJJvNSX5rNWFt7upb0DJunvrd04bgETUqKSs9h8eftzb6NsxXhwVpFx9 JP/udaRE1NpA/kZpT9tCAjzKExBq+T0TG1TAzgV6Bgd391F+hWIpJec X-Developer-Key: i=quic_abhinavk@quicinc.com; a=ed25519; pk=SD3D8dOKDDh6BoX3jEYjsHrTFwuIK8+o0cLPgQok9ys= X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: PJnDwuu67LYDulM6sF_bp-nAaWxHrNEM X-Proofpoint-ORIG-GUID: PJnDwuu67LYDulM6sF_bp-nAaWxHrNEM X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 malwarescore=0 suspectscore=0 mlxlogscore=999 impostorscore=0 adultscore=0 phishscore=0 bulkscore=0 priorityscore=1501 clxscore=1015 spamscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412020173 DP test pattern generator is a very useful tool to debug issues where monitor is showing incorrect output as it helps to isolate whether the issue is due to rest of DPU pipeline or in the DP controller itself. Expose a debugfs to use the TPG configuration to help debug DP issues. Signed-off-by: Abhinav Kumar --- drivers/gpu/drm/msm/dp/dp_debug.c | 61 +++++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/msm/dp/dp_panel.h | 2 ++ 2 files changed, 63 insertions(+) diff --git a/drivers/gpu/drm/msm/dp/dp_debug.c b/drivers/gpu/drm/msm/dp/dp_debug.c index 22fd946ee201..843fe77268f8 100644 --- a/drivers/gpu/drm/msm/dp/dp_debug.c +++ b/drivers/gpu/drm/msm/dp/dp_debug.c @@ -197,6 +197,65 @@ static const struct file_operations test_active_fops = { .write = msm_dp_test_active_write }; +static ssize_t msm_dp_tpg_write(struct file *file, const char __user *ubuf, + size_t len, loff_t *offp) +{ + const struct msm_dp_debug_private *debug; + char *input_buffer; + int val; + int status = 0; + struct msm_dp_panel *dp_panel; + + debug = ((struct seq_file *)file->private_data)->private; + dp_panel = debug->panel; + + input_buffer = memdup_user_nul(ubuf, len); + if (IS_ERR(input_buffer)) + return PTR_ERR(input_buffer); + + status = kstrtoint(input_buffer, 10, &val); + if (status < 0) { + kfree(input_buffer); + return status; + } + + msm_dp_panel_tpg_config(dp_panel, val); + + dp_panel->tpg_enabled = val; + + kfree(input_buffer); + + *offp += len; + return len; +} + +static int msm_dp_tpg_show(struct seq_file *f, void *data) +{ + struct msm_dp_debug_private *debug = f->private; + struct msm_dp_panel *dp_panel = debug->panel; + + if (dp_panel->tpg_enabled) + seq_puts(f, "1"); + else + seq_puts(f, "0"); + + return 0; +} + +static int msm_dp_tpg_open(struct inode *inode, struct file *file) +{ + return single_open(file, msm_dp_tpg_show, inode->i_private); +} + +static const struct file_operations msm_dp_tpg_fops = { + .owner = THIS_MODULE, + .open = msm_dp_tpg_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, + .write = msm_dp_tpg_write +}; + int msm_dp_debug_init(struct device *dev, struct msm_dp_panel *panel, struct msm_dp_link *link, struct drm_connector *connector, @@ -231,6 +290,8 @@ int msm_dp_debug_init(struct device *dev, struct msm_dp_panel *panel, debugfs_create_file("dp_test_type", 0444, root, debug, &msm_dp_test_type_fops); + + debugfs_create_file("dp_tpg", 0444, root, debug, &msm_dp_tpg_fops); } return 0; diff --git a/drivers/gpu/drm/msm/dp/dp_panel.h b/drivers/gpu/drm/msm/dp/dp_panel.h index 0e944db3adf2..7910b11fd685 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.h +++ b/drivers/gpu/drm/msm/dp/dp_panel.h @@ -50,6 +50,8 @@ struct msm_dp_panel { u32 max_dp_link_rate; u32 max_bw_code; + + bool tpg_enabled; }; int msm_dp_panel_init_panel_info(struct msm_dp_panel *msm_dp_panel);