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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385ccd68958sm1292959f8f.67.2024.11.28.02.43.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Nov 2024 02:43:13 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH for-10.0 01/25] fpu: handle raising Invalid for infzero in pick_nan_muladd Date: Thu, 28 Nov 2024 10:42:46 +0000 Message-Id: <20241128104310.3452934-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241128104310.3452934-1-peter.maydell@linaro.org> References: <20241128104310.3452934-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org For IEEE fused multiply-add, the (0 * inf) + NaN case should raise Invalid for the multiplication of 0 by infinity. Currently we handle this in the per-architecture ifdef ladder in pickNaNMulAdd(). However, since this isn't really architecture specific we can hoist it up to the generic code. For the cases where the infzero test in pickNaNMulAdd was returning 2, we can delete the check entirely and allow the code to fall into the normal pick-a-NaN handling, because this will return 2 anyway (input 'c' being the only NaN in this case). For the cases where infzero was returning 3 to indicate "return the default NaN", we must retain that "return 3". For Arm, this looks like it might be a behaviour change because we used to set float_flag_invalid | float_flag_invalid_imz only if C is a quiet NaN. However, it is not, because Arm target code never looks at float_flag_invalid_imz, and for the (0 * inf) + SNaN case we already raised float_flag_invalid via the "abc_mask & float_cmask_snan" check in pick_nan_muladd. For any target architecture using the "default implementation" at the bottom of the ifdef, this is a behaviour change but will be fixing a bug (where we failed to raise the Invalid exception for (0 * inf + QNaN). The architectures using the default case are: * hppa * sh4 * tricore The Tricore and SH4 CPU architecture manuals are clear that this should have raised Invalid; HPPA is a bit vaguer but still seems clear enough. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- fpu/softfloat-parts.c.inc | 13 +++++++------ fpu/softfloat-specialize.c.inc | 29 +---------------------------- 2 files changed, 8 insertions(+), 34 deletions(-) diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index cc6e06b9761..d63cd957a19 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -66,19 +66,20 @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, int ab_mask, int abc_mask) { int which; + bool infzero = (ab_mask == float_cmask_infzero); if (unlikely(abc_mask & float_cmask_snan)) { float_raise(float_flag_invalid | float_flag_invalid_snan, s); } - which = pickNaNMulAdd(a->cls, b->cls, c->cls, - ab_mask == float_cmask_infzero, s); + if (infzero) { + /* This is (0 * inf) + NaN or (inf * 0) + NaN */ + float_raise(float_flag_invalid | float_flag_invalid_imz, s); + } + + which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, s); if (s->default_nan_mode || which == 3) { - /* - * Note that this check is after pickNaNMulAdd so that function - * has an opportunity to set the Invalid flag for infzero. - */ parts_default_nan(a, s); return a; } diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 9bca03c4aed..c557c41b2af 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -480,7 +480,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, * the default NaN */ if (infzero && is_qnan(c_cls)) { - float_raise(float_flag_invalid | float_flag_invalid_imz, status); return 3; } @@ -507,7 +506,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, * case sets InvalidOp and returns the default NaN */ if (infzero) { - float_raise(float_flag_invalid | float_flag_invalid_imz, status); return 3; } /* Prefer sNaN over qNaN, in the a, b, c order. */ @@ -529,10 +527,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan) * case sets InvalidOp and returns the input value 'c' */ - if (infzero) { - float_raise(float_flag_invalid | float_flag_invalid_imz, status); - return 2; - } /* Prefer sNaN over qNaN, in the c, a, b order. */ if (is_snan(c_cls)) { return 2; @@ -553,10 +547,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) * case sets InvalidOp and returns the input value 'c' */ - if (infzero) { - float_raise(float_flag_invalid | float_flag_invalid_imz, status); - return 2; - } + /* Prefer sNaN over qNaN, in the c, a, b order. */ if (is_snan(c_cls)) { return 2; @@ -576,10 +567,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, * to return an input NaN if we have one (ie c) rather than generating * a default NaN */ - if (infzero) { - float_raise(float_flag_invalid | float_flag_invalid_imz, status); - return 2; - } /* If fRA is a NaN return it; otherwise if fRB is a NaN return it; * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB @@ -592,14 +579,9 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, return 1; } #elif defined(TARGET_RISCV) - /* For RISC-V, InvalidOp is set when multiplicands are Inf and zero */ - if (infzero) { - float_raise(float_flag_invalid | float_flag_invalid_imz, status); - } return 3; /* default NaN */ #elif defined(TARGET_S390X) if (infzero) { - float_raise(float_flag_invalid | float_flag_invalid_imz, status); return 3; } @@ -617,11 +599,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, return 2; } #elif defined(TARGET_SPARC) - /* For (inf,0,nan) return c. */ - if (infzero) { - float_raise(float_flag_invalid | float_flag_invalid_imz, status); - return 2; - } /* Prefer SNaN over QNaN, order C, B, A. */ if (is_snan(c_cls)) { return 2; @@ -641,10 +618,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, * For Xtensa, the (inf,zero,nan) case sets InvalidOp and returns * an input NaN if we have one (ie c). */ - if (infzero) { - float_raise(float_flag_invalid | float_flag_invalid_imz, status); - return 2; - } if (status->use_first_nan) { if (is_nan(a_cls)) { return 0; From patchwork Thu Nov 28 10:42:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 845919 Delivered-To: patch@linaro.org Received: by 2002:adf:f2c4:0:b0:382:43a8:7b94 with SMTP id d4csp158001wrp; Thu, 28 Nov 2024 02:44:11 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCW5wvdOT53k6i3KmQr+X8uX9MNTRJ+o62TUVEQqpSsE4GT12HXMiou/oGbwRshrngm8DNLD2g==@linaro.org X-Google-Smtp-Source: AGHT+IEcL1RyfLhU+Vd/5xlJvNG3qhrlnhDE3Rq5Oc91cJ+O9kUPzVO4p6YIHXur4k+N1hyPWin4 X-Received: by 2002:a05:620a:6608:b0:7b6:6f2b:ae02 with SMTP id af79cd13be357-7b683a887cbmr490331785a.31.1732790651464; Thu, 28 Nov 2024 02:44:11 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1732790651; cv=none; d=google.com; s=arc-20240605; b=aX/K6dvZESFNrkuxn0a5rJSrKgxmf5u8MF87Ejw+HlNuuiBUnCXxr0f3YEsj4YU//Q 5q9d58wtuWSiWOiHTF+aRLE1AcuB8jB38jdupzcdvAdwAozmkQiJHT/detGaEOtkFHDr PjoO/quaY1IAJIFQbjx8Fi5GMU6ZYsgsiSVLXNzPisxjkZ2eE3XWSIDolcAOJe9IWTwk hHGB1vNf+BZKzxppGCkqkwFxPA7e2dHc+DU/wEWBaxobxx4uZbOzFpgLRSMQVTCXZFYI wK1TkAkW51QVM513SwXNy+GBwk5n8ON0AI5ogWz2o40L5A8Sh0AQJ5tI157FnEQD33oh mG0Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=ZOEO9KTfNfjM4NNmDftZ94Iu5DxbBvsjabJVOrSGkdQ=; fh=QgE9QYJDVj//6C0QJWGeEM+qaFVaxwMel1ZWqkEy6K0=; b=kwr1HnfsWynDeves2XRMKO8CdZSucw6IoGCGIU8g/LIgKqYQP/j+xUUHupjPjtobHx ywq6dEqlNo/wMBIqM9F4FrGL0L8deW94w/TRctGQFaV+JPqvMqCnP0Le4XvWQW3pjV+U feIr7iGNYFJNu/HcocTo+grQalFnoyu/lEEe+AdQMquZXezXbMmbfd1waQ4FkbEm5wX6 oQeZxdqMtyfR5inSvKccINQd74oPLd52aIWFpLqjKhaeX2DToWUBGRQDkpicTfV4TsTo qd1coTWseFP06zigvoj1ClktAZSYOvgk2KzP8WOz/i5brXUHdYVmJu2kXyXUZuvMUBgz gNhw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=v1Cj6jut; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385ccd68958sm1292959f8f.67.2024.11.28.02.43.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Nov 2024 02:43:14 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH for-10.0 02/25] fpu: Check for default_nan_mode before calling pickNaNMulAdd Date: Thu, 28 Nov 2024 10:42:47 +0000 Message-Id: <20241128104310.3452934-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241128104310.3452934-1-peter.maydell@linaro.org> References: <20241128104310.3452934-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org If the target sets default_nan_mode then we're always going to return the default NaN, and pickNaNMulAdd() no longer has any side effects. For consistency with pickNaN(), check for default_nan_mode before calling pickNaNMulAdd(). When we convert pickNaNMulAdd() to allow runtime selection of the NaN propagation rule, this means we won't have to make the targets which use default_nan_mode also set a propagation rule. Since RiscV always uses default_nan_mode, this allows us to remove its ifdef case from pickNaNMulAdd(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- fpu/softfloat-parts.c.inc | 8 ++++++-- fpu/softfloat-specialize.c.inc | 9 +++++++-- 2 files changed, 13 insertions(+), 4 deletions(-) diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index d63cd957a19..aac1f9cd28c 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -77,9 +77,13 @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, float_raise(float_flag_invalid | float_flag_invalid_imz, s); } - which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, s); + if (s->default_nan_mode) { + which = 3; + } else { + which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, s); + } - if (s->default_nan_mode || which == 3) { + if (which == 3) { parts_default_nan(a, s); return a; } diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index c557c41b2af..81a67eb67b5 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -475,6 +475,13 @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls, static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, bool infzero, float_status *status) { + /* + * We guarantee not to require the target to tell us how to + * pick a NaN if we're always returning the default NaN. + * But if we're not in default-NaN mode then the target must + * specify. + */ + assert(!status->default_nan_mode); #if defined(TARGET_ARM) /* For ARM, the (inf,zero,qnan) case sets InvalidOp and returns * the default NaN @@ -578,8 +585,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, } else { return 1; } -#elif defined(TARGET_RISCV) - return 3; /* default NaN */ #elif defined(TARGET_S390X) if (infzero) { return 3; From patchwork Thu Nov 28 10:42:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 845918 Delivered-To: patch@linaro.org Received: by 2002:adf:f2c4:0:b0:382:43a8:7b94 with SMTP id d4csp157884wrp; Thu, 28 Nov 2024 02:43:47 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXdr+wVQOkskrXNJzzon6coUdkXCdmKklpfB692McZSR2vFlpui9XTNgscmdYVD+x+h8rAkjw==@linaro.org X-Google-Smtp-Source: AGHT+IF+YvdHlGZ/VYTPpLD6IhFXj9ZSdqsc1FBwkXYKuliGqfgta/WbOfr3c1PdqlTmab8nhdOZ X-Received: by 2002:a05:622a:48e:b0:465:2fba:71b5 with SMTP id d75a77b69052e-466c1b6daf4mr48413661cf.13.1732790627341; Thu, 28 Nov 2024 02:43:47 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1732790627; cv=none; d=google.com; s=arc-20240605; b=RPoA96T6zoVGeVutUwRdojSY4XqvKZAAdHlDtunMJUfK0yc+WQvLL81m/z2F3jxJhu Qqjg8Er8NrSnayZzgfp5c8T1/UjhZafdPQOHu4n2j+MdQxEA93hEXpEPXNBvzzovTAkO KigToeFuSRWJ/MQfgX1NIdJ5xVeHHyLwtpvp35P3u7tkU48KPXAzAlOzqPRqTuy7+AoE N/UJO2Oe4IUGxWttgTBN12IcAJh9cUO+48cgg1najWxD9r6eaWyJHlgj/m6CTS7IET2C vfCrRW3LzP2E/DbveMJg0SxgB3ogBwfoCbnBg6zCxqdSBPNhYFuS68JdQlLmZzZHo+XN qSsQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=XbqQkBG4nS4k6Fnk766q2xcLuZrRdjETQUTauBBIIX8=; fh=QgE9QYJDVj//6C0QJWGeEM+qaFVaxwMel1ZWqkEy6K0=; b=RRSKhVxWIvCTwOPSZ0/XwF000fj1LEFBPzQlLn5BgV8dPyjkZdAyMqtjw+mxRkLDvd PplCXrPaiuacP/bCJU8qJICfCbXTkH3p/MmNxaVEMbntc0KdD9tH6+wl/soOf6RZeaXH s7qAemKo65R17VoCgQUaL+StLvkYbpWYOpqJSmmKhfm6sEkasnyltf8W76/HZsn/8mQB xb780h9Dz9EnhMT2ULafJjJ3lJs1esEBiVLymJDGHUM3EI9ZtLwbdoSVkKb9lSB/hBSA Kt9uDQu/WCM48EoECAozipwyGMZXNgBJC4ZaJn7O+j4lVxEH3iOmvX+7R1/9ofob2W+D R/Zw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=M1yfbr1z; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385ccd68958sm1292959f8f.67.2024.11.28.02.43.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Nov 2024 02:43:15 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH for-10.0 03/25] softfloat: Allow runtime choice of inf * 0 + NaN result Date: Thu, 28 Nov 2024 10:42:48 +0000 Message-Id: <20241128104310.3452934-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241128104310.3452934-1-peter.maydell@linaro.org> References: <20241128104310.3452934-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org IEEE 758 does not define a fixed rule for what NaN to return in the case of a fused multiply-add of inf * 0 + NaN. Different architectures thus do different things: * some return the default NaN * some return the input NaN * Arm returns the default NaN if the input NaN is quiet, and the input NaN if it is signalling We want to make this logic be runtime selected rather than hardcoded into the binary, because: * this will let us have multiple targets in one QEMU binary * the Arm FEAT_AFP architectural feature includes letting the guest select a NaN propagation rule at runtime In this commit we add an enum for the propagation rule, the field in float_status, and the corresponding getters and setters. We change pickNaNMulAdd to honour this, but because all targets still leave this field at its default 0 value, the fallback logic will pick the rule type with the old ifdef ladder. Note that four architectures both use the muladd softfloat functions and did not have a branch of the ifdef ladder to specify their behaviour (and so were ending up with the "default" case, probably wrongly): i386, HPPA, SH4 and Tricore. SH4 and Tricore both set default_nan_mode, and so will never get into pickNaNMulAdd(). For HPPA and i386 we retain the same behaviour as the old default-case, which is to not ever return the default NaN. This might not be correct but it is not a behaviour change. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- include/fpu/softfloat-helpers.h | 11 ++++ include/fpu/softfloat-types.h | 23 +++++++++ fpu/softfloat-specialize.c.inc | 91 ++++++++++++++++++++++----------- 3 files changed, 95 insertions(+), 30 deletions(-) diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h index 453188de70b..0bf44dc6087 100644 --- a/include/fpu/softfloat-helpers.h +++ b/include/fpu/softfloat-helpers.h @@ -81,6 +81,12 @@ static inline void set_float_2nan_prop_rule(Float2NaNPropRule rule, status->float_2nan_prop_rule = rule; } +static inline void set_float_infzeronan_rule(FloatInfZeroNaNRule rule, + float_status *status) +{ + status->float_infzeronan_rule = rule; +} + static inline void set_flush_to_zero(bool val, float_status *status) { status->flush_to_zero = val; @@ -137,6 +143,11 @@ static inline Float2NaNPropRule get_float_2nan_prop_rule(float_status *status) return status->float_2nan_prop_rule; } +static inline FloatInfZeroNaNRule get_float_infzeronan_rule(float_status *status) +{ + return status->float_infzeronan_rule; +} + static inline bool get_flush_to_zero(float_status *status) { return status->flush_to_zero; diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h index 8f39691dfd0..27a1c96754d 100644 --- a/include/fpu/softfloat-types.h +++ b/include/fpu/softfloat-types.h @@ -207,6 +207,28 @@ typedef enum __attribute__((__packed__)) { float_2nan_prop_x87, } Float2NaNPropRule; +/* + * Rule for result of fused multiply-add 0 * Inf + NaN. + * This must be a NaN, but implementations differ on whether this + * is the input NaN or the default NaN. + * + * You don't need to set this if default_nan_mode is enabled. + * When not in default-NaN mode, it is an error for the target + * not to set the rule in float_status if it uses muladd, and we + * will assert if we need to handle an input NaN and no rule was + * selected. + */ +typedef enum __attribute__((__packed__)) { + /* No propagation rule specified */ + float_infzeronan_none = 0, + /* Result is never the default NaN (so always the input NaN) */ + float_infzeronan_dnan_never = 0, + /* Result is always the default NaN */ + float_infzeronan_dnan_always, + /* Result is the default NaN if the input NaN is quiet */ + float_infzeronan_dnan_if_qnan, +} FloatInfZeroNaNRule; + /* * Floating Point Status. Individual architectures may maintain * several versions of float_status for different functions. The @@ -219,6 +241,7 @@ typedef struct float_status { FloatRoundMode float_rounding_mode; FloatX80RoundPrec floatx80_rounding_precision; Float2NaNPropRule float_2nan_prop_rule; + FloatInfZeroNaNRule float_infzeronan_rule; bool tininess_before_rounding; /* should denormalised results go to zero and set the inexact flag? */ bool flush_to_zero; diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 81a67eb67b5..f5b422e07b5 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -475,6 +475,8 @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls, static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, bool infzero, float_status *status) { + FloatInfZeroNaNRule rule = status->float_infzeronan_rule; + /* * We guarantee not to require the target to tell us how to * pick a NaN if we're always returning the default NaN. @@ -482,14 +484,68 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, * specify. */ assert(!status->default_nan_mode); + + if (rule == float_infzeronan_none) { + /* + * Temporarily fall back to ifdef ladder + */ #if defined(TARGET_ARM) - /* For ARM, the (inf,zero,qnan) case sets InvalidOp and returns - * the default NaN - */ - if (infzero && is_qnan(c_cls)) { - return 3; + /* + * For ARM, the (inf,zero,qnan) case returns the default NaN, + * but (inf,zero,snan) returns the input NaN. + */ + rule = float_infzeronan_dnan_if_qnan; +#elif defined(TARGET_MIPS) + if (snan_bit_is_one(status)) { + /* + * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan) + * case sets InvalidOp and returns the default NaN + */ + rule = float_infzeronan_dnan_always; + } else { + /* + * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan) + * case sets InvalidOp and returns the input value 'c' + */ + rule = float_infzeronan_dnan_never; + } +#elif defined(TARGET_PPC) || defined(TARGET_SPARC) || \ + defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \ + defined(TARGET_I386) || defined(TARGET_LOONGARCH) + /* + * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) + * case sets InvalidOp and returns the input value 'c' + */ + /* + * For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer + * to return an input NaN if we have one (ie c) rather than generating + * a default NaN + */ + rule = float_infzeronan_dnan_never; +#elif defined(TARGET_S390X) + rule = float_infzeronan_dnan_always; +#endif } + if (infzero) { + /* + * Inf * 0 + NaN -- some implementations return the default NaN here, + * and some return the input NaN. + */ + switch (rule) { + case float_infzeronan_dnan_never: + return 2; + case float_infzeronan_dnan_always: + return 3; + case float_infzeronan_dnan_if_qnan: + return is_qnan(c_cls) ? 3 : 2; + default: + g_assert_not_reached(); + } + } + +#if defined(TARGET_ARM) + /* This looks different from the ARM ARM pseudocode, because the ARM ARM * puts the operands to a fused mac operation (a*b)+c in the order c,a,b. */ @@ -508,13 +564,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, } #elif defined(TARGET_MIPS) if (snan_bit_is_one(status)) { - /* - * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan) - * case sets InvalidOp and returns the default NaN - */ - if (infzero) { - return 3; - } /* Prefer sNaN over qNaN, in the a, b, c order. */ if (is_snan(a_cls)) { return 0; @@ -530,10 +579,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, return 2; } } else { - /* - * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan) - * case sets InvalidOp and returns the input value 'c' - */ /* Prefer sNaN over qNaN, in the c, a, b order. */ if (is_snan(c_cls)) { return 2; @@ -550,11 +595,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, } } #elif defined(TARGET_LOONGARCH64) - /* - * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) - * case sets InvalidOp and returns the input value 'c' - */ - /* Prefer sNaN over qNaN, in the c, a, b order. */ if (is_snan(c_cls)) { return 2; @@ -570,11 +610,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, return 1; } #elif defined(TARGET_PPC) - /* For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer - * to return an input NaN if we have one (ie c) rather than generating - * a default NaN - */ - /* If fRA is a NaN return it; otherwise if fRB is a NaN return it; * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB */ @@ -586,10 +621,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, return 1; } #elif defined(TARGET_S390X) - if (infzero) { - return 3; - } - if (is_snan(a_cls)) { return 0; } else if (is_snan(b_cls)) { From patchwork Thu Nov 28 10:42:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 845921 Delivered-To: patch@linaro.org Received: by 2002:adf:f2c4:0:b0:382:43a8:7b94 with SMTP id d4csp158181wrp; Thu, 28 Nov 2024 02:44:43 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWfdS6D99tk5eO0KtlcyaDT7ZJ5tXjgy1ZixPEmXsDdjjfunQx9NAS/f74yl/Pk1TvscpDiHg==@linaro.org X-Google-Smtp-Source: AGHT+IGOK+kKp2u2VcvGo7JbAx3FCP9du2h8ZTLHDp9MkfOYPqosEt6woPxpgPGkk9nXhYyEVdDL X-Received: by 2002:a05:620a:2456:b0:7b1:48f0:406 with SMTP id af79cd13be357-7b683a38fccmr437832285a.19.1732790683103; Thu, 28 Nov 2024 02:44:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1732790683; cv=none; d=google.com; s=arc-20240605; b=Y0W+QxhlPXzeXdrLv7pkDvREFP/Lt71+FPNXpsIpsWHEAIcSwQykyn+zsEopAZ45RN s2nz4T0blsBpUc7va8vhwA0WMQkfjSISz0IJ8X8qpvVcm6hEQ/0bYjOJBD6YckT3jWYz O9noyEm2pjBslDuuZHGWAENhI5Z4hByPz7qrH5M+bURaCV8Jjvk5BRIYJ7PWxUE2w7vZ LjUJ5sICPAYW5it2tYLpV3j/mp3RQoUJ93YEy2M8+9MXJcHiLpdEjxudQxpzN1miY6Ef 3O0FPoIWbhsooBIRpuRVoTwH1ZoRjHCeU8cdr0irQuQS7GC2eSN1Gq+yZFBNsjSacC3j 7lWg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=jI12Che8rR4gDrXI7XaPlHeXLQNnrp2Bpm/Wl6NH9ec=; fh=QgE9QYJDVj//6C0QJWGeEM+qaFVaxwMel1ZWqkEy6K0=; b=iWdW7ekhOM/WNJCgWm2ePP22fLVrJboUiIOs+eManZ5nwpjJA/opgqsJqQHpHT6yiG T5arzNgrr8d97BnM5avqZRk5rYinaZk1vFMrMqD6/6s3/OmOVaUfT259PN9l9AptJiP8 tt/EWkqI4+YFdZKIWo5BAvccCwmVcM7/T1+WJYgla0E+SDwVgUafdoca8c9zLFsdRtuw ZI6UMBgu2UGdFNlZsXpLfWZxLNBBFF/GFYOlaRRDVpkmoU76wA7NZ4VUy5GApyL7yrFe 56k50imTs2+FEuWSWhjuAzEV1ewPwYI0OgF4BiGh/drZVmulLI1W/x4XBwH8SOgO7MDl /lWg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="nkNI/jGO"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385ccd68958sm1292959f8f.67.2024.11.28.02.43.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Nov 2024 02:43:16 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH for-10.0 04/25] tests/fp: Explicitly set inf-zero-nan rule Date: Thu, 28 Nov 2024 10:42:49 +0000 Message-Id: <20241128104310.3452934-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241128104310.3452934-1-peter.maydell@linaro.org> References: <20241128104310.3452934-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Explicitly set a rule in the softfloat tests for the inf-zero-nan muladd special case. In meson.build we put -DTARGET_ARM in fpcflags, and so we should select here the Arm rule of float_infzeronan_dnan_if_qnan. Reviewed-by: Richard Henderson --- tests/fp/fp-bench.c | 5 +++++ tests/fp/fp-test.c | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/tests/fp/fp-bench.c b/tests/fp/fp-bench.c index 75c07d5d1f1..fde64836194 100644 --- a/tests/fp/fp-bench.c +++ b/tests/fp/fp-bench.c @@ -488,7 +488,12 @@ static void run_bench(void) { bench_func_t f; + /* + * These implementation-defined choices for various things IEEE + * doesn't specify match those used by the Arm architecture. + */ set_float_2nan_prop_rule(float_2nan_prop_s_ab, &soft_status); + set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &soft_status); f = bench_funcs[operation][precision]; g_assert(f); diff --git a/tests/fp/fp-test.c b/tests/fp/fp-test.c index 5f6f25c8821..251c278ede9 100644 --- a/tests/fp/fp-test.c +++ b/tests/fp/fp-test.c @@ -935,7 +935,12 @@ void run_test(void) { unsigned int i; + /* + * These implementation-defined choices for various things IEEE + * doesn't specify match those used by the Arm architecture. + */ set_float_2nan_prop_rule(float_2nan_prop_s_ab, &qsf); + set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &qsf); genCases_setLevel(test_level); verCases_maxErrorCount = n_max_errors; From patchwork Thu Nov 28 10:42:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 845920 Delivered-To: patch@linaro.org Received: by 2002:adf:f2c4:0:b0:382:43a8:7b94 with SMTP id d4csp158150wrp; Thu, 28 Nov 2024 02:44:38 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXzXoxw253rNrdsUPImk3NkXl3dW5Jy2uYNHERWAoBXET0gl7/HNBhzU54nCvQqZyb6mnzBLw==@linaro.org X-Google-Smtp-Source: AGHT+IFn4sungleZB5b7nBh+6p71QNrsSkFH1B+EAXw/v7laANdD/MDVYzbV//69fEjdPeu/ZJ7W X-Received: by 2002:a05:620a:4728:b0:7b6:785e:ce1a with SMTP id af79cd13be357-7b67c250b0fmr813325885a.4.1732790678704; Thu, 28 Nov 2024 02:44:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1732790678; cv=none; d=google.com; s=arc-20240605; b=hnd9BTNdA3LQPMKk/m+0cNiZ9MlH7WFfyON2rFvpL/v/Uwt7qdbd4wMYLpBVbq9T34 UNnP1QWko4j4WuQi5a0v/+aiEXwOpyfDo1/l8Qj7+/INaAjRw2JMq38zoTPRFMVUbd/8 naWUTAVLj8tR014Mk2FA33HNNZmJbBJiOvVdSxQibxH5ih+mDzP8U1nU8TKCC3h1hbBu BiLxAKazemgUjofNqEHzt7+r40oIXIM6j455g8kr0ZpP5VOnVeU8lxkP2GWEpnEXfy7k 1nf3zI9dmaTOWKwyBE0BH1HxOWVr4s4YVaNrzjHN4KqDkMNe2d8kH94EMvyqlFoPTcr/ UMAQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=4tTkIIhrcxBZurdxQEsXyUswGgpnjQ7q8C2Djt24mE4=; fh=QgE9QYJDVj//6C0QJWGeEM+qaFVaxwMel1ZWqkEy6K0=; b=GuxHL+j6vW3Fo+oOkAig15xS39hB6wa6a2FeqAWXGz3Efk66ORwVme96AeJ7VUcYe1 rWqRYJfSNKN+l2dwHPIcN5y/l7Xf0GZIEG2QnDR9n2iF0nxOcZIxDqXso8lVhmaadu3E QowRqMdBV2vVBqzKI94aeHtCA8CorOo9DxLUt07LQXyi1HsgcOW9FFqXzs8Im5WcyyNv yOuee5aFPfHm8R5FqtT49BK8iEBwpUh06rmLjgNw3O5GGZ69hvTSMZWkO7pHkx6/Al0o ZDtKVE+0Ei6sYo6w/G57fyfaYDMODm7zl4CcBchD81jxF72Wq1sWzgjeD0EwtzQsbQvD u+zg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=r9xj4aTE; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385ccd68958sm1292959f8f.67.2024.11.28.02.43.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Nov 2024 02:43:17 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH for-10.0 05/25] target/arm: Set FloatInfZeroNaNRule explicitly Date: Thu, 28 Nov 2024 10:42:50 +0000 Message-Id: <20241128104310.3452934-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241128104310.3452934-1-peter.maydell@linaro.org> References: <20241128104310.3452934-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the FloatInfZeroNaNRule explicitly for the Arm target, so we can remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.c | 3 +++ fpu/softfloat-specialize.c.inc | 8 +------- 2 files changed, 4 insertions(+), 7 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 6938161b954..ead39793985 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -173,11 +173,14 @@ void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, * * tininess-before-rounding * * 2-input NaN propagation prefers SNaN over QNaN, and then * operand A over operand B (see FPProcessNaNs() pseudocode) + * * 0 * Inf + NaN returns the default NaN if the input NaN is quiet, + * and the input NaN if it is signalling */ static void arm_set_default_fp_behaviours(float_status *s) { set_float_detect_tininess(float_tininess_before_rounding, s); set_float_2nan_prop_rule(float_2nan_prop_s_ab, s); + set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, s); } static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index f5b422e07b5..b3ffa54f368 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -489,13 +489,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, /* * Temporarily fall back to ifdef ladder */ -#if defined(TARGET_ARM) - /* - * For ARM, the (inf,zero,qnan) case returns the default NaN, - * but (inf,zero,snan) returns the input NaN. - */ - rule = float_infzeronan_dnan_if_qnan; -#elif defined(TARGET_MIPS) +#if defined(TARGET_MIPS) if (snan_bit_is_one(status)) { /* * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan) From patchwork Thu Nov 28 10:42:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 845930 Delivered-To: patch@linaro.org Received: by 2002:adf:f2c4:0:b0:382:43a8:7b94 with SMTP id d4csp159703wrp; Thu, 28 Nov 2024 02:49:20 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWTZkN1JnZMcLqe6UroDfILuVbP9EytF03f0JbHGlTgCyEHlodkWNT0kKwWsR9lSiAHlZ9wAw==@linaro.org X-Google-Smtp-Source: AGHT+IEipSQI6L5h/eeJPARENGEv1vqMzxPZ89zopbTfJA01BUxFM/PizAewMfLgsFY+jh+MdDn1 X-Received: by 2002:a05:622a:60e:b0:466:a119:f4d3 with SMTP id d75a77b69052e-466b36b7aa1mr104008251cf.45.1732790959983; Thu, 28 Nov 2024 02:49:19 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1732790959; cv=none; d=google.com; s=arc-20240605; b=KU4SRmDVY3VGC9NCpEZKTzNIJ7vzpNcK+gZXXmnVfurUipW9Xcc9kCjHpgCtzYtQwm cAm8uqKl/dbmPiP0XOlf4ksiGTaw1uzwJi+/3VcZRjREszcixummHDOaMfs5lxolfSF6 HqKZo/qB+CL10N+eWlnpTo/8qHYZpEIrNM+4gXJIY3gEC6ppgRzqK8W4IEaTErZ1rRpt Fh9GFZ4ERyrSvD/9Tpe7iRSeFDy9bGo1m/FIANM9dDI62qewsNOdAalB5b16RA/0F6Ds FzQHXXlO0UP+r/TMUTC3aO0R1NGZV1OKvxdARSC5YTZEJxVYeg6gdiC7oayiYh9LmDlW Zdsw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=CN209ow1u88/SvecQPZ/3IUJ9A/OS7lKONjS1X1zVa4=; fh=QgE9QYJDVj//6C0QJWGeEM+qaFVaxwMel1ZWqkEy6K0=; b=QVbvxJGwML0AoMbi1mZUM/Ts8TgAkDP3el42IH2oJFvBhajxXFjcXBxWyxAtz3ofKK 5Zp3KupyhEdZbqqImrJybFF9DAm6r8lRTaUzWSbU23Rzw1rzwYqIsMtGmpUaVU2MC4aA GnNxYVa4vIRr12ajdH3Fj/knGPIgul92BNKr9Lspfk/X6xm2ASpExcZ0rH6Z/F/QKQVi NRdSwfnBHqSPxZTQfFH6PV79uUJWbEABZrzfK2vBP4lS4On0iBZTBTGQ5CuGaPrXldXw Vz7YR2+AQ/EcAHRfS2K1RCQzXyuSx6AO6Z9EUdruCycarJsD/qH8L3dTrppczkAEP/xD RI8w==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=fCA8luC8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385ccd68958sm1292959f8f.67.2024.11.28.02.43.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Nov 2024 02:43:18 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH for-10.0 06/25] target/s390: Set FloatInfZeroNaNRule explicitly Date: Thu, 28 Nov 2024 10:42:51 +0000 Message-Id: <20241128104310.3452934-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241128104310.3452934-1-peter.maydell@linaro.org> References: <20241128104310.3452934-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the FloatInfZeroNaNRule explicitly for s390, so we can remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/s390x/cpu.c | 2 ++ fpu/softfloat-specialize.c.inc | 2 -- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 514c70f3010..d5941b5b9df 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -206,6 +206,8 @@ static void s390_cpu_reset_hold(Object *obj, ResetType type) set_float_detect_tininess(float_tininess_before_rounding, &env->fpu_status); set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fpu_status); + set_float_infzeronan_rule(float_infzeronan_dnan_always, + &env->fpu_status); /* fall through */ case RESET_TYPE_S390_CPU_NORMAL: env->psw.mask &= ~PSW_MASK_RI; diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index b3ffa54f368..db914ddbb1c 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -516,8 +516,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, * a default NaN */ rule = float_infzeronan_dnan_never; -#elif defined(TARGET_S390X) - rule = float_infzeronan_dnan_always; #endif } From patchwork Thu Nov 28 10:42:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 845926 Delivered-To: patch@linaro.org Received: by 2002:adf:f2c4:0:b0:382:43a8:7b94 with SMTP id d4csp159065wrp; Thu, 28 Nov 2024 02:47:16 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCUM18+hwjFS8LvPFFGDc9IOuY0Q3OsyzznDB/NNh+Z+CR87XShFOV8uyV1O+ogi1yCJc3MZBg==@linaro.org X-Google-Smtp-Source: AGHT+IH6CKwOLeCDIcQTRhAYCStuzLYWwB2SbAsg+hsK1K71HUUYTuEfrlomhiJx4hL0wfEn2Wst X-Received: by 2002:a05:6358:93a7:b0:1ca:665e:943a with SMTP id e5c5f4694b2df-1cab159d49cmr411247055d.2.1732790835899; Thu, 28 Nov 2024 02:47:15 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1732790835; cv=none; d=google.com; s=arc-20240605; b=TAvGftw062oAAaE/TBcfmGFns/kC//2q8+CYK4hmvizx5El17aaSSkkOvIxvltcHv/ /59Ms8A/F2saZm1pxCAs2CHTXOoOtjTDmBtbCrEHdvokalNzK8Pu0Hr08a9et1tuoSmb AdxQosU+tFV5hziVSOUCCCPF2KZIDo64LVIOSAHI/BQvyolqkUosF8vctmBsaGL5HRqq MGSQbDCsxIKFCzijJW41gxlVV8wkdT3EhryzvYBkcZ1B8Bxprmt3QAJEAE5M+hxprdsm 5aJetB7YLZ48HnTklwgRYq8fZ/94gOfEIDPtxL6m7d+6HODZB0oBtQ41stMC8yPRzYbM /r1w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=I7qNHcv2xsM6B0IoBDGG37yuVzj27RgfOCxf0ou+qD0=; fh=QgE9QYJDVj//6C0QJWGeEM+qaFVaxwMel1ZWqkEy6K0=; b=bQLVBhCviHQaTb+e24k7nTzsc1pQNkGrmm62h+tAbdOv+H+lB2DUZ8FrCxo7XDirCg tNCJ6zJcqQnihawE/cqlDRnI5az8iVhuxK98YkSwdsKjfZP5Fd9U1bphdkyCeNCcyy7l h5EUG/DCJWsak1TcXW178JUOgRM12ihesHYoh/5otOWj9OAvcz+sNAAV0cQuKafyXuoq 2tn5+Alpbls+yGe6lOcHjLvW4j2fXYSwyVYaVMPQ4Fj8q8vPwcc1iRaKynsKq0Mz46AY q0ZKuAb7Vz3s0vAAwshRaa+UUug6QZW+lk38eA28KnZFmb8O9ks/UvRdI+NnIXIRNhKi 1tvQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=LMIPGlVd; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385ccd68958sm1292959f8f.67.2024.11.28.02.43.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Nov 2024 02:43:18 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH for-10.0 07/25] target/ppc: Set FloatInfZeroNaNRule explicitly Date: Thu, 28 Nov 2024 10:42:52 +0000 Message-Id: <20241128104310.3452934-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241128104310.3452934-1-peter.maydell@linaro.org> References: <20241128104310.3452934-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the FloatInfZeroNaNRule explicitly for the PPC target, so we can remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/ppc/cpu_init.c | 7 +++++++ fpu/softfloat-specialize.c.inc | 7 +------ 2 files changed, 8 insertions(+), 6 deletions(-) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index efcb80d1c25..f18908a643a 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7270,6 +7270,13 @@ static void ppc_cpu_reset_hold(Object *obj, ResetType type) */ set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status); set_float_2nan_prop_rule(float_2nan_prop_ab, &env->vec_status); + /* + * For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer + * to return an input NaN if we have one (ie c) rather than generating + * a default NaN + */ + set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); + set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->vec_status); for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) { ppc_spr_t *spr = &env->spr_cb[i]; diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index db914ddbb1c..2023b2bd632 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -503,18 +503,13 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, */ rule = float_infzeronan_dnan_never; } -#elif defined(TARGET_PPC) || defined(TARGET_SPARC) || \ +#elif defined(TARGET_SPARC) || \ defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \ defined(TARGET_I386) || defined(TARGET_LOONGARCH) /* * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) * case sets InvalidOp and returns the input value 'c' */ - /* - * For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer - * to return an input NaN if we have one (ie c) rather than generating - * a default NaN - */ rule = float_infzeronan_dnan_never; #endif } From patchwork Thu Nov 28 10:42:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 845940 Delivered-To: patch@linaro.org Received: by 2002:adf:f2c4:0:b0:382:43a8:7b94 with SMTP id d4csp159859wrp; Thu, 28 Nov 2024 02:49:47 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWnxfdusCtyeJcp3WJxzQVI2rJl20h9F8ji2SI+5ugyMgD4FMxFlwtZsd2N/hYExfCBrH5pkQ==@linaro.org X-Google-Smtp-Source: AGHT+IGIwsQv05T4avP6FXPf5SY5m8u88ab1fNkujDfGM5exbi21KBSMaWH/mOzsOIwEsM3OUQ02 X-Received: by 2002:a05:620a:27d6:b0:7b6:742d:c01e with SMTP id af79cd13be357-7b67c2906e4mr849727485a.25.1732790987627; Thu, 28 Nov 2024 02:49:47 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1732790987; cv=none; d=google.com; s=arc-20240605; b=PljpDNhaBrB4mqI0PLon26lN3GBJrbHDm9sycF9CGQ1o0y8vixL+Oss7HAIZSzjQEb 3R+xb9mEJIGuMU7GKpJJUz2qb0AluvJNX8PQ5U43M9koCQ+m3q3k1CdcbyO7Cd54h6Gf FPfnpY4FhS45Y+bcSjDo8mTmBnatj6ceFLZYMtaKT6NZYtpSm5b+ztlH1gIbcU/eiqXh gYrnnb9JPAsMDZ6OZwQxktJJkz7IxJu1oX5cTJtNd6MuCtXPVuBZMaJcmY2MzclIr7wO tGoaoNjinKV6wEiApkJVq2yXjDXpx8p8vvwI8blKkX/iqBz0I4+YgWdBK886pZBEe338 FiAA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=YwvjGP9nM6OJvLHzJNmFilwr8r1rRnLYpGXxx9aO2ss=; fh=QgE9QYJDVj//6C0QJWGeEM+qaFVaxwMel1ZWqkEy6K0=; b=T6gNC3ZHGoAHK6uQRqEzwNCA9JwG19kLB2vK8PKt5Gv6UcNijrM6stddAkKzYjw4eZ fHKQq7aZrjfgrjjWJGe1vEl6mzmDaU83sszPyBBYLWIt8uUd4nQ7L3JIqkPNVK4vIBaT Eq3QT+/icoEZ/zlRT7dHxpITFvw4iABc2ldkh1ERIx23Mq3fN06JhircZxI02KJIATXZ lV9F6WK29NRwpPenFwj9JmYupwwPkLf92UwGXJB0kwcNjnoH5pyRMIxmrnwXCxkST+3P E3MlW9d1b4oAWo0zBvkHmbMYAXiIYTK1RNrxuN5fQ5jRWcQF6ipHrbV/8/003Pj5gAHg gnJQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=bc7XbSw7; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385ccd68958sm1292959f8f.67.2024.11.28.02.43.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Nov 2024 02:43:19 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH for-10.0 08/25] target/mips: Set FloatInfZeroNaNRule explicitly Date: Thu, 28 Nov 2024 10:42:53 +0000 Message-Id: <20241128104310.3452934-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241128104310.3452934-1-peter.maydell@linaro.org> References: <20241128104310.3452934-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the FloatInfZeroNaNRule explicitly for the MIPS target, so we can remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/mips/fpu_helper.h | 9 +++++++++ target/mips/msa.c | 4 ++++ fpu/softfloat-specialize.c.inc | 16 +--------------- 3 files changed, 14 insertions(+), 15 deletions(-) diff --git a/target/mips/fpu_helper.h b/target/mips/fpu_helper.h index 7c3c7897b45..be66f2f813a 100644 --- a/target/mips/fpu_helper.h +++ b/target/mips/fpu_helper.h @@ -28,6 +28,7 @@ static inline void restore_flush_mode(CPUMIPSState *env) static inline void restore_snan_bit_mode(CPUMIPSState *env) { bool nan2008 = env->active_fpu.fcr31 & (1 << FCR31_NAN2008); + FloatInfZeroNaNRule izn_rule; /* * With nan2008, SNaNs are silenced in the usual way. @@ -35,6 +36,14 @@ static inline void restore_snan_bit_mode(CPUMIPSState *env) */ set_snan_bit_is_one(!nan2008, &env->active_fpu.fp_status); set_default_nan_mode(!nan2008, &env->active_fpu.fp_status); + /* + * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan) + * case sets InvalidOp and returns the default NaN. + * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan) + * case sets InvalidOp and returns the input value 'c'. + */ + izn_rule = nan2008 ? float_infzeronan_dnan_never : float_infzeronan_dnan_always; + set_float_infzeronan_rule(izn_rule, &env->active_fpu.fp_status); } static inline void restore_fp_status(CPUMIPSState *env) diff --git a/target/mips/msa.c b/target/mips/msa.c index 9dffc428f5c..cc152db27f9 100644 --- a/target/mips/msa.c +++ b/target/mips/msa.c @@ -74,4 +74,8 @@ void msa_reset(CPUMIPSState *env) /* set proper signanling bit meaning ("1" means "quiet") */ set_snan_bit_is_one(0, &env->active_tc.msa_fp_status); + + /* Inf * 0 + NaN returns the input NaN */ + set_float_infzeronan_rule(float_infzeronan_dnan_never, + &env->active_tc.msa_fp_status); } diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 2023b2bd632..db9a466e05b 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -489,21 +489,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, /* * Temporarily fall back to ifdef ladder */ -#if defined(TARGET_MIPS) - if (snan_bit_is_one(status)) { - /* - * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan) - * case sets InvalidOp and returns the default NaN - */ - rule = float_infzeronan_dnan_always; - } else { - /* - * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan) - * case sets InvalidOp and returns the input value 'c' - */ - rule = float_infzeronan_dnan_never; - } -#elif defined(TARGET_SPARC) || \ +#if defined(TARGET_SPARC) || \ defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \ defined(TARGET_I386) || defined(TARGET_LOONGARCH) /* From patchwork Thu Nov 28 10:42:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 845942 Delivered-To: patch@linaro.org Received: by 2002:adf:f2c4:0:b0:382:43a8:7b94 with SMTP id d4csp160204wrp; Thu, 28 Nov 2024 02:50:53 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVFAbvUU2Dvw/TGevvw8xFxGPmxS73DMMVvhfdMQIriBBWpSUPLH7c/pbmiQZziF0m1r8LB7Q==@linaro.org X-Google-Smtp-Source: AGHT+IE3536pmVioKUlXeRCwHHjRTimgiG77r574813/kOziLuV2V0jHwE995VfGnBLQMx55hKFO X-Received: by 2002:a05:690c:7085:b0:6ee:b43b:62fd with SMTP id 00721157ae682-6ef3728dcc6mr75068247b3.41.1732791053155; Thu, 28 Nov 2024 02:50:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1732791053; cv=none; d=google.com; s=arc-20240605; b=j1MMqedmD1qzf9Mn2FJS7ks/f/NpLyptEyEeudM6CDA/3MwA9RxFSQtSwGzrdnR8VJ pYPRaoGhpUzAAUeRtx8HReFX/2pifFTS2vhCZ+h5aNtPRRcORPs7E+dejAWXfWeCDnQc EszgxaapZOuYotsJvWegg48Uq1L/87wM9slJVYy4bRba+/39XAKZTpy/ujqWdU2b0c48 UO2KfJ28DE/O7sL5mh35yJUzdU/lChKfZIDa6+dKN4FHALZslydoP77macjAHLJADmkc Ick8XCb318mySaxTp908s4piGDDHK1mm9M5GCPzrMSZ7rLhxjvi48x5M8V0C1xeCxf0K mYQw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=oGeQkgWiOnpuuXWXZlTMDkuSTfoKIXOn3w/Ju141f2Q=; fh=QgE9QYJDVj//6C0QJWGeEM+qaFVaxwMel1ZWqkEy6K0=; b=ZPhCIC/UK9Rwvm6sajhUaRmNahsB56Fsw2dd82rj0ZPB3UCtgG44gIsI1Ei57i06by uZV+kexSEe+GJIIfkrKgox4ymg1qhUNo7JVyheCHA66WN3I2hQ7VZwdZ6Rl5Fi635xHm ts97N7Avtx5kLL9m9y4nnD7k9rBLusUkMDAFyrmTGVFKGDWR7Z0O2/I6/l+R+hs4Vhj4 1SMpmWCiJ9m2XPG1a1BD3hZhoO4X9kGOyfdLf/XgJ/f1NyTdKbn5e8CPm6l2nNyN9JTX YrJbq8280KZXo1ZPoqfbA2oi7dN9XaanOjeCyMiQoHz8ZRozpZGu+6zqgg3/USnxXqle 1arA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=lZToagLg; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385ccd68958sm1292959f8f.67.2024.11.28.02.43.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Nov 2024 02:43:20 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH for-10.0 09/25] target/sparc: Set FloatInfZeroNaNRule explicitly Date: Thu, 28 Nov 2024 10:42:54 +0000 Message-Id: <20241128104310.3452934-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241128104310.3452934-1-peter.maydell@linaro.org> References: <20241128104310.3452934-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the FloatInfZeroNaNRule explicitly for the SPARC target, so we can remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/sparc/cpu.c | 2 ++ fpu/softfloat-specialize.c.inc | 3 +-- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index dd7af86de73..61f2d3fbf23 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -814,6 +814,8 @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp) * the CPU state struct so it won't get zeroed on reset. */ set_float_2nan_prop_rule(float_2nan_prop_s_ba, &env->fp_status); + /* For inf * 0 + NaN, return the input NaN */ + set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); cpu_exec_realizefn(cs, &local_err); if (local_err != NULL) { diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index db9a466e05b..7e57e85348b 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -489,8 +489,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, /* * Temporarily fall back to ifdef ladder */ -#if defined(TARGET_SPARC) || \ - defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \ +#if defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \ defined(TARGET_I386) || defined(TARGET_LOONGARCH) /* * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) From patchwork Thu Nov 28 10:42:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 845937 Delivered-To: patch@linaro.org Received: by 2002:adf:f2c4:0:b0:382:43a8:7b94 with SMTP id d4csp159774wrp; Thu, 28 Nov 2024 02:49:32 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXC+bb8tgMWvWRSh6eacCS6gtYK/w1XaTjIxfWdzmKDozAlwY70zY6Vn9ufaBrZ2+JCO2DRfw==@linaro.org X-Google-Smtp-Source: AGHT+IE8aBudmOIWe/zg5fPV9EqL5J+ftexki/mLhzIB8oqUndOFkFFKxj3TXPT+k2qvvOUnFMqU X-Received: by 2002:ad4:5cad:0:b0:6d4:1fc8:8e70 with SMTP id 6a1803df08f44-6d8729722efmr50920796d6.10.1732790972343; Thu, 28 Nov 2024 02:49:32 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1732790972; cv=none; d=google.com; s=arc-20240605; b=QENoAwRB8N1h0nbhKB+TMuy20u5O6w429onxpxEfjf9rto6xJHPiuUQqR08q8eIenD FRixhsFj/apmds6OPz3F6h0GMnRoOdQ3e8juyNmUXOmFbG1hnFT0Y7hYv3A7ENVPqegz wPFtExb7ZVPboTJBChZa76NWBhuqVuKdXcdSzEhX2cx+VtVaamd1K/2LJGkt53n+cWZE V6a/8sKPX4TjUQgZJS3ouhaoAUxeJMWNMlOGUppUYxqVh8CafkpJdWC7o9fkWdpbci3y cnO46C3w9h5RY+AsuleHgcr75Je1c8PxWN3fPCuH8MOhqVBasOsH+exP7tgwuUBNeiHf Sjtw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=5Xo5Wy1Oob5f6vaToYcDecYPVf+U4Qw0T3qC57WwruI=; fh=QgE9QYJDVj//6C0QJWGeEM+qaFVaxwMel1ZWqkEy6K0=; b=NFTc8A4iGDt2Z3zeEWJ/9FqJ/egkLM5tadKph964leLByPf5OqmCW57GL4O2TzT37H ySg0ffWQqCrIgsDUh1/IsW4F9YGvfXkER5AiNB95RcUgEi0yieHcBJnaIWDVLMQ909ps oBSRZVGZAr8m9oW/XD05RatJJAdspySHPfCGWvB1w1d908UpiR3421dJz0rlKOsVhggi f8SCFEDajlp6zUtcLUKAG7Qm5du26VUTfHGc04p/7ISdza9PYJROaf+uG51p7sLtJbOn n9fu26w9f1wrG7aOv5DPxcviCKaQi+eynJ9H94gHXY3mk2TrY50WIqDp6ZFvqM5rqd84 X+pA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Nc0exO5C; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385ccd68958sm1292959f8f.67.2024.11.28.02.43.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Nov 2024 02:43:21 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH for-10.0 10/25] target/xtensa: Set FloatInfZeroNaNRule explicitly Date: Thu, 28 Nov 2024 10:42:55 +0000 Message-Id: <20241128104310.3452934-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241128104310.3452934-1-peter.maydell@linaro.org> References: <20241128104310.3452934-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the FloatInfZeroNaNRule explicitly for the xtensa target, so we can remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/xtensa/cpu.c | 2 ++ fpu/softfloat-specialize.c.inc | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 6f9039abaee..3163b758235 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -133,6 +133,8 @@ static void xtensa_cpu_reset_hold(Object *obj, ResetType type) reset_mmu(env); cs->halted = env->runstall; #endif + /* For inf * 0 + NaN, return the input NaN */ + set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); set_no_signaling_nans(!dfpu, &env->fp_status); xtensa_use_first_nan(env, !dfpu); } diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 7e57e85348b..3062d19402d 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -489,7 +489,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, /* * Temporarily fall back to ifdef ladder */ -#if defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \ +#if defined(TARGET_HPPA) || \ defined(TARGET_I386) || defined(TARGET_LOONGARCH) /* * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) From patchwork Thu Nov 28 10:42:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 845925 Delivered-To: patch@linaro.org Received: by 2002:adf:f2c4:0:b0:382:43a8:7b94 with SMTP id d4csp159064wrp; Thu, 28 Nov 2024 02:47:16 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCW7IaapJpi1gcnwy8A2KZvx8WPauHLoV8IwZXLxh8ord78YcynB8l1dgM1iuDFBMrl811IJ9A==@linaro.org X-Google-Smtp-Source: AGHT+IEpiqoH1jY6wtadM54kYe9Q7g7f8Ryry4ZrIyU6OwQpD2z5DYmwSCpZwSKopBkfkPw+E83K X-Received: by 2002:a05:622a:180e:b0:463:1577:2412 with SMTP id d75a77b69052e-466b34f389cmr87929691cf.20.1732790835873; Thu, 28 Nov 2024 02:47:15 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1732790835; cv=none; d=google.com; s=arc-20240605; b=bTIRFGcjyh9DFNtezdvglR+DbuH9NMS4kKfyepOVs4n4u0dqfxmcZEkS8pd9/hSrnd /h+GnnM3yOxe+08+3DCq9QCqYAkPiFHRAzh0pPQ3o6AMZyisEQi7fa3ULlfBqCcS6dnw acW6ARoQwqa3mEvAEv0h8Ce8yjJnhMeGSQVDhpSSa8p9p/ejQor3KF+LQxWTF7e2l3Rw 9mAIrqDOnk5VqwHfd1qMVBwGWKNApY9Gw1zW4bUe1OwgWuFkA0QT6Nffd8qmwhITFBPZ e0ZB7vZXBO4yY4SXkwa8RWoSjRE892yy0gVH6vOBUYvjuXlnWu2KDXbclsncRHCSchrf QpDQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=ek+hZskUnfXDQCh1OptQZbXmCqnBmww89XjzyzcdKGw=; fh=QgE9QYJDVj//6C0QJWGeEM+qaFVaxwMel1ZWqkEy6K0=; b=cUrk4M6HXxVfV5hy81PwWfhoz+8DzVrM23LjJhsEqH2Y0VCT46Hd3ki1hF9b8lpWzU oMDtAeXXiQlGUOZQuzAHMbfSN/j3s4/eztzZjXsSYcum+GmwAE+r/XlcOHB6H3EUQwIL ODzH3KWIJPPxCWXNlJI7b0qXaWwni7lP40CuRjgWXe7KhXP0UBAN/4xXvaBdSdyMNfVj 1ksFJntLkinwbIFMz0T53KOrThvFEeptLTUHaWentU5jRIwn2Os4VIi2EL6+1mJlxDu9 g51DQMoT0pI1lI5azrnDha6PETcPFArx0hgn7gtLSnPO7MJ+YtSg2kHfJgnsgKzhbmGx uOuA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PJFES68e; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385ccd68958sm1292959f8f.67.2024.11.28.02.43.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Nov 2024 02:43:22 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH for-10.0 11/25] target/x86: Set FloatInfZeroNaNRule explicitly Date: Thu, 28 Nov 2024 10:42:56 +0000 Message-Id: <20241128104310.3452934-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241128104310.3452934-1-peter.maydell@linaro.org> References: <20241128104310.3452934-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the FloatInfZeroNaNRule explicitly for the x86 target. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/i386/tcg/fpu_helper.c | 7 +++++++ fpu/softfloat-specialize.c.inc | 2 +- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c index 53b49bb2977..e9de084a96d 100644 --- a/target/i386/tcg/fpu_helper.c +++ b/target/i386/tcg/fpu_helper.c @@ -173,6 +173,13 @@ void cpu_init_fp_statuses(CPUX86State *env) */ set_float_2nan_prop_rule(float_2nan_prop_x87, &env->mmx_status); set_float_2nan_prop_rule(float_2nan_prop_x87, &env->sse_status); + /* + * Only SSE has multiply-add instructions. + * TODO: this might be wrong, as we never implemented any x86-specific + * handling for the NaN case for multiply-add. This needs to be checked + * against the manual. + */ + set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->sse_status); } static inline uint8_t save_exception_flags(CPUX86State *env) diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 3062d19402d..ad4f7096d09 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -490,7 +490,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, * Temporarily fall back to ifdef ladder */ #if defined(TARGET_HPPA) || \ - defined(TARGET_I386) || defined(TARGET_LOONGARCH) + defined(TARGET_LOONGARCH) /* * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) * case sets InvalidOp and returns the input value 'c' From patchwork Thu Nov 28 10:42:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 845924 Delivered-To: patch@linaro.org Received: by 2002:adf:f2c4:0:b0:382:43a8:7b94 with SMTP id d4csp158741wrp; Thu, 28 Nov 2024 02:46:17 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCV54QsYTjZxh5/827ZO4KOMdFaoMoO92y2XM046M2p02j1RO1DAWQe/j83dOJj1q94J759GOQ==@linaro.org X-Google-Smtp-Source: AGHT+IHUtfyCVOzKuCSJotd+9yqpjGMNpO63/2xbCJpnjSydl4ck3djmvxwdTTl5QOuc3swfAYsF X-Received: by 2002:a05:620a:2b85:b0:7b6:7970:6506 with SMTP id af79cd13be357-7b67c43d07bmr858345485a.38.1732790777658; Thu, 28 Nov 2024 02:46:17 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1732790777; cv=none; d=google.com; s=arc-20240605; b=OcCkrNZXu9Py3fyeadBOWXdMx3BNRUP81ghoKCmAJiyuK0xQT8vE3yZ6/MxL9gu1LG PPl0Ayu6UI+CyYSBMeTBNUxJJ7oR+7yG7FaPtVmzMAa6EQA7/gsjyOlejLKNtEJC5pGl YioUACM0yX88ibIFxBI8U5R1bOhZpFSBujCHxrgMmbEsf6VvpT9mnI5S+d6qBUWwL33J bqVQn8V0JpWdLFRGpv+IBT8jfD8RPCONKphnX1tPgsV7N50V+/9QWgalDR49OHDFj/2s p89Zs3Wk+e7itocnU5krI4zByFbVdGGoh8N9KmTqnD1LN25Nc6zPkz3Z7tDh/Sla7XCf WybQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=iZVybYeuTrOgtrqao8PQeLVJYcnLhthP9z/tircoyS0=; fh=QgE9QYJDVj//6C0QJWGeEM+qaFVaxwMel1ZWqkEy6K0=; b=RvSpmvm7dxA7DRV7iN9+SlyslzyxuDzVuAUAIotMPPhZtc0BU+Eh0+bZLZDC+MLkl7 56GVbXQkl5mS3ERQjOA8SEGfneNqOVC26MuzDkMlM1GURKYdIKikRtF6V5MypnGGo048 WdCDwzAwUhcrpjtaz4HqPkZbmBx13dacPeU1ILk8FC4dahwz5V7qZ8Fo63yiONw/tq5X 8/NJeWY910VImTji7/YjpGkinBjKgKGEEfTUNGjhsBN5CGH/3IpvJXMNHey35z/dhHaf omjn4WYBrYIza7x92EJJAnQz3mHW7N5B8rpyyxPUNKBUZYxtOYJNZWqtG1B1+g25gG/5 wsdA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="znbQ/eo/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385ccd68958sm1292959f8f.67.2024.11.28.02.43.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Nov 2024 02:43:23 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH for-10.0 12/25] target/loongarch: Set FloatInfZeroNaNRule explicitly Date: Thu, 28 Nov 2024 10:42:57 +0000 Message-Id: <20241128104310.3452934-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241128104310.3452934-1-peter.maydell@linaro.org> References: <20241128104310.3452934-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the FloatInfZeroNaNRule explicitly for the loongarch target. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/loongarch/tcg/fpu_helper.c | 5 +++++ fpu/softfloat-specialize.c.inc | 7 +------ 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c index 21bc3b04a96..6a2c4b5b1db 100644 --- a/target/loongarch/tcg/fpu_helper.c +++ b/target/loongarch/tcg/fpu_helper.c @@ -32,6 +32,11 @@ void restore_fp_status(CPULoongArchState *env) &env->fp_status); set_flush_to_zero(0, &env->fp_status); set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fp_status); + /* + * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) + * case sets InvalidOp and returns the input value 'c' + */ + set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); } int ieee_ex_to_loongarch(int xcpt) diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index ad4f7096d09..05dec2fcb4c 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -489,12 +489,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, /* * Temporarily fall back to ifdef ladder */ -#if defined(TARGET_HPPA) || \ - defined(TARGET_LOONGARCH) - /* - * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) - * case sets InvalidOp and returns the input value 'c' - */ +#if defined(TARGET_HPPA) rule = float_infzeronan_dnan_never; #endif } From patchwork Thu Nov 28 10:42:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 845938 Delivered-To: patch@linaro.org Received: by 2002:adf:f2c4:0:b0:382:43a8:7b94 with SMTP id d4csp159816wrp; Thu, 28 Nov 2024 02:49:39 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXZC1+IzREt9XbOfEMM9L/jlHKJsQUgFXmPzcJMEhMwK+UYXuqAWxD+WvrS6Wk54hNAhd4rkA==@linaro.org X-Google-Smtp-Source: AGHT+IE63HPD7vDm76sRkj8gjvh6jQVLDLZKIU3vXWllc2jPYS3k52y8HWZd+unOOIkfcpl6GfTB X-Received: by 2002:a05:620a:801b:b0:7b1:5311:137b with SMTP id af79cd13be357-7b67c2fecd9mr897941085a.19.1732790979502; Thu, 28 Nov 2024 02:49:39 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1732790979; cv=none; d=google.com; s=arc-20240605; b=djlW+1N9tpDVc9l64InpkuBw/TyhyhnSL0jyGxgdrnArbuJWzTcllWxfMc0RpgQw2q bZ1PlE7FJVuJUJvQMtd0Xda3Ip5ezGwWbTcxAZ2oGxk8D3PyJzZc1R0QarKyNbJ5jQd3 YkmvdZz5Z4OTzRA1D2lTJf741UO6ornWZ2s4z7gLfIulCu+SQA7qcAJiMPUtso+rfosI 9uDK5+HcqVzqEaBgx5ZPQrIY2ZROMkClB0PAUMNsZhkk2HFGeVnYKPSwuOoZAkkLvbn4 0LcU/o5ImvbRQPeSGxDXESteDrwOiWtYZ1yX8kkfX0I3m7Kfgn1gAiicReV8kpndSTrT h3Zg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=hyYEZNn0XnxoTIdyelbgzeOaKzs7K1fWizjpa6l6dh0=; fh=QgE9QYJDVj//6C0QJWGeEM+qaFVaxwMel1ZWqkEy6K0=; b=Zryh+93LMkn7jI7nauTgQtrhKN4DJExu5vA/FhJNK4GzLrFCrs6mm26Uo16mnnKn2r EMs74ft/bfy4zt6QAZYDcuwiJK1g8QyJFqEQO7YTXqtSRVSKaxRyCVQr0dwhxTiS4Qwa DW2t2PCwS4cTMl+J7uC8ZKn2iWB+/Vmvem7K3GRmMRUagCM1PTwfpnef6bETWZwnQzuP 51RJqWsZhciyFlIG+HvbGvhSTmIHvQ3otqST0g3nQK07YuT2XMoiiq/j3s3bUpCZLECz 3o0NDDKNKlswc+TLA4/YabjYlf8O0rNAJY9blu3B+uGb3+aKC9rkpuTVwB3+tQxhR0bA D5Dw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=LSUEZ68b; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385ccd68958sm1292959f8f.67.2024.11.28.02.43.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Nov 2024 02:43:24 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH for-10.0 13/25] target/hppa: Set FloatInfZeroNaNRule explicitly Date: Thu, 28 Nov 2024 10:42:58 +0000 Message-Id: <20241128104310.3452934-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241128104310.3452934-1-peter.maydell@linaro.org> References: <20241128104310.3452934-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the FloatInfZeroNaNRule explicitly for the HPPA target, so we can remove the ifdef from pickNaNMulAdd(). As this is the last target to be converted to explicitly setting the rule, we can remove the fallback code in pickNaNMulAdd() entirely. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/hppa/fpu_helper.c | 2 ++ fpu/softfloat-specialize.c.inc | 13 +------------ 2 files changed, 3 insertions(+), 12 deletions(-) diff --git a/target/hppa/fpu_helper.c b/target/hppa/fpu_helper.c index 0e44074ba82..393cae33bf9 100644 --- a/target/hppa/fpu_helper.c +++ b/target/hppa/fpu_helper.c @@ -55,6 +55,8 @@ void HELPER(loaded_fr0)(CPUHPPAState *env) * HPPA does note implement a CPU reset method at all... */ set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fp_status); + /* For inf * 0 + NaN, return the input NaN */ + set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); } void cpu_hppa_loaded_fr0(CPUHPPAState *env) diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 05dec2fcb4c..3e4ec938b25 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -475,8 +475,6 @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls, static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, bool infzero, float_status *status) { - FloatInfZeroNaNRule rule = status->float_infzeronan_rule; - /* * We guarantee not to require the target to tell us how to * pick a NaN if we're always returning the default NaN. @@ -485,21 +483,12 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, */ assert(!status->default_nan_mode); - if (rule == float_infzeronan_none) { - /* - * Temporarily fall back to ifdef ladder - */ -#if defined(TARGET_HPPA) - rule = float_infzeronan_dnan_never; -#endif - } - if (infzero) { /* * Inf * 0 + NaN -- some implementations return the default NaN here, * and some return the input NaN. */ - switch (rule) { + switch (status->float_infzeronan_rule) { case float_infzeronan_dnan_never: return 2; case float_infzeronan_dnan_always: From patchwork Thu Nov 28 10:42:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 845935 Delivered-To: patch@linaro.org Received: by 2002:adf:f2c4:0:b0:382:43a8:7b94 with SMTP id d4csp159748wrp; Thu, 28 Nov 2024 02:49:29 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXrsuZDPLCUR3MZZWNuxqGadw5oFlVkJF5E1gBZIhboHCw69jqKUXB3xKF7e+8oyRE+dw78+Q==@linaro.org X-Google-Smtp-Source: AGHT+IGLf3fncVKplehIvYEa6RK5I296E+ZBzaPxjHT/SzL4kmV0wr9bbBQbfvgf4Ac6hPGTQrbr X-Received: by 2002:a05:6102:cd0:b0:4af:31bb:3743 with SMTP id ada2fe7eead31-4af4495fc13mr8177271137.15.1732790968998; Thu, 28 Nov 2024 02:49:28 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1732790968; cv=none; d=google.com; s=arc-20240605; b=E/EgKDHz9IoUI3bTxNcRXL/yyWOOs5ihIE3p2YSrmVUe9U5o2LoqaiM4ERImlg3+7D Dx68MrIw1iI3LLnD1N/8RFvUdVSZl+tpkyg/Xsfprx+XiTs3RC3vs7JPGBCxBHGFpo2m YwTqGbhyAQRvgoKA5Doypz+Gybg5aNNVwy06w2j/P0nA1USJY586gfnURv2v+sjdyKu+ iH/O29IEzWe6B96+8g+oyGZJjnItYIw/jU1uaCVInH75+U9MaUhDBmio3CU3z4KhHPQY 2Q8eIGX1TcqD0z9KlY7Z+g11/nOLvrlNXOYs1r8mYzVPVLkdvr+TDP7dHovf6ZD8SeA4 iftg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=BAfGDHXWne3fztjzcjDJwPhcKYYDiakCa5ET2Yl4WTw=; fh=QgE9QYJDVj//6C0QJWGeEM+qaFVaxwMel1ZWqkEy6K0=; b=Xqe712crzITOQToKm4IogdCkul55xprGMOQueRMhJi1RtdpunKpLGjaGupxVpPHrjb eA87EM/hvLDWdkF/+GhGwVIHVinhGDnG8ptHhEmmg4RtaIBVxpANTE5DGXu0sOLVj6ei o2Pa+GwU9GK/jF51Wj/d5K6JdGUaOKtlxXyvoUM+pYODczds1VwtDmeNv8tRfq20Wde8 mFq7Lmj329Z+bXm5SoHm8FCIrgxqfegQlVQ2Jedt+7BfiQBETCOguwRiI4TNbnMQOtrZ 1Dn27kXAWxwZXjb9q/oMOZqoHqT5MtH5X1OEBU0p4Co8U8J5o95r+nHcmG48XIVWGgqu HVEA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="VrRPoMb/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385ccd68958sm1292959f8f.67.2024.11.28.02.43.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Nov 2024 02:43:25 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH for-10.0 14/25] softfloat: Allow runtime choice of NaN propagation for muladd Date: Thu, 28 Nov 2024 10:42:59 +0000 Message-Id: <20241128104310.3452934-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241128104310.3452934-1-peter.maydell@linaro.org> References: <20241128104310.3452934-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org IEEE 758 does not define a fixed rule for which NaN to pick as the result if both operands of a 3-operand fused multiply-add operation are NaNs. As a result different architectures have ended up with different rules for propagating NaNs. QEMU currently hardcodes the NaN propagation logic into the binary because pickNaNMulAdd() has an ifdef ladder for different targets. We want to make the propagation rule instead be selectable at runtime, because: * this will let us have multiple targets in one QEMU binary * the Arm FEAT_AFP architectural feature includes letting the guest select a NaN propagation rule at runtime In this commit we add an enum for the propagation rule, the field in float_status, and the corresponding getters and setters. We change pickNaNMulAdd to honour this, but because all targets still leave this field at its default 0 value, the fallback logic will pick the rule type with the old ifdef ladder. It's valid not to set a propagation rule if default_nan_mode is enabled, because in that case there's no need to pick a NaN; all the callers of pickNaNMulAdd() catch this case and skip calling it. Signed-off-by: Peter Maydell --- include/fpu/softfloat-helpers.h | 11 +++ include/fpu/softfloat-types.h | 37 ++++++++ fpu/softfloat-specialize.c.inc | 160 +++++++++++++------------------- 3 files changed, 112 insertions(+), 96 deletions(-) diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h index 0bf44dc6087..cf06b4e16bf 100644 --- a/include/fpu/softfloat-helpers.h +++ b/include/fpu/softfloat-helpers.h @@ -81,6 +81,12 @@ static inline void set_float_2nan_prop_rule(Float2NaNPropRule rule, status->float_2nan_prop_rule = rule; } +static inline void set_float_3nan_prop_rule(Float3NaNPropRule rule, + float_status *status) +{ + status->float_3nan_prop_rule = rule; +} + static inline void set_float_infzeronan_rule(FloatInfZeroNaNRule rule, float_status *status) { @@ -143,6 +149,11 @@ static inline Float2NaNPropRule get_float_2nan_prop_rule(float_status *status) return status->float_2nan_prop_rule; } +static inline Float3NaNPropRule get_float_3nan_prop_rule(float_status *status) +{ + return status->float_3nan_prop_rule; +} + static inline FloatInfZeroNaNRule get_float_infzeronan_rule(float_status *status) { return status->float_infzeronan_rule; diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h index 27a1c96754d..79220f8c67f 100644 --- a/include/fpu/softfloat-types.h +++ b/include/fpu/softfloat-types.h @@ -207,6 +207,42 @@ typedef enum __attribute__((__packed__)) { float_2nan_prop_x87, } Float2NaNPropRule; +/* + * 3-input NaN propagation rule, for fused multiply-add. Individual + * architectures have different rules for which input NaN is + * propagated to the output when there is more than one NaN on the + * input. + * + * If default_nan_mode is enabled then it is valid not to set a NaN + * propagation rule, because the softfloat code guarantees not to try + * to pick a NaN to propagate in default NaN mode. When not in + * default-NaN mode, it is an error for the target not to set the rule + * in float_status if it uses a muladd, and we will assert if we need + * to handle an input NaN and no rule was selected. + * + * For QEMU, the multiply-add operation is A * B + C. + * + * NB: we don't list all 12 possibilities here or implement them + * in pickNaNMulAdd; if your architecture needs one of the missing + * combinations you should add it. + */ +typedef enum __attribute__((__packed__)) { + /* No propagation rule specified */ + float_3nan_prop_none = 0, + /* Prefer SNaN over QNaN, then operand A over B over C */ + float_3nan_prop_s_abc, + /* Prefer SNaN over QNaN, then operand C over A over B */ + float_3nan_prop_s_cab, + /* Prefer SNaN over QNaN, then operand C over B over A */ + float_3nan_prop_s_cba, + /* Prefer A over B over C regardless of SNaN vs QNaN */ + float_3nan_prop_abc, + /* Prefer A over C over B regardless of SNaN vs QNaN */ + float_3nan_prop_acb, + /* Prefer C over B over A regardless of SNaN vs QNaN */ + float_3nan_prop_cba, +} Float3NaNPropRule; + /* * Rule for result of fused multiply-add 0 * Inf + NaN. * This must be a NaN, but implementations differ on whether this @@ -241,6 +277,7 @@ typedef struct float_status { FloatRoundMode float_rounding_mode; FloatX80RoundPrec floatx80_rounding_precision; Float2NaNPropRule float_2nan_prop_rule; + Float3NaNPropRule float_3nan_prop_rule; FloatInfZeroNaNRule float_infzeronan_rule; bool tininess_before_rounding; /* should denormalised results go to zero and set the inexact flag? */ diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 3e4ec938b25..d7c0c90ea65 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -475,6 +475,7 @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls, static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, bool infzero, float_status *status) { + Float3NaNPropRule rule = status->float_3nan_prop_rule; /* * We guarantee not to require the target to tell us how to * pick a NaN if we're always returning the default NaN. @@ -500,27 +501,44 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, } } + if (rule == float_3nan_prop_none) { #if defined(TARGET_ARM) - - /* This looks different from the ARM ARM pseudocode, because the ARM ARM - * puts the operands to a fused mac operation (a*b)+c in the order c,a,b. - */ - if (is_snan(c_cls)) { - return 2; - } else if (is_snan(a_cls)) { - return 0; - } else if (is_snan(b_cls)) { - return 1; - } else if (is_qnan(c_cls)) { - return 2; - } else if (is_qnan(a_cls)) { - return 0; - } else { - return 1; - } + /* + * This looks different from the ARM ARM pseudocode, because the ARM ARM + * puts the operands to a fused mac operation (a*b)+c in the order c,a,b + */ + rule = float_3nan_prop_s_cab; #elif defined(TARGET_MIPS) - if (snan_bit_is_one(status)) { - /* Prefer sNaN over qNaN, in the a, b, c order. */ + if (snan_bit_is_one(status)) { + rule = float_3nan_prop_s_abc; + } else { + rule = float_3nan_prop_s_cab; + } +#elif defined(TARGET_LOONGARCH64) + rule = float_3nan_prop_s_cab; +#elif defined(TARGET_PPC) + /* + * If fRA is a NaN return it; otherwise if fRB is a NaN return it; + * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB + */ + rule = float_3nan_prop_acb; +#elif defined(TARGET_S390X) + rule = float_3nan_prop_s_abc; +#elif defined(TARGET_SPARC) + rule = float_3nan_prop_s_cba; +#elif defined(TARGET_XTENSA) + if (status->use_first_nan) { + rule = float_3nan_prop_abc; + } else { + rule = float_3nan_prop_cba; + } +#else + rule = float_3nan_prop_abc; +#endif + } + + switch (rule) { + case float_3nan_prop_s_abc: if (is_snan(a_cls)) { return 0; } else if (is_snan(b_cls)) { @@ -534,8 +552,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, } else { return 2; } - } else { - /* Prefer sNaN over qNaN, in the c, a, b order. */ + case float_3nan_prop_s_cab: if (is_snan(c_cls)) { return 2; } else if (is_snan(a_cls)) { @@ -549,68 +566,21 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, } else { return 1; } - } -#elif defined(TARGET_LOONGARCH64) - /* Prefer sNaN over qNaN, in the c, a, b order. */ - if (is_snan(c_cls)) { - return 2; - } else if (is_snan(a_cls)) { - return 0; - } else if (is_snan(b_cls)) { - return 1; - } else if (is_qnan(c_cls)) { - return 2; - } else if (is_qnan(a_cls)) { - return 0; - } else { - return 1; - } -#elif defined(TARGET_PPC) - /* If fRA is a NaN return it; otherwise if fRB is a NaN return it; - * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB - */ - if (is_nan(a_cls)) { - return 0; - } else if (is_nan(c_cls)) { - return 2; - } else { - return 1; - } -#elif defined(TARGET_S390X) - if (is_snan(a_cls)) { - return 0; - } else if (is_snan(b_cls)) { - return 1; - } else if (is_snan(c_cls)) { - return 2; - } else if (is_qnan(a_cls)) { - return 0; - } else if (is_qnan(b_cls)) { - return 1; - } else { - return 2; - } -#elif defined(TARGET_SPARC) - /* Prefer SNaN over QNaN, order C, B, A. */ - if (is_snan(c_cls)) { - return 2; - } else if (is_snan(b_cls)) { - return 1; - } else if (is_snan(a_cls)) { - return 0; - } else if (is_qnan(c_cls)) { - return 2; - } else if (is_qnan(b_cls)) { - return 1; - } else { - return 0; - } -#elif defined(TARGET_XTENSA) - /* - * For Xtensa, the (inf,zero,nan) case sets InvalidOp and returns - * an input NaN if we have one (ie c). - */ - if (status->use_first_nan) { + case float_3nan_prop_s_cba: + if (is_snan(c_cls)) { + return 2; + } else if (is_snan(b_cls)) { + return 1; + } else if (is_snan(a_cls)) { + return 0; + } else if (is_qnan(c_cls)) { + return 2; + } else if (is_qnan(b_cls)) { + return 1; + } else { + return 0; + } + case float_3nan_prop_abc: if (is_nan(a_cls)) { return 0; } else if (is_nan(b_cls)) { @@ -618,7 +588,15 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, } else { return 2; } - } else { + case float_3nan_prop_acb: + if (is_nan(a_cls)) { + return 0; + } else if (is_nan(c_cls)) { + return 2; + } else { + return 1; + } + case float_3nan_prop_cba: if (is_nan(c_cls)) { return 2; } else if (is_nan(b_cls)) { @@ -626,19 +604,9 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, } else { return 0; } + default: + g_assert_not_reached(); } -#else - /* A default implementation: prefer a to b to c. - * This is unlikely to actually match any real implementation. - */ - if (is_nan(a_cls)) { - return 0; - } else if (is_nan(b_cls)) { - return 1; - } else { - return 2; - } -#endif } /*---------------------------------------------------------------------------- From patchwork Thu Nov 28 10:43:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 845934 Delivered-To: patch@linaro.org Received: by 2002:adf:f2c4:0:b0:382:43a8:7b94 with SMTP id d4csp159740wrp; Thu, 28 Nov 2024 02:49:28 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVmx2cGMYSTMaGXRg3j0AwXF6aaV+yddO8bggEyJTYP465tbfwD2FunVzJggmRdaqqSE53L9w==@linaro.org X-Google-Smtp-Source: AGHT+IH6z+Vqccl9dzNrsGZbg1y9idIbU7o8qFTOhVFSpGpkPN+1VrFRqR8VT6dscZvZPXkmhD1B X-Received: by 2002:a05:620a:801b:b0:7af:c3f4:ee45 with SMTP id af79cd13be357-7b67c4a1480mr1015002085a.55.1732790967776; Thu, 28 Nov 2024 02:49:27 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1732790967; cv=none; d=google.com; s=arc-20240605; b=AHCHT49dk0GIHOjNYUpmH9NCH9k30M8tIZXdYE+TMxeoXjDncSLUf81eHKPxqWUqi+ U7KlxqBKF3oiLWoDnF4zEfxfEHKRQUdvyoLT/BhXSgSqVjNjuskpBQSkT8u8J3W2421d d+DJXw3q/V0zLnQuzF/pmpGorXOn/2kh/NuDDScl3CjmZtAx1UoYFig2IPXSI2jZjH5s Zlpx+8tp0XOzMVP3UcIJLXQngN2b2u4v3IdiVNZ55dWIzFAphNUoyH7EVD7vv6koz+L1 1bdlkJ/DLmHUXcb1f/rZZMi38yzZBV/5IwmlOL8Zhekwy/Z1cgFSn2Tam27AIy95smGP Uo7w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=QSKy4hpjmDanw2YkU8Msj9vNT9iFFxMr9XhYnZJtyOY=; fh=QgE9QYJDVj//6C0QJWGeEM+qaFVaxwMel1ZWqkEy6K0=; b=NjsnvHaNLtrbvp3YZOPOZRTfnEmDPRAVJXoxQxG7SagJ8/I+N9x4CM6QmvLUgZ3AZs VebApkYChoUdxAM7Gx9imFThbJO++AC4uYXdqjw650/MTu6vVHfuKcBzPnxFM8/9NW9b 1Aq9ylCPMaP3OVq1UaJ3POzderDrUJJ7sG6aLGFzEAbcu/307j977+UkIJAdkQGfNVLe Hf2LyqvuolaMH/HkrtnVZcJPkwdgWvUPZH4Q/mKmdczShXSBfDTkX/suXWkRedEOYLuD r2Uf/ovwzZcz7IZz3CuR2CZKAQycsIAEA02G27HSs/geewhD7bW0ScXFiucx4KtUJetL 6pRQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=pJVqARvB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385ccd68958sm1292959f8f.67.2024.11.28.02.43.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Nov 2024 02:43:26 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH for-10.0 15/25] tests/fp: Explicitly set 3-NaN propagation rule Date: Thu, 28 Nov 2024 10:43:00 +0000 Message-Id: <20241128104310.3452934-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241128104310.3452934-1-peter.maydell@linaro.org> References: <20241128104310.3452934-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Explicitly set a rule in the softfloat tests for propagating NaNs in the muladd case. In meson.build we put -DTARGET_ARM in fpcflags, and so we should select here the Arm rule of float_3nan_prop_s_cab. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- tests/fp/fp-bench.c | 1 + tests/fp/fp-test.c | 1 + 2 files changed, 2 insertions(+) diff --git a/tests/fp/fp-bench.c b/tests/fp/fp-bench.c index fde64836194..39d80c9038f 100644 --- a/tests/fp/fp-bench.c +++ b/tests/fp/fp-bench.c @@ -493,6 +493,7 @@ static void run_bench(void) * doesn't specify match those used by the Arm architecture. */ set_float_2nan_prop_rule(float_2nan_prop_s_ab, &soft_status); + set_float_3nan_prop_rule(float_3nan_prop_s_cab, &soft_status); set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &soft_status); f = bench_funcs[operation][precision]; diff --git a/tests/fp/fp-test.c b/tests/fp/fp-test.c index 251c278ede9..f290d523ab1 100644 --- a/tests/fp/fp-test.c +++ b/tests/fp/fp-test.c @@ -940,6 +940,7 @@ void run_test(void) * doesn't specify match those used by the Arm architecture. */ set_float_2nan_prop_rule(float_2nan_prop_s_ab, &qsf); + set_float_3nan_prop_rule(float_3nan_prop_s_cab, &qsf); set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &qsf); genCases_setLevel(test_level); From patchwork Thu Nov 28 10:43:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 845928 Delivered-To: patch@linaro.org Received: by 2002:adf:f2c4:0:b0:382:43a8:7b94 with SMTP id d4csp159587wrp; Thu, 28 Nov 2024 02:48:58 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWsi8i1Z0rptHCiLKHeQx5Zvv2Ns8l7BzGlrfJMaFdsgAu9bSuZdnNGihtvGzqf5JCdC/YkrQ==@linaro.org X-Google-Smtp-Source: AGHT+IHKRHVewFRn0A2soGHQXhw2HAVl+rKgcK91HjwbatmKEBxQSiwoLpXFOrIP4yHf6wkENb1N X-Received: by 2002:a05:622a:180e:b0:466:94f7:4b4f with SMTP id d75a77b69052e-466b351f7f9mr98570991cf.19.1732790937796; Thu, 28 Nov 2024 02:48:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1732790937; cv=none; d=google.com; s=arc-20240605; b=ZI0oczAe3AVXa6Se+k2fwEc/bQfzKIQsGNJwZOUEDoClMw44kVU2bZNzNVxUQf4YZ4 GQb1CuLukDI3ncmArXdd34m947E0fxJLA2FXKoLgtBpS3p9fpJIaA1FbZeNVBkbHcwbv d9Fe4SiyPGf+uHLobSI+nc0Xdppaji1kr7zHQx4mE5Eynamu7XBNCAspd9LlLhn14tX2 O8l4LJfP24q21jKNKuir82FFEJIeFSOTnQg2UZ+tQKZPDGKS01IqCuojKP1Th3P3G/zy iBEsJYm3LjaIlr59T2snJ3lBuFfjIfS4Tvp5W2ih2pvQTiHOGGa7IScQgxcpBIchcSV6 9gvw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=bWS/GNsFs6Pu4pBOarLJaqHWrc7CmHsdY5ILX0uFeec=; fh=QgE9QYJDVj//6C0QJWGeEM+qaFVaxwMel1ZWqkEy6K0=; b=V3pyuOQbp5OTY05+VXxYmCpfdNE+tKx7cxPXehNnEvQphK0e6QoJ0jUDclfEhgLW// QgRCc5BxmgVK/Ban8MXqH6dQ6xYnHfydadxlQ2pFmCGodxfFSLS2yOA7hSzyPpAcKX4n idYhVtgczBgPfhZXrgmgDWYepPj6ozWQ9Olfs626OpPlSZmQNB24q6fcqtyM6qZGy6gX lUahDa4MkZFc0mkATY7BhmuvwczWAy1Na2IvG9laeXGHYA87JuWdhDp+U7wXUUsZGwQj 6CRBrtjj1eMa72PK185gAz+N2Lp1wSceUcrceLSZL5gZzEPaKhdhUdAkZQp/pZm5eFOP ZRdw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=qSlcYqId; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385ccd68958sm1292959f8f.67.2024.11.28.02.43.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Nov 2024 02:43:26 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH for-10.0 16/25] target/arm: Set Float3NaNPropRule explicitly Date: Thu, 28 Nov 2024 10:43:01 +0000 Message-Id: <20241128104310.3452934-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241128104310.3452934-1-peter.maydell@linaro.org> References: <20241128104310.3452934-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the Float3NaNPropRule explicitly for Arm, and remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.c | 5 +++++ fpu/softfloat-specialize.c.inc | 8 +------- 2 files changed, 6 insertions(+), 7 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index ead39793985..c81f6df3fca 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -173,6 +173,10 @@ void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, * * tininess-before-rounding * * 2-input NaN propagation prefers SNaN over QNaN, and then * operand A over operand B (see FPProcessNaNs() pseudocode) + * * 3-input NaN propagation prefers SNaN over QNaN, and then + * operand C over A over B (see FPProcessNaNs3() pseudocode, + * but note that for QEMU muladd is a * b + c, whereas for + * the pseudocode function the arguments are in the order c, a, b. * * 0 * Inf + NaN returns the default NaN if the input NaN is quiet, * and the input NaN if it is signalling */ @@ -180,6 +184,7 @@ static void arm_set_default_fp_behaviours(float_status *s) { set_float_detect_tininess(float_tininess_before_rounding, s); set_float_2nan_prop_rule(float_2nan_prop_s_ab, s); + set_float_3nan_prop_rule(float_3nan_prop_s_cab, s); set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, s); } diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index d7c0c90ea65..9b5243c9529 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -502,13 +502,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, } if (rule == float_3nan_prop_none) { -#if defined(TARGET_ARM) - /* - * This looks different from the ARM ARM pseudocode, because the ARM ARM - * puts the operands to a fused mac operation (a*b)+c in the order c,a,b - */ - rule = float_3nan_prop_s_cab; -#elif defined(TARGET_MIPS) +#if defined(TARGET_MIPS) if (snan_bit_is_one(status)) { rule = float_3nan_prop_s_abc; } else { From patchwork Thu Nov 28 10:43:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 845931 Delivered-To: patch@linaro.org Received: by 2002:adf:f2c4:0:b0:382:43a8:7b94 with SMTP id d4csp159708wrp; Thu, 28 Nov 2024 02:49:20 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXGyu3TTmUtRi1vQxVySv/4dcpCYmrZCL6YtmC19ZIyznPFKLm71Dj9WhyMmhgbk1kzICGkWA==@linaro.org X-Google-Smtp-Source: AGHT+IExDyOQV2xT5i8rlbn2fBzQxdKXeBRr7iCcys9/uaPvPgU/t47qiNFkrY4YTdmL9W+PvB1d X-Received: by 2002:a05:620a:1a93:b0:7b1:8e09:513a with SMTP id af79cd13be357-7b67c46602fmr959195685a.49.1732790960569; Thu, 28 Nov 2024 02:49:20 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1732790960; cv=none; d=google.com; s=arc-20240605; b=gcwG3i1OJY+5npPgjBJUehcUbUKov49hHuZ6r3K2L8wwi/PB0a1igRmwlz03TtDuPY /RTrGgUekzMbbFWNifHyAp6tnGYL4Tmk6wozkW5GKT2iQMx4jtKeusGCgQnwSWRP/ejM jnTpc7WLrGKvKCnoZOmZTU2itUFE0gUlKdVUCdCvS5dVKEEV6aVd0hLgx18bgHdKr/4B YN51J7Yh/2wTZjbGQytBciiJebQmeh9jQIsmsZEebZu3cdeyWcCGgXcqAMnj3PpOSp/l VLrnQbJzoG1IPLlBm7p82PE3ieC8nU8htkCVuhC5GxKEWvbASF3aysHBT3tVDKNefR48 9Dkw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=x4JtTEJWuqktTR0K+Db+JfgEPXYfhnr/W1wwAJOuIfc=; fh=QgE9QYJDVj//6C0QJWGeEM+qaFVaxwMel1ZWqkEy6K0=; b=BBH3C745j/tAvjlwW3bl/sdRoSViDquNwCvBYAOMRdxxp+BoBq7u0hk2jgpDh/reN4 fevvR+k4VzpawRQzyFcZghMB9HHVwiuJ7ESANy2/tciDD/Qe7qgzz8dFWeOcMaIPKswW kQ4qoGqVwGHzV+px5TA9Fbm0NzcSeWR8XWfaDBDKENs3UmL0wRu3vDxY59akclkHr/8e R8syfIAVp/FbjdRdMdZqYTqrgPxdYQ7tWLzBlvKOqaAkSVplFLAwwkGiw1iJMLvQpqLC nAKpDO1+nxIAkVowYtt73yzqghLTC1doumeOjhDobLyWieNlcdHrvW5K56HRLIclobh2 wQDg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vTrQdMwM; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385ccd68958sm1292959f8f.67.2024.11.28.02.43.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Nov 2024 02:43:27 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH for-10.0 17/25] target/loongarch: Set Float3NaNPropRule explicitly Date: Thu, 28 Nov 2024 10:43:02 +0000 Message-Id: <20241128104310.3452934-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241128104310.3452934-1-peter.maydell@linaro.org> References: <20241128104310.3452934-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::12d; envelope-from=peter.maydell@linaro.org; helo=mail-lf1-x12d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the Float3NaNPropRule explicitly for loongarch, and remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/loongarch/tcg/fpu_helper.c | 1 + fpu/softfloat-specialize.c.inc | 2 -- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c index 6a2c4b5b1db..37a48599366 100644 --- a/target/loongarch/tcg/fpu_helper.c +++ b/target/loongarch/tcg/fpu_helper.c @@ -37,6 +37,7 @@ void restore_fp_status(CPULoongArchState *env) * case sets InvalidOp and returns the input value 'c' */ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); + set_float_3nan_prop_rule(float_3nan_prop_s_cab, &env->fp_status); } int ieee_ex_to_loongarch(int xcpt) diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 9b5243c9529..32edb493776 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -508,8 +508,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, } else { rule = float_3nan_prop_s_cab; } -#elif defined(TARGET_LOONGARCH64) - rule = float_3nan_prop_s_cab; #elif defined(TARGET_PPC) /* * If fRA is a NaN return it; otherwise if fRB is a NaN return it; From patchwork Thu Nov 28 10:43:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 845943 Delivered-To: patch@linaro.org Received: by 2002:adf:f2c4:0:b0:382:43a8:7b94 with SMTP id d4csp160311wrp; Thu, 28 Nov 2024 02:51:12 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCUvNMWUcdwlfMtO6YXtV+4gqxEowlPrFnVWF40QJPttIe/mGIQn1g8vnPVppdxPGOtt6beOqg==@linaro.org X-Google-Smtp-Source: AGHT+IFjI1DcRjP73V7pgWV4knelE8sZ3uvIOuFmUq6JqQWRlJjF5cLLZb7YMAUWwIhpz5Xp5dE0 X-Received: by 2002:a05:622a:1985:b0:466:a254:7341 with SMTP id d75a77b69052e-466b3510a34mr102493051cf.17.1732791072632; Thu, 28 Nov 2024 02:51:12 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1732791072; cv=none; d=google.com; s=arc-20240605; b=Vvs33o3wQ50NufrKWQbzJQOtRsjEXJSBu+9/sBye9I6sDKEdqS7IXgaZAs7ZHY9nzi IX00lG9pPKL3Av6Uuk+8i2GNgCSBYVjMClDCBsEFLJ0HHDkRpocsaYS7eWAIU07HQcte IiFuFGNok993qgGTnx/N3KxTOreU2ZXNls/Z2Y/ykGuKoy6rxqxbCHUZqqUcgqsv8lA5 cOxPFl+0+HEPzS0DuAbaXPS/tZ8x8vbuNQ/liTCk3hHO42fwQhRT/Bu9KxmEVNB051QK Jl1A/K8I6hP7K6p50HS34hwU2cj5z6H95mF0YMWrd5qygC3aJNfnztR2n+CWHaJXTJtU GUZQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=xHFYmwmnqcmAvgEMbarhecchly8CdIQ7oYTdDVFhVcI=; fh=QgE9QYJDVj//6C0QJWGeEM+qaFVaxwMel1ZWqkEy6K0=; b=F/bZPqjWx2cWfNCfegX52vAS56LWecRfsM/ONMcRqx54t+f6pU6MAjEcsXLWZfwQmN Rr5/00ekeWA7WuwagbU78dbsPjcxw0WOqb8KTLiGu4nx8+v/UUqPnU+DURq2wRQCPo8E tqRpkUNny1F2FQnyr+5XFS2umCIkwxe/JmUPkMUf0T9O7f7ENHH7i7eeFJsxxf1oYnbZ KNUiV7qnpoz6ugjqBEsjQukzg7gxUdlsoczffoGwc9XFPDas60Xkapbq9gWxXr9HicFM wnfyuKQqKS4nMyXH4mDjhThZ6q6ES96+/4gzXnetbe0Tuo8lekyKJk8KyG0ccejdLdQN GUWg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=YbXEve57; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385ccd68958sm1292959f8f.67.2024.11.28.02.43.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Nov 2024 02:43:28 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH for-10.0 18/25] target/ppc: Set Float3NaNPropRule explicitly Date: Thu, 28 Nov 2024 10:43:03 +0000 Message-Id: <20241128104310.3452934-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241128104310.3452934-1-peter.maydell@linaro.org> References: <20241128104310.3452934-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the Float3NaNPropRule explicitly for PPC, and remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/ppc/cpu_init.c | 8 ++++++++ fpu/softfloat-specialize.c.inc | 6 ------ 2 files changed, 8 insertions(+), 6 deletions(-) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index f18908a643a..eb9d7b13701 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7270,6 +7270,14 @@ static void ppc_cpu_reset_hold(Object *obj, ResetType type) */ set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status); set_float_2nan_prop_rule(float_2nan_prop_ab, &env->vec_status); + /* + * NaN propagation for fused multiply-add: + * if fRA is a NaN return it; otherwise if fRB is a NaN return it; + * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB + * whereas QEMU labels the operands as (a * b) + c. + */ + set_float_3nan_prop_rule(float_3nan_prop_acb, &env->fp_status); + set_float_3nan_prop_rule(float_3nan_prop_acb, &env->vec_status); /* * For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer * to return an input NaN if we have one (ie c) rather than generating diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 32edb493776..d89ef62b38a 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -508,12 +508,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, } else { rule = float_3nan_prop_s_cab; } -#elif defined(TARGET_PPC) - /* - * If fRA is a NaN return it; otherwise if fRB is a NaN return it; - * otherwise return fRC. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385ccd68958sm1292959f8f.67.2024.11.28.02.43.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Nov 2024 02:43:32 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH for-10.0 19/25] target/s390x: Set Float3NaNPropRule explicitly Date: Thu, 28 Nov 2024 10:43:04 +0000 Message-Id: <20241128104310.3452934-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241128104310.3452934-1-peter.maydell@linaro.org> References: <20241128104310.3452934-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the Float3NaNPropRule explicitly for s390x, and remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/s390x/cpu.c | 1 + fpu/softfloat-specialize.c.inc | 2 -- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index d5941b5b9df..e74055bad79 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -206,6 +206,7 @@ static void s390_cpu_reset_hold(Object *obj, ResetType type) set_float_detect_tininess(float_tininess_before_rounding, &env->fpu_status); set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fpu_status); + set_float_3nan_prop_rule(float_3nan_prop_s_abc, &env->fpu_status); set_float_infzeronan_rule(float_infzeronan_dnan_always, &env->fpu_status); /* fall through */ diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index d89ef62b38a..31b23ddb9bb 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -508,8 +508,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, } else { rule = float_3nan_prop_s_cab; } -#elif defined(TARGET_S390X) - rule = float_3nan_prop_s_abc; #elif defined(TARGET_SPARC) rule = float_3nan_prop_s_cba; #elif defined(TARGET_XTENSA) From patchwork Thu Nov 28 10:43:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 845939 Delivered-To: patch@linaro.org Received: by 2002:adf:f2c4:0:b0:382:43a8:7b94 with SMTP id d4csp159819wrp; Thu, 28 Nov 2024 02:49:40 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCUosGDc+x2NW5bAyYx4MJ6lJR7LnicyVa/scV3MHhgVGLPc3WEWEocNeR8CB/f5z1DuwvPAIg==@linaro.org X-Google-Smtp-Source: AGHT+IEHz2g9uthHLL7Zz714XVGUYhfnYp5pJURkXzwaCosuYXrxuwSo0/IidNxAREmJbmMRk9sD X-Received: by 2002:a05:6102:161e:b0:4af:5cd4:b081 with SMTP id ada2fe7eead31-4af5cd4b2d5mr1034214137.23.1732790979861; Thu, 28 Nov 2024 02:49:39 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1732790979; cv=none; d=google.com; s=arc-20240605; b=W+SOYxT+KlxryjkGU2XZXoib5RwuQCRRp/p07AiG3ImQyvzrrW41MdvSF+IbmpeLIZ hma5RJI/1hS0pmnlLMEBGF4fD6cGNl37L6Iop/eyC+vhLaaZMFfs+WOWS0fk7fLmTks1 ngYItbmENXvgPcsh6tN+HOYBC1wnOA71qpwgWKzcDH0oqZetB5Ub1EAwDkSdRHcgLDlk tqddFgaGsDLOY9bwpfSwfzZ/VPOmxmyZHvmnuVhh7CXoqDe9ZVxYAJwmJTpRULsjKBC4 GJEXYAYPAgEY3G0G3RBSKXhtjSvWFrigmHFBszJ3y8XcPwqWaPbPNzMg0dsuVWA1RSxr Fwow== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=M59b1YXia+t10MRDfuwOiG0kBN1H5nWvD2y8aDo+yb4=; fh=QgE9QYJDVj//6C0QJWGeEM+qaFVaxwMel1ZWqkEy6K0=; b=geU9NgfrWw+tadqsDMWBXI+qn4cK0SvSzrKGywPSRZNZLB3CmPolL7DVe9sZd11j7w C9+y3kYRtx9UObg7geYBMvEOkVI3FerXYXvObmIgSm03jj6Vx5ew8tegORcz4XFkP7ER cWBknRjsILvBusS9hTQiqKcT2NgBnCTeQVBs7F1H/h05zEsi4kH9o7FnaJ6qyYaBWTwx E5i7Uob5pxkHXrOWuI0drFKzWfBVY2+N4/pHdxbUR1+xoaBRFrdkOMOsK268olZ34W+f ob9FmjT2QiVy+STI0TJ/eK10EjXUxvxlbTwxzxdnFVUfyY6yBSl6Kg+uz++IIy4BehFC sQ8g==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=LRsfQH2q; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385ccd68958sm1292959f8f.67.2024.11.28.02.43.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Nov 2024 02:43:33 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH for-10.0 20/25] target/sparc: Set Float3NaNPropRule explicitly Date: Thu, 28 Nov 2024 10:43:05 +0000 Message-Id: <20241128104310.3452934-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241128104310.3452934-1-peter.maydell@linaro.org> References: <20241128104310.3452934-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the Float3NaNPropRule explicitly for SPARC, and remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/sparc/cpu.c | 2 ++ fpu/softfloat-specialize.c.inc | 2 -- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 61f2d3fbf23..0f2997a85e6 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -814,6 +814,8 @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp) * the CPU state struct so it won't get zeroed on reset. */ set_float_2nan_prop_rule(float_2nan_prop_s_ba, &env->fp_status); + /* For fused-multiply add, prefer SNaN over QNaN, then C->B->A */ + set_float_3nan_prop_rule(float_3nan_prop_s_cba, &env->fp_status); /* For inf * 0 + NaN, return the input NaN */ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 31b23ddb9bb..565790b1834 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -508,8 +508,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, } else { rule = float_3nan_prop_s_cab; } -#elif defined(TARGET_SPARC) - rule = float_3nan_prop_s_cba; #elif defined(TARGET_XTENSA) if (status->use_first_nan) { rule = float_3nan_prop_abc; From patchwork Thu Nov 28 10:43:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 845923 Delivered-To: patch@linaro.org Received: by 2002:adf:f2c4:0:b0:382:43a8:7b94 with SMTP id d4csp158428wrp; Thu, 28 Nov 2024 02:45:23 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVhcKlz/O+VCCBxkKr3umFydz7caCRUDfQrkgcnHMbk9CuXFjGqm5e598ZYppZ1a1DpB56EOg==@linaro.org X-Google-Smtp-Source: AGHT+IHamcD4OEGy80ul7MdRiqGmqxjOUNNbNJc9zeU/OkAZ0vbw170hoe9erathOk8woc2TpLkY X-Received: by 2002:ac8:7c52:0:b0:466:9360:4933 with SMTP id d75a77b69052e-466c1c0ea6cmr45295851cf.27.1732790723289; Thu, 28 Nov 2024 02:45:23 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1732790723; cv=none; d=google.com; s=arc-20240605; b=eJg7riEl7wKO+KIREchVfzddsQTfi4C1ehHnCrzo5BH1kwOsyMCjomsKcnu+x+UgW3 u5wjCMPPY7Ysv+YNPE2LuR4AwXsQe55J9KsGIFUnkx1I156OC2IVhMPEA7c4ZUCyblFN HgdI3Xn31ckFVyoVkL3yEjj45T6gjzTvifkAcMXuffZkT99TGp5RRbhFCkVcWCg/V+x/ mEofLdwGAb99jkAyIGL4VlcHUTLjZJisd0glP6Yvo+7JlDXr1rEqa5F5FkniFznC3O2F eTpECTqhTcA/5noObzVCytUTR14qJezGBJgmI40yN3H5TDKreJQjEcaKHiOfPVO9Uvad BvsQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=2TrVJRkkr5D+N0aBUkmYJt1MSRdpl5FRuyVmIZ66utw=; fh=QgE9QYJDVj//6C0QJWGeEM+qaFVaxwMel1ZWqkEy6K0=; b=ONbLJW4aWkoY7NCRbwyHo3Vj2XRcpg1T4uBZ1SNo7eWWBRDS9v8WeyJ3mv2pIXJF+7 4SpJDFkKp+5wIJpKnPOv6rexRdkCIV52Fc2gKP1IcQQMrdKjy9KzEPrrgBBqtoA5tbAw hJZb06jMi2kVh4RCFy56C/sVuKRMrUScVKUYmrmt75YFjyZpPFWJriqH3wBeTm+TwQt0 gdfQ9f4/MT/bmwZiTjkyP1m8smFQThSJOkJGh6v4YpwENaRUVsHQxxCu611vukE2A5BF 6NIG2qoJ0WDumbQui5d9o4kFwkz4U9dhWgI/KHjLiw8Ujvvg2WrcnHcJf6tW+2jEcBJX jbow==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="aFqv7/Qc"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385ccd68958sm1292959f8f.67.2024.11.28.02.43.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Nov 2024 02:43:34 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH for-10.0 21/25] target/mips: Set Float3NaNPropRule explicitly Date: Thu, 28 Nov 2024 10:43:06 +0000 Message-Id: <20241128104310.3452934-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241128104310.3452934-1-peter.maydell@linaro.org> References: <20241128104310.3452934-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the Float3NaNPropRule explicitly for Arm, and remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/mips/fpu_helper.h | 4 ++++ target/mips/msa.c | 3 +++ fpu/softfloat-specialize.c.inc | 8 +------- 3 files changed, 8 insertions(+), 7 deletions(-) diff --git a/target/mips/fpu_helper.h b/target/mips/fpu_helper.h index be66f2f813a..8ca0ca7ea39 100644 --- a/target/mips/fpu_helper.h +++ b/target/mips/fpu_helper.h @@ -29,6 +29,7 @@ static inline void restore_snan_bit_mode(CPUMIPSState *env) { bool nan2008 = env->active_fpu.fcr31 & (1 << FCR31_NAN2008); FloatInfZeroNaNRule izn_rule; + Float3NaNPropRule nan3_rule; /* * With nan2008, SNaNs are silenced in the usual way. @@ -44,6 +45,9 @@ static inline void restore_snan_bit_mode(CPUMIPSState *env) */ izn_rule = nan2008 ? float_infzeronan_dnan_never : float_infzeronan_dnan_always; set_float_infzeronan_rule(izn_rule, &env->active_fpu.fp_status); + nan3_rule = nan2008 ? float_3nan_prop_s_cab : float_3nan_prop_s_abc; + set_float_3nan_prop_rule(nan3_rule, &env->active_fpu.fp_status); + } static inline void restore_fp_status(CPUMIPSState *env) diff --git a/target/mips/msa.c b/target/mips/msa.c index cc152db27f9..93a9a87d76d 100644 --- a/target/mips/msa.c +++ b/target/mips/msa.c @@ -66,6 +66,9 @@ void msa_reset(CPUMIPSState *env) set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->active_tc.msa_fp_status); + set_float_3nan_prop_rule(float_3nan_prop_s_cab, + &env->active_tc.msa_fp_status); + /* clear float_status exception flags */ set_float_exception_flags(0, &env->active_tc.msa_fp_status); diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 565790b1834..2d029de7baa 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -502,13 +502,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, } if (rule == float_3nan_prop_none) { -#if defined(TARGET_MIPS) - if (snan_bit_is_one(status)) { - rule = float_3nan_prop_s_abc; - } else { - rule = float_3nan_prop_s_cab; - } -#elif defined(TARGET_XTENSA) +#if defined(TARGET_XTENSA) if (status->use_first_nan) { rule = float_3nan_prop_abc; } else { From patchwork Thu Nov 28 10:43:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 845927 Delivered-To: patch@linaro.org Received: by 2002:adf:f2c4:0:b0:382:43a8:7b94 with SMTP id d4csp159203wrp; Thu, 28 Nov 2024 02:47:43 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWQ6EKS7kM48mVGAmBRpl4KctRmXymfEh7P+AIvuNr16pg7MYY9F5EAYlkkOEF0n0QRSG2Kog==@linaro.org X-Google-Smtp-Source: AGHT+IHBUwxSjucfC+5m8QbbNKvwBsSlueElTKAp6Te8m4FSaB0PbzHFmxXihZDrVwb3q24uDC50 X-Received: by 2002:ad4:5fc6:0:b0:6d4:f77:613c with SMTP id 6a1803df08f44-6d864d5b11amr101130016d6.25.1732790863013; Thu, 28 Nov 2024 02:47:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1732790862; cv=none; d=google.com; s=arc-20240605; b=IkBoxHn+f86sJ+d96qjPJamVmGoB/cXtFuCWoX16QwLmfSZey7UA1b3WDG8njFewyk IvqA6JqvxmyoDZ6XaMZu0L9EefnxiNCPb3Ld45ZPNXnkc4yyBzCn6ZG2aAx6qUUEEdzE hRAGsBUWK1LIW/niWeXYgV5DWNdtWiz+/5esycFsisJemLYw+Q2e6stlpFEbSqK9dSrK tHE0+2EfT4XY2EYq8rW0NCab7DgdcqSVvNaayTMajVAQdA9b6KDdednRWgyPpDVABc0D 43/gS3lbvQQBRHDJylqX0YiYY6gUY45DxB+psq2cQ3sfxWX9A8kpUAnq3uGTRve9aow8 Fhsg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=F2oqqTya9ndnAhX2EgcTjocy//tVGNyIvLMPGaZkvBQ=; fh=QgE9QYJDVj//6C0QJWGeEM+qaFVaxwMel1ZWqkEy6K0=; b=X6BzYi47jngQD0IL2UrS8lS0uyWbURBS4uBWkePOIDaJsLr6YaEsbRoLJoajJRTMdH TMZVVcQlrQlxBIGiH34M8bWIuuoilqxxHBpEvwGhGaeHQ/zveM8M530xqMa5pfTien6S 2rWc6XCrZQFRNkIsawaHKYig8fkjsjBu/uEA3XDj61+aGMrWICyQOoSEbU0TGACNYR5j OZYUBw+WuMnTmrBF7AxjdCetyuHyIut0l0wDnkkIRWFGQixy/pHt5utXYNIjnecN8s0K uDypLIFoJxwtOS8e8Dn+fji90k5jx6WH/EWnJevvCI2g0IrhmLoStpPv6VCF6kMW7qgI tS2g==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Jvat3IMy; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385ccd68958sm1292959f8f.67.2024.11.28.02.43.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Nov 2024 02:43:34 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH for-10.0 22/25] target/xtensa: Set Float3NaNPropRule explicitly Date: Thu, 28 Nov 2024 10:43:07 +0000 Message-Id: <20241128104310.3452934-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241128104310.3452934-1-peter.maydell@linaro.org> References: <20241128104310.3452934-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the Float3NaNPropRule explicitly for xtensa, and remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/xtensa/fpu_helper.c | 2 ++ fpu/softfloat-specialize.c.inc | 8 -------- 2 files changed, 2 insertions(+), 8 deletions(-) diff --git a/target/xtensa/fpu_helper.c b/target/xtensa/fpu_helper.c index f2d212d05df..4b1b021d824 100644 --- a/target/xtensa/fpu_helper.c +++ b/target/xtensa/fpu_helper.c @@ -62,6 +62,8 @@ void xtensa_use_first_nan(CPUXtensaState *env, bool use_first) set_use_first_nan(use_first, &env->fp_status); set_float_2nan_prop_rule(use_first ? float_2nan_prop_ab : float_2nan_prop_ba, &env->fp_status); + set_float_3nan_prop_rule(use_first ? float_3nan_prop_abc : float_3nan_prop_cba, + &env->fp_status); } void HELPER(wur_fpu2k_fcr)(CPUXtensaState *env, uint32_t v) diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 2d029de7baa..60de68012e1 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -502,15 +502,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, } if (rule == float_3nan_prop_none) { -#if defined(TARGET_XTENSA) - if (status->use_first_nan) { - rule = float_3nan_prop_abc; - } else { - rule = float_3nan_prop_cba; - } -#else rule = float_3nan_prop_abc; -#endif } switch (rule) { From patchwork Thu Nov 28 10:43:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 845936 Delivered-To: patch@linaro.org Received: by 2002:adf:f2c4:0:b0:382:43a8:7b94 with SMTP id d4csp159751wrp; Thu, 28 Nov 2024 02:49:29 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWo8Lo0Tff34n+5SUt7IfCD8l25KY9EhID4bDq3KAAMZotrSpPrkdnfrPKN+4k+94wqROWukA==@linaro.org X-Google-Smtp-Source: AGHT+IGwyph5bbb8hLZwYOScmf+GGD4XF2ehKo3vm2V7BmitRAhnCGtBPSwfpuPtZs9osAd3oHZy X-Received: by 2002:a05:6214:2023:b0:6d3:b5d4:1fbb with SMTP id 6a1803df08f44-6d864d0712cmr89652126d6.1.1732790969233; Thu, 28 Nov 2024 02:49:29 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1732790969; cv=none; d=google.com; s=arc-20240605; b=cYdI6Kb5Zfu1RDKbk3C02DlBvd/PdsjA0Ns3c/MG24L5SxKM3fdcH+PVSSsH80Sj9B NhBk4v/3Jm++ndtMt7PJfRv9931SiYvLCnZTeToVp6YTqIrP+4S7tYB/7YBJOVA3UqY6 aa5Kw6Z6lATlgiwO4quidUbNOb37fIMR2SNcqTIBWFKW84uZgn5h5qlQsLd4YFJQerdY qvhu2gQ2Gku0regVftFh9uGiI12MF218zMT9epnx+p9YNDqRwDkYrAh1Oz7GHTGBC93j A4t5qErylXbAnzKQIWIikiKvtRRhY5XSCfIRGO2As4LL/TISnZqzqJf3dqqjtABgO6fV n/Aw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=eT1LXyat6VBXQfbf2ZEeygMBWdK2hSiibfIDvIYaJow=; fh=QgE9QYJDVj//6C0QJWGeEM+qaFVaxwMel1ZWqkEy6K0=; b=CEYeh6GQEFwIaPF3mEJ6ceqoeT7y0bMyn1oEpvlEJtG05gjvnI6f1IkvnnB60OEvNt cZR/1gCnTPV/CYN/rfihAHKTp5Xmdo9NQcAAmkhyrQbmIjNFhGZmAQgTvH5iKHv5Row5 eGqALyud18Jy7jPI/fawO5w1XhkeEcz39/ZBE9mENCCWsPEk/zQJDY48sdi+bgI573P8 x8LbwVj1k4mbh20T3F5khHmk+BZ9iBIV5wOBLOrHAJ01OH7CYwE2H/NB/3ns0azfPrHh XpS9sAnhYdIyOzw7HZFfrnc5sIABvDa2HCHKaKOVG1zlvyh96JwiJ2J6vFMJ1K0p26LQ ki8A==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=RFOheQh3; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385ccd68958sm1292959f8f.67.2024.11.28.02.43.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Nov 2024 02:43:35 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH for-10.0 23/25] target/i386: Set Float3NaNPropRule explicitly Date: Thu, 28 Nov 2024 10:43:08 +0000 Message-Id: <20241128104310.3452934-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241128104310.3452934-1-peter.maydell@linaro.org> References: <20241128104310.3452934-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the Float3NaNPropRule explicitly for i386. We had no i386-specific behaviour in the old ifdef ladder, so we were using the default "prefer a then b then c" fallback. This is very likely wrong for i386, but in this refactoring we don't want to make a behaviour change, so we leave a TODO note. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/i386/tcg/fpu_helper.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c index e9de084a96d..b62719dead1 100644 --- a/target/i386/tcg/fpu_helper.c +++ b/target/i386/tcg/fpu_helper.c @@ -180,6 +180,8 @@ void cpu_init_fp_statuses(CPUX86State *env) * against the manual. */ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->sse_status); + /* Similarly the NaN propagation rule is likely wrong. */ + set_float_3nan_prop_rule(float_3nan_prop_abc, &env->sse_status); } static inline uint8_t save_exception_flags(CPUX86State *env) From patchwork Thu Nov 28 10:43:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 845941 Delivered-To: patch@linaro.org Received: by 2002:adf:f2c4:0:b0:382:43a8:7b94 with SMTP id d4csp160172wrp; Thu, 28 Nov 2024 02:50:47 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXv1bXnMwut790HwshsOT9mjXcGf61xg8jyOvj3GQUjTmkJPX3j+z4zjidDzhpGhQyTKUbPsA==@linaro.org X-Google-Smtp-Source: AGHT+IHePg1SrnhIczB8Bldy3zL93DuVnUIMn/9FrLPewtSmg0oKq8hABEan41pIrkMaAEXvxIca X-Received: by 2002:a05:620a:170f:b0:7b1:440a:fdf2 with SMTP id af79cd13be357-7b67c27d4b9mr896018785a.20.1732791046923; Thu, 28 Nov 2024 02:50:46 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1732791046; cv=none; d=google.com; s=arc-20240605; b=NWVODuHSrXFLJXTid3EON+sEVj1bzN8f+DB40z2h44UtYNaYROABpH7FPUqnZpyB3U cz2e2AqQ5AfHUTX+8viKYXBnW4+NrHDVRd+j4p8ExX9IXtg1eIUc0oyEqedBaeA7FNz2 vuOCh3yysRqAQT0MiugBlEB5QY8WObsAXE9cPhW1F4GfHCGLviN+/LHio8SBniwusZ55 0Knhbr3yigmB65HdXg3XrHi9YJwrZjCg177Y8H6Dys/DAAVeRhLTkO9ck3QXAWpCqyVW 6roNCwF1hEMq8qbFWXbl47jTIc7Jt48Y/O3BO+lsVj/1HgAEDE3hkNrXZT+LS0g1G8Bm d8Gw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=SDBKL9MPqps6ny2XrO2kAvFlwZGolk654R0X02D8xvM=; fh=QgE9QYJDVj//6C0QJWGeEM+qaFVaxwMel1ZWqkEy6K0=; b=W7U5r0RFBdPe7K3BmVSHsxDsBExMeKIVDbHMsZLn7tv4JpYvViioNbfL2/EywYLz7J eQn2MZBN4EkEVIH8V9QsZw1x255gMfljL9VFMTy2YpMyT+tmzyxKEt4Ory87XA2m1NRk We1t7fb3++t8KScB98R5Dp8QIWsrzVhyWKKihFdYwnL0xWcv2cN3GyIQjstNgAyKiUTQ eTPgvlWSaiS7zGtF9JfmI6QXI8IoOm3BIyYLCA/vOpttqh1H10Hs66hO4WMldD1+U39g ClYvUZrjUwfctcwbPeCKNftqNaiqERNgv5J0lnFRW5kwSMgiMWeyh2rgj6NudwzcdTa8 X9QA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Z8w6dXZe; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385ccd68958sm1292959f8f.67.2024.11.28.02.43.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Nov 2024 02:43:36 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH for-10.0 24/25] target/hppa: Set Float3NaNPropRule explicitly Date: Thu, 28 Nov 2024 10:43:09 +0000 Message-Id: <20241128104310.3452934-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241128104310.3452934-1-peter.maydell@linaro.org> References: <20241128104310.3452934-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the Float3NaNPropRule explicitly for HPPA, and remove the ifdef from pickNaNMulAdd(). HPPA is the only target that was using the default branch of the ifdef ladder (other targets either do not use muladd or set default_nan_mode), so we can remove the ifdef fallback entirely now (allowing the "rule not set" case to fall into the default of the switch statement and assert). We add a TODO note that the HPPA rule is probably wrong; this is not a behavioural change for this refactoring. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/hppa/fpu_helper.c | 8 ++++++++ fpu/softfloat-specialize.c.inc | 7 +------ 2 files changed, 9 insertions(+), 6 deletions(-) diff --git a/target/hppa/fpu_helper.c b/target/hppa/fpu_helper.c index 393cae33bf9..69c4ce37835 100644 --- a/target/hppa/fpu_helper.c +++ b/target/hppa/fpu_helper.c @@ -55,6 +55,14 @@ void HELPER(loaded_fr0)(CPUHPPAState *env) * HPPA does note implement a CPU reset method at all... */ set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fp_status); + /* + * TODO: The HPPA architecture reference only documents its NaN + * propagation rule for 2-operand operations. Testing on real hardware + * might be necessary to confirm whether this order for muladd is correct. + * Not preferring the SNaN is almost certainly incorrect as it diverges + * from the documented rules for 2-operand operations. + */ + set_float_3nan_prop_rule(float_3nan_prop_abc, &env->fp_status); /* For inf * 0 + NaN, return the input NaN */ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); } diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 60de68012e1..353b524d2de 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -475,7 +475,6 @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls, static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, bool infzero, float_status *status) { - Float3NaNPropRule rule = status->float_3nan_prop_rule; /* * We guarantee not to require the target to tell us how to * pick a NaN if we're always returning the default NaN. @@ -501,11 +500,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, } } - if (rule == float_3nan_prop_none) { - rule = float_3nan_prop_abc; - } - - switch (rule) { + switch (status->float_3nan_prop_rule) { case float_3nan_prop_s_abc: if (is_snan(a_cls)) { return 0; From patchwork Thu Nov 28 10:43:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 845932 Delivered-To: patch@linaro.org Received: by 2002:adf:f2c4:0:b0:382:43a8:7b94 with SMTP id d4csp159735wrp; Thu, 28 Nov 2024 02:49:27 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVB6npSmdCpWt6BPOoObaUDqnOP7cBaJRzTU8SyqDUgvZSpddCZbEhDoHupfW8xnToGHNs45w==@linaro.org X-Google-Smtp-Source: AGHT+IGOEdcgrRkS8a7L+AqNJDq2/LaHLTGlTt9DwGvdgda9Fk8JBQI+CUzX1ZX57hLTOr+tp+zZ X-Received: by 2002:a05:690c:6f11:b0:6e3:153a:ff62 with SMTP id 00721157ae682-6ef37224abfmr70774007b3.23.1732790967081; Thu, 28 Nov 2024 02:49:27 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1732790967; cv=none; d=google.com; s=arc-20240605; b=lf2mAsLcrroAAP4qLapzzRTCzRTqxcZyAdowX6oO8zf2gUX3CE+Jp8hJ3ZCkx0bxtf 3R6JlRoNIp59QNZo4Kv8mPqKlTT6c5uhycMMwkNTWKXjCltjBRrMe2aVCzsraNmr1cli m1WjjwzZ4eH4D34ltijGnHYYkpet2koT3aolLasqbBH65f2EhLGUDItbW7GaiLW3QHqp z8k3IumsO5LFQAjudxnz+lSNGkgr3cfmXObCr81Ox7Sgu1KOkSekZyAt5EBBs8FCKYE6 xU3WOVtagDuYZm1QuJc+13rZF+4saQKwY7WTc5GEM02+JptuqgqWd8GuHaizB5PDl3rb fGQw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Zfa3WE0hEeXkZktlw3Eszp/UyNtqhw8PzXG1xyTaEO4=; fh=QgE9QYJDVj//6C0QJWGeEM+qaFVaxwMel1ZWqkEy6K0=; b=KpOzx9RsABZTTLPcpfL9g2oBWEp7CrvxZhposm7sqdSOSANNjs0c+HC7NJbEgb6sRl oVjoTj4GwT2xepke9Osp6Y5V9R2QaV6qBzHTR+17TqShFLThJsKPoV3k5iSi0IzseL+O T9vFmDI5BwLLdQKwJWmm7FKTbWAxFvakR9wd13NsUAld1EPfnQM0lqRtzIoyNrdoKeSv dOZtFfUhgdffvexJ2xqnUXbwSlqKllOzjPWVp2LK1HwWzRURL1MV5CQJtEr8+Xpb8SDc 05EU6/aPFP1lc6RbIBtf3SRxxyOlWoYkmYxsQgSWyxawzKVf2OdunHmjWScHGEiP8zCJ gLvg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=oqntGWrb; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385ccd68958sm1292959f8f.67.2024.11.28.02.43.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Nov 2024 02:43:37 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH for-10.0 25/25] fpu: Remove use_first_nan field from float_status Date: Thu, 28 Nov 2024 10:43:10 +0000 Message-Id: <20241128104310.3452934-26-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241128104310.3452934-1-peter.maydell@linaro.org> References: <20241128104310.3452934-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The use_first_nan field in float_status was an xtensa-specific way to select at runtime from two different NaN propagation rules. Now that xtensa is using the target-agnostic NaN propagation rule selection that we've just added, we can remove use_first_nan, because there is no longer any code that reads it. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- include/fpu/softfloat-helpers.h | 5 ----- include/fpu/softfloat-types.h | 1 - target/xtensa/fpu_helper.c | 1 - 3 files changed, 7 deletions(-) diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h index cf06b4e16bf..10a6763532c 100644 --- a/include/fpu/softfloat-helpers.h +++ b/include/fpu/softfloat-helpers.h @@ -113,11 +113,6 @@ static inline void set_snan_bit_is_one(bool val, float_status *status) status->snan_bit_is_one = val; } -static inline void set_use_first_nan(bool val, float_status *status) -{ - status->use_first_nan = val; -} - static inline void set_no_signaling_nans(bool val, float_status *status) { status->no_signaling_nans = val; diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h index 79220f8c67f..e2db92c72fa 100644 --- a/include/fpu/softfloat-types.h +++ b/include/fpu/softfloat-types.h @@ -291,7 +291,6 @@ typedef struct float_status { * softfloat-specialize.inc.c) */ bool snan_bit_is_one; - bool use_first_nan; bool no_signaling_nans; /* should overflowed results subtract re_bias to its exponent? */ bool rebias_overflow; diff --git a/target/xtensa/fpu_helper.c b/target/xtensa/fpu_helper.c index 4b1b021d824..53fc7cfd2af 100644 --- a/target/xtensa/fpu_helper.c +++ b/target/xtensa/fpu_helper.c @@ -59,7 +59,6 @@ static const struct { void xtensa_use_first_nan(CPUXtensaState *env, bool use_first) { - set_use_first_nan(use_first, &env->fp_status); set_float_2nan_prop_rule(use_first ? float_2nan_prop_ab : float_2nan_prop_ba, &env->fp_status); set_float_3nan_prop_rule(use_first ? float_3nan_prop_abc : float_3nan_prop_cba,