From patchwork Wed Nov 27 16:15:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patryk Wlazlyn X-Patchwork-Id: 845884 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 72E8B200BB3; Wed, 27 Nov 2024 16:15:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732724150; cv=none; b=VJjsqY49aKgpnMqxKVycFmx75lrttEq5f3RVfED5lsD1dURWgYJU+g17aN0tas97DnFOhoBwzDphqkiezAKxYB4wdguoxvYlH8pacZ6z3cAfZPRawLVf4sAl/183UtavzFzDffFe8843TpO3LMWQjtLAUGDkbGYtdiZxmOSpUk0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732724150; c=relaxed/simple; bh=wc4zWEKELkAS6PpC+lFAQ2biVVOOJfbXtAHMR5RiDJo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=XDTkwxKDFw/v0QISb6CHrMolQqV0G5XPu/f5yFvSC5ySe94n1FnoZBH1HRVO+bxyqY0akfIO0GL38uW7Q7gfrpV1iu4FZTw54tp7w11nhPN/MOCb3TZset75UT4GMDHqFqqnIJF0fLaS77JSOrftBRJKXC4ao0EsjYRrd5UlOJI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=glWD8j6+; arc=none smtp.client-ip=192.198.163.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="glWD8j6+" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1732724148; x=1764260148; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=wc4zWEKELkAS6PpC+lFAQ2biVVOOJfbXtAHMR5RiDJo=; b=glWD8j6+SfULOhQd3ufuO6cx371F6xnfXgZkDa5pcCzqHmSggVI8KbUR k9KCv/QptyrBhXPJtn6AHbDw+ohg8xMbpDFqxFxJ6nt/GktjknWKDxll8 /JdlmWmbGDYPggPoVQHXPoaHgvwYLyp1sVOn+M/a0iW9tMQ6DVa+gP3kr Orm7en15FPxJd/JF8Nqf98mCMhMETGm2RjJ4VBHKnA7fDpdficrwt5BjA KblCzbmOJdOS/foIse+Abb65NxCjMrZ8R/mi6IitJXYxGKZ6+L3MD3oL8 NLKEcaFpu0iOPQj3DkksTDJ/p4tyU5s8rQmSGidNtwMikqDWcNpfv7VXK g==; X-CSE-ConnectionGUID: NV4+B8moTbmXFEwp4RxL+g== X-CSE-MsgGUID: rTJN9+aHRaOCWR9NY3KOTw== X-IronPort-AV: E=McAfee;i="6700,10204,11269"; a="43597587" X-IronPort-AV: E=Sophos;i="6.12,189,1728975600"; d="scan'208";a="43597587" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Nov 2024 08:15:48 -0800 X-CSE-ConnectionGUID: MeolhsYAQlGfnSeonUB9ZQ== X-CSE-MsgGUID: fhr6MUorQK2r3CfWZdWFZg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="97042407" Received: from mlehtone-mobl.ger.corp.intel.com (HELO localhost.localdomain) ([10.245.244.148]) by ORVIESA003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Nov 2024 08:15:45 -0800 From: Patryk Wlazlyn To: x86@kernel.org Cc: linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, rafael.j.wysocki@intel.com, peterz@infradead.org, dave.hansen@linux.intel.com, gautham.shenoy@amd.com, tglx@linutronix.de, len.brown@intel.com, artem.bityutskiy@linux.intel.com, patryk.wlazlyn@linux.intel.com Subject: [PATCH v6 1/4] x86/smp: Allow calling mwait_play_dead with an arbitrary hint Date: Wed, 27 Nov 2024 17:15:15 +0100 Message-ID: <20241127161518.432616-2-patryk.wlazlyn@linux.intel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241127161518.432616-1-patryk.wlazlyn@linux.intel.com> References: <20241127161518.432616-1-patryk.wlazlyn@linux.intel.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The MWAIT instruction needs different hints on different CPUs to reach specific idle states. The current hint calculation in mwait_play_dead() code works in practice on current Intel hardware, but is not documented and fails on a recent Intel's Sierra Forest and possibly some future ones. Those newer CPUs' power efficiency suffers when the CPU is put offline. Allow cpuidle code to provide mwait_play_dead with a known hint for efficient play_dead code. Signed-off-by: Patryk Wlazlyn --- arch/x86/include/asm/smp.h | 4 +- arch/x86/kernel/smpboot.c | 86 ++++++++++++++++++++------------------ 2 files changed, 49 insertions(+), 41 deletions(-) diff --git a/arch/x86/include/asm/smp.h b/arch/x86/include/asm/smp.h index ca073f40698f..ab90b95037f3 100644 --- a/arch/x86/include/asm/smp.h +++ b/arch/x86/include/asm/smp.h @@ -114,6 +114,7 @@ void wbinvd_on_cpu(int cpu); int wbinvd_on_all_cpus(void); void smp_kick_mwait_play_dead(void); +void mwait_play_dead_with_hint(unsigned int hint); void native_smp_send_reschedule(int cpu); void native_send_call_func_ipi(const struct cpumask *mask); @@ -151,7 +152,6 @@ static inline struct cpumask *cpu_l2c_shared_mask(int cpu) { return per_cpu(cpu_l2c_shared_map, cpu); } - #else /* !CONFIG_SMP */ #define wbinvd_on_cpu(cpu) wbinvd() static inline int wbinvd_on_all_cpus(void) @@ -164,6 +164,8 @@ static inline struct cpumask *cpu_llc_shared_mask(int cpu) { return (struct cpumask *)cpumask_of(0); } + +static inline void mwait_play_dead_with_hint(unsigned int eax_hint) { } #endif /* CONFIG_SMP */ #ifdef CONFIG_DEBUG_NMI_SELFTEST diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c index b5a8f0891135..ef112143623d 100644 --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -1272,13 +1272,57 @@ void play_dead_common(void) local_irq_disable(); } +void __noreturn mwait_play_dead_with_hint(unsigned int eax_hint) +{ + struct mwait_cpu_dead *md = this_cpu_ptr(&mwait_cpu_dead); + + /* Set up state for the kexec() hack below */ + md->status = CPUDEAD_MWAIT_WAIT; + md->control = CPUDEAD_MWAIT_WAIT; + + wbinvd(); + + while (1) { + /* + * The CLFLUSH is a workaround for erratum AAI65 for + * the Xeon 7400 series. It's not clear it is actually + * needed, but it should be harmless in either case. + * The WBINVD is insufficient due to the spurious-wakeup + * case where we return around the loop. + */ + mb(); + clflush(md); + mb(); + __monitor(md, 0, 0); + mb(); + __mwait(eax_hint, 0); + + if (READ_ONCE(md->control) == CPUDEAD_MWAIT_KEXEC_HLT) { + /* + * Kexec is about to happen. Don't go back into mwait() as + * the kexec kernel might overwrite text and data including + * page tables and stack. So mwait() would resume when the + * monitor cache line is written to and then the CPU goes + * south due to overwritten text, page tables and stack. + * + * Note: This does _NOT_ protect against a stray MCE, NMI, + * SMI. They will resume execution at the instruction + * following the HLT instruction and run into the problem + * which this is trying to prevent. + */ + WRITE_ONCE(md->status, CPUDEAD_MWAIT_KEXEC_HLT); + while(1) + native_halt(); + } + } +} + /* * We need to flush the caches before going to sleep, lest we have * dirty data in our caches when we come back up. */ static inline void mwait_play_dead(void) { - struct mwait_cpu_dead *md = this_cpu_ptr(&mwait_cpu_dead); unsigned int eax, ebx, ecx, edx; unsigned int highest_cstate = 0; unsigned int highest_subcstate = 0; @@ -1316,45 +1360,7 @@ static inline void mwait_play_dead(void) (highest_subcstate - 1); } - /* Set up state for the kexec() hack below */ - md->status = CPUDEAD_MWAIT_WAIT; - md->control = CPUDEAD_MWAIT_WAIT; - - wbinvd(); - - while (1) { - /* - * The CLFLUSH is a workaround for erratum AAI65 for - * the Xeon 7400 series. It's not clear it is actually - * needed, but it should be harmless in either case. - * The WBINVD is insufficient due to the spurious-wakeup - * case where we return around the loop. - */ - mb(); - clflush(md); - mb(); - __monitor(md, 0, 0); - mb(); - __mwait(eax, 0); - - if (READ_ONCE(md->control) == CPUDEAD_MWAIT_KEXEC_HLT) { - /* - * Kexec is about to happen. Don't go back into mwait() as - * the kexec kernel might overwrite text and data including - * page tables and stack. So mwait() would resume when the - * monitor cache line is written to and then the CPU goes - * south due to overwritten text, page tables and stack. - * - * Note: This does _NOT_ protect against a stray MCE, NMI, - * SMI. They will resume execution at the instruction - * following the HLT instruction and run into the problem - * which this is trying to prevent. - */ - WRITE_ONCE(md->status, CPUDEAD_MWAIT_KEXEC_HLT); - while(1) - native_halt(); - } - } + mwait_play_dead_with_hint(eax); } /* From patchwork Wed Nov 27 16:15:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patryk Wlazlyn X-Patchwork-Id: 846076 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 01978200BBF; Wed, 27 Nov 2024 16:15:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732724154; cv=none; b=MaDyVm8SUOV3kypYnGwg1DoFVvWU4X9/MiJLYSMOpOkfiw9EJwPCMLG7Zgc8uAOjVKGzj0H96+JHvlp+bPMyuonTcdSwXL1YRLPh1x3cVQ5LXd3OIQ8pjnsYOcFyw0IG9urBsZql/WnXKzQwRWmyk7MHfYxrGRYzxgoB6Lle08M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732724154; c=relaxed/simple; bh=IJyLqWUb34HjgoRr/RZU1HX6hMKRUjvhExUqCV0J0Ws=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Hpc/z/pdhdHMj4GlnaMYr5HBPd6ajpZ7BB5LgsYuycK+lgWG9fTwHbtyl118uqFSn9GciA7Zo6dS5Q1aYGBnuXkuMgcAlRVBBWhtqhfG7Gs2FczuRZq/bd/1ACvs6SE9LTq3WgpJNgxVUNGnAZvq81YiZcZH6Vm/8rVRWSC9etY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=bdSLLVcu; arc=none smtp.client-ip=192.198.163.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="bdSLLVcu" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1732724153; x=1764260153; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=IJyLqWUb34HjgoRr/RZU1HX6hMKRUjvhExUqCV0J0Ws=; b=bdSLLVcufQC/CBLFEufYgjBIT94cYt9OkkbBtZ3Xd0BBTdyqJFB5F8+n j9pwbeRC38QYkDJl7T0NIT5FCeKu9GbVoF/F2ZMN4WRFzVIF2DFVHr27A wqL/jugQeTnMXwvvYJBDv87e4WQlQh1L5Bauo9IjcHQKnPRX3M+Vls5Oa zBCX4NiAKilvT0acox5AiCdI6YZ1ZV+Gwjz0lf0mTzagK4S4DRZRbMqx5 mN4dVylfkbLPKAjzBQgCUmz2TZyh+cnb/0F8ovI7mq7uOiPIXig07ii7b BAUINjLPYMkC3mhESiRMMRr762KmuktmTtlKOP+I1ObqR/3UMQ2/lr6wW g==; X-CSE-ConnectionGUID: U91slF+uRZGXxld74dlEcA== X-CSE-MsgGUID: SBzbm6QZSjqUbThkWOAM3g== X-IronPort-AV: E=McAfee;i="6700,10204,11269"; a="43597597" X-IronPort-AV: E=Sophos;i="6.12,189,1728975600"; d="scan'208";a="43597597" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Nov 2024 08:15:53 -0800 X-CSE-ConnectionGUID: AVUv9J3mSR+hHYGJuyaZMg== X-CSE-MsgGUID: hEQ989sDTAW9F4fvJLQUTw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="97042425" Received: from mlehtone-mobl.ger.corp.intel.com (HELO localhost.localdomain) ([10.245.244.148]) by ORVIESA003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Nov 2024 08:15:49 -0800 From: Patryk Wlazlyn To: x86@kernel.org Cc: linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, rafael.j.wysocki@intel.com, peterz@infradead.org, dave.hansen@linux.intel.com, gautham.shenoy@amd.com, tglx@linutronix.de, len.brown@intel.com, artem.bityutskiy@linux.intel.com, patryk.wlazlyn@linux.intel.com Subject: [PATCH v6 2/4] ACPI: processor_idle: Add FFH state handling Date: Wed, 27 Nov 2024 17:15:16 +0100 Message-ID: <20241127161518.432616-3-patryk.wlazlyn@linux.intel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241127161518.432616-1-patryk.wlazlyn@linux.intel.com> References: <20241127161518.432616-1-patryk.wlazlyn@linux.intel.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Recent Intel platforms will depend on the idle driver to pass the correct hint for playing dead via mwait_play_dead_with_hint(). Expand the existing enter_dead interface with handling for FFH states and pass the MWAIT hint to the mwait_play_dead code. Signed-off-by: Patryk Wlazlyn Suggested-by: Gautham R. Shenoy --- arch/x86/kernel/acpi/cstate.c | 9 +++++++++ drivers/acpi/processor_idle.c | 2 ++ include/acpi/processor.h | 5 +++++ 3 files changed, 16 insertions(+) diff --git a/arch/x86/kernel/acpi/cstate.c b/arch/x86/kernel/acpi/cstate.c index f3ffd0a3a012..c80a3e6dba5f 100644 --- a/arch/x86/kernel/acpi/cstate.c +++ b/arch/x86/kernel/acpi/cstate.c @@ -204,6 +204,15 @@ int acpi_processor_ffh_cstate_probe(unsigned int cpu, } EXPORT_SYMBOL_GPL(acpi_processor_ffh_cstate_probe); +void acpi_processor_ffh_play_dead(struct acpi_processor_cx *cx) +{ + unsigned int cpu = smp_processor_id(); + struct cstate_entry *percpu_entry; + + percpu_entry = per_cpu_ptr(cpu_cstate_entry, cpu); + mwait_play_dead_with_hint(percpu_entry->states[cx->index].eax); +} + void __cpuidle acpi_processor_ffh_cstate_enter(struct acpi_processor_cx *cx) { unsigned int cpu = smp_processor_id(); diff --git a/drivers/acpi/processor_idle.c b/drivers/acpi/processor_idle.c index ce728cf7e301..83213fa47c1b 100644 --- a/drivers/acpi/processor_idle.c +++ b/drivers/acpi/processor_idle.c @@ -590,6 +590,8 @@ static void acpi_idle_play_dead(struct cpuidle_device *dev, int index) raw_safe_halt(); else if (cx->entry_method == ACPI_CSTATE_SYSTEMIO) { io_idle(cx->address); + } else if (cx->entry_method == ACPI_CSTATE_FFH) { + acpi_processor_ffh_play_dead(cx); } else return; } diff --git a/include/acpi/processor.h b/include/acpi/processor.h index a17e97e634a6..63a37e72b721 100644 --- a/include/acpi/processor.h +++ b/include/acpi/processor.h @@ -280,6 +280,7 @@ int acpi_processor_ffh_cstate_probe(unsigned int cpu, struct acpi_processor_cx *cx, struct acpi_power_register *reg); void acpi_processor_ffh_cstate_enter(struct acpi_processor_cx *cstate); +void acpi_processor_ffh_play_dead(struct acpi_processor_cx *cx); #else static inline void acpi_processor_power_init_bm_check(struct acpi_processor_flags @@ -300,6 +301,10 @@ static inline void acpi_processor_ffh_cstate_enter(struct acpi_processor_cx { return; } +static inline void acpi_processor_ffh_play_dead(struct acpi_processor_cx *cx) +{ + return; +} #endif static inline int call_on_cpu(int cpu, long (*fn)(void *), void *arg, From patchwork Wed Nov 27 16:15:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patryk Wlazlyn X-Patchwork-Id: 845883 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6F5AB20101D; Wed, 27 Nov 2024 16:15:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732724159; cv=none; b=toU7QJisp5ww04uM5UH459YKm0lQJF9mEGFKmhW5iVI2/tkv44nRuOGGskQCga8xOWUupf1cFq3+8w2z3Oq7ecTnJBiW/OblTbDDUwb9Ln8vuNpRkyMJ2juhFdTDIz2fC+V+PLtw9DLje2nL7WHtDNLkgZ0Pc3Rds3XzUJMKSRA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732724159; c=relaxed/simple; bh=IZig5JtFcVJFRtGodHb1nn1SdFNHH+WZ6d68k4Fox6I=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=FeJGLLX8fq2AG2j/SPxC9S3w3WjcTGQ043HWsPSjRbaWTsxj7iiIVROqW6OKNw22aqkk+PwarIMjQ8QmMssrdbtqv4HcJGpWBejy8KN2IZ01j5hW/mdpDxam9sFg6f1vJzUa4Ho8MVtg2M5i+IwU7TZxB0cSoDZ90F4gAoPEN9I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=kt3vq59K; arc=none smtp.client-ip=192.198.163.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="kt3vq59K" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1732724157; x=1764260157; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=IZig5JtFcVJFRtGodHb1nn1SdFNHH+WZ6d68k4Fox6I=; b=kt3vq59K3/htemCf3F6cHaSS8DMuqD8IpLF8ZW+91QOTSmfodUen+9Q1 Idx6wp4LrRgbbi7XoYJVQWjrhiOIwSpePgQo+/YX0CnzYJzrQJrmwN97Q wmaZPU2o+aq99lQV5Msx4WgpNknNvUR9Y6OtcyYp8CjG6FOHYmoyuhz9D VDDCopZJgmNbs4PQQwB44lZZf6x1U70dmCK/SD1zmS8zo+zj56G2u12Pf R4eWDmZh6SOCXSI7WJsOxzTLzhgjzHAoXnmaten752et3PIgFdhGe3FNk 2ndSh9ccRsYS0TTx6DzNX9CYa0slr/8z0KP+EpKhvRhckEZFk4XQjIoCM Q==; X-CSE-ConnectionGUID: dSwsIgv6SRKgEehUNX4d5A== X-CSE-MsgGUID: 5fXuWngkQO6MXO/A/pEsYQ== X-IronPort-AV: E=McAfee;i="6700,10204,11269"; a="43597607" X-IronPort-AV: E=Sophos;i="6.12,189,1728975600"; d="scan'208";a="43597607" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Nov 2024 08:15:57 -0800 X-CSE-ConnectionGUID: WK6Tvta8S7Ox6lohOTRQ7Q== X-CSE-MsgGUID: TJ2XPXdCTf6GBiC9ZWt3bw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="97042461" Received: from mlehtone-mobl.ger.corp.intel.com (HELO localhost.localdomain) ([10.245.244.148]) by ORVIESA003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Nov 2024 08:15:54 -0800 From: Patryk Wlazlyn To: x86@kernel.org Cc: linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, rafael.j.wysocki@intel.com, peterz@infradead.org, dave.hansen@linux.intel.com, gautham.shenoy@amd.com, tglx@linutronix.de, len.brown@intel.com, artem.bityutskiy@linux.intel.com, patryk.wlazlyn@linux.intel.com Subject: [PATCH v6 3/4] intel_idle: Provide the default enter_dead() handler Date: Wed, 27 Nov 2024 17:15:17 +0100 Message-ID: <20241127161518.432616-4-patryk.wlazlyn@linux.intel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241127161518.432616-1-patryk.wlazlyn@linux.intel.com> References: <20241127161518.432616-1-patryk.wlazlyn@linux.intel.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Recent Intel platforms require idle driver to provide information about the MWAIT hint used to enter the deepest idle state in the play_dead code. Provide the default enter_dead() handler for all of the platforms and allow overwriting with a custom handler for each platform if needed. Signed-off-by: Patryk Wlazlyn --- drivers/idle/intel_idle.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/idle/intel_idle.c b/drivers/idle/intel_idle.c index ac4d8faa3886..291efa733356 100644 --- a/drivers/idle/intel_idle.c +++ b/drivers/idle/intel_idle.c @@ -56,6 +56,7 @@ #include #include #include +#include #define INTEL_IDLE_VERSION "0.5.1" @@ -227,6 +228,16 @@ static __cpuidle int intel_idle_s2idle(struct cpuidle_device *dev, return 0; } +static __cpuidle void intel_idle_enter_dead(struct cpuidle_device *dev, + int index) +{ + struct cpuidle_driver *drv = cpuidle_get_cpu_driver(dev); + struct cpuidle_state *state = &drv->states[index]; + unsigned long eax = flg2MWAIT(state->flags); + + mwait_play_dead_with_hint(eax); +} + /* * States are indexed by the cstate number, * which is also the index into the MWAIT hint array. @@ -1798,6 +1809,7 @@ static void __init intel_idle_init_cstates_acpi(struct cpuidle_driver *drv) state->flags |= CPUIDLE_FLAG_TIMER_STOP; state->enter = intel_idle; + state->enter_dead = intel_idle_enter_dead; state->enter_s2idle = intel_idle_s2idle; } } @@ -2143,10 +2155,12 @@ static void __init intel_idle_init_cstates_icpu(struct cpuidle_driver *drv) if (intel_idle_max_cstate_reached(cstate)) break; - if (!cpuidle_state_table[cstate].enter && - !cpuidle_state_table[cstate].enter_s2idle) + if (!cpuidle_state_table[cstate].enter) break; + if (!cpuidle_state_table[cstate].enter_dead) + cpuidle_state_table[cstate].enter_dead = intel_idle_enter_dead; + /* If marked as unusable, skip this state. */ if (cpuidle_state_table[cstate].flags & CPUIDLE_FLAG_UNUSABLE) { pr_debug("state %s is disabled\n", From patchwork Wed Nov 27 16:15:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patryk Wlazlyn X-Patchwork-Id: 846075 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 02F9E20102D; Wed, 27 Nov 2024 16:16:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732724163; cv=none; b=pbI0LpgZM/3X0d2538TUIdoZI1d3Pzo0qkJV4dyvIWqXgmBZZEiRcUZ4iWLjIJGmnh1dUV7hStTnJ8+lMaEmhmb02J6kIBOwbYN1f9ziU34lkceFvb/rGwBTZIEjs8D7xRM9snYvlpjDmhhKXOm5fTS21x280jEQ21m5IgfAl04= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732724163; c=relaxed/simple; bh=PYqpZCevWBfW3JOxBGFkpqBiONfsytVyzZ/qS4X/H4A=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=h1TZRpH16Y1ICYE9fuOX3ci/piQTVPstdKD1eAGWNWmsv2FjageuTFU7od2/rDe15gO1oCPjoMwnRHYL/IZeaCgC9F7PLdp0qcHbhqoFqcSzNGX475z/2baGIn9vWrQig1S0nXdJwqFD3N1fqkpKQkRk1pDJOYCycDT4Q3udUIU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=AryEQRAD; arc=none smtp.client-ip=192.198.163.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="AryEQRAD" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1732724162; x=1764260162; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=PYqpZCevWBfW3JOxBGFkpqBiONfsytVyzZ/qS4X/H4A=; b=AryEQRADk0AldgPUMzpYj4zrBBJJPD2IhDPh/1elurCDCITFVYRZXFr0 772Pl3EWigxDtIdugrtOluwGAVNvdorH7KPMFxKDK8r0xaikLzjDJDquO AufE+0sRY+LJtptT0CqSKAWrpyiLOCCHyb8A4CfHE0MGtqlfbyEAq8NMd EQzUvrqRRK5LhIS9B0PRZ+ccKOfuCOsjDxvoA2bu/IBUl4Ibbd2+GekJw V/79tsD8MW0lROMC34tVIheeA7/Nnv07+DZW5/uWWjEjvppNz3FJRpy20 kYh0sswzHt4idOZJlAN3fl0bcNpKzS8FSCGAoTxCNen1n/f/upiaVRUu5 A==; X-CSE-ConnectionGUID: t/QIx1WyT7GPyckDhDAlUA== X-CSE-MsgGUID: GHR7FPjgTDqGZZ6ME2x6XQ== X-IronPort-AV: E=McAfee;i="6700,10204,11269"; a="43597616" X-IronPort-AV: E=Sophos;i="6.12,189,1728975600"; d="scan'208";a="43597616" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Nov 2024 08:16:02 -0800 X-CSE-ConnectionGUID: xlkeW29ESECfgn+xE2+GGA== X-CSE-MsgGUID: Yc2wVOr2SHqL6cQMGBg7Ng== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="97042476" Received: from mlehtone-mobl.ger.corp.intel.com (HELO localhost.localdomain) ([10.245.244.148]) by ORVIESA003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Nov 2024 08:15:58 -0800 From: Patryk Wlazlyn To: x86@kernel.org Cc: linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, rafael.j.wysocki@intel.com, peterz@infradead.org, dave.hansen@linux.intel.com, gautham.shenoy@amd.com, tglx@linutronix.de, len.brown@intel.com, artem.bityutskiy@linux.intel.com, patryk.wlazlyn@linux.intel.com Subject: [PATCH v6 4/4] x86/smp native_play_dead: Prefer cpuidle_play_dead() over mwait_play_dead() Date: Wed, 27 Nov 2024 17:15:18 +0100 Message-ID: <20241127161518.432616-5-patryk.wlazlyn@linux.intel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241127161518.432616-1-patryk.wlazlyn@linux.intel.com> References: <20241127161518.432616-1-patryk.wlazlyn@linux.intel.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The current algorithm* for looking up the mwait hint for the deepest cstate, in mwait_play_dead() code works by inspecting CPUID leaf 0x5 and calculates the mwait hint based on the number of reported substates. This approach depends on the hints associated with them to be continuous in the range [0, NUM_SUBSTATES-1]. This continuity is not documented and is not met on the recent Intel platforms. * The current algorithm is implemented in the for loop inspecting edx in mwait_play_dead(). For example, Intel's Sierra Forest report two cstates with two substates each in cpuid leaf 0x5: Name* target cstate target subcstate (mwait hint) =========================================================== C1 0x00 0x00 C1E 0x00 0x01 -- 0x10 ---- C6S 0x20 0x22 C6P 0x20 0x23 -- 0x30 ---- /* No more (sub)states all the way down to the end. */ =========================================================== * Names of the cstates are not included in the CPUID leaf 0x5, they are taken from the product specific documentation. Notice that hints 0x20 and 0x21 are skipped entirely for the target cstate 0x20 (C6), being a cause of the problem for the current cpuid leaf 0x5 algorithm. Remove the old implementation of play_dead MWAIT hint calculation based on the CPUID leaf 0x5 in mwait_play_dead() and delegate calling of the mwait_play_dead_with_hint() to the idle driver. Signed-off-by: Patryk Wlazlyn --- arch/x86/kernel/smpboot.c | 52 +++------------------------------------ 1 file changed, 3 insertions(+), 49 deletions(-) diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c index ef112143623d..704a1b1d650c 100644 --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -1317,52 +1317,6 @@ void __noreturn mwait_play_dead_with_hint(unsigned int eax_hint) } } -/* - * We need to flush the caches before going to sleep, lest we have - * dirty data in our caches when we come back up. - */ -static inline void mwait_play_dead(void) -{ - unsigned int eax, ebx, ecx, edx; - unsigned int highest_cstate = 0; - unsigned int highest_subcstate = 0; - int i; - - if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD || - boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) - return; - if (!this_cpu_has(X86_FEATURE_MWAIT)) - return; - if (!this_cpu_has(X86_FEATURE_CLFLUSH)) - return; - if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF) - return; - - eax = CPUID_MWAIT_LEAF; - ecx = 0; - native_cpuid(&eax, &ebx, &ecx, &edx); - - /* - * eax will be 0 if EDX enumeration is not valid. - * Initialized below to cstate, sub_cstate value when EDX is valid. - */ - if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) { - eax = 0; - } else { - edx >>= MWAIT_SUBSTATE_SIZE; - for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) { - if (edx & MWAIT_SUBSTATE_MASK) { - highest_cstate = i; - highest_subcstate = edx & MWAIT_SUBSTATE_MASK; - } - } - eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) | - (highest_subcstate - 1); - } - - mwait_play_dead_with_hint(eax); -} - /* * Kick all "offline" CPUs out of mwait on kexec(). See comment in * mwait_play_dead(). @@ -1413,9 +1367,9 @@ void native_play_dead(void) play_dead_common(); tboot_shutdown(TB_SHUTDOWN_WFS); - mwait_play_dead(); - if (cpuidle_play_dead()) - hlt_play_dead(); + /* Below returns only on error. */ + cpuidle_play_dead(); + hlt_play_dead(); } #else /* ... !CONFIG_HOTPLUG_CPU */