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Tue, 26 Nov 2024 05:45:43 -0800 From: Vishwaroop A To: , , , , , , , , , CC: Vishwaroop A Subject: [PATCH 1/3] arm64: tegra: Add spidev nodes for SPI controllers Date: Tue, 26 Nov 2024 13:45:27 +0000 Message-ID: <20241126134529.936451-2-va@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241126134529.936451-1-va@nvidia.com> References: <20241126134529.936451-1-va@nvidia.com> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE30:EE_|SA1PR12MB9515:EE_ X-MS-Office365-Filtering-Correlation-Id: 122d5784-99bc-47a6-bb31-08dd0e20aaa1 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|376014|82310400026|1800799024|36860700013|921020; X-Microsoft-Antispam-Message-Info: GhQpLUEdNWhWLZaxpN80pCE86+ZTjDg3UP62gW6fihxMh/IQGUT9xA/xhaW3eJ/94shPzmtKx9DGzx7qlpb0uQpGapFx+GIR48SPelmMv7v/dK0+9GRwGKwJzZNYZSrAVvhOeCSr4G7NsP77yeX36SpW72o2ddXDo0ESQTRroJkdpu/SdLtj6O2tlMfdlZuCBySRexs7Znvi63Lb06kwGUeqgmKJhKVgHKP0P8gwl02n+a2vAYYtTQwNy31PHsuXkoX/siWLr8qZOsdB/L3tBeIC2OT2ACWMbamT+H8aT41FZ5/nPiUi+ikzftAAJ8xrzFCiOO1uSp0ygxPgL6ff7p9yVlKjZGqZoCPGCQ8qxPeEYkjq5PGY+grpBzdiWK7YWQ5Fw61jgVypDSRSdC1vwNce2SFHHrKNViMEpHkDoRXr2zAynWUujdgqmsVHa2UyM7FJ6dEHubKJeb/yNKT9L3JybMUuVUJ+l6D3CQDSyEymk8NuqoyI9GE0DctzQbQn4MfcI4Yozv9SvfBlLzdeipb1GhAHok5h1b8pQzEU9HpSDLzX4Ko3UDTOdsgUgf6F/d4hAdG5To099o/kSyuWUMTKxbKd6BBQkg1IQzPxH6FZ9XS2t+NRI0WxZAD/aa6pqcyN1DbSRZwwN7pDMKdissbt4h/t8Rhg2UBkrc05NOh2dRnKqbpRwng8WI7SkNQfOk9ZfGMDboUIMg4Je2XeJhDq/pJJyLhqfAAEZnH9BDXLFqxHMxAb7J0Nb/Tln86V80bVTENYarMWVZAkm1JEoFlPqWgrdpxVw6DgKLKDXfGSuA6lfMqZZ2JvgW0owW4jruyJhtUQBsS+cxQ5G7baQLC82xh9sEpXxfAvJUXZEqt/2fX3iYS50PXuPVuxztvH4VK2NyOdDXi8IBkeImKtreX+mru5TcbWHhWNZaWDUlBK0/SQXr2QJcfS4tqeafHohvPMMSik61owWPQysUsHXz7VtTlFuCU4xQml5vFsjF1rUARSf9ljV9vPgynqCJ/S8CTNFWiWl5ziZF0cpKQSxqMexka1iQfxGVOzCGcex9Nuc1Ev9Xe3qYviMsSw2W7jSxedT3Ic5+7o+eTvSBQmjL94lEK1Mv8cyvoNi0+kmUaCNumFw5T+D3fLNSBjr28w+6A66/PEGQc2yBfYu7YfEg+n3zwKoFYgOdCQ3frJ33eOUY3kA/gbF8jRNWIHXsyt/qygw29lQG1kCAEmGG0P6JFmTjdXSpxx1O4P51cByFVI/tzOU+cZ8TvhperVEo4vjZCyG4JoLCmAzl8TIp32IAzQvFQuv49h/wfqpL3/WGUNv+Rx/pv88aqekBqUvoUXaqhLzG/Fv84YfeXEd2s4LEXsR0K4a2FU1Q9gUv++tWC2DPlBntfNN1fVAYcDyPwA6lkaxL+cghB35KYoH00nwZ3imZ3A/ejJygDPai2A6YMyaRHHF5z3rI2gOWdNP+u5ZCC/rWs6xI7jYrxzH9V4Tg== X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(376014)(82310400026)(1800799024)(36860700013)(921020); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Nov 2024 13:46:01.9852 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 122d5784-99bc-47a6-bb31-08dd0e20aaa1 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE30.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB9515 Add spidev nodes to two existing SPI controllers on the NVIDIA Tegra234 SoC. These additions enable user-space SPI device support for testing and development purposes. Specifies a maximum frequency of 81MHz for each spidev node. The 81MHz maximum frequency is defined to ensure stable operation while allowing for high-speed SPI communication. This frequency can be adjusted based on specific hardware capabilities and requirements. Signed-off-by: Vishwaroop A --- .../dts/nvidia/tegra234-p3737-0000+p3701.dtsi | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701.dtsi index f6cad29355e6..17de3d0feb45 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701.dtsi @@ -84,6 +84,34 @@ }; }; + spi@3210000 { + status = "okay"; + spi@0 { + compatible = "nvidia,tegra-spidev"; + reg = <0x0>; + spi-max-frequency = <81000000>; + }; + spi@1 { + compatible = "nvidia,tegra-spidev"; + reg = <0x1>; + spi-max-frequency = <81000000>; + }; + }; + + spi@3230000 { + status = "okay"; + spi@0 { + compatible = "nvidia,tegra-spidev"; + reg = <0x0>; + spi-max-frequency = <81000000>; + }; + spi@1 { + compatible = "nvidia,tegra-spidev"; + reg = <0x1>; + spi-max-frequency = <81000000>; + }; + }; + pwm@3280000 { status = "okay"; }; From patchwork Tue Nov 26 13:45:28 2024 Content-Type: text/plain; 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(1800799024)(36860700013)(376014)(82310400026)(921020); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Nov 2024 13:46:08.2643 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 46adf3dc-7e9f-4707-d60a-08dd0e20ae5f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE32.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7235 Add DeviceTree schema for NVIDIA'S SPIDEV controller. The schema supports both master and slave modes for data transfer purposes. Specifies required properties: "compatible", "reg", and "spi-max-frequency". Signed-off-by: Vishwaroop A --- Documentation/devicetree/bindings/trivial-devices.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/trivial-devices.yaml b/Documentation/devicetree/bindings/trivial-devices.yaml index 88abb5c174f3..c8b39a513fc5 100644 --- a/Documentation/devicetree/bindings/trivial-devices.yaml +++ b/Documentation/devicetree/bindings/trivial-devices.yaml @@ -293,6 +293,8 @@ properties: - national,lm85 # I2C ±0.33°C Accurate, 12-Bit + Sign Temperature Sensor and Thermal Window Comparator - national,lm92 + # NVIDIA Tegra SPIDEV Controller device + - nvidia,tegra-spidev # Nuvoton Temperature Sensor - nuvoton,w83773g # OKI ML86V7667 video decoder From patchwork Tue Nov 26 13:45:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vishwaroop A X-Patchwork-Id: 845707 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2057.outbound.protection.outlook.com [40.107.94.57]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2818E193408; 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Signed-off-by: Vishwaroop A --- drivers/spi/spidev.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/spi/spidev.c b/drivers/spi/spidev.c index 653f82984216..1d2c01bd76a9 100644 --- a/drivers/spi/spidev.c +++ b/drivers/spi/spidev.c @@ -711,6 +711,7 @@ static const struct spi_device_id spidev_spi_ids[] = { { .name = "spi-authenta" }, { .name = "em3581" }, { .name = "si3210" }, + { .name = "tegra-spidev" }, {}, }; MODULE_DEVICE_TABLE(spi, spidev_spi_ids); @@ -741,6 +742,7 @@ static const struct of_device_id spidev_dt_ids[] = { { .compatible = "semtech,sx1301", .data = &spidev_of_check }, { .compatible = "silabs,em3581", .data = &spidev_of_check }, { .compatible = "silabs,si3210", .data = &spidev_of_check }, + { .compatible = "nvidia,tegra-spidev", .data = &spidev_of_check }, {}, }; MODULE_DEVICE_TABLE(of, spidev_dt_ids);