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Wysocki" , Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , Simona Vetter , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Connor Abbott , linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=10146; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=I07ngYL9Ra1f9h+CP4yA7pd1FaT3h7r+nDReMCfjPD8=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBnPNFXvsfG19CuOcSshzsLLrl9P5JiCVdB6NQYWhe+ leGk+k2JAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZzzRVwAKCRB33NvayMhJ0aqAD/ 9BdW9LZzIoIYl35jeVi9cqCgNGXipLp/slLxcES64BRqOg55WgP8C+mC9AQY0K2p40Vh9Km2z9+QXA FonK8lkCmQXlP8i+4UWolxNN5NeQ0TXbzWqovX6t3o26ubGTzeciItmtaR99LfzgRTNVp6EmpUUFME BYXQRayCUWbyjQfpS62gs+vxwc0AdTaBe18Eh/rfbowEmWxH25J9Btc/LrVIubMwDHtqAz+REGSKui bQG7Gv4+Z2w7m8v35UYqWAqJ7bTl8tFTKYZvo0tGCW7lKu1CZji0ZrIAyzTBhrsZljUUzRpCaAqxCA tSGA3yTLPI8U2MdzektRPFBSEfQU/TlTwSNdFhxdNTAacs1HCHpXnSXATf38I2HsT4OR8f9zynEg/n PZqJ67Lv+iOnZx3ESzZ6ublhomHwSM3zL/Nua3WhLwh7S8jABMdjsAJueh7DuQu1ngJPkiqvBZPDUk aVwH27cPcNRTGmDdMefC5vJGwmcI39uedMVCyJ2TeO3ZA7tENg1xvJgn2anAM5rCSzQx2gKlMNGpnI gFqPqxsD5SzgmFhy397X7jvBeEGSTxdQqGrxyQDGa+YfhDY0OwsvX3dvvGIf8zaLTPPvYf3RgV1NfY rKhaYudkqE+JEI+cQm8DQ5SvLjRBeJWr7QeNLTowDyOSKUUOpJLrSGER9tew== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Half of the current "Quirks" are in fact features, so rename the defines with FEAT instead of QUIRK. They will be moved in a separate bitfield in a second time. No functional changes. Signed-off-by: Neil Armstrong --- drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 62 +++++++++++++++--------------- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 4 +- drivers/gpu/drm/msm/adreno/adreno_device.c | 2 +- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 7 ++-- 4 files changed, 38 insertions(+), 37 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c index 0c560e84ad5a53bb4e8a49ba4e153ce9cf33f7ae..825c820def315968d508973c8ae40c7c7b646569 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c @@ -743,7 +743,7 @@ static const struct adreno_info a6xx_gpus[] = { }, .gmem = SZ_512K, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, + .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT, .init = a6xx_gpu_init, .zapfw = "a615_zap.mbn", .a6xx = &(const struct a6xx_info) { @@ -769,7 +769,7 @@ static const struct adreno_info a6xx_gpus[] = { }, .gmem = SZ_512K, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, + .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT, .init = a6xx_gpu_init, .a6xx = &(const struct a6xx_info) { .protect = &a630_protect, @@ -839,7 +839,7 @@ static const struct adreno_info a6xx_gpus[] = { }, .gmem = SZ_512K, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, + .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT, .init = a6xx_gpu_init, .zapfw = "a615_zap.mdt", .a6xx = &(const struct a6xx_info) { @@ -864,8 +864,8 @@ static const struct adreno_info a6xx_gpus[] = { }, .gmem = SZ_512K, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | - ADRENO_QUIRK_HAS_HW_APRIV, + .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT | + ADRENO_FEAT_HAS_HW_APRIV, .init = a6xx_gpu_init, .zapfw = "a620_zap.mbn", .a6xx = &(const struct a6xx_info) { @@ -892,7 +892,7 @@ static const struct adreno_info a6xx_gpus[] = { }, .gmem = SZ_1M, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, + .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT, .init = a6xx_gpu_init, .zapfw = "a630_zap.mdt", .a6xx = &(const struct a6xx_info) { @@ -911,7 +911,7 @@ static const struct adreno_info a6xx_gpus[] = { }, .gmem = SZ_1M, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, + .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT, .init = a6xx_gpu_init, .zapfw = "a640_zap.mdt", .a6xx = &(const struct a6xx_info) { @@ -934,8 +934,8 @@ static const struct adreno_info a6xx_gpus[] = { }, .gmem = SZ_1M + SZ_128K, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | - ADRENO_QUIRK_HAS_HW_APRIV, + .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT | + ADRENO_FEAT_HAS_HW_APRIV, .init = a6xx_gpu_init, .zapfw = "a650_zap.mdt", .a6xx = &(const struct a6xx_info) { @@ -961,8 +961,8 @@ static const struct adreno_info a6xx_gpus[] = { }, .gmem = SZ_1M + SZ_512K, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | - ADRENO_QUIRK_HAS_HW_APRIV, + .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT | + ADRENO_FEAT_HAS_HW_APRIV, .init = a6xx_gpu_init, .zapfw = "a660_zap.mdt", .a6xx = &(const struct a6xx_info) { @@ -981,8 +981,8 @@ static const struct adreno_info a6xx_gpus[] = { }, .gmem = SZ_1M + SZ_512K, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | - ADRENO_QUIRK_HAS_HW_APRIV, + .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT | + ADRENO_FEAT_HAS_HW_APRIV, .init = a6xx_gpu_init, .a6xx = &(const struct a6xx_info) { .hwcg = a690_hwcg, @@ -1000,8 +1000,8 @@ static const struct adreno_info a6xx_gpus[] = { }, .gmem = SZ_512K, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | - ADRENO_QUIRK_HAS_HW_APRIV, + .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT | + ADRENO_FEAT_HAS_HW_APRIV, .init = a6xx_gpu_init, .zapfw = "a660_zap.mbn", .a6xx = &(const struct a6xx_info) { @@ -1028,7 +1028,7 @@ static const struct adreno_info a6xx_gpus[] = { }, .gmem = SZ_2M, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, + .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT, .init = a6xx_gpu_init, .zapfw = "a640_zap.mdt", .a6xx = &(const struct a6xx_info) { @@ -1046,8 +1046,8 @@ static const struct adreno_info a6xx_gpus[] = { }, .gmem = SZ_4M, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | - ADRENO_QUIRK_HAS_HW_APRIV, + .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT | + ADRENO_FEAT_HAS_HW_APRIV, .init = a6xx_gpu_init, .zapfw = "a690_zap.mdt", .a6xx = &(const struct a6xx_info) { @@ -1331,7 +1331,7 @@ static const struct adreno_info a7xx_gpus[] = { }, .gmem = SZ_128K, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_HW_APRIV, + .quirks = ADRENO_FEAT_HAS_HW_APRIV, .init = a6xx_gpu_init, .zapfw = "a702_zap.mbn", .a6xx = &(const struct a6xx_info) { @@ -1355,9 +1355,9 @@ static const struct adreno_info a7xx_gpus[] = { }, .gmem = SZ_2M, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | - ADRENO_QUIRK_HAS_HW_APRIV | - ADRENO_QUIRK_PREEMPTION, + .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT | + ADRENO_FEAT_HAS_HW_APRIV | + ADRENO_FEAT_PREEMPTION, .init = a6xx_gpu_init, .zapfw = "a730_zap.mdt", .a6xx = &(const struct a6xx_info) { @@ -1377,9 +1377,9 @@ static const struct adreno_info a7xx_gpus[] = { }, .gmem = 3 * SZ_1M, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | - ADRENO_QUIRK_HAS_HW_APRIV | - ADRENO_QUIRK_PREEMPTION, + .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT | + ADRENO_FEAT_HAS_HW_APRIV | + ADRENO_FEAT_PREEMPTION, .init = a6xx_gpu_init, .zapfw = "a740_zap.mdt", .a6xx = &(const struct a6xx_info) { @@ -1400,9 +1400,9 @@ static const struct adreno_info a7xx_gpus[] = { }, .gmem = 3 * SZ_1M, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | - ADRENO_QUIRK_HAS_HW_APRIV | - ADRENO_QUIRK_PREEMPTION, + .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT | + ADRENO_FEAT_HAS_HW_APRIV | + ADRENO_FEAT_PREEMPTION, .init = a6xx_gpu_init, .a6xx = &(const struct a6xx_info) { .hwcg = a740_hwcg, @@ -1422,9 +1422,9 @@ static const struct adreno_info a7xx_gpus[] = { }, .gmem = 3 * SZ_1M, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | - ADRENO_QUIRK_HAS_HW_APRIV | - ADRENO_QUIRK_PREEMPTION, + .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT | + ADRENO_FEAT_HAS_HW_APRIV | + ADRENO_FEAT_PREEMPTION, .init = a6xx_gpu_init, .zapfw = "gen70900_zap.mbn", .a6xx = &(const struct a6xx_info) { diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 019610341df1506c89f44e86b8d1deeb27d61857..2ebd3fac212576a1507e0b6afe2560cd0408dd89 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2478,7 +2478,7 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) adreno_gpu->gmu_is_wrapper = of_device_is_compatible(node, "qcom,adreno-gmu-wrapper"); adreno_gpu->base.hw_apriv = - !!(config->info->quirks & ADRENO_QUIRK_HAS_HW_APRIV); + !!(config->info->quirks & ADRENO_FEAT_HAS_HW_APRIV); /* gpu->info only gets assigned in adreno_gpu_init() */ is_a7xx = config->info->family == ADRENO_7XX_GEN1 || @@ -2495,7 +2495,7 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) } if ((enable_preemption == 1) || (enable_preemption == -1 && - (config->info->quirks & ADRENO_QUIRK_PREEMPTION))) + (config->info->quirks & ADRENO_FEAT_PREEMPTION))) ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs_a7xx, 4); else if (is_a7xx) ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs_a7xx, 1); diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index 9ffe91920fbfb4841b28aabec9fbde94539fdd83..09d4569f77528c2a20cabc814668c4c930dd07f1 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -207,7 +207,7 @@ static int adreno_bind(struct device *dev, struct device *master, void *data) priv->is_a2xx = info->family < ADRENO_3XX; priv->has_cached_coherent = - !!(info->quirks & ADRENO_QUIRK_HAS_CACHED_COHERENT); + !!(info->quirks & ADRENO_FEAT_HAS_CACHED_COHERENT); gpu = info->init(drm); if (IS_ERR(gpu)) { diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index e71f420f8b3a8e6cfc52dd1c4d5a63ef3704a07f..8782c25e8a393ec7d9dc23ad450908d039bd08c5 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -54,9 +54,10 @@ enum adreno_family { #define ADRENO_QUIRK_TWO_PASS_USE_WFI BIT(0) #define ADRENO_QUIRK_FAULT_DETECT_MASK BIT(1) #define ADRENO_QUIRK_LMLOADKILL_DISABLE BIT(2) -#define ADRENO_QUIRK_HAS_HW_APRIV BIT(3) -#define ADRENO_QUIRK_HAS_CACHED_COHERENT BIT(4) -#define ADRENO_QUIRK_PREEMPTION BIT(5) + +#define ADRENO_FEAT_HAS_HW_APRIV BIT(3) +#define ADRENO_FEAT_HAS_CACHED_COHERENT BIT(4) +#define ADRENO_FEAT_PREEMPTION BIT(5) /* Helper for formating the chip_id in the way that userspace tools like * crashdec expect. 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Wysocki" , Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , Simona Vetter , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Connor Abbott , linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1306; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=n7AjLch9953BuDVwIlWrOSl9FaavH+aib8ySJTyoxTo=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBnPNFYMO7EyC4T4TF/e7BGzAu0nBPzu5e8pKgbvKGl RBFXRhKJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZzzRWAAKCRB33NvayMhJ0fSpEA Cw3SShkE7iSaedv/beI78snfZ1LAHYcu9+c9tv42VvGDREihcCBoe3XopqonDAGrx1AXztqeSu5Pz+ 5wrYOc2TTfOSQO//QRHjDNpNPBO9tmrrnf3+aXTMDGlYNtcWpfvY21x7XjKdj4sc4wLzDYVZsehNec cdqKihmWrxbMJEQBWI7vOyDI62OVapFRm589i2jwA8etBaC62AV3fPT2qKkc+0saKe61lgjJLamTWu Uf6uBXvV2n9/ke2JNjgyAI13yG8Z9lumnXayLGTUU3rGmHIFYxev82ZAZpLQDtEeve7hZPQQnqz/c1 YGdOqxcxAK+w0edPQZiqakrPS2TgBCDC2WJwsOUrqmaowXOzhjTNH89iMJksIcc90rPQtSszCK3vib cS4+tweYJJhV0MWolbL0JMFJvaRoPLmCAuiIWY1j8M51AQgS8tn2cgivPmavajsqQhvluHFVrAEI4f 3I4o29J5dozRXWuvbuvyQEWQI6q05TpnAqq6WjYE0PW99ajcvEUXT+oU0+mMCbLl+P/sRYsAD3Niem 2IRU5SkNbdoDSWwa8XwxtIJzE3G+Yk7M33gUfGvqo4CQUhEq+M4c2FCTjTv8DyzmpYg5u8xHS7Fn/y nlVYppeOmQ0H3paslgGx62JPgrw+73piVyUILInwYQXVyoRZuDwY7wfzdTtg== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE The Adreno GMU Management Unit (GNU) can also scale the DDR Bandwidth along the Frequency and Power Domain level, but by default we leave the OPP core vote for the interconnect ddr path. While scaling via the interconnect path was sufficient, newer GPUs like the A750 requires specific vote paremeters and bandwidth to achieve full functionality. While the feature will require some data in a6xx_info, it's safer to only enable tested platforms with this flag first. Add a new feature enabling DDR Bandwidth vote via GMU. Signed-off-by: Neil Armstrong --- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index 4702d4cfca3b58fb3cbb25cb6805f1c19be2ebcb..394b96eb6c83354ae008b15b562bedb96cd391dd 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -58,6 +58,7 @@ enum adreno_family { #define ADRENO_FEAT_HAS_HW_APRIV BIT(0) #define ADRENO_FEAT_HAS_CACHED_COHERENT BIT(1) #define ADRENO_FEAT_PREEMPTION BIT(2) +#define ADRENO_FEAT_GMU_BW_VOTE BIT(3) /* Helper for formating the chip_id in the way that userspace tools like * crashdec expect. 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Wysocki" , Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , Simona Vetter , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Connor Abbott , linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2755; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=8YGZ9WKDiwlY9CXdycHEn+g53UomsCDyNV7cpV/GbpI=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBnPNFZkDlMgucCKOVG3spwNDcQZ0ZydMSrArihhW/Y vFgoe8OJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZzzRWQAKCRB33NvayMhJ0bjFD/ 9Mm8Si6vY3yrr2jLQmK9hIOxIo7VQGaygEeTkajDIJBFkFAFPQXGV5BNeb7ZEWXTXcNYlDIqs0qRb1 JOF/h1vPRq3pDdOEnG5JcF45su6IX9V935mkZDOhynF9D4dfaVySkMl8vSYI8PbBxLQSzj/vLcVd8o YGiWIm+8ZzZ5yT5UxZLeEeyjrBP5tOcyw6EmgiLf0snPQYsDadgXnpDO3+E71tmdcUHMsVGwJsEqTr g0uYhy3CsZK9eGEcyH3BvnjPQg2xP4ln6pEXC49Et1S9kpcpRzlZ6NPvBK5Li+TNX3GCL3eg3/ciUw 0x4TkUHAtlTQl2K7c/Ucm6rhadLnn8y86WWnlVepGCHZx1K3upgvczZbs/6mtob5xrp8xgfJWH/vbB BmTy+I6vhg+a9nle+Scw+KpcTF2L7UMam1Kiu4vKcXiniSHVO3GMwAp4845Mpc4PrwYiIofLS/0mUX zdMoAGfH8G7hzfQ/B4YNsXQAZ3cIuvC5XESP35Whkjtd635QbmeB6XFkhUrkofR6A8bY81WRuWltqP XuTJ4hq777J3vSZB/xSkBbj6T40vviF+j+CiwcJOLnja5qAYzgbmbi1jNRDstLj68//tK3vEU/gKW6 menmwvCUhLMg4vKU3j5zhTxgQRw3ZlwdCmTDWchXJnGvzssONP8cVOc1nQ/g== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE The Adreno GPU Management Unit (GMU) can also scale the ddr bandwidth along the frequency and power domain level, but for now we statically fill the bw_table with values from the downstream driver. Only the first entry is used, which is a disable vote, so we currently rely on scaling via the linux interconnect paths. Let's dynamically generate the bw_table with the vote values previously calculated from the OPPs. Those entried will then be used by the GMU when passing the appropriate bandwidth level while voting for a gpu frequency. Signed-off-by: Neil Armstrong --- drivers/gpu/drm/msm/adreno/a6xx_hfi.c | 39 ++++++++++++++++++++++++++++++++--- 1 file changed, 36 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c index cb8844ed46b29c4569d05eb7a24f7b27e173190f..0c8aa9f8cabe1d9cb20445a4274b728236a99fad 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c @@ -621,6 +621,36 @@ static void a740_build_bw_table(struct a6xx_hfi_msg_bw_table *msg) msg->cnoc_cmds_data[1][0] = 0x60000001; } +static void a740_generate_bw_table(struct adreno_gpu *adreno_gpu, struct a6xx_gmu *gmu, + struct a6xx_hfi_msg_bw_table *msg) +{ + const struct a6xx_info *info = adreno_gpu->info->a6xx; + unsigned int i, j; + + msg->ddr_wait_bitmask = 0x7; + + for (i = 0; i < 3; i++) { + if (!info->bcm[i].name) + break; + msg->ddr_cmds_addrs[i] = cmd_db_read_addr(info->bcm[i].name); + } + msg->ddr_cmds_num = i; + + for (i = 0; i < gmu->nr_gpu_bws; ++i) + for (j = 0; j < msg->ddr_cmds_num; j++) + msg->ddr_cmds_data[i][j] = gmu->gpu_bw_votes[i][j]; + msg->bw_level_num = gmu->nr_gpu_bws; + + /* TODO also generate CNOC commands */ + + msg->cnoc_cmds_num = 1; + msg->cnoc_wait_bitmask = 0x1; + + msg->cnoc_cmds_addrs[0] = cmd_db_read_addr("CN0"); + msg->cnoc_cmds_data[0][0] = 0x40000000; + msg->cnoc_cmds_data[1][0] = 0x60000001; +} + static void a6xx_build_bw_table(struct a6xx_hfi_msg_bw_table *msg) { /* Send a single "off" entry since the 630 GMU doesn't do bus scaling */ @@ -690,9 +720,12 @@ static int a6xx_hfi_send_bw_table(struct a6xx_gmu *gmu) a690_build_bw_table(msg); else if (adreno_is_a730(adreno_gpu)) a730_build_bw_table(msg); - else if (adreno_is_a740_family(adreno_gpu)) - a740_build_bw_table(msg); - else + else if (adreno_is_a740_family(adreno_gpu)) { + if ((adreno_gpu->info->features & ADRENO_FEAT_GMU_BW_VOTE) && gmu->nr_gpu_bws) + a740_generate_bw_table(adreno_gpu, gmu, msg); + else + a740_build_bw_table(msg); + } else a6xx_build_bw_table(msg); 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AJvYcCXcZww2kqsn9Ky+sYZ1wegf/sDaVa//I9BBL2hr6X7QBsU9xyMlkYYpl5vBibE1Ipu3gzt4JH6vfQ==@vger.kernel.org X-Gm-Message-State: AOJu0YzNMSzw1hdHvODh7Uo4iWx6mpMwCI8wQfjY4z8t7MX4gSodr5FA Tc0lro4gWwNHEYE+lexYHzTIesalVcicBeG65Ae+deDb0PeQIYDAHkBt4srYXYg= X-Google-Smtp-Source: AGHT+IETH0Hm2buMkvy/Ll4++F3Vi1yZx/qAIhcIkteGjWjEm1IVZlr1JHBK3iJywT3czzSrxctNNg== X-Received: by 2002:a05:600c:3491:b0:431:58bc:ad5e with SMTP id 5b1f17b1804b1-432df7901femr123471485e9.28.1732039015397; Tue, 19 Nov 2024 09:56:55 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432da27fe68sm208302275e9.24.2024.11.19.09.56.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Nov 2024 09:56:55 -0800 (PST) From: Neil Armstrong Date: Tue, 19 Nov 2024 18:56:43 +0100 Subject: [PATCH v2 08/11] drm/msm: adreno: request for maximum bus bandwidth usage Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241119-topic-sm8x50-gpu-bw-vote-v2-8-4deb87be2498@linaro.org> References: <20241119-topic-sm8x50-gpu-bw-vote-v2-0-4deb87be2498@linaro.org> In-Reply-To: <20241119-topic-sm8x50-gpu-bw-vote-v2-0-4deb87be2498@linaro.org> To: Akhil P Oommen , Viresh Kumar , Nishanth Menon , Stephen Boyd , "Rafael J. Wysocki" , Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , Simona Vetter , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Connor Abbott , linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1851; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=oXkj1C6Jx8yUMHy3C9MjrWlRZXnbo4AjWBLbi4B14uI=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBnPNFaHpmsc8d0QhqhvhKQzuhIHbOW/nweLHVI4J4K yOvheo2JAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZzzRWgAKCRB33NvayMhJ0a6wD/ wMgXLGer+Gwmpc2QXN/wUIVfxGxIJekwSowXEGKXdUnynbp8xruE7XqMXPRugx8J70wKaRkPVIDBAq YlvzhmgygfqOd99bB4cxv/m+LhYaB/sqeIpGxXxIFg9JUTmOww07+g5wSg8uS6g4x/6m/AE1QW6inw 6Vi/BiDDegOqKGTC04oXy/3wuJGJkjx/hLAsfoQnmKO6rNLc7nlepQN+a86EgENOC9uP5dWo51XxiH Qcw0D+UEhPz7Sywxlxx7/x7hYR42vAQ9XIZE6df2tJtl+qSn5RqVSdnuk+VpVOZeN5GLzycCdaAQZZ +BpzDDGet1cB9RPKolF1+3rtxHRPKGaf44xlgrXdngpLlCDX3feji1t2DqUyVLy26qj+wBGcF3yC62 5zcZUam9IXez+ZA6dmDUpWQ8bDHDUN8pH/tnJQ5NxqC5H2AUPhl6X7UgH1GVhn4wBI6oACdLFbfRLS cMR6fJTddxi7KPzvhhZo+GYeEA1oP/PnjjCSPMzGW/h+tSi/RVAGm5s/NBp+sO//57MwUqIIcmMYhO 74L35njgwh0bb2h+YhE8Sbonu83uTFPWOvTov/B+Qp8FRQOiZkHZnmAgPO6L5jvzvJUZhLOTrl/Tda bmMyLXaUOA/pQYp//Bky30nqQHwALOEFRZJO8MR5XVxt+ciFfsVHs8vCb7uQ== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE When requesting a DDR bandwidth level along a GPU frequency level via the GMU, we can also specify the bus bandwidth usage in a 16bit quantitized value. For now simply request the maximum bus usage. Signed-off-by: Neil Armstrong --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 11 +++++++++++ drivers/gpu/drm/msm/adreno/a6xx_hfi.h | 5 +++++ 2 files changed, 16 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c index dc2d0035544e7848e5c4ea27f1ea9a191f9c4991..36c0f67fd8e109aabf09a0804bacbed3593c39d7 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -134,6 +134,17 @@ void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp, if (bw == gmu->gpu_bw_table[bw_index]) break; } + + if (bw_index) { + /* + * Append AB vote to the maximum bus usage. + * AB represents a quantitized 16bit value of the + * max ddr bandwidth we could use, let's simply + * request the maximum for now. + */ + bw_index |= AB_VOTE(MAX_AB_VOTE); + bw_index |= AB_VOTE_ENABLE; + } } gmu->current_perf_index = perf_index; diff --git a/drivers/gpu/drm/msm/adreno/a6xx_hfi.h b/drivers/gpu/drm/msm/adreno/a6xx_hfi.h index 528110169398f69f16443a29a1594d19c36fb595..52ba4a07d7b9a709289acd244a751ace9bdaab5d 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_hfi.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_hfi.h @@ -173,6 +173,11 @@ struct a6xx_hfi_gx_bw_perf_vote_cmd { u32 bw; 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Tue, 19 Nov 2024 09:56:57 -0800 (PST) From: Neil Armstrong Date: Tue, 19 Nov 2024 18:56:45 +0100 Subject: [PATCH v2 10/11] arm64: qcom: dts: sm8550: add interconnect and opp-peak-kBps for GPU Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241119-topic-sm8x50-gpu-bw-vote-v2-10-4deb87be2498@linaro.org> References: <20241119-topic-sm8x50-gpu-bw-vote-v2-0-4deb87be2498@linaro.org> In-Reply-To: <20241119-topic-sm8x50-gpu-bw-vote-v2-0-4deb87be2498@linaro.org> To: Akhil P Oommen , Viresh Kumar , Nishanth Menon , Stephen Boyd , "Rafael J. Wysocki" , Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , Simona Vetter , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Connor Abbott , linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2162; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=xTy0814t50k26n3IdWEnCW6RpXe9FNt3pkGR9JMo8Wo=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBnPNFbd07WfUX+D3DO8S9DCJmtm3fmLCUXBbP0PPX5 yQHxYC6JAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZzzRWwAKCRB33NvayMhJ0dxhD/ 0eLXNGnWTLn0HhT5yDPUlg/ODVerSk5fLn5D0uGYbMNd6xHehmhMi7HzPEVFIlHAqzm0mbVZ8aXz3U xV7/qI2EAkv70rCMw9s269YKLo4UBvAc5DL0pflSy+gJaMeEPH3pCpCoRzVahSWTnYnfKEbUDTLaHV sO13U/ZkaHm4B3RCHbdglvwFS9kRz5Snqw/kXBzvsFTWhJfO25VsGiGE3iiWOtN3t8mKq19B59WCK1 aMzFlsensMqpdXOMPihgc3TkDXleatgpi6n+p/shVsUeyrxLvLp0LSxI0fiUCB3k/JDK/MiR4nKNeJ 9d9YgeuCEaPajGFk/H1MsfJ8HjjxPQhfLzrNcd51u+dJxlOOSqLXdWAfNDJFvqJWLd28yUSBeclw3j iGerbFp9eGbfn2PNDJgA73NmDT/e81goHVXesCs00ET40y5TPrcvq+PN1hZ6H4gYId4QVmNioMIu7Q cvFagAEBfgItx/18KTFIxatu6J8x/f4ZSetvCgU3e3tUgrHi5m2Av4bMoZkjn7pVnlycEXq2+bAbVy L8Pc8dHEGHh0+EZPumH9bYKCUiv85Odas2Mg7k0HrYcSRGIULlh7XMhc7j8Bi+o+KQLwc35xsj2+Pn eKCapM6aujBfwjSimn9B4NP0SvuYrtbyAe+AjnBKhhEEu3q6wf0JpwBD0LWA== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Each GPU OPP requires a specific peak DDR bandwidth, let's add those to each OPP and also the related interconnect path. Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 9dc0ee3eb98f8711e01934e47331b99e3bb73682..808dce3a624197d38222f53fffa280e63088c1c1 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -2113,6 +2113,9 @@ gpu: gpu@3d00000 { qcom,gmu = <&gmu>; #cooling-cells = <2>; + interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "gfx-mem"; + status = "disabled"; zap-shader { @@ -2126,41 +2129,49 @@ gpu_opp_table: opp-table { opp-680000000 { opp-hz = /bits/ 64 <680000000>; opp-level = ; + opp-peak-kBps = <16500000>; }; opp-615000000 { opp-hz = /bits/ 64 <615000000>; opp-level = ; + opp-peak-kBps = <16500000>; }; opp-550000000 { opp-hz = /bits/ 64 <550000000>; opp-level = ; + opp-peak-kBps = <12449218>; }; opp-475000000 { opp-hz = /bits/ 64 <475000000>; opp-level = ; + opp-peak-kBps = <8171875>; }; opp-401000000 { opp-hz = /bits/ 64 <401000000>; opp-level = ; + opp-peak-kBps = <6671875>; }; opp-348000000 { opp-hz = /bits/ 64 <348000000>; opp-level = ; + opp-peak-kBps = <6074218>; }; opp-295000000 { opp-hz = /bits/ 64 <295000000>; opp-level = ; + opp-peak-kBps = <6074218>; }; opp-220000000 { opp-hz = /bits/ 64 <220000000>; opp-level = ; + opp-peak-kBps = <6074218>; }; }; };