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All other ports (including USB super-speed pins) are unused. Set it up in the device tree together with the NXP PTN3222 repeater. Signed-off-by: Stephan Gerhold Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/x1e80100-crd.dts | 48 +++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts index 39f9d9cdc10d..44942931c18f 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts @@ -735,6 +735,26 @@ keyboard@3a { }; }; +&i2c5 { + clock-frequency = <400000>; + + status = "okay"; + + eusb6_repeater: redriver@4f { + compatible = "nxp,ptn3222"; + reg = <0x4f>; + #phy-cells = <0>; + + vdd3v3-supply = <&vreg_l13b_3p0>; + vdd1v8-supply = <&vreg_l4b_1p8>; + + reset-gpios = <&tlmm 184 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&eusb6_reset_n>; + pinctrl-names = "default"; + }; +}; + &i2c8 { clock-frequency = <400000>; @@ -1047,6 +1067,14 @@ edp_reg_en: edp-reg-en-state { bias-disable; }; + eusb6_reset_n: eusb6-reset-n-state { + pins = "gpio184"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; + hall_int_n_default: hall-int-n-state { pins = "gpio92"; function = "gpio"; @@ -1260,3 +1288,23 @@ &usb_1_ss2_dwc3_hs { &usb_1_ss2_qmpphy_out { remote-endpoint = <&pmic_glink_ss2_ss_in>; }; + +&usb_mp { + status = "okay"; +}; + +&usb_mp_dwc3 { + /* Limit to USB 2.0 and single port */ + maximum-speed = "high-speed"; + phys = <&usb_mp_hsphy1>; + phy-names = "usb2-1"; +}; + +&usb_mp_hsphy1 { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + phys = <&eusb6_repeater>; + + status = "okay"; +}; From patchwork Mon Nov 18 10:34:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephan Gerhold X-Patchwork-Id: 844160 Received: from mail-wr1-f46.google.com (mail-wr1-f46.google.com [209.85.221.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8FD1E17BB32 for ; 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Mon, 18 Nov 2024 02:34:36 -0800 (PST) Received: from [127.0.0.2] ([2a02:2454:ff21:ef40:5b7a:75b3:1e72:6e3d]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38245e95925sm3162979f8f.111.2024.11.18.02.34.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Nov 2024 02:34:36 -0800 (PST) From: Stephan Gerhold Date: Mon, 18 Nov 2024 11:34:30 +0100 Subject: [PATCH 2/2] arm64: defconfig: enable NXP PTN3222 eUSB2 to USB2 redriver driver Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241118-x1e80100-crd-fp-v1-2-ec6b553a2e53@linaro.org> References: <20241118-x1e80100-crd-fp-v1-0-ec6b553a2e53@linaro.org> In-Reply-To: <20241118-x1e80100-crd-fp-v1-0-ec6b553a2e53@linaro.org> To: Bjorn Andersson , Konrad Dybcio Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Abel Vesa , Johan Hovold X-Mailer: b4 0.13.0 It is used in many of the Qualcomm X1 Elite laptops for additional USB-A ports, USB fingerprint readers or similar peripherals. Signed-off-by: Stephan Gerhold --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 0b8303eb498d..8b17d70b3b58 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1530,6 +1530,7 @@ CONFIG_RESET_RZG2L_USBPHY_CTRL=y CONFIG_RESET_TI_SCI=y CONFIG_PHY_XGENE=y CONFIG_PHY_CAN_TRANSCEIVER=m +CONFIG_PHY_NXP_PTN3222=m CONFIG_PHY_SUN4I_USB=y CONFIG_PHY_CADENCE_TORRENT=m CONFIG_PHY_CADENCE_DPHY_RX=m