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([71.212.136.242]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-211d0f47adbsm32399055ad.223.2024.11.16.16.11.25 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 16 Nov 2024 16:11:26 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH RISU] risugen/aarch64: FCMP*Z* require rm == 0 Date: Sat, 16 Nov 2024 16:11:25 -0800 Message-ID: <20241117001125.497129-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Do not generate rm other than 0, as it is UNPREDICTABLE whether the instruction will trap as invalid. Signed-off-by: Richard Henderson --- aarch64.risu | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/aarch64.risu b/aarch64.risu index 87d9c72..bfea659 100644 --- a/aarch64.risu +++ b/aarch64.risu @@ -2632,14 +2632,14 @@ SHA256SU0 A64_V 0101 1110 sz:2 10100 00010 10 rn:5 rd:5 @DataProcessingScalarFP FCMPS A64_V 000 11110 00 1 rm:5 00 1000 rn:5 00 000 -FCMPZS A64_V 000 11110 00 1 rm:5 00 1000 rn:5 01 000 +FCMPZS A64_V 000 11110 00 1 00000 00 1000 rn:5 01 000 FCMPES A64_V 000 11110 00 1 rm:5 00 1000 rn:5 10 000 -FCMPEZS A64_V 000 11110 00 1 rm:5 00 1000 rn:5 11 000 +FCMPEZS A64_V 000 11110 00 1 00000 00 1000 rn:5 11 000 FCMPD A64_V 000 11110 01 1 rm:5 00 1000 rn:5 00 000 -FCMPZD A64_V 000 11110 01 1 rm:5 00 1000 rn:5 01 000 +FCMPZD A64_V 000 11110 01 1 00000 00 1000 rn:5 01 000 FCMPED A64_V 000 11110 01 1 rm:5 00 1000 rn:5 10 000 -FCMPEZD A64_V 000 11110 01 1 rm:5 00 1000 rn:5 11 000 +FCMPEZD A64_V 000 11110 01 1 00000 00 1000 rn:5 11 000 # Unallocated Encodings and ReservedValues FCMP_RES1 A64_V mos:3 11110 0 type:1 1 rm:5 00 1000 rn:5 opc:2 000 \