From patchwork Fri Nov 15 13:43:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 843770 Received: from mail-wr1-f50.google.com (mail-wr1-f50.google.com [209.85.221.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DA1DA1CD21C for ; Fri, 15 Nov 2024 13:44:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731678256; cv=none; b=Mb06CXVmWg1jU0sNsVS1Af2qEMwUXsiWQQzFf162aqc1ilR2Nj9lTeHL9TCpFRlhD2N/T27i9/9fRmqIVWMglJRwRLsZAg4SnhlsQEU5an0Hqp+z1ovNs5NtFH94r38xx0R4PSXcuLynI9W6Xn1noqbUBa1YC0ecMJv1HOQXkcw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731678256; c=relaxed/simple; bh=tXuRLP65pk0Y4kcWqeCQieYYW8KQLH1NVgss4OHIrGM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=V6bp+Dn+9aowKXqePTo/n0wV10Pw2Lk6LLrKXTiIWUZVuK6dgjbcY4NK9oKIjtqVXXbN0MzzRHqWCfPzqdIydbwsWACil+uamEfql5xQfZ5iSHDkrjAbV55QyS59cDtJ85WCrYdJmZFnML2zZ4kUsQ0Y9OGcLMTTM/QhEKzq1oA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=Z/ngXqMn; arc=none smtp.client-ip=209.85.221.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="Z/ngXqMn" Received: by mail-wr1-f50.google.com with SMTP id ffacd0b85a97d-37d3e8d923fso1289472f8f.0 for ; Fri, 15 Nov 2024 05:44:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1731678252; x=1732283052; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xVAv9/ONcMTOzGTP5wXiAVcgC8zzS7afKKpaMu2n2EA=; b=Z/ngXqMn9YUXPmpX7XCuwEiYf+6/Ma+p2LycwfHnXLQgKqmloI7ulYFqbpNa8HgUS6 9ehV2igh36YX4bsxOSU/zPYmDD75fGIo0LfuZ5q0wq2kvHg4BzrZHd/uHsn95jqbTMKK e4IQ5QWcTty/ZTrJyhiy2SL7jX8NyN+R5EXoEN++adAOgoV7cjZx0eSW+VixdaVqFqLl m/Tr3SDAFy2NaiMfsE9VFYabnLCIDWDSynfTfU5j1mac989dLBmNmEJ/eautDiZpP95Y +GAUSq3D+hZOKlS680pZyjuAquW53TkGq/FjI/ywlv/P2mgoojSyJfTSK8bfCo9l0WId 6TFA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731678252; x=1732283052; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xVAv9/ONcMTOzGTP5wXiAVcgC8zzS7afKKpaMu2n2EA=; b=L9eZSSxvGvAdZB4RZ65kbDn7AOazYtp33/0iv2ZdDF7pO/kNcR2g5LFZT6dnm7Mcgr mx7aF098YyyRKDAfNZCE5sOu4MgluWdPOKRxB5vVSopNXDLxfjVcC9A086dCIiLRw4gM NGf9Dy00lXyE369BkE1W/hHHkNJEVXa7iVrpuoKnRqEDhxFpw/AegJKm9jXv0Us7315u ANTXTcAtWqMtM2lz3jiz3/2Vu5d9nChCtFlu9EoMTpwMzMiYT9isS+tylka16iHT5nGK p4Grw7e/uwHUP0g7LNztb0LItN/LLg8vJziSDrkxcdMe2t/hYlqOCecyfsCJaI8bxvNk gCXQ== X-Forwarded-Encrypted: i=1; AJvYcCWkKtrkqLwrcxnhkCzsJyTPsuW9bmuDKkMNaDctPXMeXxF4hkgybXpEfkxb0dMYrDOk0Y8LSxcwnVr2bj4=@vger.kernel.org X-Gm-Message-State: AOJu0YxxRdY464IEqYronIHh8SL1MLKZm7sPncmLaUz8jtSeOEprkiOe UhPKdJLE1nCzlQfjKgm+1DiyKmC9pbB9GfWwpXYTpemhgFlR9JjWrMO6B59dF3A= X-Google-Smtp-Source: AGHT+IFIDOIXghS5KIj0k3ZbhD6JCey6zJvQ+3RcAsBVuLIPMWnrUGxM3x/f+/74OyXEXYZ28L8UNg== X-Received: by 2002:a5d:47a2:0:b0:37d:4ab2:9cdc with SMTP id ffacd0b85a97d-38225a06c76mr2335122f8f.13.1731678252132; Fri, 15 Nov 2024 05:44:12 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.28]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3821ada3fc9sm4378016f8f.20.2024.11.15.05.44.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Nov 2024 05:44:11 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, magnus.damm@gmail.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, gregkh@linuxfoundation.org, jirislaby@kernel.org, p.zabel@pengutronix.de, lethal@linux-sh.org, g.liakhovetski@gmx.de Cc: linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-serial@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v3 1/8] clk: renesas: r9a08g045: Add clock, reset and power domain for the remaining SCIFs Date: Fri, 15 Nov 2024 15:43:54 +0200 Message-Id: <20241115134401.3893008-2-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241115134401.3893008-1-claudiu.beznea.uj@bp.renesas.com> References: <20241115134401.3893008-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-serial@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea The Renesas RZ/G3S SoC has 6 SCIF interfaces. SCIF0 is used as debug console and is already enabled. Add the clock, reset and power domain support for the remaining ones. Signed-off-by: Claudiu Beznea --- Changes in v3: - none Changes in v2: - none drivers/clk/renesas/r9a08g045-cpg.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/clk/renesas/r9a08g045-cpg.c b/drivers/clk/renesas/r9a08g045-cpg.c index b2ae8cdc4723..da6dfffa089a 100644 --- a/drivers/clk/renesas/r9a08g045-cpg.c +++ b/drivers/clk/renesas/r9a08g045-cpg.c @@ -224,6 +224,11 @@ static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = { DEF_MOD("i2c2_pclk", R9A08G045_I2C2_PCLK, R9A08G045_CLK_P0, 0x580, 2), DEF_MOD("i2c3_pclk", R9A08G045_I2C3_PCLK, R9A08G045_CLK_P0, 0x580, 3), DEF_MOD("scif0_clk_pck", R9A08G045_SCIF0_CLK_PCK, R9A08G045_CLK_P0, 0x584, 0), + DEF_MOD("scif1_clk_pck", R9A08G045_SCIF1_CLK_PCK, R9A08G045_CLK_P0, 0x584, 1), + DEF_MOD("scif2_clk_pck", R9A08G045_SCIF2_CLK_PCK, R9A08G045_CLK_P0, 0x584, 2), + DEF_MOD("scif3_clk_pck", R9A08G045_SCIF3_CLK_PCK, R9A08G045_CLK_P0, 0x584, 3), + DEF_MOD("scif4_clk_pck", R9A08G045_SCIF4_CLK_PCK, R9A08G045_CLK_P0, 0x584, 4), + DEF_MOD("scif5_clk_pck", R9A08G045_SCIF5_CLK_PCK, R9A08G045_CLK_P0, 0x584, 5), DEF_MOD("gpio_hclk", R9A08G045_GPIO_HCLK, R9A08G045_OSCCLK, 0x598, 0), DEF_MOD("vbat_bclk", R9A08G045_VBAT_BCLK, R9A08G045_OSCCLK, 0x614, 0), }; @@ -249,6 +254,11 @@ static const struct rzg2l_reset r9a08g045_resets[] = { DEF_RST(R9A08G045_I2C2_MRST, 0x880, 2), DEF_RST(R9A08G045_I2C3_MRST, 0x880, 3), DEF_RST(R9A08G045_SCIF0_RST_SYSTEM_N, 0x884, 0), + DEF_RST(R9A08G045_SCIF1_RST_SYSTEM_N, 0x884, 1), + DEF_RST(R9A08G045_SCIF2_RST_SYSTEM_N, 0x884, 2), + DEF_RST(R9A08G045_SCIF3_RST_SYSTEM_N, 0x884, 3), + DEF_RST(R9A08G045_SCIF4_RST_SYSTEM_N, 0x884, 4), + DEF_RST(R9A08G045_SCIF5_RST_SYSTEM_N, 0x884, 5), DEF_RST(R9A08G045_GPIO_RSTN, 0x898, 0), DEF_RST(R9A08G045_GPIO_PORT_RESETN, 0x898, 1), DEF_RST(R9A08G045_GPIO_SPARE_RESETN, 0x898, 2), @@ -306,6 +316,16 @@ static const struct rzg2l_cpg_pm_domain_init_data r9a08g045_pm_domains[] = { DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(13)), 0), DEF_PD("scif0", R9A08G045_PD_SCIF0, DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(1)), 0), + DEF_PD("scif1", R9A08G045_PD_SCIF1, + DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(2)), 0), + DEF_PD("scif2", R9A08G045_PD_SCIF2, + DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(3)), 0), + DEF_PD("scif3", R9A08G045_PD_SCIF3, + DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(4)), 0), + DEF_PD("scif4", R9A08G045_PD_SCIF4, + DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(5)), 0), + DEF_PD("scif5", R9A08G045_PD_SCIF5, + DEF_REG_CONF(CPG_BUS_MCPU3_MSTOP, BIT(4)), 0), DEF_PD("vbat", R9A08G045_PD_VBAT, DEF_REG_CONF(CPG_BUS_MCPU3_MSTOP, BIT(8)), GENPD_FLAG_ALWAYS_ON), From patchwork Fri Nov 15 13:43:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 843769 Received: from mail-wm1-f52.google.com (mail-wm1-f52.google.com [209.85.128.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E34C71D4604 for ; Fri, 15 Nov 2024 13:44:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731678260; cv=none; b=lPDK8J/91pp3/B6rwmDoZrdi74h7Y/wYVdb3IWUpen9KCe1eSSddediXSz3FFso4YQ9iR+eAQ5vSuk5zuxdlluaizJUEmkHvnymrGIsozN212Fofrbzqgf3ZQCn5RZn6/pDK1cpnqdxo6ZeMYt7i+N/upBzk8Y1Mz51bGLkktLk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731678260; c=relaxed/simple; bh=cvXLylORKw894oxYTuEZeViXynITomEuscveNdNCxgQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=eiquyn35+Nl0g4hQT/Z7GAdsEE05xdP1RmeLu/tMpfSZhD1v07z3wcYukFeqbmUS9reYpPanQ0MirqScA1MAsHSGtkIp3AmjbRhwHygx1Tf5m82hBUra8f2BOWvZr8bHR7Q9WCPWnqgoN9dwrtFHXlAdhEQXT3DlIZBcXauTR+0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=keO9F3W+; arc=none smtp.client-ip=209.85.128.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="keO9F3W+" Received: by mail-wm1-f52.google.com with SMTP id 5b1f17b1804b1-4316cce103dso19482585e9.3 for ; Fri, 15 Nov 2024 05:44:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1731678256; x=1732283056; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QflYe9Uttnm4Ku+Zy3VUc0FNhJJkvv+YuMrekm3fOjY=; b=keO9F3W+nVGZMNuY9V21Pj8J3bkho7f9utN5jPPVrY2g9srF3vAgjhXs7ZnLKVb7qN GMGzYuClPBl+WGjPcqmSGTZDCghwYsV7P2U/9vbzEfv1vg6Yz4Sbl6oENNKszIlXKsnw JJ+r9HVVBkQeMYDOHuQQMXiSxA1J8TOvqIJdEXsiHhYq7J13VVOda6RBiMPWnNC6GG90 fIrX3BGV3pWaSqpTv8dVt3ZY6EiDBVtBAc0fjNuEBe4G/aMnNrkQ2ef4lzagcmw8XZlZ DcI2BcPdR4anOiJcVDEJCvH2qx88lXffgL3HPylpMjvRG4escJAWsW6IzUp/u0lJr3id USBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731678256; x=1732283056; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QflYe9Uttnm4Ku+Zy3VUc0FNhJJkvv+YuMrekm3fOjY=; b=TwM48fLJq5F78u92jCVRFMZBFQww6QoSZ5fcM3Z9AoLgk4vlxQq9opJjjjs2qj0NFp 3J3TBMqkxbqstrkqRU5qOKydjiBYwUXGoNQJ2XigucU6i58AXUBBpFpL5wxtGCzDpCzY pKDnOxAJRZWbrhiCqJ3bSys8sX2BfWMcenfkHukLqLLs5IbSJHtOV1VD/V5ihFSTdZCZ h+eelomQ7nAhahiaLFaB7JyDgidUuM3s7ebvYK1gjn/WESTY0ykaSpXQQ0NPgnCqw93X 8ZqxlmkEA8HK5kZqwoS99sFi2V+MSN8YMNZKaO/2lWMyVMrMO8CdRS363n7Bf4zmhZyG 2w+A== X-Forwarded-Encrypted: i=1; AJvYcCUo4dXL9T+iGvCrZ5rmFJemx+l3QiwELS7sfHOKYy/W1UBcLPoTLStBqMYjO4WPSHepdfhwKGhadc7oaQA=@vger.kernel.org X-Gm-Message-State: AOJu0YwDiaoqRex3WCFuQIIyCw7WeNXF3eQ6U3oKq4GkStRPq0vCob7d VMhzLjwlbkHGBkXaR9XrDtD8avPsZHA+nGdyx/8X/lz/EYyXzg1V899FwKArruA= X-Google-Smtp-Source: AGHT+IEsR7G1hgK+fmAed/LYpCR8sEfBfQmvxReRtCLi1L0/hyDVglC8dL6z2/8gYOyTa/fuZVe4iw== X-Received: by 2002:a05:6000:18af:b0:37d:7e71:67a0 with SMTP id ffacd0b85a97d-38225a21d40mr2940930f8f.9.1731678256207; Fri, 15 Nov 2024 05:44:16 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.28]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3821ada3fc9sm4378016f8f.20.2024.11.15.05.44.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Nov 2024 05:44:15 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, magnus.damm@gmail.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, gregkh@linuxfoundation.org, jirislaby@kernel.org, p.zabel@pengutronix.de, lethal@linux-sh.org, g.liakhovetski@gmx.de Cc: linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-serial@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v3 3/8] serial: sh-sci: Update the suspend/resume support Date: Fri, 15 Nov 2024 15:43:56 +0200 Message-Id: <20241115134401.3893008-4-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241115134401.3893008-1-claudiu.beznea.uj@bp.renesas.com> References: <20241115134401.3893008-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-serial@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea The Renesas RZ/G3S supports a power saving mode where power to most of the SoC components is turned off. When returning from this power saving mode, SoC components need to be re-configured. The SCIFs on the Renesas RZ/G3S need to be re-configured as well when returning from this power saving mode. The sh-sci code already configures the SCIF clocks, power domain and registers by calling uart_resume_port() in sci_resume(). On suspend path the SCIF UART ports are suspended accordingly (by calling uart_suspend_port() in sci_suspend()). The only missing setting is the reset signal. For this assert/de-assert the reset signal on driver suspend/resume. In case the no_console_suspend is specified by the user, the registers need to be saved on suspend path and restore on resume path. To do this the sci_console_setup() function was added. There is no need to cache/restore the status or FIFO registers. Only the control registers. To differentiate b/w these, the struct sci_port_params::regs was updated with a new member that specifies if the register needs to be chached on suspend. Only the RZ_SCIFA instances were updated with this new support as the hardware for the rest of variants was missing for testing. Signed-off-by: Claudiu Beznea --- Changes in v3: - none Changes in v2: - rebased on top of the update version of patch 2/8 from this series drivers/tty/serial/sh-sci.c | 53 ++++++++++++++++++++++++++++++------- 1 file changed, 44 insertions(+), 9 deletions(-) diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c index ade151ff39d2..e53496d2708e 100644 --- a/drivers/tty/serial/sh-sci.c +++ b/drivers/tty/serial/sh-sci.c @@ -101,7 +101,7 @@ enum SCI_CLKS { if ((_port)->sampling_rate_mask & SCI_SR((_sr))) struct plat_sci_reg { - u8 offset, size; + u8 offset, size, suspend_cacheable; }; struct sci_port_params { @@ -134,6 +134,8 @@ struct sci_port { struct dma_chan *chan_tx; struct dma_chan *chan_rx; + struct reset_control *rstc; + #ifdef CONFIG_SERIAL_SH_SCI_DMA struct dma_chan *chan_tx_saved; struct dma_chan *chan_rx_saved; @@ -153,6 +155,7 @@ struct sci_port { int rx_trigger; struct timer_list rx_fifo_timer; int rx_fifo_timeout; + unsigned int console_cached_regs[SCIx_NR_REGS]; u16 hscif_tot; bool has_rtscts; @@ -298,17 +301,17 @@ static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = { */ [SCIx_RZ_SCIFA_REGTYPE] = { .regs = { - [SCSMR] = { 0x00, 16 }, - [SCBRR] = { 0x02, 8 }, - [SCSCR] = { 0x04, 16 }, + [SCSMR] = { 0x00, 16, 1 }, + [SCBRR] = { 0x02, 8, 1 }, + [SCSCR] = { 0x04, 16, 1 }, [SCxTDR] = { 0x06, 8 }, [SCxSR] = { 0x08, 16 }, [SCxRDR] = { 0x0A, 8 }, - [SCFCR] = { 0x0C, 16 }, + [SCFCR] = { 0x0C, 16, 1 }, [SCFDR] = { 0x0E, 16 }, - [SCSPTR] = { 0x10, 16 }, + [SCSPTR] = { 0x10, 16, 1 }, [SCLSR] = { 0x12, 16 }, - [SEMR] = { 0x14, 8 }, + [SEMR] = { 0x14, 8, 1 }, }, .fifosize = 16, .overrun_reg = SCLSR, @@ -3380,6 +3383,7 @@ static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev, } sp = &sci_ports[id]; + sp->rstc = rstc; *dev_id = id; p->type = SCI_OF_TYPE(data); @@ -3507,13 +3511,34 @@ static int sci_probe(struct platform_device *dev) return 0; } +static void sci_console_setup(struct sci_port *s, bool save) +{ + for (u16 i = 0; i < SCIx_NR_REGS; i++) { + struct uart_port *port = &s->port; + + if (!s->params->regs[i].suspend_cacheable) + continue; + + if (save) + s->console_cached_regs[i] = sci_serial_in(port, i); + else + sci_serial_out(port, i, s->console_cached_regs[i]); + } +} + static __maybe_unused int sci_suspend(struct device *dev) { struct sci_port *sport = dev_get_drvdata(dev); - if (sport) + if (sport) { uart_suspend_port(&sci_uart_driver, &sport->port); + if (!console_suspend_enabled && uart_console(&sport->port)) + sci_console_setup(sport, true); + else + return reset_control_assert(sport->rstc); + } + return 0; } @@ -3521,8 +3546,18 @@ static __maybe_unused int sci_resume(struct device *dev) { struct sci_port *sport = dev_get_drvdata(dev); - if (sport) + if (sport) { + if (!console_suspend_enabled && uart_console(&sport->port)) { + sci_console_setup(sport, false); + } else { + int ret = reset_control_deassert(sport->rstc); + + if (ret) + return ret; + } + uart_resume_port(&sci_uart_driver, &sport->port); + } return 0; } From patchwork Fri Nov 15 13:43:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 843768 Received: from mail-wr1-f45.google.com (mail-wr1-f45.google.com [209.85.221.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9A6881D5165 for ; Fri, 15 Nov 2024 13:44:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731678263; cv=none; b=IQIvL2eb2Up5visyFpIivSnWLOOKif5SNHmnarMxPE6JAGsY0AzYs+pYRDNi8whl5cOLMISddbaj0MZUp7d4sQ8+JQgpcDSzTeIpzHkBJU7+lldvCqytTaav45+YQ6A02lx46XiNpEVer6LT61ePRFcqkoYDIbvoELteC8zvuVg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731678263; c=relaxed/simple; bh=wtEJOHWb57zTAiri+QKgQmXTlVnXlZ7+4fhBUT3i/40=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ZcI2DjoXJ2yB2lUroLVzRuDs8Tx7APh7gjryDg38oO5g1IHWPTzF4B76eEEJG7zhmgYaxc2IFvUmIXCdYz+eUyCBUelu9GJ2yIrNY+hm9D4qKS9p95rvHFp7QnCO0Kme+cdq8azs8E/7TAtSBSFXQqS8Qu38lqM1jZaFBDAim8E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=lubXZk1Z; arc=none smtp.client-ip=209.85.221.45 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="lubXZk1Z" Received: by mail-wr1-f45.google.com with SMTP id ffacd0b85a97d-3821c81f165so1557639f8f.3 for ; Fri, 15 Nov 2024 05:44:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1731678260; x=1732283060; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Y+YZBVsJh/VAUGpi27AVY3ok+hT+IMM3cBf29hG05qA=; b=lubXZk1Zw5kX3u1zKHF4nCSltamqcgiPkhXREvA89U2bxDFodJKhXEYbUYrgqwcrFu Od85TqB7HJpDw10X/LeLKGi/sdamDhe3xamaCz79D3ai4y0/F0go/PgiWO2MuZyV15V7 Em2Oh55hRWb5rBD04ge0KzxINKMhIHi+JdIstshvhlf5NUGJl013BwJIsg76Z06hKc1Y V3fEbECo6MIyXm8KxgXjlwubw1lu2iR+c/4tPmfseQtDOeqIYo5V+0iUKfFC5r0UCXpb ybz/DocitE6UBKFZJQg5ItMXIPTzxtddWrYf2idLxIDsoBob/YCNJjkYWGC0O0TdCH9I /pOQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731678260; x=1732283060; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Y+YZBVsJh/VAUGpi27AVY3ok+hT+IMM3cBf29hG05qA=; b=NKVoZzebIIpb+hQg8MxnCvaUeMQCvoZ3aXMyUCOyFxaTAFc5f+L1bysLu9v0Omx5AF zdkpRysXXBgP8Ru/e8ckLYk3js5TFxGxa+gBTWJA6P4MYmvUS73dVsea7g2KFHHu/5IE dV08Z/dTDXg0CvsEc213MNG9xc12R5rhSycCE3II4tRpQRqndsgBSF4MR7IRBEreCruM r1nVoioaNsO3E3m6c5IpDcfm03hXNS8OUtexmg0ezEckFon9KRVmIDZ5yTgwK40LDWjB LZjWMm+F7P1FN6s7SUKntlInuYNsWIgxtKf5w+8P1UEae7up4xIKCpypCycBT0Eabo+0 aFoA== X-Forwarded-Encrypted: i=1; AJvYcCXjItRQBOStbJbsLwHtSCBJyunCwf7J5WVMeSFRXMPZbMkBaECK2VHyUALRCbXurbF0OCFGAxYdjqFBRoA=@vger.kernel.org X-Gm-Message-State: AOJu0YyBm3rOjIYcE4MUmNLiX9I00qdivxZmBwWgrEIHmmDznarM/14m 2UPFqRYUOIcfDjYmINL2KQ8KxNNUM92WOx3u3g6k/gk8dkH7oewIJ80ThbVV88E= X-Google-Smtp-Source: AGHT+IG+ynyyYjZn6sC7e7CuEgzQ8b+B6wg20HRVZIxHAkl7FPzEzqPlVzLenjKMoEK/3eaNxUgqNA== X-Received: by 2002:a05:6000:1ac7:b0:37d:5359:6753 with SMTP id ffacd0b85a97d-38225a41fb8mr2761194f8f.15.1731678260009; Fri, 15 Nov 2024 05:44:20 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.28]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3821ada3fc9sm4378016f8f.20.2024.11.15.05.44.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Nov 2024 05:44:19 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, magnus.damm@gmail.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, gregkh@linuxfoundation.org, jirislaby@kernel.org, p.zabel@pengutronix.de, lethal@linux-sh.org, g.liakhovetski@gmx.de Cc: linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-serial@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v3 5/8] arm64: dts: renesas: rzg3s-smarc: Fix the debug serial alias Date: Fri, 15 Nov 2024 15:43:58 +0200 Message-Id: <20241115134401.3893008-6-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241115134401.3893008-1-claudiu.beznea.uj@bp.renesas.com> References: <20241115134401.3893008-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-serial@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea The debug serial of the RZ/G3S is SCIF0 which is routed on the Renesas RZ SMARC Carrier II board on the SER3_UART. Use serial3 alias for it for better hardware description. Along with it, the chosen properties were moved to the device tree corresponding to the RZ SMARC Carrier II board. Fixes: adb4f0c5699c ("arm64: dts: renesas: Add initial support for RZ/G3S SMARC SoM") Fixes: d1ae4200bb26 ("arm64: dts: renesas: Add initial device tree for RZ SMARC Carrier-II Board") Signed-off-by: Claudiu Beznea --- Changes in v3: - none Changes in v2: - none arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi | 5 ----- arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi | 7 ++++++- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi index 2ed01d391554..55c72c8a0735 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi @@ -43,11 +43,6 @@ aliases { #endif }; - chosen { - bootargs = "ignore_loglevel"; - stdout-path = "serial0:115200n8"; - }; - memory@48000000 { device_type = "memory"; /* First 128MB is reserved for secure area. */ diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi index 4509151344c4..33b9873b225a 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi @@ -12,10 +12,15 @@ / { aliases { i2c0 = &i2c0; - serial0 = &scif0; + serial3 = &scif0; mmc1 = &sdhi1; }; + chosen { + bootargs = "ignore_loglevel"; + stdout-path = "serial3:115200n8"; + }; + keys { compatible = "gpio-keys"; From patchwork Fri Nov 15 13:44:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 843767 Received: from mail-wm1-f50.google.com (mail-wm1-f50.google.com [209.85.128.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0FB101D5CCC for ; Fri, 15 Nov 2024 13:44:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731678267; cv=none; b=QuETQxmGibUpoUIZ49t2S8KIHYZ4NKlHg/bwZ8Y37HQVyGX6AXdiU/i2YoLpZJdh+MFSpZoHuIlL02Ne3KYMtN72ykjzC7yPIbHWQRwR973mSPzXXf5GcjOcW0Eo+skmLHXn3lcRMUTDn7KMxlc+TWP4RNiyfy7GofrEU1x5vNs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731678267; c=relaxed/simple; bh=LrCs+Ft93mkejJjJfAZXNdagefh5tGGc4YtY6FNYOrg=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=UUZnJpGPc6c0okTOzdXmEIjCYaSLGqdwBXuN0k7qtkSkW5vVBWBtdR/btavUf/9AJxq27pHfLzIgYbAN3VEeY5lvcENKCf558NVWN3GwrmLC3x+I+QOs2Fkeq8x92REz5MJTCflLeTiuvOQASc/G3E/NqijL1cjajWBIFqEdmQY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=d47pbgHn; arc=none smtp.client-ip=209.85.128.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="d47pbgHn" Received: by mail-wm1-f50.google.com with SMTP id 5b1f17b1804b1-4315baa51d8so5896185e9.0 for ; Fri, 15 Nov 2024 05:44:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1731678264; x=1732283064; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wbikK54OyStuo16iZrOIOl8rBYONkOS/JF88KYtuMkg=; b=d47pbgHn8v+kjUS8Dq7DO6zGQ1KQMsW8yLiNrwqzfU+m0WirSU/Uh9Q42sP/ddZQb0 ceaRbwRTP0XirehB9tkzHOvOzHbFM+ujatYB2u3qvwYBEA/1uihIUGU0QI3y6IUuNmYO JZfQWalOLMPv6xlEAXjr8RhIAaSKpDGUD/k9yUfvwxInsP1a5Kg79Dl244rwxSWmAi6k FPBz5qcYpLJTv6R/TTMtohI6QzPycYiRejLAxfFCqsPR3AUhGHuIQ83OGxP4tZukyZs/ c9bka1dkJTVEfUEDtB7kS6gfPw0eSKKwJ+zYIUyjQRq8zr5K6eVrD2OaeV9wUQt/+uh5 wyXA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731678264; x=1732283064; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wbikK54OyStuo16iZrOIOl8rBYONkOS/JF88KYtuMkg=; b=KwBqsH/KCer7WN9YgOHHX6Ki2f/uJHIHmg7kmseuIwLT2DrC9g9QaxFEl0McxA7mwt 7gCPnHifNED0DnCZ+ygtg3ojQP4Jn5f/1MiKGYxQDRTNjN+rUN0GY23uoBitIaYWJ7V7 9JxOALFqdbYv6FCobO2hNitYH0ck1hNBKhV9oOAMysRqpW4GKyBI36Q3xnFwY14WXKqi OM29e8f4JHzxFhHZ+sE5yazaoQ/wUs5rd+Oj8S01bbd+Bz8xTZhM+xrihuZEvL34Pvq9 +ABHpxRZagxIpL+5YHNIfLpgqajO1msiPTv+OHlBq5KGT3Kc1Op/LNlvOcIVFBx2dzhK 7Yjg== X-Forwarded-Encrypted: i=1; AJvYcCVKJB/UNMvBHNrJWH7tYMdjNG8+aKR6Yw2obbl42R2egLdqw67OV06kkKBIdKQs5hgtpgjehmymKAHC58Q=@vger.kernel.org X-Gm-Message-State: AOJu0YzA2+5YKsXcvWnoM07MAeWilRvyQvAVzNn5dxaXRil/J5avC44S BCk0/jJqVgS9AqZ6mQ0R1gLNgQaBvC6AZqOjDlDZU44j5RMcw6crtBiBP58tXRE= X-Google-Smtp-Source: AGHT+IGrZltzKer/dm8m8qYDs7z7mwJoTu/1frSmXqBSSagNZ5FvyYqOjugYq2GKqHZ+Vm6ZI9Uk1Q== X-Received: by 2002:a05:600c:3aca:b0:432:c774:2e24 with SMTP id 5b1f17b1804b1-432df72514fmr22784765e9.9.1731678264401; Fri, 15 Nov 2024 05:44:24 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.28]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3821ada3fc9sm4378016f8f.20.2024.11.15.05.44.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Nov 2024 05:44:23 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, magnus.damm@gmail.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, gregkh@linuxfoundation.org, jirislaby@kernel.org, p.zabel@pengutronix.de, lethal@linux-sh.org, g.liakhovetski@gmx.de Cc: linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-serial@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v3 7/8] arm64: dts: renesas: rzg3s-smarc: Enable SCIF3 Date: Fri, 15 Nov 2024 15:44:00 +0200 Message-Id: <20241115134401.3893008-8-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241115134401.3893008-1-claudiu.beznea.uj@bp.renesas.com> References: <20241115134401.3893008-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-serial@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Enable SCIF3. It is routed on the RZ SMARC Carrier II board on SER1_UART interface. Signed-off-by: Claudiu Beznea --- Changes in v3: - none Changes in v2: - none arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi index 33b9873b225a..1be21ece131e 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi @@ -9,9 +9,14 @@ #include #include +#include "rzg3s-smarc-switches.h" + / { aliases { i2c0 = &i2c0; +#if SW_CONFIG3 == SW_ON + serial1 = &scif3; +#endif serial3 = &scif0; mmc1 = &sdhi1; }; @@ -102,6 +107,11 @@ scif0_pins: scif0 { ; /* TXD */ }; + scif3_pins: scif3 { + pinmux = , /* RXD */ + ; /* TXD */ + }; + sdhi1_pins: sd1 { data { pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3"; @@ -141,6 +151,14 @@ &scif0 { status = "okay"; }; +#if SW_CONFIG3 == SW_ON +&scif3 { + pinctrl-names = "default"; + pinctrl-0 = <&scif3_pins>; + status = "okay"; +}; +#endif + &sdhi1 { pinctrl-0 = <&sdhi1_pins>; pinctrl-1 = <&sdhi1_pins_uhs>;