From patchwork Fri Nov 15 15:20:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 843493 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcc:0:b0:382:184f:390f with SMTP id e12csp898269wrc; Fri, 15 Nov 2024 07:21:38 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCUaVNvYGAQWtTp3tmf7DD3pehQ+3D+MVBK0E71IuppYrvFJpAXsQKWlXQI11RmPRcYfOjBJTg==@linaro.org X-Google-Smtp-Source: AGHT+IEXngajN+exe16VKZdbGkXNNsDOgwfEtyiO5/SCzSj5qRd0eMb9yL5GYKYf+vugdKPOmGZ2 X-Received: by 2002:a05:6830:660d:b0:703:fdda:fe2b with SMTP id 46e09a7af769-71a77936012mr3336804a34.11.1731684098024; Fri, 15 Nov 2024 07:21:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1731684097; cv=none; d=google.com; s=arc-20240605; b=j1oqFdLYSV6ELrA3RrPw135BY6hXKAQrbjuYnQ1UmRDFAZm1aVAdI8xOTkYjwgXcxL CMsbV5JgGFkB0tsyhAFxyBMl1D5qwNdYKvrgCv7e2La9RbENlHtxe4BlncvN4UHgOYjp Z49HzcBLg3ibAE2lnphabJrGdTD3XfgDISc9EyOOADnnye4TQupel1Hw37j7/OhxSSct DhI60hTP7w+oI/L/lsvjenP+MDQyF5ccIxDB1gFWkokZ2lnjMQRFvrIXpvkTnHyFwrkG 18bw8ZobMvEGTWn3gvfkq2GyUQ4JYMH0tow+nlLo2rSrHsIIxa6sk5uqytGH1AtriGFx YSaw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=ZHhL6wb85s4vVZ9BFDdlVsTHRSAYWS3+Ku4UPdQPugs=; fh=ZXDWg7hKG7Hj19AbRuutTLw+Zvn/B9RsGUUw/YagpFI=; b=Ur0yb8rcxGOrtXkw3XQ2K+TkbSnymFpCKNHA58dvJ5eUJV1vFcrFJr7NI7AX/a/Wtg XkcmFlipWB9N329XqLrCj7iVHIZl3EXazljLKSdH6QYZXPdT7Qup57w7Z+HkyQpx3CWX 8BfXvvab1X+QYUlZdUtfKK/qzC1flZrDtb6TME1KxfK1ZeA7swgws3PXsRDXyjLHB209 NZlzC8md7cOjUJNSPXU9YyDAVp8ZuCLPts4Hpb5cFtqWkzL8k4/7CB0o8ixetuDH5mXu kqOp476oQsbmuLGxPnESn57DY1kl2bDMllcZyTWfYd2gJmg5jffD5dLTsMzBuOhfbpds pfaw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kwQghvE4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id ada2fe7eead31-4ad646f7d2bsi462352137.127.2024.11.15.07.21.37 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 15 Nov 2024 07:21:37 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kwQghvE4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tBy8C-0001nN-1M; Fri, 15 Nov 2024 10:21:08 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tBy89-0001nD-W6 for qemu-devel@nongnu.org; Fri, 15 Nov 2024 10:21:06 -0500 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tBy87-00043e-MT for qemu-devel@nongnu.org; Fri, 15 Nov 2024 10:21:05 -0500 Received: by mail-wm1-x329.google.com with SMTP id 5b1f17b1804b1-4315df7b43fso16214175e9.0 for ; Fri, 15 Nov 2024 07:21:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1731684061; x=1732288861; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ZHhL6wb85s4vVZ9BFDdlVsTHRSAYWS3+Ku4UPdQPugs=; b=kwQghvE43+ZoRdzJTiKU8xE0miAcJaXEO0apx7YYj66PN0B3Zhm+Ajn0geIZIGdyAX dWekkX5+xj0wnXUt8XSvBdH7BHKa//s5AXkPUFQa//AphWcyfoe2ebtyx7t6p8JTw7lK LyVU0WzXchJYc0rnZDmDmzgj3/2gGPxnUu5xB3sK0DjE/ndsnO9B+V5mqR+g0yOYhFJ/ JXoTV+RjEnm8mQmdK1q0cl/Uj/JiaRtPtrejjPR2curnpW5gkzd2xzySgfAw4QvRKXFN BB9GNtQzW/75aBSqYHGpBAf8wADo81CqaxLY1U1expkcTIJAqCFOcuicxZ3BjrlPnYl5 Tllw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731684061; x=1732288861; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZHhL6wb85s4vVZ9BFDdlVsTHRSAYWS3+Ku4UPdQPugs=; b=ai8sWhkaQCm+JgUlPT/so9PNIIHnLyawcfOxhW6md38deWPb9WnnXkc49ZEYHpFR0H PQuFjXlc6j263i7th4yKZ0xlRkaHIKPlVXiB8czMrOd66qP8QQeF0xzlte3bkJ+BgIVy Q7nm6Pet0B1iClArzOj1W3JSbpdU1pOam9JizQ1cGPjw3EpGI41cnpcPsUZyothJ18Ik q/yBsUUGYNP3TXZC4R8qq8+QPlRRZjwQssM519VltRykDDeA50qNXN+qoBb2rST0kx2e 6hlTBzdHEH+Zne07wHPoUdRDa4WTNw0qDu4XiF/znmzuH8fubLJVFT/7BLH7mKg5AAua 1v0g== X-Gm-Message-State: AOJu0Yy9INRXZcC1GweCOhjgdqapyiF2N+hWVpHkP3z4eC/BcxV3C04a ZXXU+TDertlrAgIIUi0RB3c0EdIMTvc4aypnHe9rpxBhoQ4yyhnL/8mxPBZsQpOFa5gUSVxH9zZ 5 X-Received: by 2002:a05:600c:1382:b0:431:5d4f:73a3 with SMTP id 5b1f17b1804b1-432df74f0d4mr23861875e9.18.1731684060699; Fri, 15 Nov 2024 07:21:00 -0800 (PST) Received: from localhost.localdomain ([176.187.214.209]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432dab721d7sm58337185e9.9.2024.11.15.07.20.59 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 15 Nov 2024 07:21:00 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= Subject: [PATCH 01/10] target/mips: Drop left-over comment about Jazz machine Date: Fri, 15 Nov 2024 16:20:44 +0100 Message-ID: <20241115152053.66442-2-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241115152053.66442-1-philmd@linaro.org> References: <20241115152053.66442-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=philmd@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Commit 3803b6b427 ("target/mips: Fold jazz behaviour into mips_cpu_do_transaction_failed") removed update on TCGCPUOps and commit 119065574d ("hw/core: Constify TCGCPUOps") made it const. Remove the now irrelevant comment. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell Reviewed-by: Richard Henderson --- target/mips/cpu.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/target/mips/cpu.c b/target/mips/cpu.c index d0a43b6d5c..7c6f438e5d 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -546,10 +546,6 @@ static Property mips_cpu_properties[] = { #ifdef CONFIG_TCG #include "hw/core/tcg-cpu-ops.h" -/* - * NB: cannot be const, as some elements are changed for specific - * mips hardware (see hw/mips/jazz.c). - */ static const TCGCPUOps mips_tcg_ops = { .initialize = mips_tcg_init, .synchronize_from_tb = mips_cpu_synchronize_from_tb, From patchwork Fri Nov 15 15:20:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 843491 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcc:0:b0:382:184f:390f with SMTP id e12csp898234wrc; Fri, 15 Nov 2024 07:21:35 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXcPSfuWDgcvl9xwYQAudL6HeRFLsK+BPLl8QAOZEf9DGuXEjv6CBqY0jM3MM7VBQL9akj8Kg==@linaro.org X-Google-Smtp-Source: AGHT+IF9Dpo8Hm5U2Z3nmf2xbJ4qOGTeo8azpQtcxy1ybmC4uDX8HiwKsigAZFRt69LTyMPpEtJo X-Received: by 2002:aca:90a:0:b0:3e7:c366:cf6f with SMTP id 5614622812f47-3e7c366d0b7mr1292186b6e.6.1731684094769; Fri, 15 Nov 2024 07:21:34 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1731684094; cv=none; d=google.com; s=arc-20240605; b=Zr7jbXXd910V2HhcrCggoA1KBO3FSa5IN2Af8d0SbtTA+Eij+h4IoQdWPp5WkTftjk 6kO5gC8mMxMU9UgLrjwbKRyrqXLVtZolYFEFzN9SS3iTvCNOlyZc14oTSIfAh8mJFZte 5TN37P3lw7JiZ/AlpoJ4K1oKTZ5qfeGVEEamhNBbilCacTh1ZhrdBd8QS+MuMYYd8ahq LNWWULTbiiYALbD3lNF7ClUTeD9K6sgaq5nTFcTRB6Lv37yTX9wF9EjkpHqIY0+qWxbK +56TGKVLjr0Efw7j88i3fzlcH/WAb0FzZap7ZKcPwLK5ASw6jMP79mFEL3WNrJiN80ic 5Xtg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=GRasMU/kl6pU0nKOnvS8/V9PVLoGYuKbLYq4L4yKpFo=; fh=ZXDWg7hKG7Hj19AbRuutTLw+Zvn/B9RsGUUw/YagpFI=; b=AWq8ETohwcHbyF2Pk6Nkv3DFzR7uTXR1XLr9FHwJ6OjedhTN88NxHu6rIJl/rjv3Zj dyqlmwkEjKcPWzi6CBxudeTIurmtBBIffBNUzFs+LvMYNEhmbAdxYCkth7+kiQaeogc8 PlE+JBhdQ3aZu2rXRpxKLgpNsNXpecx98cvNypR+uWydDJLPrGnKbrK1aPX7UktwJOT0 AR+OgA0TZ0Ya5OaBF2iJiZB/B8avha+I7Pi0pZjBxWzk0aYdIMSDZRUERJyS4FKV8k/A ER8sdaw1sCFmEwEOSynPPcdb50B3PJ07cdUxx9n+nHX8Q38+czT35OpENny8hquiX44m ldLQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=imh5T0mc; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 71dfb90a1353d-51479ae70easi514966e0c.28.2024.11.15.07.21.34 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 15 Nov 2024 07:21:34 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=imh5T0mc; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tBy8H-0001nx-KC; Fri, 15 Nov 2024 10:21:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tBy8F-0001nm-Lv for qemu-devel@nongnu.org; Fri, 15 Nov 2024 10:21:11 -0500 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tBy8D-00044J-Hi for qemu-devel@nongnu.org; Fri, 15 Nov 2024 10:21:11 -0500 Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-4314f38d274so20707455e9.1 for ; Fri, 15 Nov 2024 07:21:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1731684066; x=1732288866; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=GRasMU/kl6pU0nKOnvS8/V9PVLoGYuKbLYq4L4yKpFo=; b=imh5T0mcRvm6fKylrnHKff4C7xlbk7SdFcLkuqqGjSfrUrtGrhuJhMgErU58bJV8TT 2Y/+L3cfVDIw9jbmZqkljnpcBYFCQKI2F/bvHMurwSeV3lQOY8xw54AmuTrMaatrHy2U kZh+PcjYEy1F2112aoSzaAupRGKYP0ASi0ddgpYKaus/ia0He/sZqaHcLDQNiHadfKHH n6ygmaVSg9V7oAahQXfk5szx/SrPPTwEJhRluL4uYuDGa8da90VVmD76aZWYV5SZ/Ve2 TBXT6kCA23HPDATIeMhSCeq4xilD8zjeFAev+Bg2SqGHRyfJj9F820yy0xtfc+3m3Emq uh0w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731684066; x=1732288866; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GRasMU/kl6pU0nKOnvS8/V9PVLoGYuKbLYq4L4yKpFo=; b=duNP7PDreVE/CQDhYUtQGUMDxPDndOdELV6xiuAa39+sdRg9pByvPfin19TubYqX1g u1eI3xTnEfqtbvX5aikV0iWQnARSKsLCKT3885EEHlPQ2qZLQy3jH4gQi81oDXOP9qpw 0p062lvOqX0bNxcuUICNLP+3rnyYJPdGSE51vCoiF83LcKsgNx9KLM1oCWqdpTHefRiB sjP+NupBLNfHnzTlituGJJsVk8p6zxpTrK3BIOaa4teryHifS2z8J6aN9zHQWKWSP8qI RyJ6MhR5u8UVfI/1s1YxEx5YhrGyMMp2EMttwsAc8CObfoB89rPva7M93bqFfvC2LCKL V3sw== X-Gm-Message-State: AOJu0YyU5IqbEQ7QP7Lzuc8o51oTo8ELVwQNVD+9NUflmmT9uvVyrtPU Lkgf6x6ihMe1pBTLuaUwqNBcEdOYIo4eCn8PLWQU3wcTLFX1fJAFfW1W1Zr063XnfA4kaEoN3Sg o X-Received: by 2002:a05:600c:4e8d:b0:432:bb4d:cd77 with SMTP id 5b1f17b1804b1-432df74fda2mr30187755e9.19.1731684065835; Fri, 15 Nov 2024 07:21:05 -0800 (PST) Received: from localhost.localdomain ([176.187.214.209]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3821ae2f651sm4785315f8f.87.2024.11.15.07.21.04 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 15 Nov 2024 07:21:05 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= Subject: [PATCH 02/10] target/loongarch: Declare loongarch_cpu_dump_state() locally Date: Fri, 15 Nov 2024 16:20:45 +0100 Message-ID: <20241115152053.66442-3-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241115152053.66442-1-philmd@linaro.org> References: <20241115152053.66442-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philmd@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org loongarch_cpu_dump_state() is not used outside of cpu.c, no need to expose its prototype. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell Reviewed-by: Richard Henderson --- target/loongarch/internals.h | 2 -- target/loongarch/cpu.c | 2 +- 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/target/loongarch/internals.h b/target/loongarch/internals.h index 1a02427627..0655ac948b 100644 --- a/target/loongarch/internals.h +++ b/target/loongarch/internals.h @@ -18,8 +18,6 @@ void loongarch_translate_init(void); -void loongarch_cpu_dump_state(CPUState *cpu, FILE *f, int flags); - void G_NORETURN do_raise_exception(CPULoongArchState *env, uint32_t exception, uintptr_t pc); diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 57cc4f314b..e599beb30a 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -742,7 +742,7 @@ static ObjectClass *loongarch_cpu_class_by_name(const char *cpu_model) return oc; } -void loongarch_cpu_dump_state(CPUState *cs, FILE *f, int flags) +static void loongarch_cpu_dump_state(CPUState *cs, FILE *f, int flags) { CPULoongArchState *env = cpu_env(cs); int i; From patchwork Fri Nov 15 15:20:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 843496 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcc:0:b0:382:184f:390f with SMTP id e12csp898653wrc; Fri, 15 Nov 2024 07:22:22 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVh/biRE1jFoeS79iFPvnUTUP1SyvDybEuqz0iOOHeM5CbHXfGEjp9MePNEY7TtgM5J6Mhlwg==@linaro.org X-Google-Smtp-Source: AGHT+IEntPhGePLyis4a0oSy1OghIjWJLFM3F2awLyZqWvK8Fouw75G5EyRQo0RM3PDKDTxbrY9d X-Received: by 2002:a05:6214:451f:b0:6d3:e890:6846 with SMTP id 6a1803df08f44-6d3fb863d74mr35019346d6.48.1731684142067; Fri, 15 Nov 2024 07:22:22 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1731684142; cv=none; d=google.com; s=arc-20240605; b=BGascxwR3KApLQy2iCCXcnMY3bjtdZPoQlJxFhuErYBlr0m6c3qjc6t66MuGi7QoQe oNGukbifpEiBWtqkuwb7mU/2F8q+w0LPWFYFg0NExanp7qk9rliDq32k2kg/VsJ8ywBb 3cZJhqOAs+Jsp3FkFIB23zL/xc5P89MAfzHgjiEgE0DY5MDMDtpImyINxTAv5/ubzMFa HS/u+YF+zGmds/cGrXPzezfLvxmO//ch+vZCDHSsIh9DOTLAUYU7phOHo09HsAJxg+ee t7BFFfQtvrex+nWzwG9A4q+lO5KhDFIumfTdDwtf8BvEon/63z2qnHajA55D/O7//mR1 p/QQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=LzsaTbH/TKzp8tqs/UlH1bp9VqSjjTrJOViR/Wph0HQ=; fh=ZXDWg7hKG7Hj19AbRuutTLw+Zvn/B9RsGUUw/YagpFI=; b=EvYsKgG0nzGj7OFOiTeNxqHTM5WLOgMD7oj9jTbZu7qm1ctXym7e2QXmOYxh+WBPDL epixucIUrQBTmluGbE1HTx4LwrfkIWCE9w0hvb52ajQiDY8D7WN/L1YaLIhV/DlXceSN RLuNyN3D2AvEL/lEvIOytoboVea2MTSmWHKC9GorV1aPYAkdrYt7hAfDUHFFf+6VIR10 +JnEDhPuSbaAeei1y7ZHW3wg1Or7slRq1a7zItyQi9SAdTuKI2IakWAmIyfz7Hr/WRP6 ERrCaUuz64WcvmtsVlwt4HRT6CoOeAhzQwm6nf1SNHWCf2b8Gr348jiOnFRgeKB/6VNX yg2Q==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=SSD8KP13; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 6a1803df08f44-6d40a1c7817si3310246d6.268.2024.11.15.07.22.21 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 15 Nov 2024 07:22:22 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=SSD8KP13; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tBy8K-0001oX-E8; Fri, 15 Nov 2024 10:21:16 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tBy8J-0001oM-DC for qemu-devel@nongnu.org; Fri, 15 Nov 2024 10:21:15 -0500 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tBy8H-00045H-QW for qemu-devel@nongnu.org; Fri, 15 Nov 2024 10:21:15 -0500 Received: by mail-wm1-x333.google.com with SMTP id 5b1f17b1804b1-4314fa33a35so15834675e9.1 for ; Fri, 15 Nov 2024 07:21:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1731684071; x=1732288871; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=LzsaTbH/TKzp8tqs/UlH1bp9VqSjjTrJOViR/Wph0HQ=; b=SSD8KP13PVIm5XMoKG/p7LRjIqGP3pT9fqdQ/xNTpYWlW63kQxSwdBMIVd30QPix/u 9E68mf5o0r1nwz86983LC9mHBr0Cl18v4J5U7cBKeJEONXOK5GWF09xFK9skTf7x/S3v Y72Hn6+CoPM7FNIwpv7D6IKtN3p3epT5rT1Dk7ULi0vRtE/TI611+9Q1dOWXa3zK44X1 d3XEc5S5DpJQyugPDvIbdTmTb35AsH942oH5w5gXwkilxsuNLEOB1lvYooN1+Ui8ztEs eDBoXNAwy9aNtOlnp7BdYi03ZNsJ6FKtQCWfpXlbKWmkczsCQf9z0PTv64yV98UTMUS5 FoPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731684071; x=1732288871; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LzsaTbH/TKzp8tqs/UlH1bp9VqSjjTrJOViR/Wph0HQ=; b=az9Sz/++sJpukaoCBHzW15QBihKwrMP3FXb33GSpQLRNUN9abjmXBa3OXRbXSJRtrP mrOV5SiHzLdlt3vsLkjps5ZeQIynk5+Tq2d9VBApcpOSJ0Jl4WGccbxqiScjp0pNSGiY OrVNOj0DYxrB8Jvrko2JaHs2/8icWL1C2mb7sblwhqEMyiz8p90TaluLG9Hwn4gdsQ+n 7LmbPImsHRf/vQIxOHa5aUYPKC5NlLFNd8QsiQpXvpQ9ZU0Uu382W/mPaf9sMoSCX0pC sxQm3PxvtyZR3ytpJb3w6tyABfj5OHkG9gsHg+wfkskZAe47fcdtL9yov02WFeVBFTVb 7Oug== X-Gm-Message-State: AOJu0Yytw5jQnKgBsr26sinlzcMxJIA6Wcf9ytjmm3KvYpUSsQeH+udb QmBsrDhQCJY9YwPgK8IfkCExcEPHXHLFbkK2IW5tn6V1f3AyZR5pGX0XKAH7Li+tDWfK3U1qZs7 y X-Received: by 2002:a05:600c:4595:b0:42c:b80e:5e50 with SMTP id 5b1f17b1804b1-432df67991emr26832545e9.0.1731684070978; Fri, 15 Nov 2024 07:21:10 -0800 (PST) Received: from localhost.localdomain ([176.187.214.209]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432dac0ae45sm57136675e9.30.2024.11.15.07.21.09 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 15 Nov 2024 07:21:10 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= Subject: [PATCH 03/10] target/sparc: Move sparc_restore_state_to_opc() to cpu.c Date: Fri, 15 Nov 2024 16:20:46 +0100 Message-ID: <20241115152053.66442-4-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241115152053.66442-1-philmd@linaro.org> References: <20241115152053.66442-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=philmd@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Most targets define their restore_state_to_opc() handler in cpu.c. In order to keep SPARC aligned, move sparc_restore_state_to_opc() from translate.c to cpu.c. Suggested-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell --- target/sparc/cpu.h | 11 ++++++++--- target/sparc/cpu.c | 23 +++++++++++++++++++++++ target/sparc/translate.c | 32 -------------------------------- 3 files changed, 31 insertions(+), 35 deletions(-) diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index f517e5a383..bcb3566a92 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -607,12 +607,17 @@ int sparc_cpu_memory_rw_debug(CPUState *cpu, vaddr addr, uint8_t *buf, int len, bool is_write); #endif +/* Dynamic PC, must exit to main loop. */ +#define DYNAMIC_PC 1 +/* Dynamic PC, one of two values according to jump_pc[T2]. */ +#define JUMP_PC 2 +/* Dynamic PC, may lookup next TB. */ +#define DYNAMIC_PC_LOOKUP 3 + +#define DISAS_EXIT DISAS_TARGET_0 /* translate.c */ void sparc_tcg_init(void); -void sparc_restore_state_to_opc(CPUState *cs, - const TranslationBlock *tb, - const uint64_t *data); /* fop_helper.c */ target_ulong cpu_get_fsr(CPUSPARCState *); diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index dd7af86de7..59db8c8472 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -713,6 +713,29 @@ static void sparc_cpu_synchronize_from_tb(CPUState *cs, cpu->env.npc = tb->cs_base; } +static void sparc_restore_state_to_opc(CPUState *cs, + const TranslationBlock *tb, + const uint64_t *data) +{ + CPUSPARCState *env = cpu_env(cs); + target_ulong pc = data[0]; + target_ulong npc = data[1]; + + env->pc = pc; + if (npc == DYNAMIC_PC) { + /* dynamic NPC: already stored */ + } else if (npc & JUMP_PC) { + /* jump PC: use 'cond' and the jump targets of the translation */ + if (env->cond) { + env->npc = npc & ~3; + } else { + env->npc = pc + 4; + } + } else { + env->npc = npc; + } +} + static bool sparc_cpu_has_work(CPUState *cs) { return (cs->interrupt_request & CPU_INTERRUPT_HARD) && diff --git a/target/sparc/translate.c b/target/sparc/translate.c index cdd0a95c03..9942e78412 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -101,15 +101,6 @@ # define MAXTL_MASK 0 #endif -/* Dynamic PC, must exit to main loop. */ -#define DYNAMIC_PC 1 -/* Dynamic PC, one of two values according to jump_pc[T2]. */ -#define JUMP_PC 2 -/* Dynamic PC, may lookup next TB. */ -#define DYNAMIC_PC_LOOKUP 3 - -#define DISAS_EXIT DISAS_TARGET_0 - /* global register indexes */ static TCGv_ptr cpu_regwptr; static TCGv cpu_pc, cpu_npc; @@ -5881,26 +5872,3 @@ void sparc_tcg_init(void) gregnames[i]); } } - -void sparc_restore_state_to_opc(CPUState *cs, - const TranslationBlock *tb, - const uint64_t *data) -{ - CPUSPARCState *env = cpu_env(cs); - target_ulong pc = data[0]; - target_ulong npc = data[1]; - - env->pc = pc; - if (npc == DYNAMIC_PC) { - /* dynamic NPC: already stored */ - } else if (npc & JUMP_PC) { - /* jump PC: use 'cond' and the jump targets of the translation */ - if (env->cond) { - env->npc = npc & ~3; - } else { - env->npc = pc + 4; - } - } else { - env->npc = npc; - } -} From patchwork Fri Nov 15 15:20:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 843499 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcc:0:b0:382:184f:390f with SMTP id e12csp898822wrc; Fri, 15 Nov 2024 07:22:41 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVg5nx/Ow3BZ0816F0MVl8KAxRqpBYsxz/3c+MbqQwsmfUV5vpSZy16ixvGo3LfhMKw7A2YbA==@linaro.org X-Google-Smtp-Source: AGHT+IEDMpqMDL9g+OXE9dhpDC7O5xluydL/Wq28YrY8gBgktqOeJLLIQxAqklBjnbzftCZzx0NO X-Received: by 2002:a05:6102:dcb:b0:4a4:8fc3:9c8 with SMTP id ada2fe7eead31-4ad62ba7fadmr3407686137.10.1731684161450; Fri, 15 Nov 2024 07:22:41 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1731684161; cv=none; d=google.com; s=arc-20240605; b=cqmes/kYH5qTpGAJcNOS46u8b5sishg2ei6FSsyEn5uaQlh7XkoT51PjLHNi1pmkYK 1M10unvfo9VUz98HZS5Q6lieNxxA5/7R66aYMDVyNLW3w53mP8PSudoBeTg/vnrIqbrx rKgesmA+ERjV/pnVJoGs6sKaOYXBBIr3hHeNK/dH7cGkY4cvan6GbbWouM0rRG9XhnRL WfEHmRK/aEn5PDZ8GhDigwESwojKvL+8j/+sTAbq3s/MbW2IyvssrxS4AABXPzARN3Pr 2HNgQinPLaoxF/ThPToNqKltHfmWymYYpZH0ZEBwGE749YlunTxnVKrhWU4HO77S+Rzd 7lwg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=TnuuZBWq4DxU5k19EAiGN+H/ymSE9dnfe0SjDUoaWnw=; fh=ZXDWg7hKG7Hj19AbRuutTLw+Zvn/B9RsGUUw/YagpFI=; b=kZqhk/nAmUtkTSdeXpmxBL1i4ebrMw+fnaKeJOuc/wGB9TllYt7kEIB5psAJVEURh0 sYswc4pALicddyCWCuLi34TBd5/vRX3qAG+f+Wh6C3d47A8ScsFf1tlAGEomuqT5XzNg jNrT362N2DvwkCjTccP8JGlCnVr9JyN5nB2Fumj0FKSlFu64zwpbaBJ5wGpD4q2DTnve A63jC+JcLJTtmou2jyXnr9Ux9YA+/978/hF3p6uKR/DaHQWOlkv+wP/ANsOAn2Z/eVst 7pO9LVeDPlSAGF6i057SohdPutH2eK7TEeEAU/NGfHvTOI4RIKUyHZAVEe4uM/xonk2h I6gg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="NKdojp/n"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id ada2fe7eead31-4ad64907c78si428861137.596.2024.11.15.07.22.40 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 15 Nov 2024 07:22:41 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="NKdojp/n"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tBy8P-0001sc-E4; Fri, 15 Nov 2024 10:21:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tBy8O-0001ru-1I for qemu-devel@nongnu.org; Fri, 15 Nov 2024 10:21:20 -0500 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tBy8M-000467-HQ for qemu-devel@nongnu.org; Fri, 15 Nov 2024 10:21:19 -0500 Received: by mail-wr1-x433.google.com with SMTP id ffacd0b85a97d-37d55f0cf85so590172f8f.3 for ; Fri, 15 Nov 2024 07:21:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1731684076; x=1732288876; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TnuuZBWq4DxU5k19EAiGN+H/ymSE9dnfe0SjDUoaWnw=; b=NKdojp/n8YqKb99tZfKol2/ejbqDVmOXRt6LvJV1E3+O0C4zo96WosMZ6YoWP8HCdG 1U7KJNH2TZ9ovKzRfi7P+L+MaonTciC7DtXZQvASwObLCP14eVaZV7xoc/QOEFQdNXoa OB6GxqdM/AZ31VqZPE1ny9wHAyvPdtE3IyKPSbsWe/J6XcgyKVhuGRaYzCSyIhr8rker MSIQsQTld3JUI6ZsnUF3ml68FgKtwpbrCoNYFHPUkJzkUkoAQYPYtJRuP/sdP8tyS8le QguEO2mkF6VI0cejgKiY0lL6oOKQ/sqCelW9Ivgcr04AwTUd9+4prRW5klQdkrzlB0+8 8avA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731684076; x=1732288876; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TnuuZBWq4DxU5k19EAiGN+H/ymSE9dnfe0SjDUoaWnw=; b=mMunJWBjYI/G4rmFZcxujBQOVVcgXbolgxj4rS/sSs0NssqC8eMVEWW9xl7FHy1Tpq 7+m8PNvbDz2Z8AwHCIjtbkOxL19db2Uj4pifY2p/ABu7DLZxJy7gEp9poXbmwh+g67/v kFsykFDGjc/1HJv1NJJJU362qp4NttdP8YTNPy7YZGg1LhbCC5VKEiWU/HWv9nggslFZ nL5XK9pFGAXt0viXyfuNatVQXQDbzRXBwccoj27lwsFpvJstFke4nHKalQdXjiiRtoxQ KWo0pWU6sxjs4MMRv2NdaaRlNrcxCUVbhtQZmdoI++Hg+5BvCMk/OpyoGdVNmlXIdI+L vuYw== X-Gm-Message-State: AOJu0YwlUZAmEHTuI1zE/fx42P6v/SAKQfNTyoq8JBljHwi3X2Gpr+On tCc3CuPxoZJJZlYZ25FoCeCh42JMso8eo9q9TL5tMOQRQAP2LC+024b3jTfM/nsTn66YJfuDjL3 0 X-Received: by 2002:a5d:598e:0:b0:37c:cee0:96e6 with SMTP id ffacd0b85a97d-38225a0d457mr2875097f8f.27.1731684076105; Fri, 15 Nov 2024 07:21:16 -0800 (PST) Received: from localhost.localdomain ([176.187.214.209]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3821ae311fbsm4551060f8f.95.2024.11.15.07.21.15 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 15 Nov 2024 07:21:15 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= Subject: [PATCH 04/10] accel/tcg: Ensure frontends define restore_state_to_opc handler Date: Fri, 15 Nov 2024 16:20:47 +0100 Message-ID: <20241115152053.66442-5-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241115152053.66442-1-philmd@linaro.org> References: <20241115152053.66442-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=philmd@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- accel/tcg/cpu-exec.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 8163295f34..033f5fab10 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -1074,11 +1074,15 @@ bool tcg_exec_realizefn(CPUState *cpu, Error **errp) if (!tcg_target_initialized) { /* Check mandatory TCGCPUOps handlers */ + const TCGCPUOps *tcg_ops = cpu->cc->tcg_ops; + + assert(tcg_ops->restore_state_to_opc); #ifndef CONFIG_USER_ONLY - assert(cpu->cc->tcg_ops->cpu_exec_halt); - assert(cpu->cc->tcg_ops->cpu_exec_interrupt); + assert(tcg_ops->cpu_exec_halt); + assert(tcg_ops->cpu_exec_interrupt); #endif /* !CONFIG_USER_ONLY */ - cpu->cc->tcg_ops->initialize(); + + tcg_ops->initialize(); tcg_target_initialized = true; } From patchwork Fri Nov 15 15:20:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 843492 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcc:0:b0:382:184f:390f with SMTP id e12csp898268wrc; Fri, 15 Nov 2024 07:21:38 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVRyHya34kMOMK/CvuxALAU4UYbv42U/so04+Vrk0a27bs9EiSAC+KNZ+0z+6PfH1+tkUFGEw==@linaro.org X-Google-Smtp-Source: AGHT+IEHyJpFOEZE5gyEx2nYm1SBpC7xFD2iB8sDnys0eyqgDh3zFT+1x22fmEBtOsF3GAJWG6m5 X-Received: by 2002:a05:6808:2006:b0:3e3:a99a:433f with SMTP id 5614622812f47-3e7bc7ca5camr3846222b6e.13.1731684098001; Fri, 15 Nov 2024 07:21:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1731684097; cv=none; d=google.com; s=arc-20240605; b=UVAqcGTDnZ+CvtWiIRcchKzZGjrnoIH68YMI361OdaRm2AkDA6/zoZYlgCAyb8lYVg rHH36ZG8Vv3qFIj0VMwaILORONEnvV+fB0/1OoinKsM6QOy5cwVoUq/kaiAXtUlrWjY0 E+jdiTqqPHAblfrjYcC+RSSgG6pNMdhw5o/MDhvmvWQ8djDoYMSLrZsVi/2z/bOj0C9q OYDxG7KywClt2Nva6TjniPCBRGIlKH9t+UWxOawqhkHQU/lxvnFANi5ey4gPZVqeS4Eu jetREvcPYrRAZTSgkzzVuVAOwwECU76abkgRQbttJvvTVHWBO4ZtJ0s9+mJwCr5DG2u0 EXJQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=m4OKJRqPnTe7YcrvpW1zRARrSn3+9ueaSfuhvBrykFc=; fh=ZXDWg7hKG7Hj19AbRuutTLw+Zvn/B9RsGUUw/YagpFI=; b=Dr0pD2U6heEoGp5uLEpXpfUagAZY8Tb5+qIZK+/hKC2rwfqNrXbbZIjr6cPIbfwWf9 E7ZFCyPExM80uqS1tMtfxGeH5B9QhZSlXnrnCLQP40pxijA2TwlYkhDhoX6EA6a9xwP4 wLRr1fSrGtslDR0PIMF0YCSf3nOJAr0zjOGU+9yo5u5o/CmPApt7LBf3jxGFNl2jGloq tTuhGflyYjycbzeei/b7agLcUhUaM8ir3rTxa3vlbhS+0Z88f3nITC2vBaOhaeRkFfsV 1o4oU70D0pyHpTtPYy7hv5dTIQTg147K2O5Y6uDh3oj+UhPJqzonbOa9i/qC/90scZEM /P0g==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Q+ImcEyY; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id a1e0cc1a2514c-856dfbf856esi429477241.88.2024.11.15.07.21.37 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 15 Nov 2024 07:21:37 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Q+ImcEyY; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tBy8c-0002FB-1n; Fri, 15 Nov 2024 10:21:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tBy8Y-0002E5-R0 for qemu-devel@nongnu.org; Fri, 15 Nov 2024 10:21:30 -0500 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tBy8X-00047N-9q for qemu-devel@nongnu.org; Fri, 15 Nov 2024 10:21:30 -0500 Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-4315c1c7392so17230905e9.1 for ; Fri, 15 Nov 2024 07:21:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1731684083; x=1732288883; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=m4OKJRqPnTe7YcrvpW1zRARrSn3+9ueaSfuhvBrykFc=; b=Q+ImcEyYKSQEeyJW7bHwgOl5q//FN01StOW1m7rk2yzNYgk4n0p5XZ/BEw/za9QwOH HW/iS1YjUNNr1ehRqyGSwnK3+Cn6NQM4EC9NXVYjyvzTxVXI9vEEgmv6QgGIRLIx6DF+ wY3mfXa1/Li7ztsV3KGNhOgmckCkba3hxTn6hEdrgQ2iCjCb1m1RGywrUAa2EAhA+uJr glDHvdfuZQ3kC19RF+TCJNE9x6kfBXCREtq353/GKIomJO6bzg2Y6qu9qYVwZPRls/RD jDTZR9GCkcHEqo18LsqbX0jF+liDw/HAJCdTcpC7WZO+OcaqsNzb+/7TINr6PXU7un8h S+NQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731684083; x=1732288883; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=m4OKJRqPnTe7YcrvpW1zRARrSn3+9ueaSfuhvBrykFc=; b=SFZ5fau38EnYPnrHsOP416QkSZg426EJm48An9zMxSUwsHVXc2pg6FuoMQvoVcMG8p L+l/VVseF43S+ee4I1c057DogXZKt7xrhdpcEysuHSq0Ct2j9L7StC45he4siGBbg3uw YQpZTRq4uPSNLZXIo58GBzElZEjq5TS2oHWSYkyDZPFw8099x3ieBTCOf2OUoO8GppaS O/L/U6obhmi/vKE1r2teRCtnmk9PjwLKKEV3g+vViXm9ohauATgJDBSdluvkeCCRwnlB zJUOtDaZAyjIz45h7f3WR47dURDxDG6SLZYUVj/XgmvFFLgothgGkdaQeoBn9vFB5i1r ibXQ== X-Gm-Message-State: AOJu0YyZu9HHUDyLV2GpinIolU7DjvInZ2351lYAxektW80soAkrZ1qO 2CxfCkh6fNkPnozb8KbmFN3/X3weE391ruANuMx/vQCVfWwO4ZM3mcQ0obVHMaQM5gJV64lweVY a X-Received: by 2002:a05:600c:3c9a:b0:431:5465:807b with SMTP id 5b1f17b1804b1-432df793de8mr22303915e9.32.1731684081208; Fri, 15 Nov 2024 07:21:21 -0800 (PST) Received: from localhost.localdomain ([176.187.214.209]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432dab80582sm57070575e9.19.2024.11.15.07.21.20 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 15 Nov 2024 07:21:20 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= Subject: [PATCH 05/10] accel/tcg: Move cpu_unwind_state_data() declaration Date: Fri, 15 Nov 2024 16:20:48 +0100 Message-ID: <20241115152053.66442-6-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241115152053.66442-1-philmd@linaro.org> References: <20241115152053.66442-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=philmd@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org cpu_unwind_state_data() is specific to TCG accelerator, move it to "exec/translate-all.h". Signed-off-by: Philippe Mathieu-Daudé --- include/exec/cpu-common.h | 13 ------------- include/exec/translate-all.h | 12 ++++++++++++ 2 files changed, 12 insertions(+), 13 deletions(-) diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index 638dc806a5..b36fbf2a39 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -193,19 +193,6 @@ void tcg_cflags_set(CPUState *cpu, uint32_t flags); /* current cflags for hashing/comparison */ uint32_t curr_cflags(CPUState *cpu); -/** - * cpu_unwind_state_data: - * @cpu: the cpu context - * @host_pc: the host pc within the translation - * @data: output data - * - * Attempt to load the the unwind state for a host pc occurring in - * translated code. If @host_pc is not in translated code, the - * function returns false; otherwise @data is loaded. - * This is the same unwind info as given to restore_state_to_opc. - */ -bool cpu_unwind_state_data(CPUState *cpu, uintptr_t host_pc, uint64_t *data); - /** * cpu_restore_state: * @cpu: the cpu context diff --git a/include/exec/translate-all.h b/include/exec/translate-all.h index 85c9460c7c..f06cfedd52 100644 --- a/include/exec/translate-all.h +++ b/include/exec/translate-all.h @@ -21,6 +21,18 @@ #include "exec/exec-all.h" +/** + * cpu_unwind_state_data: + * @cpu: the cpu context + * @host_pc: the host pc within the translation + * @data: output data + * + * Attempt to load the the unwind state for a host pc occurring in + * translated code. If @host_pc is not in translated code, the + * function returns false; otherwise @data is loaded. + * This is the same unwind info as given to restore_state_to_opc. + */ +bool cpu_unwind_state_data(CPUState *cpu, uintptr_t host_pc, uint64_t *data); /* translate-all.c */ void tb_check_watchpoint(CPUState *cpu, uintptr_t retaddr); From patchwork Fri Nov 15 15:20:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 843501 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcc:0:b0:382:184f:390f with SMTP id e12csp899004wrc; Fri, 15 Nov 2024 07:23:01 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCW0eLyhPtNXTw2DzCqOlrWF6RUOGvh+1Be3J5vbXRlDCdykzMpMwg35XIu1LDBuXx1xmKrRYA==@linaro.org X-Google-Smtp-Source: AGHT+IHVQ+eraJcPWoQaYePQbeMC1tV22JXQejRnCIqAVY8Uy/OVHgDa6LmUyidvyqmrlD8aPjqb X-Received: by 2002:a05:620a:4625:b0:7b1:43e2:712b with SMTP id af79cd13be357-7b3622c6430mr439907685a.11.1731684181707; Fri, 15 Nov 2024 07:23:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1731684181; cv=none; d=google.com; s=arc-20240605; b=K1r1yU6EZSA9tvdwmc9wby6Xot3MXxGe25tiI4yrqh8aSa/29DVSrLn+2Fx/T8EveK 0cnHiqt7uRkAddjdiQuDgSqprzqwcnJGlj2zGH5NkkFeNyCm8//7saq0o0TVh3C7F9wE w/PnGbYSSRiLhn3a5lP90NJdRzKTSrW4fgDK2xtTBQqdA244TZyir6gKXeZOs2otqEu1 nr6RaSsIdokUkhjBVAQMCbNzc5T0KO/1Q13AaClrdX4XN2RJqXtn8Ih/UNP6J1zXvHwQ fdGNaCBeoHxf146lglIDwGYcFXEuGPs8PCswl6iO+1KWseuT+Ciq26TgGnGzQO9xcsS8 5J7A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=yp1aCpXr3wZU6pqXqUnr6GbiNobZzfh44qbynt7h1+g=; fh=ZXDWg7hKG7Hj19AbRuutTLw+Zvn/B9RsGUUw/YagpFI=; b=ADb50MjY4MBu+EClmDhWaaa6qwA2k6SlrgwpbBnL6KFgI5RgUhwSJY4ZMXfKlCXRra R7pMmLMTp/F3whholLJIoqXVDgUzTSzIsJ80sl9JXjdXZyVz3DfpS4VQU5O+hy0TOoBj Ff9dBHUniGd5RaEtJGRFX/CBDRyjJI5WQJAyk98y6DjyzJk2ZnAOwhQZSipGs/Jmagia n5pIQB1ee5ifYyYch1oFzefus4SzGmSjobRraTInGhb1hlYe1+dnJANgLvYKhUJjZSxx szkcAycsTMfbii7RXTEHdoE2dHSCEdh6lI8VPQ7kksE+qM9+OxXYBodnV88tPXIlXtWX 9N0w==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=N2Wl7E5j; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id af79cd13be357-7b35caf545dsi384373385a.640.2024.11.15.07.23.01 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 15 Nov 2024 07:23:01 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=N2Wl7E5j; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tBy8a-0002EQ-6i; Fri, 15 Nov 2024 10:21:32 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tBy8Y-0002E4-Pq for qemu-devel@nongnu.org; Fri, 15 Nov 2024 10:21:30 -0500 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tBy8W-00047L-Te for qemu-devel@nongnu.org; Fri, 15 Nov 2024 10:21:30 -0500 Received: by mail-wm1-x334.google.com with SMTP id 5b1f17b1804b1-432d86a3085so17181895e9.2 for ; Fri, 15 Nov 2024 07:21:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1731684087; x=1732288887; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=yp1aCpXr3wZU6pqXqUnr6GbiNobZzfh44qbynt7h1+g=; b=N2Wl7E5jXDQ0SsfJQ2oD+rd1jHzKElM9eihLlNQ9lls7CGnsnXf9219rjfKFVSiKLd DGYWaQwr6X4rt2vvK2eTyt5Mn/UL0EucdVF4lV6dkrVAwxNe0XGNjAZxf0UF9VkHaFH1 GcNuzIiPkGPCwjBqyhLr8uoahJuHt5jZMegzkSSb5q+waBZ+bulOQRtAMT7uZUJGugn2 ABMdHk2iqRHrFcDL8t7FMKL/O+aQK9laCdkd2Xod+SUMxLwU/9Z/w1G9gfVe3Dzr961W Aqm/23SC/Ylf5bhFYSs3cBdCx+uqwdIIJCWPBDVtKJ9NfAGSShFkYRZk12ZwfGLXGnT7 UDRQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731684087; x=1732288887; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yp1aCpXr3wZU6pqXqUnr6GbiNobZzfh44qbynt7h1+g=; b=rHd2xdZqgw5Ygsk8oqQaWNxJohD5IQ/kxnX/+BJ4CMHRRr5E4SDXcMn4XEk6jB0VtE VKQva2OlTxuaG1qtWEz2R9MBUM7EJP2yhfPBdqz7B+8UypppQ8DECjjIRCFM1hdFNff/ 4KIdLLAmlYRCpD5tFhlVUEPjwLQ9pfKuXW+nQlM1O49EhuV7twzc/Q5oz+P2unk7/uN6 fHwoDCYIfDtB/KLCSfkDCmOEaL2l/RdlQzofYNoGgZXgIRVaKTUoktiPCWfOUfs7b65K uOkUfwL01gAI16f8n1RdKE8SMlCf2JTRUPL11wlpQYObzrtbbV4XTi2YAQioV7nFiaGR YOIQ== X-Gm-Message-State: AOJu0YyYiE/OPfSI50f37rj/iCGNTMte/tbdqljFYxbja6LMSeUo4AiX Acq6hbnCDVm0aYlgoAJO/qMDYqRmYl1KnYUEFEZMejkwfBP4tK4Q4BGiFcbI4RJPoJMI2JDEBAe B X-Received: by 2002:a05:6000:1868:b0:37e:f1ed:67e8 with SMTP id ffacd0b85a97d-38225a21d77mr2952048f8f.35.1731684087066; Fri, 15 Nov 2024 07:21:27 -0800 (PST) Received: from localhost.localdomain ([176.187.214.209]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-382224253f6sm3301155f8f.111.2024.11.15.07.21.25 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 15 Nov 2024 07:21:25 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= Subject: [PATCH 06/10] accel/tcg: Remove cpu_unwind_state_data() unused CPUState argument Date: Fri, 15 Nov 2024 16:20:49 +0100 Message-ID: <20241115152053.66442-7-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241115152053.66442-1-philmd@linaro.org> References: <20241115152053.66442-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philmd@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- include/exec/translate-all.h | 3 +-- accel/tcg/translate-all.c | 2 +- target/i386/helper.c | 3 ++- target/openrisc/sys_helper.c | 7 +++---- 4 files changed, 7 insertions(+), 8 deletions(-) diff --git a/include/exec/translate-all.h b/include/exec/translate-all.h index f06cfedd52..9303318953 100644 --- a/include/exec/translate-all.h +++ b/include/exec/translate-all.h @@ -23,7 +23,6 @@ /** * cpu_unwind_state_data: - * @cpu: the cpu context * @host_pc: the host pc within the translation * @data: output data * @@ -32,7 +31,7 @@ * function returns false; otherwise @data is loaded. * This is the same unwind info as given to restore_state_to_opc. */ -bool cpu_unwind_state_data(CPUState *cpu, uintptr_t host_pc, uint64_t *data); +bool cpu_unwind_state_data(uintptr_t host_pc, uint64_t *data); /* translate-all.c */ void tb_check_watchpoint(CPUState *cpu, uintptr_t retaddr); diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index fdf6d8ac19..8d5530e341 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -243,7 +243,7 @@ bool cpu_restore_state(CPUState *cpu, uintptr_t host_pc) return false; } -bool cpu_unwind_state_data(CPUState *cpu, uintptr_t host_pc, uint64_t *data) +bool cpu_unwind_state_data(uintptr_t host_pc, uint64_t *data) { if (in_code_gen_buffer((const void *)(host_pc - tcg_splitwx_diff))) { TranslationBlock *tb = tcg_tb_lookup(host_pc); diff --git a/target/i386/helper.c b/target/i386/helper.c index 01a268a30b..b848936441 100644 --- a/target/i386/helper.c +++ b/target/i386/helper.c @@ -29,6 +29,7 @@ #endif #include "qemu/log.h" #ifdef CONFIG_TCG +#include "exec/translate-all.h" #include "tcg/insn-start-words.h" #endif @@ -526,7 +527,7 @@ static inline target_ulong get_memio_eip(CPUX86State *env) uint64_t data[TARGET_INSN_START_WORDS]; CPUState *cs = env_cpu(env); - if (!cpu_unwind_state_data(cs, cs->mem_io_pc, data)) { + if (!cpu_unwind_state_data(cs->mem_io_pc, data)) { return env->eip; } diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index 77567afba4..67e1f53fca 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -20,7 +20,7 @@ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/exec-all.h" +#include "exec/translate-all.h" #include "exec/helper-proto.h" #include "exception.h" #ifndef CONFIG_USER_ONLY @@ -219,7 +219,6 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd, #ifndef CONFIG_USER_ONLY uint64_t data[TARGET_INSN_START_WORDS]; MachineState *ms = MACHINE(qdev_get_machine()); - CPUState *cs = env_cpu(env); int idx; #endif @@ -260,7 +259,7 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd, return env->evbar; case TO_SPR(0, 16): /* NPC (equals PC) */ - if (cpu_unwind_state_data(cs, GETPC(), data)) { + if (cpu_unwind_state_data(GETPC(), data)) { return data[0]; } return env->pc; @@ -269,7 +268,7 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd, return cpu_get_sr(env); case TO_SPR(0, 18): /* PPC */ - if (cpu_unwind_state_data(cs, GETPC(), data)) { + if (cpu_unwind_state_data(GETPC(), data)) { if (data[1] & 2) { return data[0] - 4; } From patchwork Fri Nov 15 15:20:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 843498 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcc:0:b0:382:184f:390f with SMTP id e12csp898755wrc; Fri, 15 Nov 2024 07:22:34 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXzwpXxZy81OZvk8rPaqnYV0KqPp0TOcikqSHZhBTUfjZ2jkU85RsQiciKZoYnl8BNcK7745Q==@linaro.org X-Google-Smtp-Source: AGHT+IEty6fmU2dIJvYJoFF4+tMYMe0R9fmTeuYWswm9BDyU8LFx/oDGZ4pOLVOV8q4EWytUni1l X-Received: by 2002:ac8:57cb:0:b0:463:5a70:4cb8 with SMTP id d75a77b69052e-46363e0580cmr40865561cf.17.1731684154531; Fri, 15 Nov 2024 07:22:34 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1731684154; cv=none; d=google.com; s=arc-20240605; b=SQ22K9NTv3p7h0SXFv0775yfm+zP/ly00DT+iO8FNgu3za1+5Gp10NTg8o57XcWqC/ 7hg4ZThjrkhWyJeD0QRp3zcrUsDFC5fio1KKxCZwlNipM7gPzlUP3f4NF8dAryjr19Rd QMy4NW5gGJQNgR55+RauKpz+bwvqUojRnLG6QTCYYEUDYuRNrNnaqfltaEHrN6ji2dxo hYnwSdrwGgHm8RVzxwCgLuSOqqSc+HnVfhYO+M2SSFAvx1uNYFS/j1cKjXcqjzzl6huk qUjKbjJx7YTbadvB0mcAHsIBzVKZUbaiKWZR6QFbLXzSiuncEYVkVONP/nUAdZ2k24RU o6aQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=u5wTkh/tztyRKNsfUcuDCaLezbrFiqbSDF32QCsIdnM=; fh=ZXDWg7hKG7Hj19AbRuutTLw+Zvn/B9RsGUUw/YagpFI=; b=AbAQBOSW3/NyS5dOB3kY0HgNe9Pu97d08m8VFiebxFxxnFmdPD2cu2bPE0quX7R00F UkXttLoJJ0ILI7FcFl5ObDGGJ8uOscVBMAzPHTTyZy5OpLSPmA6TfGzNBj68+PGb82tr pcsmwW2S9K6EJ3NU93Ng89RChajRor/QswHxlQ9F3xM9zPhDBC8fsVmB+NMYbFP3lbTI Dfgr0oiBN5SDKBWAcTtHIxUeSfH+LfAZtwF4HejO3tb1eUaYSRs+l5QB4J8IJO+PfxFa N1AMR0NzZr/Vs02VNYA4JlnC0Lv73R60b2p8/u1Ll0CwDa+hWCMBAyS4efjoocfyvZgw we7w==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=lTJLxhxo; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d75a77b69052e-4635a9cb266si36777981cf.179.2024.11.15.07.22.34 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 15 Nov 2024 07:22:34 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=lTJLxhxo; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tBy8i-0002ga-0s; Fri, 15 Nov 2024 10:21:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tBy8f-0002Wu-QZ for qemu-devel@nongnu.org; Fri, 15 Nov 2024 10:21:37 -0500 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tBy8e-000485-26 for qemu-devel@nongnu.org; Fri, 15 Nov 2024 10:21:37 -0500 Received: by mail-wm1-x333.google.com with SMTP id 5b1f17b1804b1-43168d9c6c9so16090545e9.3 for ; Fri, 15 Nov 2024 07:21:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1731684092; x=1732288892; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=u5wTkh/tztyRKNsfUcuDCaLezbrFiqbSDF32QCsIdnM=; b=lTJLxhxoldrbF3mcvntkIDDDmt2DAPDfZuZgPLYKoVYqN0WGkf6/EHJyjjsFEAlxZb SKZZkhSWR2258yoiTdwiYbN+tHk+lHo7sGdityBF2CLtwu175wz6wrgs1BG/jyK9niq3 Ns0z89k4wxzx3Gh1SKZ60kpvyvTOAFju86NWAicQgT7ZXpcwg6cKSYJDoZorAWh5laZ1 5MfF0JPJRZeJ4hWBYZrA9PdnKrf/3zv5H+t9vGMs2QayMxrPUELny9pxFuAKvasnueu9 eSq9a16+uT/3Wx4MbVC79KsmyfW2hCpFoeTPAkjfOULoncusKdIMcPZP62xJf4hI6uMG HP/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731684092; x=1732288892; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=u5wTkh/tztyRKNsfUcuDCaLezbrFiqbSDF32QCsIdnM=; b=IR35S5K3JjyRJKwXXVYjuvDqYuaSvi45G/ALjb7wEoycoTVZLm7wg/t6RUQqG0WgSA vAKXHsTNznl7PmwIRA+zpKInMeQTS8L6LD9ixenVxUd373ZNH3f0995KWKEcgR8XvMet 3eXwalyg7SHhkGd5PZZ2fNHr0/fbmyvbUX9huK9HlzWWxcFYn4v06bdrDR8JRiJpgR5C cZWfAbwLfdTNAetWiUm2ZtLjdHvnXbBbvuD0Xqs/Nb6tAZWiImuqnUAOGhXox1M3u/kM 3U1LIGZLnB1eNXxIowx11mn5sxfB0YkugXANVO2ML9RV+Y5z5h11HS0a8nEcv/1b8/Hf liXQ== X-Gm-Message-State: AOJu0YxHNqaX8VnzGrEs48PpzDsPGFKANZq6Kle0O7gdahwFUxQ3CUW9 tqPkMb+Xc03qro0UM4n870RjUHHHWojphx9FFRZ6zXkrIO0I+yEens1jAxAQtX+yBs+2lEZIreB R X-Received: by 2002:a05:600c:1387:b0:42c:b45d:4a7b with SMTP id 5b1f17b1804b1-432df78a971mr24952685e9.25.1731684092591; Fri, 15 Nov 2024 07:21:32 -0800 (PST) Received: from localhost.localdomain ([176.187.214.209]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432da24459bsm61825705e9.6.2024.11.15.07.21.31 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 15 Nov 2024 07:21:31 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= Subject: [PATCH 07/10] accel/tcg: Reduce log_pc() declaration scope Date: Fri, 15 Nov 2024 16:20:50 +0100 Message-ID: <20241115152053.66442-8-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241115152053.66442-1-philmd@linaro.org> References: <20241115152053.66442-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=philmd@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org log_pc() is only used in cpu-exec.c, move it there. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell Reviewed-by: Richard Henderson --- accel/tcg/internal-target.h | 10 ---------- accel/tcg/cpu-exec.c | 10 ++++++++++ 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/accel/tcg/internal-target.h b/accel/tcg/internal-target.h index fe109724c6..750b3706b1 100644 --- a/accel/tcg/internal-target.h +++ b/accel/tcg/internal-target.h @@ -71,16 +71,6 @@ G_NORETURN void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr); bool tb_invalidate_phys_page_unwind(tb_page_addr_t addr, uintptr_t pc); -/* Return the current PC from CPU, which may be cached in TB. */ -static inline vaddr log_pc(CPUState *cpu, const TranslationBlock *tb) -{ - if (tb_cflags(tb) & CF_PCREL) { - return cpu->cc->get_pc(cpu); - } else { - return tb->pc; - } -} - /** * tcg_req_mo: * @type: TCGBar diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 033f5fab10..73bc9f00f7 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -433,6 +433,16 @@ const void *HELPER(lookup_tb_ptr)(CPUArchState *env) return tb->tc.ptr; } +/* Return the current PC from CPU, which may be cached in TB. */ +static inline vaddr log_pc(CPUState *cpu, const TranslationBlock *tb) +{ + if (tb_cflags(tb) & CF_PCREL) { + return cpu->cc->get_pc(cpu); + } else { + return tb->pc; + } +} + /* Execute a TB, and fix up the CPU state afterwards if necessary */ /* * Disable CFI checks. From patchwork Fri Nov 15 15:20:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 843500 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcc:0:b0:382:184f:390f with SMTP id e12csp898979wrc; Fri, 15 Nov 2024 07:22:58 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVs3FCHidrdn11O7/Jd/f2XWpdn+FoNYbpY0C5RcTc7VwU7Cyjzkft4MxhdjB6gGyzUJ+mcRQ==@linaro.org X-Google-Smtp-Source: AGHT+IFSFZZRW5pjE+YJgshPRS+qu/I15t4t48kN6gWcBA9VfTofcWC87nUtAF6zO2BBoLaLN3Wx X-Received: by 2002:ac8:7f88:0:b0:462:b856:c8fe with SMTP id d75a77b69052e-46356b0570bmr111849301cf.1.1731684178325; Fri, 15 Nov 2024 07:22:58 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1731684178; cv=none; d=google.com; s=arc-20240605; b=XCH+mmRdRrKwgqWNgWqe8r18mZxPgakoDPkFie4LuUJpjU40oZy2LIrIRbZn1+sVLP gpvt6fwLWW9sJXVubLmWpNIBqK8HxmXGklwiuQYdzWrlVXkrTufn3WcJNhmNmmmHPOzM nogLn/Frq0lpJlR1+Pv2zubCUgOAbKRASPGKVmQVNIdhT3kq/3H8nLLYgwMg2UkLym0n ReZexlxoYTuZW/ut9/M+ZHzA3CNcM9n1tP1w6UzmyY+HeDCXbqbahVxIP5l2uyo1H5dk W2WkRWv4/UOtY4bKz1iQ76fRtKA/lgJxFJVrNTVj4coKq4GJ427mOEgcIqysICW0w1kW KldA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=XKWMGwmFv0czeolnzZbx5rlDe+HwftXAS8FGuJHXNJM=; fh=ZXDWg7hKG7Hj19AbRuutTLw+Zvn/B9RsGUUw/YagpFI=; b=eqYjVauXKmqtFzW8uodaroqaleOlC4g0YWe01UxwzyMtL3WIx8IbJAxpF/7tDqXuVz urfuTfQ234p3zuRvfN9qGSSYJbSTlTLos/eNCMKbMALyUv2DkwicFLkYC27KFTl3tFm1 btQhXUcwRMqxFP4M6TU5LWmdSisP6IpzLMSJo1t0PzsUEv/jukoQVb7ezK04qmOnyroa obUwHKzFqILYTdeOaVHRm0IpiXKKZA+iNrgOIQgab0eUx88Y6083ruPXjB+OKl5XhEhV ZAPSgvKstiBCYgW3JNl7ttsqkCU8g7bmuooKukOpoX1w+APRsNi4VrjsZAiHl/ExXFW8 4lUA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=AHYPns+X; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d75a77b69052e-4635aa9739dsi37789911cf.271.2024.11.15.07.22.58 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 15 Nov 2024 07:22:58 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=AHYPns+X; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tBy8u-0003NF-SQ; Fri, 15 Nov 2024 10:21:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tBy8t-0003Mk-9F for qemu-devel@nongnu.org; Fri, 15 Nov 2024 10:21:51 -0500 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tBy8l-00048o-J0 for qemu-devel@nongnu.org; Fri, 15 Nov 2024 10:21:51 -0500 Received: by mail-wm1-x333.google.com with SMTP id 5b1f17b1804b1-4316cce103dso20620645e9.3 for ; Fri, 15 Nov 2024 07:21:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1731684098; x=1732288898; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=XKWMGwmFv0czeolnzZbx5rlDe+HwftXAS8FGuJHXNJM=; b=AHYPns+X9tpPo0vjtN4ZV/r8GDMGXE84ad766+k6wKFGKRHDSpNeOytxmbnGG6ama4 i7IvJRjoLeHuk0B2M9If7X5DIVrFN2OMhJs95ysySXD4EpZECZgFgzxaETjGReuSpxow CeE0nfaUI4iKwtvzkDEv8/vJrSoqB8m54BAl06/SvKR9loyrE/Z5C8N/pGAYcJcqHcwa PW37oIdiEZcQCpmpeToWaKdX110D6WlR8nmFuu0Re5rnroafqKOnblezKhHIaxAU/s7U tysQIfWWk4KSlqzwFnI8WYFQTothSrXqFkeFHjiZSbGpqEmSF3IsDwbLHRrz4Be5xAGx n9YQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731684098; x=1732288898; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=XKWMGwmFv0czeolnzZbx5rlDe+HwftXAS8FGuJHXNJM=; b=QWhCSq0hgiEbqEh+2JFAW/r5YmKx37m9E9h3049vZpVBmNCfmOA4V2aafhae8LIxoX AVQMm1y9vKuCc9nUcS44rjRT22E0FfZHruVO9we6TCHVPGJqa4qIReGuSDqQl5WJdqpZ ePxGa+hzVQxqh9Rq53rmJea/TKsBVs6ARwPYdwYHoIXG75kDt/oUG0jwY4jonjBkua+F n82eTHNUg3xxN9hvuTdz6p5aj/wH6ZG+Olk3k32VV1Xy5XPsUYrxh8njwVPhrxieIdnX Br9h1AQ/KCfnw25u7gpk/jjJs2JvRHPRcwcRzYyskNh6DkM+eHnCql2l2oVj7HiGjew7 Xvvg== X-Gm-Message-State: AOJu0YwfbYqPkIO1EQb5C/st1MU9b8hx3awrdT3nHUd1wdxG8JOJgsig ZEKTOY8BBhds+S/APAkWVbREag/uk8aAyt99WwLk4hsYL0twBiTGCbt7ALibPXGU9R4W/pE/eKy u X-Received: by 2002:a5d:584f:0:b0:382:2467:cb32 with SMTP id ffacd0b85a97d-38225a21be3mr2660319f8f.4.1731684098165; Fri, 15 Nov 2024 07:21:38 -0800 (PST) Received: from localhost.localdomain ([176.187.214.209]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3821ae161d8sm4718500f8f.78.2024.11.15.07.21.36 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 15 Nov 2024 07:21:37 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= Subject: [PATCH 08/10] hw/core/cpu: Pass CPUArchState to set/get_pc() handlers Date: Fri, 15 Nov 2024 16:20:51 +0100 Message-ID: <20241115152053.66442-9-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241115152053.66442-1-philmd@linaro.org> References: <20241115152053.66442-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=philmd@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org CPUClass set_pc() and get_pc() handlers are target specific. Rather than passing a generic CPUState and forcing QOM casts, we can directly pass the target CPUArchState, simplifying. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/core/cpu.h | 6 +++--- accel/tcg/cpu-exec.c | 7 ++++--- accel/tcg/translate-all.c | 2 +- hw/core/generic-loader.c | 2 +- target/alpha/cpu.c | 6 ++---- target/arm/cpu.c | 10 ++-------- target/avr/cpu.c | 12 ++++-------- target/hexagon/cpu.c | 8 ++++---- target/hppa/cpu.c | 14 +++++--------- target/i386/cpu.c | 12 ++++-------- target/loongarch/cpu.c | 8 ++++---- target/m68k/cpu.c | 12 ++++-------- target/microblaze/cpu.c | 14 +++++--------- target/mips/cpu.c | 10 ++++------ target/openrisc/cpu.c | 14 +++++--------- target/ppc/cpu_init.c | 12 ++++-------- target/riscv/cpu.c | 10 ++-------- target/rx/cpu.c | 12 ++++-------- target/s390x/cpu.c | 12 ++++-------- target/sh4/cpu.c | 12 ++++-------- target/sparc/cpu.c | 14 +++++--------- target/tricore/cpu.c | 8 ++++---- target/xtensa/cpu.c | 12 ++++-------- 23 files changed, 83 insertions(+), 146 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index db8a6fbc6e..70f5f8c3bf 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -160,8 +160,8 @@ struct CPUClass { int64_t (*get_arch_id)(CPUState *cpu); bool (*cpu_persistent_status)(CPUState *cpu); bool (*cpu_enabled_status)(CPUState *cpu); - void (*set_pc)(CPUState *cpu, vaddr value); - vaddr (*get_pc)(CPUState *cpu); + void (*set_pc)(CPUArchState *env, vaddr value); + vaddr (*get_pc)(CPUArchState *env); int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg); int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg); vaddr (*gdb_adjust_breakpoint)(CPUState *cpu, vaddr addr); @@ -972,7 +972,7 @@ static inline void cpu_set_pc(CPUState *cpu, vaddr addr) { CPUClass *cc = CPU_GET_CLASS(cpu); - cc->set_pc(cpu, addr); + cc->set_pc(cpu_env(cpu), addr); } /** diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 73bc9f00f7..b73607fea0 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -437,7 +437,7 @@ const void *HELPER(lookup_tb_ptr)(CPUArchState *env) static inline vaddr log_pc(CPUState *cpu, const TranslationBlock *tb) { if (tb_cflags(tb) & CF_PCREL) { - return cpu->cc->get_pc(cpu); + return cpu->cc->get_pc(cpu_env(cpu)); } else { return tb->pc; } @@ -459,13 +459,14 @@ cpu_tb_exec(CPUState *cpu, TranslationBlock *itb, int *tb_exit) uintptr_t ret; TranslationBlock *last_tb; const void *tb_ptr = itb->tc.ptr; + CPUArchState *env = cpu_env(cpu); if (qemu_loglevel_mask(CPU_LOG_TB_CPU | CPU_LOG_EXEC)) { log_cpu_exec(log_pc(cpu, itb), cpu, itb); } qemu_thread_jit_execute(); - ret = tcg_qemu_tb_exec(cpu_env(cpu), tb_ptr); + ret = tcg_qemu_tb_exec(env, tb_ptr); cpu->neg.can_do_io = true; qemu_plugin_disable_mem_helpers(cpu); /* @@ -494,7 +495,7 @@ cpu_tb_exec(CPUState *cpu, TranslationBlock *itb, int *tb_exit) } else { tcg_debug_assert(!(tb_cflags(last_tb) & CF_PCREL)); assert(cc->set_pc); - cc->set_pc(cpu, last_tb->pc); + cc->set_pc(env, last_tb->pc); } if (qemu_loglevel_mask(CPU_LOG_EXEC)) { vaddr pc = log_pc(cpu, last_tb); diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 8d5530e341..375100b483 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -634,7 +634,7 @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr) cpu->cflags_next_tb = curr_cflags(cpu) | CF_MEMI_ONLY | n; if (qemu_loglevel_mask(CPU_LOG_EXEC)) { - vaddr pc = cpu->cc->get_pc(cpu); + vaddr pc = cpu->cc->get_pc(cpu_env(cpu)); if (qemu_log_in_addr_range(pc)) { qemu_log("cpu_io_recompile: rewound execution of TB to %016" VADDR_PRIx "\n", pc); diff --git a/hw/core/generic-loader.c b/hw/core/generic-loader.c index ea8628b892..32cb5d9639 100644 --- a/hw/core/generic-loader.c +++ b/hw/core/generic-loader.c @@ -51,7 +51,7 @@ static void generic_loader_reset(void *opaque) CPUClass *cc = CPU_GET_CLASS(s->cpu); cpu_reset(s->cpu); if (cc) { - cc->set_pc(s->cpu, s->addr); + cc->set_pc(cpu_env(s->cpu), s->addr); } } diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 5d75c941f7..dce7a3ea5d 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -27,15 +27,13 @@ #include "fpu/softfloat.h" -static void alpha_cpu_set_pc(CPUState *cs, vaddr value) +static void alpha_cpu_set_pc(CPUAlphaState *env, vaddr value) { - CPUAlphaState *env = cpu_env(cs); env->pc = value; } -static vaddr alpha_cpu_get_pc(CPUState *cs) +static vaddr alpha_cpu_get_pc(CPUAlphaState *env) { - CPUAlphaState *env = cpu_env(cs); return env->pc; } diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 6938161b95..b7cf084019 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -51,11 +51,8 @@ #include "target/arm/cpu-qom.h" #include "target/arm/gtimer.h" -static void arm_cpu_set_pc(CPUState *cs, vaddr value) +static void arm_cpu_set_pc(CPUARMState *env, vaddr value) { - ARMCPU *cpu = ARM_CPU(cs); - CPUARMState *env = &cpu->env; - if (is_a64(env)) { env->pc = value; env->thumb = false; @@ -65,11 +62,8 @@ static void arm_cpu_set_pc(CPUState *cs, vaddr value) } } -static vaddr arm_cpu_get_pc(CPUState *cs) +static vaddr arm_cpu_get_pc(CPUARMState *env) { - ARMCPU *cpu = ARM_CPU(cs); - CPUARMState *env = &cpu->env; - if (is_a64(env)) { return env->pc; } else { diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 3132842d56..e85e54feb8 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -27,18 +27,14 @@ #include "tcg/debug-assert.h" #include "hw/qdev-properties.h" -static void avr_cpu_set_pc(CPUState *cs, vaddr value) +static void avr_cpu_set_pc(CPUAVRState *env, vaddr value) { - AVRCPU *cpu = AVR_CPU(cs); - - cpu->env.pc_w = value / 2; /* internally PC points to words */ + env->pc_w = value / 2; /* internally PC points to words */ } -static vaddr avr_cpu_get_pc(CPUState *cs) +static vaddr avr_cpu_get_pc(CPUAVRState *env) { - AVRCPU *cpu = AVR_CPU(cs); - - return cpu->env.pc_w * 2; + return env->pc_w * 2; } static bool avr_cpu_has_work(CPUState *cs) diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 020038fc49..828b7d1df3 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -245,14 +245,14 @@ void hexagon_debug(CPUHexagonState *env) hexagon_dump(env, stdout, CPU_DUMP_FPU); } -static void hexagon_cpu_set_pc(CPUState *cs, vaddr value) +static void hexagon_cpu_set_pc(CPUHexagonState *env, vaddr value) { - cpu_env(cs)->gpr[HEX_REG_PC] = value; + env->gpr[HEX_REG_PC] = value; } -static vaddr hexagon_cpu_get_pc(CPUState *cs) +static vaddr hexagon_cpu_get_pc(CPUHexagonState *env) { - return cpu_env(cs)->gpr[HEX_REG_PC]; + return env->gpr[HEX_REG_PC]; } static void hexagon_cpu_synchronize_from_tb(CPUState *cs, diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index c38439c180..d73a88b279 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -28,21 +28,17 @@ #include "fpu/softfloat.h" #include "tcg/tcg.h" -static void hppa_cpu_set_pc(CPUState *cs, vaddr value) +static void hppa_cpu_set_pc(CPUHPPAState *env, vaddr value) { - HPPACPU *cpu = HPPA_CPU(cs); - #ifdef CONFIG_USER_ONLY value |= PRIV_USER; #endif - cpu->env.iaoq_f = value; - cpu->env.iaoq_b = value + 4; + env->iaoq_f = value; + env->iaoq_b = value + 4; } -static vaddr hppa_cpu_get_pc(CPUState *cs) +static vaddr hppa_cpu_get_pc(CPUHPPAState *env) { - CPUHPPAState *env = cpu_env(cs); - return hppa_form_gva_psw(env->psw, (env->psw & PSW_C ? env->iasq_f : 0), env->iaoq_f & -4); } @@ -59,7 +55,7 @@ void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc, * incomplete virtual address. This also means that we must separate * out current cpu privilege from the low bits of IAOQ_F. */ - *pc = hppa_cpu_get_pc(env_cpu(env)); + *pc = hppa_cpu_get_pc(env); flags |= (env->iaoq_f & 3) << TB_FLAG_PRIV_SHIFT; /* diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 3725dbbc4b..5f063b18c4 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -8251,19 +8251,15 @@ static bool x86_cpu_get_paging_enabled(const CPUState *cs) } #endif /* !CONFIG_USER_ONLY */ -static void x86_cpu_set_pc(CPUState *cs, vaddr value) +static void x86_cpu_set_pc(CPUX86State *env, vaddr value) { - X86CPU *cpu = X86_CPU(cs); - - cpu->env.eip = value; + env->eip = value; } -static vaddr x86_cpu_get_pc(CPUState *cs) +static vaddr x86_cpu_get_pc(CPUX86State *env) { - X86CPU *cpu = X86_CPU(cs); - /* Match cpu_get_tb_cpu_state. */ - return cpu->env.eip + cpu->env.segs[R_CS].base; + return env->eip + env->segs[R_CS].base; } int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request) diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index e599beb30a..add7323f05 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -101,14 +101,14 @@ void G_NORETURN do_raise_exception(CPULoongArchState *env, cpu_loop_exit_restore(cs, pc); } -static void loongarch_cpu_set_pc(CPUState *cs, vaddr value) +static void loongarch_cpu_set_pc(CPULoongArchState *env, vaddr value) { - set_pc(cpu_env(cs), value); + set_pc(env, value); } -static vaddr loongarch_cpu_get_pc(CPUState *cs) +static vaddr loongarch_cpu_get_pc(CPULoongArchState *env) { - return cpu_env(cs)->pc; + return env->pc; } #ifndef CONFIG_USER_ONLY diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 5fe335558a..39bf6f3d90 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -24,18 +24,14 @@ #include "migration/vmstate.h" #include "fpu/softfloat.h" -static void m68k_cpu_set_pc(CPUState *cs, vaddr value) +static void m68k_cpu_set_pc(CPUM68KState *env, vaddr value) { - M68kCPU *cpu = M68K_CPU(cs); - - cpu->env.pc = value; + env->pc = value; } -static vaddr m68k_cpu_get_pc(CPUState *cs) +static vaddr m68k_cpu_get_pc(CPUM68KState *env) { - M68kCPU *cpu = M68K_CPU(cs); - - return cpu->env.pc; + return env->pc; } static void m68k_restore_state_to_opc(CPUState *cs, diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 710eb1146c..3e68c73898 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -78,20 +78,16 @@ static const struct { /* If no specific version gets selected, default to the following. */ #define DEFAULT_CPU_VERSION "10.0" -static void mb_cpu_set_pc(CPUState *cs, vaddr value) +static void mb_cpu_set_pc(CPUMBState *env, vaddr value) { - MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); - - cpu->env.pc = value; + env->pc = value; /* Ensure D_FLAG and IMM_FLAG are clear for the new PC */ - cpu->env.iflags = 0; + env->iflags = 0; } -static vaddr mb_cpu_get_pc(CPUState *cs) +static vaddr mb_cpu_get_pc(CPUMBState *env) { - MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); - - return cpu->env.pc; + return env->pc; } static void mb_cpu_synchronize_from_tb(CPUState *cs, diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 7c6f438e5d..506494f7e6 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -120,16 +120,14 @@ void cpu_set_exception_base(int vp_index, target_ulong address) vp->env.exception_base = address; } -static void mips_cpu_set_pc(CPUState *cs, vaddr value) +static void mips_cpu_set_pc(CPUMIPSState *env, vaddr value) { - mips_env_set_pc(cpu_env(cs), value); + mips_env_set_pc(env, value); } -static vaddr mips_cpu_get_pc(CPUState *cs) +static vaddr mips_cpu_get_pc(CPUMIPSState *env) { - MIPSCPU *cpu = MIPS_CPU(cs); - - return cpu->env.active_tc.PC; + return env->active_tc.PC; } static bool mips_cpu_has_work(CPUState *cs) diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index b96561d1f2..51ab0df82b 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -25,19 +25,15 @@ #include "fpu/softfloat-helpers.h" #include "tcg/tcg.h" -static void openrisc_cpu_set_pc(CPUState *cs, vaddr value) +static void openrisc_cpu_set_pc(CPUOpenRISCState *env, vaddr value) { - OpenRISCCPU *cpu = OPENRISC_CPU(cs); - - cpu->env.pc = value; - cpu->env.dflag = 0; + env->pc = value; + env->dflag = 0; } -static vaddr openrisc_cpu_get_pc(CPUState *cs) +static vaddr openrisc_cpu_get_pc(CPUOpenRISCState *env) { - OpenRISCCPU *cpu = OPENRISC_CPU(cs); - - return cpu->env.pc; + return env->pc; } static void openrisc_cpu_synchronize_from_tb(CPUState *cs, diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index efcb80d1c2..c8b4445aea 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7152,18 +7152,14 @@ void ppc_cpu_list(void) #endif } -static void ppc_cpu_set_pc(CPUState *cs, vaddr value) +static void ppc_cpu_set_pc(CPUPPCState *env, vaddr value) { - PowerPCCPU *cpu = POWERPC_CPU(cs); - - cpu->env.nip = value; + env->nip = value; } -static vaddr ppc_cpu_get_pc(CPUState *cs) +static vaddr ppc_cpu_get_pc(CPUPPCState *env) { - PowerPCCPU *cpu = POWERPC_CPU(cs); - - return cpu->env.nip; + return env->nip; } #ifdef CONFIG_TCG diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f219f0c3b5..dfaa9a9c1c 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -878,11 +878,8 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) } } -static void riscv_cpu_set_pc(CPUState *cs, vaddr value) +static void riscv_cpu_set_pc(CPURISCVState *env, vaddr value) { - RISCVCPU *cpu = RISCV_CPU(cs); - CPURISCVState *env = &cpu->env; - if (env->xl == MXL_RV32) { env->pc = (int32_t)value; } else { @@ -890,11 +887,8 @@ static void riscv_cpu_set_pc(CPUState *cs, vaddr value) } } -static vaddr riscv_cpu_get_pc(CPUState *cs) +static vaddr riscv_cpu_get_pc(CPURISCVState *env) { - RISCVCPU *cpu = RISCV_CPU(cs); - CPURISCVState *env = &cpu->env; - /* Match cpu_get_tb_cpu_state. */ if (env->xl == MXL_RV32) { return env->pc & UINT32_MAX; diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 65a74ce720..0c4b63b114 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -27,18 +27,14 @@ #include "fpu/softfloat.h" #include "tcg/debug-assert.h" -static void rx_cpu_set_pc(CPUState *cs, vaddr value) +static void rx_cpu_set_pc(CPURXState *env, vaddr value) { - RXCPU *cpu = RX_CPU(cs); - - cpu->env.pc = value; + env->pc = value; } -static vaddr rx_cpu_get_pc(CPUState *cs) +static vaddr rx_cpu_get_pc(CPURXState *env) { - RXCPU *cpu = RX_CPU(cs); - - return cpu->env.pc; + return env->pc; } static void rx_cpu_synchronize_from_tb(CPUState *cs, diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 514c70f301..12975385e0 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -112,18 +112,14 @@ uint64_t s390_cpu_get_psw_mask(CPUS390XState *env) return r; } -static void s390_cpu_set_pc(CPUState *cs, vaddr value) +static void s390_cpu_set_pc(CPUS390XState *env, vaddr value) { - S390CPU *cpu = S390_CPU(cs); - - cpu->env.psw.addr = value; + env->psw.addr = value; } -static vaddr s390_cpu_get_pc(CPUState *cs) +static vaddr s390_cpu_get_pc(CPUS390XState *env) { - S390CPU *cpu = S390_CPU(cs); - - return cpu->env.psw.addr; + return env->psw.addr; } static bool s390_cpu_has_work(CPUState *cs) diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 8f07261dcf..5c6840841b 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -28,18 +28,14 @@ #include "fpu/softfloat-helpers.h" #include "tcg/tcg.h" -static void superh_cpu_set_pc(CPUState *cs, vaddr value) +static void superh_cpu_set_pc(CPUSH4State *env, vaddr value) { - SuperHCPU *cpu = SUPERH_CPU(cs); - - cpu->env.pc = value; + env->pc = value; } -static vaddr superh_cpu_get_pc(CPUState *cs) +static vaddr superh_cpu_get_pc(CPUSH4State *env) { - SuperHCPU *cpu = SUPERH_CPU(cs); - - return cpu->env.pc; + return env->pc; } static void superh_cpu_synchronize_from_tb(CPUState *cs, diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 59db8c8472..e1f0dfcbbd 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -688,19 +688,15 @@ static void sparc_cpu_dump_state(CPUState *cs, FILE *f, int flags) qemu_fprintf(f, "\n"); } -static void sparc_cpu_set_pc(CPUState *cs, vaddr value) +static void sparc_cpu_set_pc(CPUSPARCState *env, vaddr value) { - SPARCCPU *cpu = SPARC_CPU(cs); - - cpu->env.pc = value; - cpu->env.npc = value + 4; + env->pc = value; + env->npc = value + 4; } -static vaddr sparc_cpu_get_pc(CPUState *cs) +static vaddr sparc_cpu_get_pc(CPUSPARCState *env) { - SPARCCPU *cpu = SPARC_CPU(cs); - - return cpu->env.pc; + return env->pc; } static void sparc_cpu_synchronize_from_tb(CPUState *cs, diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 1a26171590..20de29d114 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -34,14 +34,14 @@ static const gchar *tricore_gdb_arch_name(CPUState *cs) return "tricore"; } -static void tricore_cpu_set_pc(CPUState *cs, vaddr value) +static void tricore_cpu_set_pc(CPUTriCoreState *env, vaddr value) { - cpu_env(cs)->PC = value & ~(target_ulong)1; + env->PC = value & ~(target_ulong)1; } -static vaddr tricore_cpu_get_pc(CPUState *cs) +static vaddr tricore_cpu_get_pc(CPUTriCoreState *env) { - return cpu_env(cs)->PC; + return env->PC; } static void tricore_cpu_synchronize_from_tb(CPUState *cs, diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 6f9039abae..3ab7b794f0 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -40,18 +40,14 @@ #endif -static void xtensa_cpu_set_pc(CPUState *cs, vaddr value) +static void xtensa_cpu_set_pc(CPUXtensaState *env, vaddr value) { - XtensaCPU *cpu = XTENSA_CPU(cs); - - cpu->env.pc = value; + env->pc = value; } -static vaddr xtensa_cpu_get_pc(CPUState *cs) +static vaddr xtensa_cpu_get_pc(CPUXtensaState *env) { - XtensaCPU *cpu = XTENSA_CPU(cs); - - return cpu->env.pc; + return env->pc; } static void xtensa_restore_state_to_opc(CPUState *cs, From patchwork Fri Nov 15 15:20:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 843495 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcc:0:b0:382:184f:390f with SMTP id e12csp898619wrc; Fri, 15 Nov 2024 07:22:18 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVqNy0Ec5Jl3qsoshkIwFHCxd87oWXVGLMDMjs3JKKhb5An42c2xzgv7UBRcds+bheRbgbQ6w==@linaro.org X-Google-Smtp-Source: AGHT+IHL9NPxQQzAO8mvma+kGSN0iziTHfiDy7CUa2/weI9qh6aU0X9sAYacqmxH8vWUR8jMKi5r X-Received: by 2002:a05:620a:1787:b0:7af:c5cf:1d4c with SMTP id af79cd13be357-7b3622961b7mr350861585a.8.1731684138097; Fri, 15 Nov 2024 07:22:18 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1731684138; cv=none; d=google.com; s=arc-20240605; b=hvZsV2NhI9T9l6RNTWVtNpC/WSZ3CnF9J4sKcR8/AWYOLHufSrtiEhwRShwL75JyZk Pp9CeFOM6SfqGBPC3MtyDlP5QYVyxlhRIgD/mY4dXGmd53ZwX5+43bn3+4PeufZ5PsrY 94Ok9dyTq+OZ5ci12CpbQmvZ2ky0k0qZzvJyMfOvsxGggyPahi9xFfM3fCqzVdNyXDsj VF8SXh/NZZblCYWgwa16Sy+pXjJ2ZE1UmQ4FIW4YceBcXP+jlfjzjEQ0XUBcaaVigLGi pVJSzqHIVguleORF5sb1Kqn6nCCHGCL+JOhbcwkYix5Xm5EPTnVnYu9kzdnwe9GwUSSg rIPQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=kKSZFc6XXY/YHJVgF3fFpq0PBmuORvG1PCcPSzgM2YQ=; fh=ZXDWg7hKG7Hj19AbRuutTLw+Zvn/B9RsGUUw/YagpFI=; b=GRoz0yVB+VsmDzE+D+zp++Rpl2F7VJ68HwUStAxT4pfsYFMZ3CfMCdG9Tw8l7QQNyM Z8IQmGdYR23ohx3xxNqOoYScy1Zc3EArTAkSs/cmfZjuNj5sNIwASAe4ZPXSWoCP6uwk qA9VIjcsdvLhHefHgCgfjWTmn0HVYcOinWaUh334OK8ZzFp/tBOu0H+KliUyfi+C2F2f 0aO6xWzCijujVKjjS/MU/84JgLJFvrwSq8E1/SZhw1zpwvJ0j/LlIRNrVRBiGIjzXaoQ FKQF57BXSpouIhOtPr2eCd5ZWj2M2waHE2mUJK+2s7ZvHbKDeQGfgHBLVX0JRMm7sVjl 2w6A==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XOXuMI4p; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id af79cd13be357-7b35cacc439si384415585a.556.2024.11.15.07.22.17 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 15 Nov 2024 07:22:18 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XOXuMI4p; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tBy8t-0003Ma-5u; Fri, 15 Nov 2024 10:21:51 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tBy8r-0003M7-To for qemu-devel@nongnu.org; Fri, 15 Nov 2024 10:21:49 -0500 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tBy8p-00049O-Df for qemu-devel@nongnu.org; Fri, 15 Nov 2024 10:21:49 -0500 Received: by mail-wr1-x42c.google.com with SMTP id ffacd0b85a97d-37d533b5412so1349254f8f.2 for ; Fri, 15 Nov 2024 07:21:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1731684104; x=1732288904; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=kKSZFc6XXY/YHJVgF3fFpq0PBmuORvG1PCcPSzgM2YQ=; b=XOXuMI4pbCwLBlXlUfxq2UGawbGOWUTUwi+gLTEzbbDisreoduUGQ3AqDWLzKf4HqP bAZd4LPctd1w9IEevRbGCG+WOatHO/gFC6fNwvnWyjDoTavU6pfxt5H1hvixCJuxXN8h 9bJdmQ9+m+iJec8fOlchsWAuS1npzgQIIdfeZNq2adLsDmy/bdXdlU+GRi1NYyAW0miT JIw6Y1iJRQAiXcWiau0OYbF3ImniGLEwbLoYUbzi4nGw7AlELLN1S4QyGl5892gE0Tl3 Yf2e6aN3BUJghxUK/kND4S0vp5iGZwg38CDVo6Lrgl/ZpqcPzeELd8Ny6U1PIkUoCRfN k6Pg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731684104; x=1732288904; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kKSZFc6XXY/YHJVgF3fFpq0PBmuORvG1PCcPSzgM2YQ=; b=o9KHbCTqNfQkNO66h7vhXoMyDx3OnwFCIFKaoNlzM1AURFcJ14KDJVFrLEGHNsWMG+ AVPwV/0Ly9hSivY9n7ynp6UMjjXlDPVTCeTgSrPgVj9pkySFwR+sZXFeych5/ud8ad1Q 5QYf4PWCHGSSSzCpeMH4oWgDPTMkvqtnOaiY3DNJ39BQwtmW/dnm7jxVvKoXXvRWOukU ckvRssnhD/wDX8++3SoDP14pn7tWH9V2pxHqeDq77oEy4ygB6JoJw6ysoXRN7HE3LcuR 4NuKAkZdi/aDmSvP2mxkditxWEzglnmFd7/lSUqLy6NKdN6y3/cBFae4uJbIS6sB4LsK Wm2A== X-Gm-Message-State: AOJu0YwnSZGq4RK076I4M5ff0V+ZU00ZEBsdF5ygb3+xFgbFrUsE4gx7 /7pLYWeQWI8FRKNZmLArnhfC+LNFwXKaAu5YaEqcQhwUSnPwqUMII73JwjPA8qhdY7brvTz+oFE n X-Received: by 2002:a05:6000:710:b0:37d:4ebe:164f with SMTP id ffacd0b85a97d-38225a88ce3mr2573803f8f.46.1731684103895; Fri, 15 Nov 2024 07:21:43 -0800 (PST) Received: from localhost.localdomain ([176.187.214.209]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3821adad994sm4575668f8f.38.2024.11.15.07.21.42 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 15 Nov 2024 07:21:42 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= Subject: [PATCH 09/10] hw/core/cpu: Pass CPUArchState to restore_state_to_opc() handler Date: Fri, 15 Nov 2024 16:20:52 +0100 Message-ID: <20241115152053.66442-10-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241115152053.66442-1-philmd@linaro.org> References: <20241115152053.66442-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=philmd@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org CPUClass::restore_state_to_opc() handler is target specific. Rather than passing a generic CPUState and forcing QOM casts, we can directly pass the target CPUArchState, simplifying. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/core/tcg-cpu-ops.h | 2 +- target/arm/internals.h | 2 +- target/mips/tcg/tcg-internal.h | 2 +- target/s390x/s390x-internal.h | 2 +- accel/tcg/translate-all.c | 2 +- target/alpha/cpu.c | 4 +--- target/arm/cpu.c | 4 +--- target/avr/cpu.c | 4 ++-- target/hexagon/cpu.c | 4 ++-- target/hppa/cpu.c | 4 +--- target/i386/tcg/tcg-cpu.c | 4 +--- target/loongarch/cpu.c | 4 ++-- target/m68k/cpu.c | 7 +++---- target/microblaze/cpu.c | 8 +++----- target/mips/tcg/translate.c | 4 +--- target/openrisc/cpu.c | 10 ++++------ target/ppc/cpu_init.c | 6 ++---- target/riscv/tcg/tcg-cpu.c | 4 +--- target/rx/cpu.c | 6 ++---- target/s390x/tcg/translate.c | 3 +-- target/sh4/cpu.c | 8 +++----- target/sparc/cpu.c | 3 +-- target/tricore/cpu.c | 4 ++-- target/xtensa/cpu.c | 6 ++---- 24 files changed, 40 insertions(+), 67 deletions(-) diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index 663efb9133..a15ff36dd7 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -44,7 +44,7 @@ struct TCGCPUOps { * state which are tracked insn-by-insn in the target-specific * arguments to start_insn, passed as @data. */ - void (*restore_state_to_opc)(CPUState *cpu, const TranslationBlock *tb, + void (*restore_state_to_opc)(CPUArchState *env, const TranslationBlock *tb, const uint64_t *data); /** @cpu_exec_enter: Callback for cpu_exec preparation */ diff --git a/target/arm/internals.h b/target/arm/internals.h index e37f459af3..b7b15800e8 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -362,7 +362,7 @@ void arm_cpu_register_gdb_commands(ARMCPU *cpu); void aarch64_cpu_register_gdb_commands(ARMCPU *cpu, GString *, GPtrArray *, GPtrArray *); -void arm_restore_state_to_opc(CPUState *cs, +void arm_restore_state_to_opc(CPUARMState *env, const TranslationBlock *tb, const uint64_t *data); diff --git a/target/mips/tcg/tcg-internal.h b/target/mips/tcg/tcg-internal.h index aef032c48d..79d39801a6 100644 --- a/target/mips/tcg/tcg-internal.h +++ b/target/mips/tcg/tcg-internal.h @@ -21,7 +21,7 @@ void mips_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb); G_NORETURN void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); -void mips_restore_state_to_opc(CPUState *cs, +void mips_restore_state_to_opc(CPUMIPSState *env, const TranslationBlock *tb, const uint64_t *data); diff --git a/target/s390x/s390x-internal.h b/target/s390x/s390x-internal.h index 825252d728..891e5f576c 100644 --- a/target/s390x/s390x-internal.h +++ b/target/s390x/s390x-internal.h @@ -399,7 +399,7 @@ void handle_diag_308(CPUS390XState *env, uint64_t r1, uint64_t r3, /* translate.c */ void s390x_translate_init(void); -void s390x_restore_state_to_opc(CPUState *cs, +void s390x_restore_state_to_opc(CPUS390XState *env, const TranslationBlock *tb, const uint64_t *data); diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 375100b483..264bc968e7 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -218,7 +218,7 @@ void cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb, cpu->neg.icount_decr.u16.low += insns_left; } - cpu->cc->tcg_ops->restore_state_to_opc(cpu, tb, data); + cpu->cc->tcg_ops->restore_state_to_opc(cpu_env(cpu), tb, data); } bool cpu_restore_state(CPUState *cpu, uintptr_t host_pc) diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index dce7a3ea5d..2b55bb0bd9 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -47,12 +47,10 @@ static void alpha_cpu_synchronize_from_tb(CPUState *cs, } } -static void alpha_restore_state_to_opc(CPUState *cs, +static void alpha_restore_state_to_opc(CPUAlphaState *env, const TranslationBlock *tb, const uint64_t *data) { - CPUAlphaState *env = cpu_env(cs); - if (tb_cflags(tb) & CF_PCREL) { env->pc = (env->pc & TARGET_PAGE_MASK) | data[0]; } else { diff --git a/target/arm/cpu.c b/target/arm/cpu.c index b7cf084019..c8e032d433 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -90,12 +90,10 @@ void arm_cpu_synchronize_from_tb(CPUState *cs, } } -void arm_restore_state_to_opc(CPUState *cs, +void arm_restore_state_to_opc(CPUARMState *env, const TranslationBlock *tb, const uint64_t *data) { - CPUARMState *env = cpu_env(cs); - if (is_a64(env)) { if (tb_cflags(tb) & CF_PCREL) { env->pc = (env->pc & TARGET_PAGE_MASK) | data[0]; diff --git a/target/avr/cpu.c b/target/avr/cpu.c index e85e54feb8..19b6298a31 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -55,11 +55,11 @@ static void avr_cpu_synchronize_from_tb(CPUState *cs, cpu_env(cs)->pc_w = tb->pc / 2; /* internally PC points to words */ } -static void avr_restore_state_to_opc(CPUState *cs, +static void avr_restore_state_to_opc(CPUAVRState *env, const TranslationBlock *tb, const uint64_t *data) { - cpu_env(cs)->pc_w = data[0]; + env->pc_w = data[0]; } static void avr_cpu_reset_hold(Object *obj, ResetType type) diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 828b7d1df3..8038df1c82 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -267,11 +267,11 @@ static bool hexagon_cpu_has_work(CPUState *cs) return true; } -static void hexagon_restore_state_to_opc(CPUState *cs, +static void hexagon_restore_state_to_opc(CPUHexagonState *env, const TranslationBlock *tb, const uint64_t *data) { - cpu_env(cs)->gpr[HEX_REG_PC] = data[0]; + env->gpr[HEX_REG_PC] = data[0]; } static void hexagon_cpu_reset_hold(Object *obj, ResetType type) diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index d73a88b279..ff937c8171 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -101,12 +101,10 @@ static void hppa_cpu_synchronize_from_tb(CPUState *cs, cpu->env.psw_xb = tb->flags & (PSW_X | PSW_B); } -static void hppa_restore_state_to_opc(CPUState *cs, +static void hppa_restore_state_to_opc(CPUHPPAState *env, const TranslationBlock *tb, const uint64_t *data) { - CPUHPPAState *env = cpu_env(cs); - env->iaoq_f = (env->iaoq_f & TARGET_PAGE_MASK) | data[0]; if (data[1] != INT32_MIN) { env->iaoq_b = env->iaoq_f + data[1]; diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index cca19cd40e..6e624710f5 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -61,12 +61,10 @@ static void x86_cpu_synchronize_from_tb(CPUState *cs, } } -static void x86_restore_state_to_opc(CPUState *cs, +static void x86_restore_state_to_opc(CPUX86State *env, const TranslationBlock *tb, const uint64_t *data) { - X86CPU *cpu = X86_CPU(cs); - CPUX86State *env = &cpu->env; int cc_op = data[1]; uint64_t new_pc; diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index add7323f05..6962f4b6de 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -340,11 +340,11 @@ static void loongarch_cpu_synchronize_from_tb(CPUState *cs, set_pc(cpu_env(cs), tb->pc); } -static void loongarch_restore_state_to_opc(CPUState *cs, +static void loongarch_restore_state_to_opc(CPULoongArchState *env, const TranslationBlock *tb, const uint64_t *data) { - set_pc(cpu_env(cs), data[0]); + set_pc(env, data[0]); } #endif /* CONFIG_TCG */ diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 39bf6f3d90..fc923dcf83 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -34,16 +34,15 @@ static vaddr m68k_cpu_get_pc(CPUM68KState *env) return env->pc; } -static void m68k_restore_state_to_opc(CPUState *cs, +static void m68k_restore_state_to_opc(CPUM68KState *env, const TranslationBlock *tb, const uint64_t *data) { - M68kCPU *cpu = M68K_CPU(cs); int cc_op = data[1]; - cpu->env.pc = data[0]; + env->pc = data[0]; if (cc_op != CC_OP_DYNAMIC) { - cpu->env.cc_op = cc_op; + env->cc_op = cc_op; } } diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 3e68c73898..c2cfecd78f 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -100,14 +100,12 @@ static void mb_cpu_synchronize_from_tb(CPUState *cs, cpu->env.iflags = tb->flags & IFLAGS_TB_MASK; } -static void mb_restore_state_to_opc(CPUState *cs, +static void mb_restore_state_to_opc(CPUMBState *env, const TranslationBlock *tb, const uint64_t *data) { - MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); - - cpu->env.pc = data[0]; - cpu->env.iflags = data[1]; + env->pc = data[0]; + env->iflags = data[1]; } static bool mb_cpu_has_work(CPUState *cs) diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index de7045874d..7a6fedb758 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -15302,12 +15302,10 @@ void mips_tcg_init(void) } } -void mips_restore_state_to_opc(CPUState *cs, +void mips_restore_state_to_opc(CPUMIPSState *env, const TranslationBlock *tb, const uint64_t *data) { - CPUMIPSState *env = cpu_env(cs); - env->active_tc.PC = data[0]; env->hflags &= ~MIPS_HFLAG_BMASK; env->hflags |= data[1]; diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 51ab0df82b..5601465789 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -45,16 +45,14 @@ static void openrisc_cpu_synchronize_from_tb(CPUState *cs, cpu->env.pc = tb->pc; } -static void openrisc_restore_state_to_opc(CPUState *cs, +static void openrisc_restore_state_to_opc(CPUOpenRISCState *env, const TranslationBlock *tb, const uint64_t *data) { - OpenRISCCPU *cpu = OPENRISC_CPU(cs); - - cpu->env.pc = data[0]; - cpu->env.dflag = data[1] & 1; + env->pc = data[0]; + env->dflag = data[1] & 1; if (data[1] & 2) { - cpu->env.ppc = cpu->env.pc - 4; + env->ppc = env->pc - 4; } } diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index c8b4445aea..95bf78a3b7 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7163,13 +7163,11 @@ static vaddr ppc_cpu_get_pc(CPUPPCState *env) } #ifdef CONFIG_TCG -static void ppc_restore_state_to_opc(CPUState *cs, +static void ppc_restore_state_to_opc(CPUPPCState *env, const TranslationBlock *tb, const uint64_t *data) { - PowerPCCPU *cpu = POWERPC_CPU(cs); - - cpu->env.nip = data[0]; + env->nip = data[0]; } #endif /* CONFIG_TCG */ diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index c62c221696..82689f06c4 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -108,12 +108,10 @@ static void riscv_cpu_synchronize_from_tb(CPUState *cs, } } -static void riscv_restore_state_to_opc(CPUState *cs, +static void riscv_restore_state_to_opc(CPURISCVState *env, const TranslationBlock *tb, const uint64_t *data) { - RISCVCPU *cpu = RISCV_CPU(cs); - CPURISCVState *env = &cpu->env; RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); target_ulong pc; diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 0c4b63b114..0f24893f86 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -46,13 +46,11 @@ static void rx_cpu_synchronize_from_tb(CPUState *cs, cpu->env.pc = tb->pc; } -static void rx_restore_state_to_opc(CPUState *cs, +static void rx_restore_state_to_opc(CPURXState *env, const TranslationBlock *tb, const uint64_t *data) { - RXCPU *cpu = RX_CPU(cs); - - cpu->env.pc = data[0]; + env->pc = data[0]; } static bool rx_cpu_has_work(CPUState *cs) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index bcfff40b25..182be8b3ca 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -6488,11 +6488,10 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, translator_loop(cs, tb, max_insns, pc, host_pc, &s390x_tr_ops, &dc.base); } -void s390x_restore_state_to_opc(CPUState *cs, +void s390x_restore_state_to_opc(CPUS390XState *env, const TranslationBlock *tb, const uint64_t *data) { - CPUS390XState *env = cpu_env(cs); int cc_op = data[1]; env->psw.addr = data[0]; diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 5c6840841b..c378d0ec83 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -48,14 +48,12 @@ static void superh_cpu_synchronize_from_tb(CPUState *cs, cpu->env.flags = tb->flags & TB_FLAG_ENVFLAGS_MASK; } -static void superh_restore_state_to_opc(CPUState *cs, +static void superh_restore_state_to_opc(CPUSH4State *env, const TranslationBlock *tb, const uint64_t *data) { - SuperHCPU *cpu = SUPERH_CPU(cs); - - cpu->env.pc = data[0]; - cpu->env.flags = data[1]; + env->pc = data[0]; + env->flags = data[1]; /* * Theoretically delayed_pc should also be restored. In practice the * branch instruction is re-executed after exception, so the delayed diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index e1f0dfcbbd..83c86c03bd 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -709,11 +709,10 @@ static void sparc_cpu_synchronize_from_tb(CPUState *cs, cpu->env.npc = tb->cs_base; } -static void sparc_restore_state_to_opc(CPUState *cs, +static void sparc_restore_state_to_opc(CPUSPARCState *env, const TranslationBlock *tb, const uint64_t *data) { - CPUSPARCState *env = cpu_env(cs); target_ulong pc = data[0]; target_ulong npc = data[1]; diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 20de29d114..f8a5bb8979 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -51,11 +51,11 @@ static void tricore_cpu_synchronize_from_tb(CPUState *cs, cpu_env(cs)->PC = tb->pc; } -static void tricore_restore_state_to_opc(CPUState *cs, +static void tricore_restore_state_to_opc(CPUTriCoreState *env, const TranslationBlock *tb, const uint64_t *data) { - cpu_env(cs)->PC = data[0]; + env->PC = data[0]; } static void tricore_cpu_reset_hold(Object *obj, ResetType type) diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 3ab7b794f0..8ba8280ae9 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -50,13 +50,11 @@ static vaddr xtensa_cpu_get_pc(CPUXtensaState *env) return env->pc; } -static void xtensa_restore_state_to_opc(CPUState *cs, +static void xtensa_restore_state_to_opc(CPUXtensaState *env, const TranslationBlock *tb, const uint64_t *data) { - XtensaCPU *cpu = XTENSA_CPU(cs); - - cpu->env.pc = data[0]; + env->pc = data[0]; } static bool xtensa_cpu_has_work(CPUState *cs) From patchwork Fri Nov 15 15:20:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 843494 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcc:0:b0:382:184f:390f with SMTP id e12csp898470wrc; Fri, 15 Nov 2024 07:22:00 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXp+xWzqA1dmdPxleYJIFc10yOMAEiZ3eTEZVsYwM3vdo3DkDZg9MfVfxmCro3sqi6Kkch6Cg==@linaro.org X-Google-Smtp-Source: AGHT+IFYL71xFEM0xULoPopvck/AfH1PyumOlZiYIKPgRlrOs0YwOiY2heyylvEe+NeONk5zNPT2 X-Received: by 2002:a05:6214:2b9a:b0:6d3:f924:cede with SMTP id 6a1803df08f44-6d3fac234bbmr44655096d6.7.1731684120696; Fri, 15 Nov 2024 07:22:00 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1731684120; cv=none; d=google.com; s=arc-20240605; b=YIpADKWZWzlZzFVm9zBxWy5VwimqL7/Y7nBgqeooqqEE/VMAFIKS8LJp3GK0k5olJM e84xW1BVISePtAO3Co3V11D+VboM9FOAoLdjgNtpl8qjShCSx1alVSdEwDvzqOWgjqQA Ndh3M0d6W7x1tGmsImmk6wczZhPKVaUVOrfB5m62OuDQWU7tQRQd/l3YtcooI1FGp8gG AueT+XVyWK7rcD5ndVKw6tBuysVl9szF/ro7RtE0qDEa8Iyw+/m2Qo2PedfIe0D0KQoH pvGYrkB5CCrB1evxFvFI0DvNVFdsonuhKDeyR1KO5MslkKKnDlK9hD0Smrl+sGh7DsiP CRaA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=yeQRT281dCHMdV0wKef8zCTDvxfHEabnq4IySE7RO9M=; fh=ZXDWg7hKG7Hj19AbRuutTLw+Zvn/B9RsGUUw/YagpFI=; b=RaEB9j8e2GYxitWExPqRzqK+sKNdWJ09PAfI+w8pLSH1NRWY4U2JrmwySIwxxj7myL F2ARLE01KqfuPGnvaj2Vo+hF4xMXtOU4ke63Dhq6DOR0EZrbrZMPZTBE6xfSUk3w5gBv J/Ju/gRFWgESmLbyy+1NAXdgriMNRGQ444HN2DQ274N8y5EAzoGjcXAVqi2GAJQZU7/C JXXlI5heGtFlQ3tI7E+ZIPp81PtRShAI//jIHrxbNQqljcCQp+rLXtnEWWyjG0XtWZQM EbuOt6lVBMPnvVecYce+BgIQo3Ut/IEn7OmTsDh8rPnwayMcskd2bAtJcpzS6Bsi86NG Cujg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=UUod3XU1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 6a1803df08f44-6d3ee7a072esi37124246d6.119.2024.11.15.07.22.00 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 15 Nov 2024 07:22:00 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=UUod3XU1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tBy8y-0003Ns-SK; Fri, 15 Nov 2024 10:21:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tBy8x-0003NT-R7 for qemu-devel@nongnu.org; Fri, 15 Nov 2024 10:21:55 -0500 Received: from mail-lf1-x12d.google.com ([2a00:1450:4864:20::12d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tBy8u-00049o-RW for qemu-devel@nongnu.org; Fri, 15 Nov 2024 10:21:55 -0500 Received: by mail-lf1-x12d.google.com with SMTP id 2adb3069b0e04-53a097aa3daso2004099e87.1 for ; Fri, 15 Nov 2024 07:21:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1731684110; x=1732288910; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=yeQRT281dCHMdV0wKef8zCTDvxfHEabnq4IySE7RO9M=; b=UUod3XU19G3EXjnrhOu9lTYfIOTfUJzdBitmsIXaSiUv4KmzsYcCiEuYqEndV/kZ6H qOAgY0ajw6cHO5mMeXfPn4/qcqYYC4iklUi7Jbd4FbGzs5e7AyT8E79ilSu9hImbm1b0 FZvnW0OAqxrVSZIyRCdHc/+NmFy0W/Hni4b008sCd350jSGq6qyYcq0VBbMeQNars/rx fKvLcjSQ9+S1CUhqjd3oV1xoVvcg117z7cKR0lotyEhl5wqsb3niIyJnaU7pc97OdiHn uVZb7xrwM2zj/3HjB9tCLbiX3ZBbnT9k4iMyhM8VHIb8fVsOpVewmYIwgDPDhMi5tyTR j6zw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731684110; x=1732288910; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yeQRT281dCHMdV0wKef8zCTDvxfHEabnq4IySE7RO9M=; b=CRx3XeXfE6wZqJEX8bBoQLfBBLQ3ZQpHZmvwhQzTbMZ0/HzDEViKPyrlwi0e1bJqMX /EJkgDkC1NxCQu/+XKqVdjrbYIWeCer/o9CHMAH2HIHdT///G1s71R1oaANU+JgTh5fN bx/5Ia9DFeGs4dafyX6PMvG5pUj/F6j1zgtytX8RUSuxFqJUmVnJL6DDSbBJRBms1RTl Y2Zdqsw8XHuCesI7m4qgzV9cCj7Al6uVqqf/g33M1EYm7+QVeJDEkQTUlmM2y3PB5JAA 3w3kMzaMyQ0ZntANIG6dpRYw61dTp+9x39ZCEJJy9SbwgPZR/58qCPpjMMi/68iqaTAR nlyw== X-Gm-Message-State: AOJu0Yyyg5MSClbuJsWClF2HtOjNPtwSKinxpI7GN4Qf9RY9l0lG+fxm zF3h9awbb+BVGJMC4M7KfxndUTh3qjfLeAv4UYR+F1Lbv9ONVdZRqsPpteWkzT30cCDcOsh1Mm6 U X-Received: by 2002:a05:6512:a84:b0:53d:a99e:b765 with SMTP id 2adb3069b0e04-53dab2a2205mr1575519e87.27.1731684109572; Fri, 15 Nov 2024 07:21:49 -0800 (PST) Received: from localhost.localdomain ([176.187.214.209]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432dab78881sm56456745e9.13.2024.11.15.07.21.48 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 15 Nov 2024 07:21:48 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= Subject: [PATCH 10/10] hw/core/cpu: Pass CPUArchState to cpu_dump_state() handler Date: Fri, 15 Nov 2024 16:20:53 +0100 Message-ID: <20241115152053.66442-11-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241115152053.66442-1-philmd@linaro.org> References: <20241115152053.66442-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::12d; envelope-from=philmd@linaro.org; helo=mail-lf1-x12d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org CPUClass::cpu_dump_state() handler is target specific. Rather than passing a generic CPUState and forcing QOM casts, we can directly pass the target CPUArchState, simplifying. Only x86_cpu_dump_state() has to do an extra env_cpu() to access the original CPUState. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/core/cpu.h | 2 +- target/alpha/cpu.h | 2 +- target/hppa/cpu.h | 2 +- target/i386/cpu.h | 2 +- target/m68k/cpu.h | 2 +- target/microblaze/cpu.h | 2 +- target/openrisc/cpu.h | 2 +- target/ppc/cpu.h | 2 +- target/rx/cpu.h | 2 +- target/s390x/s390x-internal.h | 2 +- target/sh4/cpu.h | 2 +- target/tricore/cpu.h | 2 +- target/xtensa/cpu.h | 2 +- hw/core/cpu-common.c | 2 +- target/alpha/helper.c | 3 +-- target/arm/cpu.c | 14 ++++++-------- target/avr/cpu.c | 3 +-- target/hexagon/cpu.c | 9 ++------- target/hppa/helper.c | 3 +-- target/hppa/int_helper.c | 2 +- target/hppa/sys_helper.c | 6 ++---- target/i386/cpu-dump.c | 5 ++--- target/loongarch/cpu.c | 3 +-- target/m68k/translate.c | 3 +-- target/microblaze/translate.c | 3 +-- target/mips/cpu.c | 3 +-- target/openrisc/translate.c | 3 +-- target/ppc/cpu_init.c | 5 ++--- target/riscv/cpu.c | 6 ++---- target/rx/translate.c | 3 +-- target/s390x/cpu-dump.c | 3 +-- target/sh4/translate.c | 3 +-- target/sparc/cpu.c | 3 +-- target/tricore/translate.c | 3 +-- target/xtensa/translate.c | 3 +-- 35 files changed, 45 insertions(+), 72 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 70f5f8c3bf..f647717add 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -155,7 +155,7 @@ struct CPUClass { int (*mmu_index)(CPUState *cpu, bool ifetch); int (*memory_rw_debug)(CPUState *cpu, vaddr addr, uint8_t *buf, int len, bool is_write); - void (*dump_state)(CPUState *cpu, FILE *, int flags); + void (*dump_state)(CPUArchState *env, FILE *, int flags); void (*query_cpu_fast)(CPUState *cpu, CpuInfoFast *value); int64_t (*get_arch_id)(CPUState *cpu); bool (*cpu_persistent_status)(CPUState *cpu); diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index 3556d3227f..e05bc70428 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -283,7 +283,7 @@ void alpha_cpu_do_interrupt(CPUState *cpu); bool alpha_cpu_exec_interrupt(CPUState *cpu, int int_req); hwaddr alpha_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); #endif /* !CONFIG_USER_ONLY */ -void alpha_cpu_dump_state(CPUState *cs, FILE *f, int flags); +void alpha_cpu_dump_state(CPUAlphaState *env, FILE *f, int flags); int alpha_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int alpha_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index e45ba50a59..43bdcccb2f 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -358,7 +358,7 @@ void cpu_hppa_change_prot_id(CPUHPPAState *env); int hppa_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int hppa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); -void hppa_cpu_dump_state(CPUState *cs, FILE *f, int); +void hppa_cpu_dump_state(CPUHPPAState *env, FILE *f, int); #ifndef CONFIG_USER_ONLY void hppa_ptlbe(CPUHPPAState *env); hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr); diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 4c239a6970..94c3d09fe3 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2284,7 +2284,7 @@ int x86_cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu, bool x86_cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list, Error **errp); -void x86_cpu_dump_state(CPUState *cs, FILE *f, int flags); +void x86_cpu_dump_state(CPUX86State *env, FILE *f, int flags); int x86_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int x86_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index b5bbeedb7a..7df68b8dbd 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -188,7 +188,7 @@ void m68k_cpu_do_interrupt(CPUState *cpu); bool m68k_cpu_exec_interrupt(CPUState *cpu, int int_req); hwaddr m68k_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); #endif /* !CONFIG_USER_ONLY */ -void m68k_cpu_dump_state(CPUState *cpu, FILE *f, int flags); +void m68k_cpu_dump_state(CPUM68KState *env, FILE *f, int flags); int m68k_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int m68k_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 3e5a3e5c60..1571038979 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -375,7 +375,7 @@ hwaddr mb_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, G_NORETURN void mb_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); -void mb_cpu_dump_state(CPUState *cpu, FILE *f, int flags); +void mb_cpu_dump_state(CPUMBState *env, FILE *f, int flags); int mb_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int mb_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); int mb_cpu_gdb_read_stack_protect(CPUState *cs, GByteArray *buf, int reg); diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index c9fe9ae12d..7bd7578eee 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -297,7 +297,7 @@ struct ArchCPU { CPUOpenRISCState env; }; -void openrisc_cpu_dump_state(CPUState *cpu, FILE *f, int flags); +void openrisc_cpu_dump_state(CPUOpenRISCState *env, FILE *f, int flags); int openrisc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int openrisc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void openrisc_translate_init(void); diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 945af07a64..14da103db7 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1554,7 +1554,7 @@ static inline bool vhyp_cpu_in_nested(PowerPCCPU *cpu) } #endif /* CONFIG_USER_ONLY */ -void ppc_cpu_dump_state(CPUState *cpu, FILE *f, int flags); +void ppc_cpu_dump_state(CPUPPCState *env, FILE *f, int flags); int ppc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int ppc_cpu_gdb_read_register_apple(CPUState *cpu, GByteArray *buf, int reg); int ppc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); diff --git a/target/rx/cpu.h b/target/rx/cpu.h index c53593d7aa..b582304a48 100644 --- a/target/rx/cpu.h +++ b/target/rx/cpu.h @@ -134,7 +134,7 @@ void rx_cpu_do_interrupt(CPUState *cpu); bool rx_cpu_exec_interrupt(CPUState *cpu, int int_req); hwaddr rx_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); #endif /* !CONFIG_USER_ONLY */ -void rx_cpu_dump_state(CPUState *cpu, FILE *f, int flags); +void rx_cpu_dump_state(CPURXState *env, FILE *f, int flags); int rx_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int rx_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); diff --git a/target/s390x/s390x-internal.h b/target/s390x/s390x-internal.h index 891e5f576c..9ae89b3d24 100644 --- a/target/s390x/s390x-internal.h +++ b/target/s390x/s390x-internal.h @@ -322,7 +322,7 @@ void s390_cpu_gdb_init(CPUState *cs); /* helper.c */ -void s390_cpu_dump_state(CPUState *cpu, FILE *f, int flags); +void s390_cpu_dump_state(CPUS390XState *env, FILE *f, int flags); void do_restart_interrupt(CPUS390XState *env); #ifndef CONFIG_USER_ONLY void s390_cpu_recompute_watchpoints(CPUState *cs); diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index d928bcf006..f4f38a9ab2 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -240,7 +240,7 @@ struct SuperHCPUClass { uint32_t cvr; }; -void superh_cpu_dump_state(CPUState *cpu, FILE *f, int flags); +void superh_cpu_dump_state(CPUSH4State *env, FILE *f, int flags); int superh_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int superh_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); G_NORETURN void superh_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h index 220af69fc2..423589f609 100644 --- a/target/tricore/cpu.h +++ b/target/tricore/cpu.h @@ -76,7 +76,7 @@ struct TriCoreCPUClass { }; hwaddr tricore_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); -void tricore_cpu_dump_state(CPUState *cpu, FILE *f, int flags); +void tricore_cpu_dump_state(CPUTriCoreState *env, FILE *f, int flags); FIELD(PCXI, PCPN_13, 24, 8) FIELD(PCXI, PCPN_161, 22, 8) diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 77e48eef19..28ebba10e3 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -592,7 +592,7 @@ void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); bool xtensa_debug_check_breakpoint(CPUState *cs); #endif -void xtensa_cpu_dump_state(CPUState *cpu, FILE *f, int flags); +void xtensa_cpu_dump_state(CPUXtensaState *env, FILE *f, int flags); void xtensa_count_regs(const XtensaConfig *config, unsigned *n_regs, unsigned *n_core_regs); int xtensa_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c index 09c7903594..bc608b38f5 100644 --- a/hw/core/cpu-common.c +++ b/hw/core/cpu-common.c @@ -105,7 +105,7 @@ void cpu_dump_state(CPUState *cpu, FILE *f, int flags) if (cc->dump_state) { cpu_synchronize_state(cpu); - cc->dump_state(cpu, f, flags); + cc->dump_state(cpu_env(cpu), f, flags); } } diff --git a/target/alpha/helper.c b/target/alpha/helper.c index 2f1000c99f..990b2edde4 100644 --- a/target/alpha/helper.c +++ b/target/alpha/helper.c @@ -476,7 +476,7 @@ bool alpha_cpu_exec_interrupt(CPUState *cs, int interrupt_request) #endif /* !CONFIG_USER_ONLY */ -void alpha_cpu_dump_state(CPUState *cs, FILE *f, int flags) +void alpha_cpu_dump_state(CPUAlphaState *env, FILE *f, int flags) { static const char linux_reg_names[31][4] = { "v0", "t0", "t1", "t2", "t3", "t4", "t5", "t6", @@ -484,7 +484,6 @@ void alpha_cpu_dump_state(CPUState *cs, FILE *f, int flags) "a0", "a1", "a2", "a3", "a4", "a5", "t8", "t9", "t10", "t11", "ra", "t12", "at", "gp", "sp" }; - CPUAlphaState *env = cpu_env(cs); int i; qemu_fprintf(f, "PC " TARGET_FMT_lx " PS %02x\n", diff --git a/target/arm/cpu.c b/target/arm/cpu.c index c8e032d433..a7bb025c11 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1213,10 +1213,9 @@ static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) #ifdef TARGET_AARCH64 -static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) +static void aarch64_cpu_dump_state(CPUARMState *env, FILE *f, int flags) { - ARMCPU *cpu = ARM_CPU(cs); - CPUARMState *env = &cpu->env; + ARMCPU *cpu = env_archcpu(env); uint32_t psr = pstate_read(env); int i, j; int el = arm_current_el(env); @@ -1372,21 +1371,20 @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) #else -static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) +static inline void aarch64_cpu_dump_state(CPUARMState *env, FILE *f, int flags) { g_assert_not_reached(); } #endif -static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags) +static void arm_cpu_dump_state(CPUARMState *env, FILE *f, int flags) { - ARMCPU *cpu = ARM_CPU(cs); - CPUARMState *env = &cpu->env; + ARMCPU *cpu = env_archcpu(env); int i; if (is_a64(env)) { - aarch64_cpu_dump_state(cs, f, flags); + aarch64_cpu_dump_state(env, f, flags); return; } diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 19b6298a31..46a1ba3b3a 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -155,9 +155,8 @@ static ObjectClass *avr_cpu_class_by_name(const char *cpu_model) return object_class_by_name(cpu_model); } -static void avr_cpu_dump_state(CPUState *cs, FILE *f, int flags) +static void avr_cpu_dump_state(CPUAVRState *env, FILE *f, int flags) { - CPUAVRState *env = cpu_env(cs); int i; qemu_fprintf(f, "\n"); diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 8038df1c82..58c627946b 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -176,7 +176,7 @@ void hexagon_debug_qreg(CPUHexagonState *env, int regnum) print_qreg(stdout, env, regnum, false); } -static void hexagon_dump(CPUHexagonState *env, FILE *f, int flags) +static void hexagon_dump_state(CPUHexagonState *env, FILE *f, int flags) { HexagonCPU *cpu = env_archcpu(env); @@ -235,14 +235,9 @@ static void hexagon_dump(CPUHexagonState *env, FILE *f, int flags) } } -static void hexagon_dump_state(CPUState *cs, FILE *f, int flags) -{ - hexagon_dump(cpu_env(cs), f, flags); -} - void hexagon_debug(CPUHexagonState *env) { - hexagon_dump(env, stdout, CPU_DUMP_FPU); + hexagon_dump_state(env, stdout, CPU_DUMP_FPU); } static void hexagon_cpu_set_pc(CPUHexagonState *env, vaddr value) diff --git a/target/hppa/helper.c b/target/hppa/helper.c index d4b1a3cd5a..2456d36abe 100644 --- a/target/hppa/helper.c +++ b/target/hppa/helper.c @@ -100,7 +100,7 @@ void cpu_hppa_put_psw(CPUHPPAState *env, target_ulong psw) env->psw_cb = cb; } -void hppa_cpu_dump_state(CPUState *cs, FILE *f, int flags) +void hppa_cpu_dump_state(CPUHPPAState *env, FILE *f, int flags) { #ifndef CONFIG_USER_ONLY static const char cr_name[32][5] = { @@ -115,7 +115,6 @@ void hppa_cpu_dump_state(CPUState *cs, FILE *f, int flags) }; #endif - CPUHPPAState *env = cpu_env(cs); target_ulong psw = cpu_hppa_get_psw(env); target_ulong psw_cb; char psw_c[20]; diff --git a/target/hppa/int_helper.c b/target/hppa/int_helper.c index 58695def82..8cb9defa50 100644 --- a/target/hppa/int_helper.c +++ b/target/hppa/int_helper.c @@ -254,7 +254,7 @@ void hppa_cpu_do_interrupt(CPUState *cs) } else { fprintf(logfile, "INT: cpu %d unknown %d\n", cs->cpu_index, i); } - hppa_cpu_dump_state(cs, logfile, 0); + hppa_cpu_dump_state(env, logfile, 0); qemu_log_unlock(logfile); } } diff --git a/target/hppa/sys_helper.c b/target/hppa/sys_helper.c index 9b43b556fd..320d8ad995 100644 --- a/target/hppa/sys_helper.c +++ b/target/hppa/sys_helper.c @@ -98,10 +98,8 @@ void HELPER(rfi)(CPUHPPAState *env) if (qemu_loglevel_mask(CPU_LOG_INT)) { FILE *logfile = qemu_log_trylock(); if (logfile) { - CPUState *cs = env_cpu(env); - - fprintf(logfile, "RFI: cpu %d\n", cs->cpu_index); - hppa_cpu_dump_state(cs, logfile, 0); + fprintf(logfile, "RFI: cpu %d\n", env_cpu(env)->cpu_index); + hppa_cpu_dump_state(env, logfile, 0); qemu_log_unlock(logfile); } } diff --git a/target/i386/cpu-dump.c b/target/i386/cpu-dump.c index a72ed93bd2..9e4b8d6742 100644 --- a/target/i386/cpu-dump.c +++ b/target/i386/cpu-dump.c @@ -341,10 +341,9 @@ void x86_cpu_dump_local_apic_state(CPUState *cs, int flags) #define DUMP_CODE_BYTES_TOTAL 50 #define DUMP_CODE_BYTES_BACKWARD 20 -void x86_cpu_dump_state(CPUState *cs, FILE *f, int flags) +void x86_cpu_dump_state(CPUX86State *env, FILE *f, int flags) { - X86CPU *cpu = X86_CPU(cs); - CPUX86State *env = &cpu->env; + CPUState *cs = env_cpu(env); int eflags, i, nb; static const char *seg_name[6] = { "ES", "CS", "SS", "DS", "FS", "GS" }; diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 6962f4b6de..ae00d5e222 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -742,9 +742,8 @@ static ObjectClass *loongarch_cpu_class_by_name(const char *cpu_model) return oc; } -static void loongarch_cpu_dump_state(CPUState *cs, FILE *f, int flags) +static void loongarch_cpu_dump_state(CPULoongArchState *env, FILE *f, int flags) { - CPULoongArchState *env = cpu_env(cs); int i; qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc); diff --git a/target/m68k/translate.c b/target/m68k/translate.c index ad3ce34501..aafc32aa48 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -6136,9 +6136,8 @@ static double floatx80_to_double(CPUM68KState *env, uint16_t high, uint64_t low) return u.d; } -void m68k_cpu_dump_state(CPUState *cs, FILE *f, int flags) +void m68k_cpu_dump_state(CPUM68KState *env, FILE *f, int flags) { - CPUM68KState *env = cpu_env(cs); int i; uint16_t sr; for (i = 0; i < 8; i++) { diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 4beaf69e76..98404a3036 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1785,9 +1785,8 @@ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns, translator_loop(cpu, tb, max_insns, pc, host_pc, &mb_tr_ops, &dc.base); } -void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags) +void mb_cpu_dump_state(CPUMBState *env, FILE *f, int flags) { - CPUMBState *env = cpu_env(cs); uint32_t iflags; int i; diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 506494f7e6..d631249216 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -78,9 +78,8 @@ static void fpu_dump_state(CPUMIPSState *env, FILE *f, int flags) } } -static void mips_cpu_dump_state(CPUState *cs, FILE *f, int flags) +static void mips_cpu_dump_state(CPUMIPSState *env, FILE *f, int flags) { - CPUMIPSState *env = cpu_env(cs); int i; qemu_fprintf(f, "pc=0x" TARGET_FMT_lx " HI=0x" TARGET_FMT_lx diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index ca566847cb..3ca94f00b1 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -1654,9 +1654,8 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, &openrisc_tr_ops, &ctx.base); } -void openrisc_cpu_dump_state(CPUState *cs, FILE *f, int flags) +void openrisc_cpu_dump_state(CPUOpenRISCState *env, FILE *f, int flags) { - CPUOpenRISCState *env = cpu_env(cs); int i; qemu_fprintf(f, "PC=%08x\n", env->pc); diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 95bf78a3b7..b8d859846f 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7522,18 +7522,17 @@ static void ppc_cpu_register_types(void) #endif } -void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags) +void ppc_cpu_dump_state(CPUPPCState *env, FILE *f, int flags) { #define RGPL 4 #define RFPL 4 - CPUPPCState *env = cpu_env(cs); int i; qemu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR " TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n", env->nip, env->lr, env->ctr, cpu_read_xer(env), - cs->cpu_index); + env_cpu(env)->cpu_index); qemu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF " "%08x iidx %d didx %d\n", env->msr, env->spr[SPR_HID0], env->hflags, diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index dfaa9a9c1c..152f5c4e76 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -746,10 +746,8 @@ char *riscv_cpu_get_name(RISCVCPU *cpu) return cpu_model_from_type(typename); } -static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) +static void riscv_cpu_dump_state(CPURISCVState *env, FILE *f, int flags) { - RISCVCPU *cpu = RISCV_CPU(cs); - CPURISCVState *env = &cpu->env; int i, j; uint8_t *p; @@ -865,7 +863,7 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) csr_ops[csrno].name, val); } } - uint16_t vlenb = cpu->cfg.vlenb; + uint16_t vlenb = env_archcpu(env)->cfg.vlenb; for (i = 0; i < 32; i++) { qemu_fprintf(f, " %-8s ", riscv_rvv_regnames[i]); diff --git a/target/rx/translate.c b/target/rx/translate.c index 9aade2b6e5..5747425345 100644 --- a/target/rx/translate.c +++ b/target/rx/translate.c @@ -131,9 +131,8 @@ static int bdsp_s(DisasContext *ctx, int d) /* Include the auto-generated decoder. */ #include "decode-insns.c.inc" -void rx_cpu_dump_state(CPUState *cs, FILE *f, int flags) +void rx_cpu_dump_state(CPURXState *env, FILE *f, int flags) { - CPURXState *env = cpu_env(cs); int i; uint32_t psw; diff --git a/target/s390x/cpu-dump.c b/target/s390x/cpu-dump.c index 69cc9f7746..c33d6b2855 100644 --- a/target/s390x/cpu-dump.c +++ b/target/s390x/cpu-dump.c @@ -25,9 +25,8 @@ #include "qemu/qemu-print.h" #include "sysemu/tcg.h" -void s390_cpu_dump_state(CPUState *cs, FILE *f, int flags) +void s390_cpu_dump_state(CPUS390XState *env, FILE *f, int flags) { - CPUS390XState *env = cpu_env(cs); int i; qemu_fprintf(f, "PSW=mask %016" PRIx64 " addr %016" PRIx64, diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 53b092175d..b4eaafe2c4 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -156,9 +156,8 @@ void sh4_translate_init(void) fregnames[i]); } -void superh_cpu_dump_state(CPUState *cs, FILE *f, int flags) +void superh_cpu_dump_state(CPUSH4State *env, FILE *f, int flags) { - CPUSH4State *env = cpu_env(cs); int i; qemu_fprintf(f, "pc=0x%08x sr=0x%08x pr=0x%08x fpscr=0x%08x\n", diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 83c86c03bd..bf37734efd 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -616,9 +616,8 @@ static void cpu_print_cc(FILE *f, uint32_t cc) #define REGS_PER_LINE 8 #endif -static void sparc_cpu_dump_state(CPUState *cs, FILE *f, int flags) +static void sparc_cpu_dump_state(CPUSPARCState *env, FILE *f, int flags) { - CPUSPARCState *env = cpu_env(cs); int i, x; qemu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc, diff --git a/target/tricore/translate.c b/target/tricore/translate.c index 4a12d2ca19..c9f96ef3ae 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -92,9 +92,8 @@ enum { MODE_UU = 3, }; -void tricore_cpu_dump_state(CPUState *cs, FILE *f, int flags) +void tricore_cpu_dump_state(CPUTriCoreState *env, FILE *f, int flags) { - CPUTriCoreState *env = cpu_env(cs); uint32_t psw; int i; diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index f4da4a40f9..6827f39492 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -1235,9 +1235,8 @@ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns, &xtensa_translator_ops, &dc.base); } -void xtensa_cpu_dump_state(CPUState *cs, FILE *f, int flags) +void xtensa_cpu_dump_state(CPUXtensaState *env, FILE *f, int flags) { - CPUXtensaState *env = cpu_env(cs); xtensa_isa isa = env->config->isa; int i, j;