From patchwork Thu Nov 14 07:59:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhang Rui X-Patchwork-Id: 843414 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 30B9C1E8857 for ; Thu, 14 Nov 2024 08:03:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731571411; cv=none; b=ROjoAld1o/LAvwzl6cnIoClQ/fAgmHY4L2wXMK2tbizI4F1jIbQR8ev//Wgg8P57lG0Y3jzIE2S6wZNmzgRBVQwW40VJefwSBKCfXQUeNwIkqcm43IUowU3wNVVF9SRUoxSa+zY/wfacJo0JSduD6BH5zTBZSMOnGUrd4cB6ZCM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731571411; c=relaxed/simple; bh=Irfwz6f+CCffVc4a2X3/8hjZ28G+Gyv2lmT80b3w2wY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=EPWY0srfhJbDvJmIwe+eP7A9vm2ZD7DvjFTrByfk0PXJJJw1R7zpdVNYu91FgwiAtS02LWprTZ4ADYXmNOIED5bXR9XOiN0stz2FdSHGvt5EFB3K0/dCPwX5HIDgr5aHK5XOf1a87EW/YrLpGAuXeauDRnscaSeRRgs8dWobpkY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Mpr56vOJ; arc=none smtp.client-ip=192.198.163.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Mpr56vOJ" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1731571410; x=1763107410; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Irfwz6f+CCffVc4a2X3/8hjZ28G+Gyv2lmT80b3w2wY=; b=Mpr56vOJhRIoyY6xXbApaqmLYrMuKC7kDZT6NLD3Bki8Rv4jDJwrpITU ljAJKr37oO3IyXxl957wJlf9znISHHvNRWmLwHjXws9C+7h5nKzCmRRyD rSg7w/U8kjz31gsGc9DTryID4kZYE+LuQBlMKtT1IIbAr6dGjMp7uxg82 Shkfts9CQcMeOlJuV8lm1hZsVbvKy06RPy5xpr9T/JjC9VwwL0UR04MiC nlOxp+TjgtHbBYpM2a8ylDVEWOndjeQhwqyK/J+I+e65q4emOnUfbHc5Y 3VuJvz3BGW1DpTBS4R6g0KlunEr4wbkcy0pRlhqw3c3OqNG7XdV+J9mtH Q==; X-CSE-ConnectionGUID: TUU9aEM1QhKiZke7PjdqwQ== X-CSE-MsgGUID: mCOnnN/+QH2vHqzdF1bxlg== X-IronPort-AV: E=McAfee;i="6700,10204,11255"; a="31600433" X-IronPort-AV: E=Sophos;i="6.12,153,1728975600"; d="scan'208";a="31600433" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Nov 2024 00:03:16 -0800 X-CSE-ConnectionGUID: 7/gel0/GT5GC+XtbEcU/2w== X-CSE-MsgGUID: k9A9jbp/R82MAmgSJf+4Ag== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,153,1728975600"; d="scan'208";a="125627444" Received: from rzhang1-mobl.sh.intel.com ([10.239.158.59]) by orviesa001.jf.intel.com with ESMTP; 14 Nov 2024 00:03:14 -0800 From: Zhang Rui To: rafael.j.wysocki@intel.com, len.brown@intel.com Cc: linux-pm@vger.kernel.org Subject: [PATCH 01/10] tools/power turbostat: Remove PC7/PC9 support on MTL Date: Thu, 14 Nov 2024 15:59:37 +0800 Message-ID: <20241114075946.118577-2-rui.zhang@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241114075946.118577-1-rui.zhang@intel.com> References: <20241114075946.118577-1-rui.zhang@intel.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Similar to ADL/RPL, MTL support CC1/CC6/CC7/PC2/PC3/PC6/PC8/CP10. Remove PC7/PC9 support on MTL. Signed-off-by: Zhang Rui --- tools/power/x86/turbostat/turbostat.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tools/power/x86/turbostat/turbostat.c b/tools/power/x86/turbostat/turbostat.c index 089220aaa5c9..bf1b5fe1f00d 100644 --- a/tools/power/x86/turbostat/turbostat.c +++ b/tools/power/x86/turbostat/turbostat.c @@ -1003,8 +1003,8 @@ static const struct platform_data turbostat_pdata[] = { { INTEL_RAPTORLAKE, &adl_features }, { INTEL_RAPTORLAKE_P, &adl_features }, { INTEL_RAPTORLAKE_S, &adl_features }, - { INTEL_METEORLAKE, &cnl_features }, - { INTEL_METEORLAKE_L, &cnl_features }, + { INTEL_METEORLAKE, &adl_features }, + { INTEL_METEORLAKE_L, &adl_features }, { INTEL_ARROWLAKE_H, &arl_features }, { INTEL_ARROWLAKE_U, &arl_features }, { INTEL_ARROWLAKE, &arl_features }, From patchwork Thu Nov 14 07:59:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhang Rui X-Patchwork-Id: 843416 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E29291E8857 for ; Thu, 14 Nov 2024 08:03:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731571409; cv=none; b=dKeJH5FDssuFUVz+g7RF85jQZksfH/rbbq0xEOy2CL0TCscKftz0NFNI43hhJfaL5j74imbJ8eQD+dfBWSO/O7hRXZvIQiNURE7YIX9jrpHmMbbMYkE8jyCpOiy8xoHsEjfpxEUiXu6PsTK20e0TzyiaflZvI+oD+tPPkzxmzgs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731571409; c=relaxed/simple; bh=IQjSfD8xjGG2y6k7Z3sum460fevHAohcPX5rFtkmUQw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=JbRbWb/1OWxImt2xF8QqEE5rMyljKJih+xQ5i/plp2lerJh6Lt1Y7sk1N75JIkh0efERHe1PBYCWDk6Vjzj1Devu48lXFeAb+pjcn5GtP9o53RrgCtUrD9zzVHlXoqadIg5NpMJXxRmy5iEDne+c1L29HxQHrCX0GApHValfToo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=eevRHBWu; arc=none smtp.client-ip=192.198.163.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="eevRHBWu" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1731571408; x=1763107408; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=IQjSfD8xjGG2y6k7Z3sum460fevHAohcPX5rFtkmUQw=; b=eevRHBWuN/cLiZWvnbTax8mm5L376e+WuVK6Vusw8ID1flDjrlh6/FAU VX6BsLlB1SulCJ2SP7NTHxbgFIvNtwH+A9BVuki8iVxmBn1lf2m6kVnWM Ufg6oUGNTM5QO6YTh5HOZ89CEIZPKgMeExgQjAT9/Ow7bhC4YlsTLfwnE b2IPXUEJPPQ0XMjn1OJE8oyZea2w03W47eFT2uI3ll1JxaJd2Jk7HXU3+ DdgNbLDMX3OiXAYa+TV3YW0Wp/U8p/KA3dKpapgabHZhoBJIk6gjsnQR3 HdNerembGBxAXIws3JM8cvGmBTz5gW52lp/KUsBX8uy1mq/tR3EbnID6Q g==; X-CSE-ConnectionGUID: brB03X7/TVy2XZpbNbuvSg== X-CSE-MsgGUID: ZVTYpCCETRmgbs9Nu+TnLw== X-IronPort-AV: E=McAfee;i="6700,10204,11255"; a="31600437" X-IronPort-AV: E=Sophos;i="6.12,153,1728975600"; d="scan'208";a="31600437" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Nov 2024 00:03:19 -0800 X-CSE-ConnectionGUID: gQ1k/PmrRkSdJmHudPPOfA== X-CSE-MsgGUID: FxZ5mvL+SIamuUa/7s/nuA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,153,1728975600"; d="scan'208";a="125627463" Received: from rzhang1-mobl.sh.intel.com ([10.239.158.59]) by orviesa001.jf.intel.com with ESMTP; 14 Nov 2024 00:03:18 -0800 From: Zhang Rui To: rafael.j.wysocki@intel.com, len.brown@intel.com Cc: linux-pm@vger.kernel.org Subject: [PATCH 04/10] tools/power turbostat: Remove PC3 support on Lunarlake Date: Thu, 14 Nov 2024 15:59:40 +0800 Message-ID: <20241114075946.118577-5-rui.zhang@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241114075946.118577-1-rui.zhang@intel.com> References: <20241114075946.118577-1-rui.zhang@intel.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Lunarlake supports CC1/CC6/CC7/PC2/PC6/PC10. Remove PC3 support on Lunarlake. Signed-off-by: Zhang Rui --- tools/power/x86/turbostat/turbostat.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/power/x86/turbostat/turbostat.c b/tools/power/x86/turbostat/turbostat.c index 3d59718516df..9d76329e108f 100644 --- a/tools/power/x86/turbostat/turbostat.c +++ b/tools/power/x86/turbostat/turbostat.c @@ -752,7 +752,7 @@ static const struct platform_features lnl_features = { .has_nhm_msrs = 1, .has_config_tdp = 1, .bclk_freq = BCLK_100MHZ, - .supported_cstates = CC1 | CC6 | CC7 | PC2 | PC3 | PC6 | PC10, + .supported_cstates = CC1 | CC6 | CC7 | PC2 | PC6 | PC10, .cst_limit = CST_LIMIT_HSW, .has_irtl_msrs = 1, .has_msr_core_c1_res = 1, From patchwork Thu Nov 14 07:59:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhang Rui X-Patchwork-Id: 843415 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 240C822611 for ; Thu, 14 Nov 2024 08:03:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731571410; cv=none; b=cTk2dEMISoHMy0zlx9Um7bVm8FRu153e6mf4apzM0TqfavquEUu+m0quklSlLrryVGwDdyKKPRYY6aN9monAdhiqwBkWWnS+ugXHrCj3Ks1i1F0yWK+k2YzYd+DRk6VB0HaZBisVd4b3RQGb3AX9P2Qq61f/ovU3qoJEdr43R5w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731571410; c=relaxed/simple; bh=GQBIc9cNmBVfSCy0H2v7jCxrHQRrUvAhVov6nj7t06Q=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=VrzJ4ssfRHSNF/Pmthp6iubAoVAHQSP1faxg0aAgCm9e8ZfeH19gyq992BwzzZz280PSXAgMi5+1UIP0chRNoAB37G3eldHrV8jBIIwilN5fQtBPEq91Z4pKaxbU6d0rtsRBI5y/5/4wTxTnDFcoOk3Xwbj8oQRM5TTVf6RW/40= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=EhfGjtvM; arc=none smtp.client-ip=192.198.163.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="EhfGjtvM" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1731571409; x=1763107409; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=GQBIc9cNmBVfSCy0H2v7jCxrHQRrUvAhVov6nj7t06Q=; b=EhfGjtvMzwhixFDjmiqmEoS5JP+3tyFHjRLbOA1lyrOxxgrnAh7GVpEP H2kkkt0zBPaJ1YEKBkn2e70d4D3v2HOHQTLev76OUofG5G9BU3hykHWjm /du3StRH/r2bHID5fnYjz6oeuthub6RWAVq3doZkezGtAYOBpk1ECmc/s N+NmjpzwUH3U8abvxuRZ2Hi7Vhy0vQNnEWT1VtMAzgyJd3ap2+Jy29Ppk VBk1a+DyKsZBZRcmBjxPE9RW3Frfpq496Na8qHk4o4tPlxU5dNsdFUMQS sdMMwscCys8ZzNGgg/GyML1dnqm0YxQz+P+Afp3Gh239KABnlRqBxgJ8+ g==; X-CSE-ConnectionGUID: leDVKGx+QSS/vfzAObMhiw== X-CSE-MsgGUID: KXG96DgQQ9mRZ8CGcSNs+A== X-IronPort-AV: E=McAfee;i="6700,10204,11255"; a="31600439" X-IronPort-AV: E=Sophos;i="6.12,153,1728975600"; d="scan'208";a="31600439" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Nov 2024 00:03:21 -0800 X-CSE-ConnectionGUID: UOle5x4RSlyjdBNOxM2B4A== X-CSE-MsgGUID: hZbHitiUQv6+bV3+JsGZPA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,153,1728975600"; d="scan'208";a="125627469" Received: from rzhang1-mobl.sh.intel.com ([10.239.158.59]) by orviesa001.jf.intel.com with ESMTP; 14 Nov 2024 00:03:19 -0800 From: Zhang Rui To: rafael.j.wysocki@intel.com, len.brown@intel.com Cc: linux-pm@vger.kernel.org Subject: [PATCH 05/10] tools/power turbostat: Add initial support for GraniteRapids-D Date: Thu, 14 Nov 2024 15:59:41 +0800 Message-ID: <20241114075946.118577-6-rui.zhang@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241114075946.118577-1-rui.zhang@intel.com> References: <20241114075946.118577-1-rui.zhang@intel.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add initial support for GraniteRapids-D. It shares the same features with SapphireRapids. Signed-off-by: Zhang Rui --- tools/power/x86/turbostat/turbostat.c | 1 + 1 file changed, 1 insertion(+) diff --git a/tools/power/x86/turbostat/turbostat.c b/tools/power/x86/turbostat/turbostat.c index 9d76329e108f..d8338458d031 100644 --- a/tools/power/x86/turbostat/turbostat.c +++ b/tools/power/x86/turbostat/turbostat.c @@ -997,6 +997,7 @@ static const struct platform_data turbostat_pdata[] = { { INTEL_SAPPHIRERAPIDS_X, &spr_features }, { INTEL_EMERALDRAPIDS_X, &spr_features }, { INTEL_GRANITERAPIDS_X, &spr_features }, + { INTEL_GRANITERAPIDS_D, &spr_features }, { INTEL_LAKEFIELD, &cnl_features }, { INTEL_ALDERLAKE, &adl_features }, { INTEL_ALDERLAKE_L, &adl_features }, From patchwork Thu Nov 14 07:59:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhang Rui X-Patchwork-Id: 843413 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B85251F6671 for ; Thu, 14 Nov 2024 08:03:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731571413; cv=none; b=Co6WSw+aXvpjW8E+3XnHuIdFG1eNEVTpJ32JoZmdP17QJH45DNH+CDGQe/sJnTOn6kj6MNXFot+arbRmdrNOZ9BE68Ve5InAn/UcRAcxeBpsrbWnE7C4DvjZqdstcxAZ0QPAxJdCoDU4ozEWP38ivYWfJuyvWk03vYt+5gJ9jiw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731571413; c=relaxed/simple; bh=pvS1h4Gp7T7xHYcLKeXGBr2z+uIKQs0CI+BDqdqe/qI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=cQKCSKpxb5R8SJcpLEHp3Lb/eLuFan2BdZrpJ2Yo9EWEsMsihyEBEic898n4+E41R1emN7KASgXRTblfBXz0ouqG/Loy3n+58QIvE1j3KbiGkcH1wh470Q/YvtBOT6F5WND4UPIuXXKhx4oRQHL7vVA3r/rzTyW+CjAY5cYtlVE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=gS8oxjsU; arc=none smtp.client-ip=192.198.163.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="gS8oxjsU" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1731571411; x=1763107411; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=pvS1h4Gp7T7xHYcLKeXGBr2z+uIKQs0CI+BDqdqe/qI=; b=gS8oxjsULT1/9S+sd7C8h0BBdbc39BwymqnzV9VqvHjclVu287HW18/9 isyeL9c36lB5uk9gsSbbqxwpun7N79sW86BTaenW8+TDFebcngFdEPrW+ aNSqEyD6ZsUj7jYwtLDefMURslKpdvcVoGeZyyZCr4ZXY19gExHH68N1L a7pwQQgKW/r7BYSJNoFPjfM1zqO2fIqW1R5tw0GGaIUjcGg9YqcAyvcnR mhqx+YajyuwL/jtAE+18QgdBh8eb1WiqrfVk8loWxzISVnLd5iGUL9O/7 TDU06GMlJu1Yufso8CwrG3mzMyO0Hhce1BOIbtCyn+vGX/k+Wxyxs73cP A==; X-CSE-ConnectionGUID: VIwDIklWSP+cPV9lWobeuQ== X-CSE-MsgGUID: 0Jh5mnM3Sc+wC0g59BWREQ== X-IronPort-AV: E=McAfee;i="6700,10204,11255"; a="31600442" X-IronPort-AV: E=Sophos;i="6.12,153,1728975600"; d="scan'208";a="31600442" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Nov 2024 00:03:22 -0800 X-CSE-ConnectionGUID: 56werRu4TRqkGa2hAtb4YQ== X-CSE-MsgGUID: 8q6vYVKbQ+WnoZm49j9W3A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,153,1728975600"; d="scan'208";a="125627475" Received: from rzhang1-mobl.sh.intel.com ([10.239.158.59]) by orviesa001.jf.intel.com with ESMTP; 14 Nov 2024 00:03:20 -0800 From: Zhang Rui To: rafael.j.wysocki@intel.com, len.brown@intel.com Cc: linux-pm@vger.kernel.org Subject: [PATCH 06/10] tools/power turbostat: Enhance platform divergence description Date: Thu, 14 Nov 2024 15:59:42 +0800 Message-ID: <20241114075946.118577-7-rui.zhang@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241114075946.118577-1-rui.zhang@intel.com> References: <20241114075946.118577-1-rui.zhang@intel.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 In various generations, platforms often share a majority of features, diverging only in a few specific aspects. The current approach of using hardcoded values in 'platform_features' structure fails to effectively represent these divergences. To improve the description of platform divergence: 1. Each newly introduced 'platform_features' structure must have a base, typically derived from the previous generation. 2. Platform feature values should be inherited from the base structure rather than being hardcoded. This approach ensures a more accurate and maintainable representation of platform-specific features across different generations. Converts `adl_features` and `lnl_features` to follow this new scheme. No functional change. Signed-off-by: Zhang Rui --- tools/power/x86/turbostat/turbostat.c | 58 ++++++++++++++------------- 1 file changed, 30 insertions(+), 28 deletions(-) diff --git a/tools/power/x86/turbostat/turbostat.c b/tools/power/x86/turbostat/turbostat.c index d8338458d031..8a45b1c4c225 100644 --- a/tools/power/x86/turbostat/turbostat.c +++ b/tools/power/x86/turbostat/turbostat.c @@ -729,38 +729,40 @@ static const struct platform_features cnl_features = { .enable_tsc_tweak = 1, }; +/* Copied from cnl_features, with PC7/PC9 removed */ static const struct platform_features adl_features = { - .has_msr_misc_feature_control = 1, - .has_msr_misc_pwr_mgmt = 1, - .has_nhm_msrs = 1, - .has_config_tdp = 1, - .bclk_freq = BCLK_100MHZ, - .supported_cstates = CC1 | CC6 | CC7 | PC2 | PC3 | PC6 | PC8 | PC10, - .cst_limit = CST_LIMIT_HSW, - .has_irtl_msrs = 1, - .has_msr_core_c1_res = 1, - .has_ext_cst_msrs = 1, - .trl_msrs = TRL_BASE, - .tcc_offset_bits = 6, - .rapl_msrs = RAPL_PKG_ALL | RAPL_CORE_ALL | RAPL_DRAM | RAPL_DRAM_PERF_STATUS | RAPL_GFX, - .enable_tsc_tweak = 1, + .has_msr_misc_feature_control = cnl_features.has_msr_misc_feature_control, + .has_msr_misc_pwr_mgmt = cnl_features.has_msr_misc_pwr_mgmt, + .has_nhm_msrs = cnl_features.has_nhm_msrs, + .has_config_tdp = cnl_features.has_config_tdp, + .bclk_freq = cnl_features.bclk_freq, + .supported_cstates = CC1 | CC6 | CC7 | PC2 | PC3 | PC6 | PC8 | PC10, + .cst_limit = cnl_features.cst_limit, + .has_irtl_msrs = cnl_features.has_irtl_msrs, + .has_msr_core_c1_res = cnl_features.has_msr_core_c1_res, + .has_ext_cst_msrs = cnl_features.has_ext_cst_msrs, + .trl_msrs = cnl_features.trl_msrs, + .tcc_offset_bits = cnl_features.tcc_offset_bits, + .rapl_msrs = cnl_features.rapl_msrs, + .enable_tsc_tweak = cnl_features.enable_tsc_tweak, }; +/* Copied from adl_features, with PC3/PC8 removed */ static const struct platform_features lnl_features = { - .has_msr_misc_feature_control = 1, - .has_msr_misc_pwr_mgmt = 1, - .has_nhm_msrs = 1, - .has_config_tdp = 1, - .bclk_freq = BCLK_100MHZ, - .supported_cstates = CC1 | CC6 | CC7 | PC2 | PC6 | PC10, - .cst_limit = CST_LIMIT_HSW, - .has_irtl_msrs = 1, - .has_msr_core_c1_res = 1, - .has_ext_cst_msrs = 1, - .trl_msrs = TRL_BASE, - .tcc_offset_bits = 6, - .rapl_msrs = RAPL_PKG_ALL | RAPL_CORE_ALL | RAPL_DRAM | RAPL_DRAM_PERF_STATUS | RAPL_GFX, - .enable_tsc_tweak = 1, + .has_msr_misc_feature_control = adl_features.has_msr_misc_feature_control, + .has_msr_misc_pwr_mgmt = adl_features.has_msr_misc_pwr_mgmt, + .has_nhm_msrs = adl_features.has_nhm_msrs, + .has_config_tdp = adl_features.has_config_tdp, + .bclk_freq = adl_features.bclk_freq, + .supported_cstates = CC1 | CC6 | CC7 | PC2 | PC6 | PC10, + .cst_limit = adl_features.cst_limit, + .has_irtl_msrs = adl_features.has_irtl_msrs, + .has_msr_core_c1_res = adl_features.has_msr_core_c1_res, + .has_ext_cst_msrs = adl_features.has_ext_cst_msrs, + .trl_msrs = adl_features.trl_msrs, + .tcc_offset_bits = adl_features.tcc_offset_bits, + .rapl_msrs = adl_features.rapl_msrs, + .enable_tsc_tweak = adl_features.enable_tsc_tweak, }; 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14 Nov 2024 00:03:26 -0800 From: Zhang Rui To: rafael.j.wysocki@intel.com, len.brown@intel.com Cc: linux-pm@vger.kernel.org Subject: [PATCH 10/10] tools/power turbostat: Add support for /sys/class/drm/card1 Date: Thu, 14 Nov 2024 15:59:46 +0800 Message-ID: <20241114075946.118577-11-rui.zhang@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241114075946.118577-1-rui.zhang@intel.com> References: <20241114075946.118577-1-rui.zhang@intel.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On some machines, the graphics device is enumerated as /sys/class/drm/card1 instead of /sys/class/drm/card0. The current implementation does not handle this scenario, resulting in the loss of graphics C6 residency and frequency information. Add support for /sys/class/drm/card1, ensuring that turbostat can retrieve and display the graphics columns for these platforms. Signed-off-by: Zhang Rui --- tools/power/x86/turbostat/turbostat.c | 38 ++++++++++++++++++++------- 1 file changed, 29 insertions(+), 9 deletions(-) diff --git a/tools/power/x86/turbostat/turbostat.c b/tools/power/x86/turbostat/turbostat.c index 52b6ffc41bdf..43ca50107e1a 100644 --- a/tools/power/x86/turbostat/turbostat.c +++ b/tools/power/x86/turbostat/turbostat.c @@ -6443,8 +6443,14 @@ static void set_graphics_fp(char *path, int idx) gfx_info[idx].fp = fopen_or_die(path, "r"); } +/* Enlarge this if there are /sys/class/drm/card2 ... */ +#define GFX_MAX_CARDS 2 + static void probe_graphics(void) { + char path[PATH_MAX]; + int i; + /* Xe graphics sysfs knobs */ if (!access("/sys/class/drm/card0/device/tile0/gt0/gtidle/idle_residency_ms", R_OK)) { FILE *fp; @@ -6485,22 +6491,36 @@ static void probe_graphics(void) next: /* New i915 graphics sysfs knobs */ - if (!access("/sys/class/drm/card0/gt/gt0/rc6_residency_ms", R_OK)) { - set_graphics_fp("/sys/class/drm/card0/gt/gt0/rc6_residency_ms", GFX_rc6); + for (i = 0; i < GFX_MAX_CARDS; i++) { + snprintf(path, PATH_MAX, "/sys/class/drm/card%d/gt/gt0/rc6_residency_ms", i); + if (!access(path, R_OK)) + break; + } - set_graphics_fp("/sys/class/drm/card0/gt/gt0/rps_cur_freq_mhz", GFX_MHz); + if (i == GFX_MAX_CARDS) + goto legacy_i915; - set_graphics_fp("/sys/class/drm/card0/gt/gt0/rps_act_freq_mhz", GFX_ACTMHz); + snprintf(path, PATH_MAX, "/sys/class/drm/card%d/gt/gt0/rc6_residency_ms", i); + set_graphics_fp(path, GFX_rc6); - set_graphics_fp("/sys/class/drm/card0/gt/gt1/rc6_residency_ms", SAM_mc6); + snprintf(path, PATH_MAX, "/sys/class/drm/card%d/gt/gt0/rps_cur_freq_mhz", i); + set_graphics_fp(path, GFX_MHz); - set_graphics_fp("/sys/class/drm/card0/gt/gt1/rps_cur_freq_mhz", SAM_MHz); + snprintf(path, PATH_MAX, "/sys/class/drm/card%d/gt/gt0/rps_act_freq_mhz", i); + set_graphics_fp(path, GFX_ACTMHz); - set_graphics_fp("/sys/class/drm/card0/gt/gt1/rps_act_freq_mhz", SAM_ACTMHz); + snprintf(path, PATH_MAX, "/sys/class/drm/card%d/gt/gt1/rc6_residency_ms", i); + set_graphics_fp(path, SAM_mc6); - goto end; - } + snprintf(path, PATH_MAX, "/sys/class/drm/card%d/gt/gt1/rps_cur_freq_mhz", i); + set_graphics_fp(path, SAM_MHz); + + snprintf(path, PATH_MAX, "/sys/class/drm/card%d/gt/gt1/rps_act_freq_mhz", i); + set_graphics_fp(path, SAM_ACTMHz); + + goto end; +legacy_i915: /* Fall back to traditional i915 graphics sysfs knobs */ set_graphics_fp("/sys/class/drm/card0/power/rc6_residency_ms", GFX_rc6);