From patchwork Thu Nov 14 13:36:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 843684 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C71F0210FB; Thu, 14 Nov 2024 13:37:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731591431; cv=none; b=UCPBDrHP/bsIThzWye6XF7KsiI4SfSVzJ+uOsNKYzICkTukr3t/FiT0m3PqCBfTm3DKySEaaTtDZygSFcYoI9EeDVg4sff89lbNiNQ43vyM8UfA6xzD+vU5+AyhgRytF5D48lyFnk5t4r89kK08FCjZPE5X92fqCaTFMjmbczo4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731591431; c=relaxed/simple; bh=nH5ZbJEfnNtqpVAJdxQPimoXQFIYYcfa/hUchSNyuLA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=MoSX1HfxWY7JeaSLubn1jUWIv41uuni1Yr6KZX4jFIWBgWnBj+GlUZNDI9mZSDef+tdGqOeklgV2q1UMe6E5raLIY/ZK+BqInZwgmyPdAyKekbcknk+P0+SlK0/QZin4844sLfxoJK62abzedpLNF2u1b0R5ysNGIBcscshpioo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=qKh5Stmc; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="qKh5Stmc" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0BF32C4CED8; Thu, 14 Nov 2024 13:37:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1731591431; bh=nH5ZbJEfnNtqpVAJdxQPimoXQFIYYcfa/hUchSNyuLA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=qKh5StmcVBtM/I/ZSER9ZsAy93sMeBbJguRosTsmTZ2N/tpBZujoXRsnBMCbwFKYE 0eecR2BFdinknvUuzO3vhO/Wgkpjby408lYVps9nQoEZZtwHCXaBwOcdBIP1s1ul7Q F4dz4xAR+sq/2t2r5eOYYlE1TAV52jUtmvmsDVyRUe5uFLVX4tpOSgn329h6ZDkP6n Xiy7A+wrPnEQXzOPgNJhl0vbRm853hlo/K8oFlPtMKTC4Ilyd7CxDoMIq9FSb91uzN DKn8b1aSEdQWjsGCBFfwVAp/YwtARxFggSOXbYQtB3kZv6G3VvFeVN0xvfwS4Sh+oa IjzNFsUtG5CdA== From: Roger Quadros Date: Thu, 14 Nov 2024 15:36:52 +0200 Subject: [PATCH net-next v4 1/2] net: ethernet: ti: am65-cpsw: update pri_thread_map as per IEEE802.1Q-2014 Precedence: bulk X-Mailing-List: linux-omap@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241114-am65-cpsw-multi-rx-dscp-v4-1-93eaf6760759@kernel.org> References: <20241114-am65-cpsw-multi-rx-dscp-v4-0-93eaf6760759@kernel.org> In-Reply-To: <20241114-am65-cpsw-multi-rx-dscp-v4-0-93eaf6760759@kernel.org> To: Siddharth Vadapalli , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Simon Horman , Guillaume Nault Cc: linux-omap@vger.kernel.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, srk@ti.com, Pekka Varis , Roger Quadros X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=2982; i=rogerq@kernel.org; h=from:subject:message-id; bh=nH5ZbJEfnNtqpVAJdxQPimoXQFIYYcfa/hUchSNyuLA=; b=owEBbQKS/ZANAwAIAdJaa9O+djCTAcsmYgBnNfz/v8cIP3B7VtnfeDCJMZAu81vTLTi1HM1W7 3r4QxFCer+JAjMEAAEIAB0WIQRBIWXUTJ9SeA+rEFjSWmvTvnYwkwUCZzX8/wAKCRDSWmvTvnYw k2zED/9GragteYn3PLE5hfVQ+5wvS2F4PIBWzcKKjEZKm8mMjZvEqWlPQQGpg770edHmHM8Cn0l ASSAPukcG1Ja86mclzWNITqY/MI3EqUY/w1H+XoBC4ik7oDtniHLE3I3LKJZlHtddKw5awvx8e2 zFvqm5KRNIyIhfuLlS2YEpYLOwsu2BA9L7M7tPzEwvvnS0GcfkrZnS1WdSQlSFq55BBZw3qIgMt Er0LEiR3L3cXmfYZtt4w9nXbTSrQSY19n31WgXNubfhfBtH10TF6b9SMLTa2kt3uBCuuPAg2iV9 /8SOabUMY33IU9dY8U30C4q/Ya+NIeDa2ceBz/bWw9rZD2sb0oy1CPm92MxEOa4c48Z6hG0kngB rJ5D7Gt9RLxR1yNECDWraQLhL8Zod/lQOOvsl3yX2cMoSp5VM8txhwIwvmTGY46jEC0C4LcvWDV MX4nQtN00H0EOb9gONgnaF3yAmXee8NOsiC6xne6rHXP7LIP+6+nQMv2OS1VCfmIUNrIYdhgxPI cLEukDBvi2k51OXMqHha8GtLHdanAVHOPEbZ1rRd3V/OOvmJu5rGy2/pp2MaKBr353/iK7Dze3g 3ojKd+B/4RVn/zGGTRaA+ksmpqfCa1s4gXO49SnhnMJiDdmcXYBPg97dkID60aCnijLWE2q7+c2 jbNdm7vNXNsyaPA== X-Developer-Key: i=rogerq@kernel.org; a=openpgp; fpr=412165D44C9F52780FAB1058D25A6BD3BE763093 IEEE802.1Q-2014 supersedes IEEE802.1D-2004. Now Priority Code Point (PCP) 2 is no longer at a lower priority than PCP 0. PCP 1 (Background) is still at a lower priority than PCP 0 (Best Effort). Reference: IEEE802.1Q-2014, Standard for Local and metropolitan area networks Table I-2 - Traffic type acronyms Table I-3 - Defining traffic types Signed-off-by: Roger Quadros Reviewed-by: Siddharth Vadapalli --- drivers/net/ethernet/ti/cpsw_ale.c | 36 ++++++++++++++++++++++-------------- 1 file changed, 22 insertions(+), 14 deletions(-) diff --git a/drivers/net/ethernet/ti/cpsw_ale.c b/drivers/net/ethernet/ti/cpsw_ale.c index 8d02d2b21429..9f79056b3f48 100644 --- a/drivers/net/ethernet/ti/cpsw_ale.c +++ b/drivers/net/ethernet/ti/cpsw_ale.c @@ -1692,26 +1692,34 @@ static void cpsw_ale_policer_reset(struct cpsw_ale *ale) void cpsw_ale_classifier_setup_default(struct cpsw_ale *ale, int num_rx_ch) { int pri, idx; - /* IEEE802.1D-2004, Standard for Local and metropolitan area networks - * Table G-2 - Traffic type acronyms - * Table G-3 - Defining traffic types - * User priority values 1 and 2 effectively communicate a lower - * priority than 0. In the below table 0 is assigned to higher priority - * thread than 1 and 2 wherever possible. - * The below table maps which thread the user priority needs to be + + /* Reference: + * IEEE802.1Q-2014, Standard for Local and metropolitan area networks + * Table I-2 - Traffic type acronyms + * Table I-3 - Defining traffic types + * Section I.4 Traffic types and priority values, states: + * "0 is thus used both for default priority and for Best Effort, and + * Background is associated with a priority value of 1. This means + * that the value 1 effectively communicates a lower priority than 0." + * + * In the table below, Priority Code Point (PCP) 0 is assigned + * to a higher priority thread than PCP 1 wherever possible. + * The table maps which thread the PCP traffic needs to be * sent to for a given number of threads (RX channels). Upper threads * have higher priority. * e.g. if number of threads is 8 then user priority 0 will map to - * pri_thread_map[8-1][0] i.e. thread 2 + * pri_thread_map[8-1][0] i.e. thread 1 */ - int pri_thread_map[8][8] = { { 0, 0, 0, 0, 0, 0, 0, 0, }, + + int pri_thread_map[8][8] = { /* BK,BE,EE,CA,VI,VO,IC,NC */ + { 0, 0, 0, 0, 0, 0, 0, 0, }, { 0, 0, 0, 0, 1, 1, 1, 1, }, { 0, 0, 0, 0, 1, 1, 2, 2, }, - { 1, 0, 0, 1, 2, 2, 3, 3, }, - { 1, 0, 0, 1, 2, 3, 4, 4, }, - { 1, 0, 0, 2, 3, 4, 5, 5, }, - { 1, 0, 0, 2, 3, 4, 5, 6, }, - { 2, 0, 1, 3, 4, 5, 6, 7, } }; + { 0, 0, 1, 1, 2, 2, 3, 3, }, + { 0, 0, 1, 1, 2, 2, 3, 4, }, + { 1, 0, 2, 2, 3, 3, 4, 5, }, + { 1, 0, 2, 3, 4, 4, 5, 6, }, + { 1, 0, 2, 3, 4, 5, 6, 7 } }; cpsw_ale_policer_reset(ale); From patchwork Thu Nov 14 13:36:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 843403 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9E12C36AEC; Thu, 14 Nov 2024 13:37:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731591434; cv=none; b=BubuXqjEyWZw5VJ5jmdRaYOB8uEhtgvRuatsgqnFWL7bZMPz8s7ZXY+/J5ittUQWxesGLBqS9wIp6yzyAjAgJ/NlRdem8wRjByRTgdxr9xjDFYTkWh49gG3QRtgWrfVPi7YhaFEzJ4doj+VLoFDYC3/uPbgYaS31QLPCtBEttkA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731591434; c=relaxed/simple; bh=z0ibvP2+uFf2NigqDZN1BTPasnFxzj7OMV2W7BeLjtk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=mJxQwScFpnlJU8nS2UaArzHOWxkGzoH+Vp4LtWurqjL4/9q0YhHuFQDiofopFv250GDqsDT2fBEZCwGtfONybCv26xwsQtgfcqSnPQFmk64XlwCZmj4FNx/sHH4jBC+jAlhGqOwOnYQbSfRWLvbAOHfVlz+632qswh2knFwpFzw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=YMyXZRn+; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="YMyXZRn+" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7ED19C4CECD; Thu, 14 Nov 2024 13:37:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1731591434; bh=z0ibvP2+uFf2NigqDZN1BTPasnFxzj7OMV2W7BeLjtk=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=YMyXZRn+HhLi/gerWB9ktVwYFdfAs25Wg7SqUOYukeGHYtiLF7xV6skBVTiTL3Rcp TV8KqtXkh0DdkthCNQjd2uLcAFyGJjd8cp2XDas5PiinvVNsY6BbexjLIkc3oFcnXU mf6DAPGsIN7dnsEZ5gyBJECZOwJkgAPiP7U7U6RhimjYJRVSkk/JnR2/a6KysApXLb BQub3r5rJxPRh7bv2jSaWmJ9IWKzj2fYGIEBBsNkKUqZbSaSf4MKG+1YWqlxRnV1kV RCGHXxR0A5y9B3/z4uFPhn+5x+2ECXeQ8/YaqO+Y3Tl1dyYwYXZ3Y9LyzPN2PoRD/Q goIEG+szOkhRQ== From: Roger Quadros Date: Thu, 14 Nov 2024 15:36:53 +0200 Subject: [PATCH net-next v4 2/2] net: ethernet: ti: am65-cpsw: enable DSCP to priority map for RX Precedence: bulk X-Mailing-List: linux-omap@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241114-am65-cpsw-multi-rx-dscp-v4-2-93eaf6760759@kernel.org> References: <20241114-am65-cpsw-multi-rx-dscp-v4-0-93eaf6760759@kernel.org> In-Reply-To: <20241114-am65-cpsw-multi-rx-dscp-v4-0-93eaf6760759@kernel.org> To: Siddharth Vadapalli , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Simon Horman , Guillaume Nault Cc: linux-omap@vger.kernel.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, srk@ti.com, Pekka Varis , Roger Quadros X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=4439; i=rogerq@kernel.org; h=from:subject:message-id; bh=z0ibvP2+uFf2NigqDZN1BTPasnFxzj7OMV2W7BeLjtk=; b=owEBbQKS/ZANAwAIAdJaa9O+djCTAcsmYgBnNf0AHuDqyqgGS25QnmggNIMqhYH+U6v67V6s6 1naCcHveWGJAjMEAAEIAB0WIQRBIWXUTJ9SeA+rEFjSWmvTvnYwkwUCZzX9AAAKCRDSWmvTvnYw kzFpEACgdyykrz7NgAUhIgedUGbQu5jwz8sRk6f3Et8ZW9z0yhi7zKnVYj/HNRCMToKKCP2Rnkr +rNmMbivrHQ4rC5/A01VYN52JkjVfQUqd7fM4d5YtjQPPDMgZOIXDhPxuDJGNRZTnol51gMnk+1 W8htG14vcBpmE3xVgWc0jAYuT5XGJGYcTgwfFgV5IQRywoPeZzGBd8NCL1Ls8m6XWiHq/vxy625 7QgEsHhLkTyPAG7sE9B2EzTbQN3c+68affbNU999s+e6FC9FsoBgApZSiYWpb+vKOJEhspdBezQ TBb8xyykhL2HAEOWgegJX3VYme+PkeVYFJF4eqfnvAslLlSqnRplrUHHqaoqaUbDMCclU2AYL1e gr+AxygsJ7LAKlYUlI6kHNhjnm5tOgf5F5DkCRJ0qosk4VkQdEcX7C3YHLwL97QhmQRmWT37L89 IkmHJILESNaS5++1KfZ8GSPZW9YXBDpfO6ePYl/h78Xcd5POzbe+6gAUuZhIIR4PaZmh6yoG1bD KYpOFSRLkUNh6ElXy1biOr09JvJgUAn0EFidgbEZo3x/e/RFRtRLHEJolQ/WXCqyDx+r/pg3m7W 7dRAwU4cNmIe97Xvhz4jSq2r6990JQEgwz9klGhI0U+pExsFLA6InpBbC0AgGsYHjtvFXwxa7u3 3Amydvz64lwxlvw== X-Developer-Key: i=rogerq@kernel.org; a=openpgp; fpr=412165D44C9F52780FAB1058D25A6BD3BE763093 AM65 CPSW hardware can map the 6-bit DSCP/TOS field to appropriate priority queue via DSCP to Priority mapping registers (CPSW_PN_RX_PRI_MAP_REG). Use a default DSCP to User Priority (UP) mapping as per https://datatracker.ietf.org/doc/html/rfc8325#section-4.3 and https://datatracker.ietf.org/doc/html/rfc8622#section-11 Signed-off-by: Roger Quadros --- drivers/net/ethernet/ti/am65-cpsw-nuss.c | 100 +++++++++++++++++++++++++++++++ 1 file changed, 100 insertions(+) diff --git a/drivers/net/ethernet/ti/am65-cpsw-nuss.c b/drivers/net/ethernet/ti/am65-cpsw-nuss.c index 0520e9f4bea7..8a6429aaded2 100644 --- a/drivers/net/ethernet/ti/am65-cpsw-nuss.c +++ b/drivers/net/ethernet/ti/am65-cpsw-nuss.c @@ -71,6 +71,8 @@ #define AM65_CPSW_PORT_REG_RX_PRI_MAP 0x020 #define AM65_CPSW_PORT_REG_RX_MAXLEN 0x024 +#define AM65_CPSW_PORTN_REG_CTL 0x004 +#define AM65_CPSW_PORTN_REG_DSCP_MAP 0x120 #define AM65_CPSW_PORTN_REG_SA_L 0x308 #define AM65_CPSW_PORTN_REG_SA_H 0x30c #define AM65_CPSW_PORTN_REG_TS_CTL 0x310 @@ -94,6 +96,10 @@ /* AM65_CPSW_PORT_REG_PRI_CTL */ #define AM65_CPSW_PORT_REG_PRI_CTL_RX_PTYPE_RROBIN BIT(8) +/* AM65_CPSW_PN_REG_CTL */ +#define AM65_CPSW_PN_REG_CTL_DSCP_IPV4_EN BIT(1) +#define AM65_CPSW_PN_REG_CTL_DSCP_IPV6_EN BIT(2) + /* AM65_CPSW_PN_TS_CTL register fields */ #define AM65_CPSW_PN_TS_CTL_TX_ANX_F_EN BIT(4) #define AM65_CPSW_PN_TS_CTL_TX_VLAN_LT1_EN BIT(5) @@ -176,6 +182,99 @@ static void am65_cpsw_port_set_sl_mac(struct am65_cpsw_port *slave, writel(mac_lo, slave->port_base + AM65_CPSW_PORTN_REG_SA_L); } +#define AM65_CPSW_DSCP_MAX GENMASK(5, 0) +#define AM65_CPSW_PRI_MAX GENMASK(2, 0) +#define AM65_CPSW_DSCP_PRI_PER_REG 8 +#define AM65_CPSW_DSCP_PRI_SIZE 4 /* in bits */ +static int am65_cpsw_port_set_dscp_map(struct am65_cpsw_port *slave, u8 dscp, u8 pri) +{ + int reg_ofs; + int bit_ofs; + u32 val; + + if (dscp > AM65_CPSW_DSCP_MAX) + return -EINVAL; + + if (pri > AM65_CPSW_PRI_MAX) + return -EINVAL; + + /* 32-bit register offset to this dscp */ + reg_ofs = (dscp / AM65_CPSW_DSCP_PRI_PER_REG) * 4; + /* bit field offset to this dscp */ + bit_ofs = AM65_CPSW_DSCP_PRI_SIZE * (dscp % AM65_CPSW_DSCP_PRI_PER_REG); + + val = readl(slave->port_base + AM65_CPSW_PORTN_REG_DSCP_MAP + reg_ofs); + val &= ~(AM65_CPSW_PRI_MAX << bit_ofs); /* clear */ + val |= pri << bit_ofs; /* set */ + writel(val, slave->port_base + AM65_CPSW_PORTN_REG_DSCP_MAP + reg_ofs); + + return 0; +} + +static void am65_cpsw_port_enable_dscp_map(struct am65_cpsw_port *slave) +{ + int dscp, pri; + u32 val; + + /* Default DSCP to User Priority mapping as per: + * https://datatracker.ietf.org/doc/html/rfc8325#section-4.3 + * and + * https://datatracker.ietf.org/doc/html/rfc8622#section-11 + */ + for (dscp = 0; dscp <= AM65_CPSW_DSCP_MAX; dscp++) { + switch (dscp) { + case 56: /* CS7 */ + case 48: /* CS6 */ + pri = 7; + break; + case 46: /* EF */ + case 44: /* VA */ + pri = 6; + break; + case 40: /* CS5 */ + pri = 5; + break; + case 34: /* AF41 */ + case 36: /* AF42 */ + case 38: /* AF43 */ + case 32: /* CS4 */ + case 26: /* AF31 */ + case 28: /* AF32 */ + case 30: /* AF33 */ + case 24: /* CS3 */ + pri = 4; + break; + case 18: /* AF21 */ + case 20: /* AF22 */ + case 22: /* AF23 */ + pri = 3; + break; + case 16: /* CS2 */ + case 10: /* AF11 */ + case 12: /* AF12 */ + case 14: /* AF13 */ + case 0: /* DF */ + pri = 0; + break; + case 8: /* CS1 */ + case 1: /* LE */ + pri = 1; + break; + default: + pri = 0; + break; + } + + am65_cpsw_port_set_dscp_map(slave, dscp, pri); + } + + /* enable port IPV4 and IPV6 DSCP for this port */ + val = readl(slave->port_base + AM65_CPSW_PORTN_REG_CTL); + val |= AM65_CPSW_PN_REG_CTL_DSCP_IPV4_EN | + AM65_CPSW_PN_REG_CTL_DSCP_IPV6_EN; + writel(val, slave->port_base + AM65_CPSW_PORTN_REG_CTL); +} + static void am65_cpsw_sl_ctl_reset(struct am65_cpsw_port *port) { cpsw_sl_reset(port->slave.mac_sl, 100); @@ -921,6 +1020,7 @@ static int am65_cpsw_nuss_ndo_slave_open(struct net_device *ndev) common->usage_count++; am65_cpsw_port_set_sl_mac(port, ndev->dev_addr); + am65_cpsw_port_enable_dscp_map(port); if (common->is_emac_mode) am65_cpsw_init_port_emac_ale(port);