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[209.51.188.17]) by mx.google.com with ESMTPS id ada2fe7eead31-4ad646f9b47si7723137.47.2024.11.14.13.01.05 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 14 Nov 2024 13:01:05 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=cx41yGx3; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tBgx2-0008EL-OO; Thu, 14 Nov 2024 16:00:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tBgx0-0008CK-G8 for qemu-devel@nongnu.org; Thu, 14 Nov 2024 16:00:26 -0500 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tBgwz-0007uP-05 for qemu-devel@nongnu.org; Thu, 14 Nov 2024 16:00:26 -0500 Received: by mail-wr1-x432.google.com with SMTP id ffacd0b85a97d-382026ba43eso737315f8f.1 for ; Thu, 14 Nov 2024 13:00:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1731618023; x=1732222823; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dxalhuJA3V9Mf8DxAADrs85j1mYwG4uCtR+wwxiXnFU=; b=cx41yGx3ew8rlJ4Cxv3ogkRDgC2SfNrX8u9YYSdhNhtU90cxa6DMlk1hHC/ciKbvpj ZiHmSkfWi7s8mIiLrD3zw0U2g6vtxkEjbpWJN3nLp6st7LzDjQHL8BQdmpZBg7u9kc8S 0ZsDMM5yRMOIn/RMhjWZvLTL1SABDonCfXbVziTGQf4knd6NWHGhdKzSQ6ZsO6TVnvF7 HxAwxjOK0puUh7Z5kwx+FQ2kvqAvi01LnQ2LfJzdsCtvAQ5auEQwInwlJxDnnFltURlF 2rXfLxuom5oLX+/8WhZEh+6UPlaql/oq4W4HA1zqA0ZPcssklYtVQGCnyTLOWs+YcW/l DBxQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731618023; x=1732222823; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dxalhuJA3V9Mf8DxAADrs85j1mYwG4uCtR+wwxiXnFU=; b=u22N0COEbxiaFtygexT0+Txv9vus5+9wNCqRU7B63PGbOPO0QaCpMHRD4hnzjRAcz1 eLhwBtpQdMjOvF04bX/BdIqW7ePiw4Ijq/1NhMVqQx3YRGFTYb1qXrFCMqkZHtNILTPv pCGowmB+uFOc0/KApMrnzk0Gp+zCQNgPW9zEjr7z+ya07lQGIBh914IopLrJsA6SvNFe Ywm3JKf6G9oQ+xKUiC4YqW5uP7fMGgdYvH2STYLZ2VEQ6XlX2MLL/7oZlpP6A4Ok2OzY EYT0SD5Bp9KqzYHn3SCJvmQ+urzAdXyaOhBX1Okv2o+uNskdkXhTnICatDe9FXzskJW9 ZvpA== X-Gm-Message-State: AOJu0YxHEpcLocg3O3FT6W2ymK7qpwNNtEgOntfyxfys3y5uYWxOKMO1 2N5mDjKsjqf3iMqEJxQz6EFDr7gs/fe2JRAbPvncfopTEg9F0YbBIhPajkKcVj/RO7gsgoZQoc1 a X-Received: by 2002:a05:6000:2a01:b0:37d:4332:e91d with SMTP id ffacd0b85a97d-38225aa6246mr158254f8f.52.1731618022950; Thu, 14 Nov 2024 13:00:22 -0800 (PST) Received: from localhost.localdomain ([176.187.209.228]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3821ada2da2sm2430618f8f.15.2024.11.14.13.00.20 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 14 Nov 2024 13:00:21 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , qemu-arm@nongnu.org, Richard Henderson , Thomas Huth , Anton Johansson , Bernhard Beschow , Alistair Francis , Paolo Bonzini , Gustavo Romero , =?utf-8?q?Marc-Andr=C3=A9_Lurea?= =?utf-8?q?u?= , Peter Maydell , Jason Wang , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH RESEND v2 01/19] hw/microblaze: Restrict MemoryRegionOps are implemented as 32-bit Date: Thu, 14 Nov 2024 21:59:52 +0100 Message-ID: <20241114210010.34502-2-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241114210010.34502-1-philmd@linaro.org> References: <20241114210010.34502-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=philmd@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org All these MemoryRegionOps read() and write() handlers are implemented expecting 32-bit accesses. Clarify that setting .impl.min/max_access_size fields. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Anton Johansson --- hw/char/xilinx_uartlite.c | 4 ++++ hw/intc/xilinx_intc.c | 4 ++++ hw/net/xilinx_ethlite.c | 4 ++++ hw/timer/xilinx_timer.c | 4 ++++ 4 files changed, 16 insertions(+) diff --git a/hw/char/xilinx_uartlite.c b/hw/char/xilinx_uartlite.c index f325084f8b..3022b3d8ef 100644 --- a/hw/char/xilinx_uartlite.c +++ b/hw/char/xilinx_uartlite.c @@ -170,6 +170,10 @@ static const MemoryRegionOps uart_ops = { .read = uart_read, .write = uart_write, .endianness = DEVICE_NATIVE_ENDIAN, + .impl = { + .min_access_size = 4, + .max_access_size = 4, + }, .valid = { .min_access_size = 1, .max_access_size = 4 diff --git a/hw/intc/xilinx_intc.c b/hw/intc/xilinx_intc.c index 6e5012e66e..8fb6b4f1a5 100644 --- a/hw/intc/xilinx_intc.c +++ b/hw/intc/xilinx_intc.c @@ -144,6 +144,10 @@ static const MemoryRegionOps pic_ops = { .read = pic_read, .write = pic_write, .endianness = DEVICE_NATIVE_ENDIAN, + .impl = { + .min_access_size = 4, + .max_access_size = 4, + }, .valid = { .min_access_size = 4, .max_access_size = 4 diff --git a/hw/net/xilinx_ethlite.c b/hw/net/xilinx_ethlite.c index bd81290808..e84b4cdd35 100644 --- a/hw/net/xilinx_ethlite.c +++ b/hw/net/xilinx_ethlite.c @@ -170,6 +170,10 @@ static const MemoryRegionOps eth_ops = { .read = eth_read, .write = eth_write, .endianness = DEVICE_NATIVE_ENDIAN, + .impl = { + .min_access_size = 4, + .max_access_size = 4, + }, .valid = { .min_access_size = 4, .max_access_size = 4 diff --git a/hw/timer/xilinx_timer.c b/hw/timer/xilinx_timer.c index 32a9df69e0..383fc8b3c8 100644 --- a/hw/timer/xilinx_timer.c +++ b/hw/timer/xilinx_timer.c @@ -193,6 +193,10 @@ static const MemoryRegionOps timer_ops = { .read = timer_read, .write = timer_write, .endianness = DEVICE_NATIVE_ENDIAN, + .impl = { + .min_access_size = 4, + .max_access_size = 4, + }, .valid = { .min_access_size = 4, .max_access_size = 4 From patchwork Thu Nov 14 20:59:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 843208 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcc:0:b0:382:184f:390f with SMTP id e12csp506046wrc; Thu, 14 Nov 2024 13:05:05 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVHmNMUJAeZAtowtmUD7Pwv1U29FRSXQe8DxnOL5uWmMY81TwzIXfoXUZCRIiSAW3Lg8nJo/w==@linaro.org X-Google-Smtp-Source: AGHT+IHgXdF/Oo5XWMwP82e15N4BKIGcak1hLi0GReXGkYnXsbDBWvE5FDmGy7Wcd9ELlEITaga9 X-Received: by 2002:ac8:6909:0:b0:460:ad75:300a with SMTP id d75a77b69052e-46363e924a3mr3791941cf.37.1731618305474; Thu, 14 Nov 2024 13:05:05 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1731618305; cv=none; d=google.com; s=arc-20240605; b=F7X9XDxCz4KQHgUxEB9sgI8pIjrm1v581cihruCURtxpa/RIlC4k5klH45MZTK4drl 4WPYZU2iJ6+LOqmWBCd7Qtx2VYGChOt3xp6u83KAk3rrVD16mnRAZkTtpTnxkLjAW6hN Rezu3fPjwaSmC3Doi9rpWCE5WSt2bDy3EXDsHAQ0uLPsVvN4pXvEJkotvIURu1tNZ77G kainQn+ZvDRC1vLtL6mA/CEHIxoT+1S4hqv06B7KXAJtUZwQYhDijLdVB5ESB3lmyLGQ VtWFiNifsXk0/S9QSlyrEm0rX9JqWzAO12EkqF/+BMCzkA8HYmStlvB1PXRRkEzXweIF WORw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=YlgtA2w+nkGpq6odlZPv7GuJkitbYlthMfvxp2Wzgbg=; fh=IRuGWMvTeecxgxjKSI7QmRflMkYktes0sVu/RVhAZQM=; b=LoRUaH11LoQlQvnrg4iCYO3zb1Ij6fahGSVmQg5h3wYNyA9kYwgLvo1H0RCtldSsml rsz459d0xVipRAhkhYVboitq+ghCXAT5UfOnVU80ygZBZRvSH90zvGyTDHBBS2rXdhz2 vnlG6zOWaAydaxLL/x5Jdxny7nW2EhIUaucZm7N/dj53I8Yru4hA/zRiGuIe3YVd9MPX fztdrm8FaDDeSIHONWeLHEnrnI6pZ4q/rXBBY3vf+DvkVidh5H1MiJSL0k3PAbPUwV/7 NUVOLssmgkMYjltLhId0mJ9SAvORgfCISlJJ9I6KJvCiLhsjilNeqjPAUudl501Ata2i vJSA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zvaJYErv; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Iglesias" , qemu-arm@nongnu.org, Richard Henderson , Thomas Huth , Anton Johansson , Bernhard Beschow , Alistair Francis , Paolo Bonzini , Gustavo Romero , =?utf-8?q?Marc-Andr=C3=A9_Lurea?= =?utf-8?q?u?= , Peter Maydell , Jason Wang , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , "Edgar E . Iglesias" Subject: [PATCH RESEND v2 02/19] hw/net/xilinx_ethlite: Convert some debug logs to trace events Date: Thu, 14 Nov 2024 21:59:53 +0100 Message-ID: <20241114210010.34502-3-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241114210010.34502-1-philmd@linaro.org> References: <20241114210010.34502-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=philmd@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Edgar E. Iglesias --- hw/net/xilinx_ethlite.c | 5 +++-- hw/net/trace-events | 4 ++++ 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/hw/net/xilinx_ethlite.c b/hw/net/xilinx_ethlite.c index e84b4cdd35..bb330a233f 100644 --- a/hw/net/xilinx_ethlite.c +++ b/hw/net/xilinx_ethlite.c @@ -30,6 +30,7 @@ #include "hw/irq.h" #include "hw/qdev-properties.h" #include "net/net.h" +#include "trace.h" #define D(x) #define R_TX_BUF0 0 @@ -198,13 +199,13 @@ static ssize_t eth_rx(NetClientState *nc, const uint8_t *buf, size_t size) return size; if (s->regs[rxbase + R_RX_CTRL0] & CTRL_S) { - D(qemu_log("ethlite lost packet %x\n", s->regs[R_RX_CTRL0])); + trace_ethlite_pkt_lost(s->regs[R_RX_CTRL0]); return -1; } D(qemu_log("%s %zd rxbase=%x\n", __func__, size, rxbase)); if (size > (R_MAX - R_RX_BUF0 - rxbase) * 4) { - D(qemu_log("ethlite packet is too big, size=%x\n", size)); + trace_ethlite_pkt_size_too_big(size); return -1; } memcpy(&s->regs[rxbase + R_RX_BUF0], buf, size); diff --git a/hw/net/trace-events b/hw/net/trace-events index d0f1d8c0fb..2b36cd967e 100644 --- a/hw/net/trace-events +++ b/hw/net/trace-events @@ -511,3 +511,7 @@ xen_netdev_connect(int dev, unsigned int tx, unsigned int rx, int port) "vif%u t xen_netdev_frontend_changed(const char *dev, int state) "vif%s state %d" xen_netdev_tx(int dev, int ref, int off, int len, unsigned int flags, const char *c, const char *d, const char *m, const char *e) "vif%u ref %u off %u len %u flags 0x%x%s%s%s%s" xen_netdev_rx(int dev, int idx, int status, int flags) "vif%u idx %d status %d flags 0x%x" + +# xilinx_ethlite.c +ethlite_pkt_lost(uint32_t rx_ctrl) "rx_ctrl:0x%" PRIx32 +ethlite_pkt_size_too_big(uint64_t size) "size:0x%" PRIx64 From patchwork Thu Nov 14 20:59:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 843194 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcc:0:b0:382:184f:390f with SMTP id e12csp504271wrc; Thu, 14 Nov 2024 13:01:52 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVoCn5IXhbxBFjgXElMtBaoQpXBVYkfxKJmWAcst6v8aeBTei1l72rEVXwNgxkI+eCqYuRmmQ==@linaro.org X-Google-Smtp-Source: AGHT+IGeUf5F/93b+4v32ilQI8O3TgEypKJ8ELQQzFruyKRqnQKRworLxR19QRXG/B4HPsIcFNz6 X-Received: by 2002:a05:620a:2945:b0:7b1:5763:4ba2 with SMTP id af79cd13be357-7b3623311c3mr48536085a.40.1731618111843; Thu, 14 Nov 2024 13:01:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1731618111; cv=none; d=google.com; s=arc-20240605; b=FyyXTmfobFI7ZAW3Fdc89E2KI6fJMj8dDn+VZ9VhH1Ppx7ocKlGQGtda9AiTk9J4zr U+TnECjbHI+P/aTwIQ2bp6CmpZadbBIHZzLizY5aOjGl6m0VszKZxyiMzsIOUZxZnpoB qZW4Uv+3gqi5rThJJWktN9AkJvLyT9mPezRbZrglc1D2WF8FapxVHNgj7b+1ZLunMMsZ 6Zj+6j2EQd4wno3CIdk1yq86d33IyUZKd1FDr8muhJyBjywib0aJwBynSmbcFDmcxs9B il60HnlUNeSB1UQYr3BIVeeMJLtBHso09fEhmMKp6t17MF3Z+VR7La8KPf382FxZOc4/ 6FWw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=yTK4l6Ykvzc6k9RKpIP/b45MtLRJEjbQSCPD8FRx8u8=; fh=IRuGWMvTeecxgxjKSI7QmRflMkYktes0sVu/RVhAZQM=; b=Pwr6FgixJl4lp9gbBzCsViLDlBkAJd0h/N+iB2EcLnHK7RULhYSmWAxfXbGjIUtEZp 1SLUvwDORPDWE7126/UzDeQzOQsTqyqlq1SQPuXNOQVCdYs3W8aocIOwnN5mQLFS/Enm BHQV2Q/xVGqwRJZWyb9TZT2DDOZSWvR4BaJcpZwk0EPPaf/ylp2AGkZuZA+oiaa/jmEW 5tIaue8fn4GzAncwlM+Q088JCciZLSVci6IV+CtEpfXf8N5ownKRR7BLtXtTl9U2kAoO XiZMsvqPwwewXEFxZPE2VlfWgBZto8cLwg3uSQJT7yPSlDD4dMaZScIcxYBl82rRaj0W EzQw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=TyK9DdyM; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Iglesias" , qemu-arm@nongnu.org, Richard Henderson , Thomas Huth , Anton Johansson , Bernhard Beschow , Alistair Francis , Paolo Bonzini , Gustavo Romero , =?utf-8?q?Marc-Andr=C3=A9_Lurea?= =?utf-8?q?u?= , Peter Maydell , Jason Wang , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , "Edgar E . Iglesias" Subject: [PATCH RESEND v2 03/19] hw/net/xilinx_ethlite: Remove unuseful debug logs Date: Thu, 14 Nov 2024 21:59:54 +0100 Message-ID: <20241114210010.34502-4-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241114210010.34502-1-philmd@linaro.org> References: <20241114210010.34502-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Edgar E. Iglesias --- hw/net/xilinx_ethlite.c | 8 -------- 1 file changed, 8 deletions(-) diff --git a/hw/net/xilinx_ethlite.c b/hw/net/xilinx_ethlite.c index bb330a233f..2b52597f03 100644 --- a/hw/net/xilinx_ethlite.c +++ b/hw/net/xilinx_ethlite.c @@ -32,7 +32,6 @@ #include "net/net.h" #include "trace.h" -#define D(x) #define R_TX_BUF0 0 #define R_TX_LEN0 (0x07f4 / 4) #define R_TX_GIE0 (0x07f8 / 4) @@ -100,7 +99,6 @@ eth_read(void *opaque, hwaddr addr, unsigned int size) case R_RX_CTRL1: case R_RX_CTRL0: r = s->regs[addr]; - D(qemu_log("%s " HWADDR_FMT_plx "=%x\n", __func__, addr * 4, r)); break; default: @@ -126,13 +124,10 @@ eth_write(void *opaque, hwaddr addr, if (addr == R_TX_CTRL1) base = 0x800 / 4; - D(qemu_log("%s addr=" HWADDR_FMT_plx " val=%x\n", - __func__, addr * 4, value)); if ((value & (CTRL_P | CTRL_S)) == CTRL_S) { qemu_send_packet(qemu_get_queue(s->nic), (void *) &s->regs[base], s->regs[base + R_TX_LEN0]); - D(qemu_log("eth_tx %d\n", s->regs[base + R_TX_LEN0])); if (s->regs[base + R_TX_CTRL0] & CTRL_I) eth_pulse_irq(s); } else if ((value & (CTRL_P | CTRL_S)) == (CTRL_P | CTRL_S)) { @@ -156,8 +151,6 @@ eth_write(void *opaque, hwaddr addr, case R_TX_LEN0: case R_TX_LEN1: case R_TX_GIE0: - D(qemu_log("%s addr=" HWADDR_FMT_plx " val=%x\n", - __func__, addr * 4, value)); s->regs[addr] = value; break; @@ -203,7 +196,6 @@ static ssize_t eth_rx(NetClientState *nc, const uint8_t *buf, size_t size) return -1; } - D(qemu_log("%s %zd rxbase=%x\n", __func__, size, rxbase)); if (size > (R_MAX - R_RX_BUF0 - rxbase) * 4) { trace_ethlite_pkt_size_too_big(size); return -1; From patchwork Thu Nov 14 20:59:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 843195 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcc:0:b0:382:184f:390f with SMTP id e12csp504290wrc; Thu, 14 Nov 2024 13:01:53 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCUtCU1WZtpPfGIg59Sdxwrkm9mV0itgV6gDPFhDBqgjyYCes/H9wr0felnD6exSfI3eh1t+kQ==@linaro.org X-Google-Smtp-Source: AGHT+IHJlVpY9kBiAcEnNtWHj+emOR9r+w/KzGFXkACIFYPWPVQzPmxRA7F6Sdlirl9d/Wd2vnJT X-Received: by 2002:a05:6830:3592:b0:718:9c32:9fbf with SMTP id 46e09a7af769-71a779cd1f3mr430200a34.22.1731618113677; Thu, 14 Nov 2024 13:01:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1731618113; cv=none; d=google.com; s=arc-20240605; b=ZVnbGcAylydC2kxuw4ovjZA4HOKf0bVRV6Z8KymKT4lxqy9PQCU9Ol2NO3IweArUl4 7i5+klXPaDHQ4oDaGDKv6NU45qPWUIxh0OV9IQw5vQ5hJBxE8bBAWDuxCkhM/j6AQl47 QcFGLVo5PP42NTmG0FrYNm8MZw/sF++r3lhY4jZMSkdBPhOdmuGxYR7rLkBD0UxsZKBE Pq/Zy/MENziFItjW6zquo0SWXupbuQpfVzLsg58oliKeYXpKMnd+bCUqmYa6ubAYVkIT dO2ZgDlbX1BECVmgP2hBvI1EygU5Ep3VcJjcODWrbdioxDFNvVOpBeYFhmwShaR4SVN9 dFYA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=GtXVKpSIpZsJQkvyHDSbG39GxcMu+Qe8sXh7gatQ/Yw=; fh=IRuGWMvTeecxgxjKSI7QmRflMkYktes0sVu/RVhAZQM=; b=GQzmPXz/cnkXgFtRb9kd33hy5OE9K44BFm5GHNRU/Raw/Ol+rHZ1TQXWQXCsAbpAej 78eNmSfEao8Mid3JesNBFKZkVSCEDYcIssywo/d2isF/lx977kVgAM7entShpuMCK/03 30pNygXFSt3G+XWv+H6X4f0kG0fr94m+ftNE5rNxJ/0cJWmh9e1Cr6UEVQeZOb4ZHOa8 zTBFk0UQJVlJl2WBM7kv4Dn52tvi0nXifLISClMQBSshnLatfV9SmVAZF4sS5BJ/7zsb jIaIrWY76j4RK9Xxj8SEp9g5DcUR1NoOZIGukj/8li5iLnHcXCsefHcfO2kAYNdyKe4x tl+g==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="OcCip/nh"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Iglesias" , qemu-arm@nongnu.org, Richard Henderson , Thomas Huth , Anton Johansson , Bernhard Beschow , Alistair Francis , Paolo Bonzini , Gustavo Romero , =?utf-8?q?Marc-Andr=C3=A9_Lurea?= =?utf-8?q?u?= , Peter Maydell , Jason Wang , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , "Edgar E . Iglesias" Subject: [PATCH RESEND v2 04/19] hw/net/xilinx_ethlite: Update QOM style Date: Thu, 14 Nov 2024 21:59:55 +0100 Message-ID: <20241114210010.34502-5-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241114210010.34502-1-philmd@linaro.org> References: <20241114210010.34502-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=philmd@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Use XlnxXpsEthLite typedef, OBJECT_DECLARE_SIMPLE_TYPE macro; convert type_init() to DEFINE_TYPES(). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Edgar E. Iglesias --- hw/net/xilinx_ethlite.c | 48 +++++++++++++++++++---------------------- 1 file changed, 22 insertions(+), 26 deletions(-) diff --git a/hw/net/xilinx_ethlite.c b/hw/net/xilinx_ethlite.c index 2b52597f03..0f59811c78 100644 --- a/hw/net/xilinx_ethlite.c +++ b/hw/net/xilinx_ethlite.c @@ -53,10 +53,9 @@ #define CTRL_S 0x1 #define TYPE_XILINX_ETHLITE "xlnx.xps-ethernetlite" -DECLARE_INSTANCE_CHECKER(struct xlx_ethlite, XILINX_ETHLITE, - TYPE_XILINX_ETHLITE) +OBJECT_DECLARE_SIMPLE_TYPE(XlnxXpsEthLite, XILINX_ETHLITE) -struct xlx_ethlite +struct XlnxXpsEthLite { SysBusDevice parent_obj; @@ -73,7 +72,7 @@ struct xlx_ethlite uint32_t regs[R_MAX]; }; -static inline void eth_pulse_irq(struct xlx_ethlite *s) +static inline void eth_pulse_irq(XlnxXpsEthLite *s) { /* Only the first gie reg is active. */ if (s->regs[R_TX_GIE0] & GIE_GIE) { @@ -84,7 +83,7 @@ static inline void eth_pulse_irq(struct xlx_ethlite *s) static uint64_t eth_read(void *opaque, hwaddr addr, unsigned int size) { - struct xlx_ethlite *s = opaque; + XlnxXpsEthLite *s = opaque; uint32_t r = 0; addr >>= 2; @@ -112,7 +111,7 @@ static void eth_write(void *opaque, hwaddr addr, uint64_t val64, unsigned int size) { - struct xlx_ethlite *s = opaque; + XlnxXpsEthLite *s = opaque; unsigned int base = 0; uint32_t value = val64; @@ -176,7 +175,7 @@ static const MemoryRegionOps eth_ops = { static bool eth_can_rx(NetClientState *nc) { - struct xlx_ethlite *s = qemu_get_nic_opaque(nc); + XlnxXpsEthLite *s = qemu_get_nic_opaque(nc); unsigned int rxbase = s->rxbuf * (0x800 / 4); return !(s->regs[rxbase + R_RX_CTRL0] & CTRL_S); @@ -184,7 +183,7 @@ static bool eth_can_rx(NetClientState *nc) static ssize_t eth_rx(NetClientState *nc, const uint8_t *buf, size_t size) { - struct xlx_ethlite *s = qemu_get_nic_opaque(nc); + XlnxXpsEthLite *s = qemu_get_nic_opaque(nc); unsigned int rxbase = s->rxbuf * (0x800 / 4); /* DA filter. */ @@ -214,7 +213,7 @@ static ssize_t eth_rx(NetClientState *nc, const uint8_t *buf, size_t size) static void xilinx_ethlite_reset(DeviceState *dev) { - struct xlx_ethlite *s = XILINX_ETHLITE(dev); + XlnxXpsEthLite *s = XILINX_ETHLITE(dev); s->rxbuf = 0; } @@ -228,7 +227,7 @@ static NetClientInfo net_xilinx_ethlite_info = { static void xilinx_ethlite_realize(DeviceState *dev, Error **errp) { - struct xlx_ethlite *s = XILINX_ETHLITE(dev); + XlnxXpsEthLite *s = XILINX_ETHLITE(dev); qemu_macaddr_default_if_unset(&s->conf.macaddr); s->nic = qemu_new_nic(&net_xilinx_ethlite_info, &s->conf, @@ -239,7 +238,7 @@ static void xilinx_ethlite_realize(DeviceState *dev, Error **errp) static void xilinx_ethlite_init(Object *obj) { - struct xlx_ethlite *s = XILINX_ETHLITE(obj); + XlnxXpsEthLite *s = XILINX_ETHLITE(obj); sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); @@ -249,9 +248,9 @@ static void xilinx_ethlite_init(Object *obj) } static Property xilinx_ethlite_properties[] = { - DEFINE_PROP_UINT32("tx-ping-pong", struct xlx_ethlite, c_tx_pingpong, 1), - DEFINE_PROP_UINT32("rx-ping-pong", struct xlx_ethlite, c_rx_pingpong, 1), - DEFINE_NIC_PROPERTIES(struct xlx_ethlite, conf), + DEFINE_PROP_UINT32("tx-ping-pong", XlnxXpsEthLite, c_tx_pingpong, 1), + DEFINE_PROP_UINT32("rx-ping-pong", XlnxXpsEthLite, c_rx_pingpong, 1), + DEFINE_NIC_PROPERTIES(XlnxXpsEthLite, conf), DEFINE_PROP_END_OF_LIST(), }; @@ -264,17 +263,14 @@ static void xilinx_ethlite_class_init(ObjectClass *klass, void *data) device_class_set_props(dc, xilinx_ethlite_properties); } -static const TypeInfo xilinx_ethlite_info = { - .name = TYPE_XILINX_ETHLITE, - .parent = TYPE_SYS_BUS_DEVICE, - .instance_size = sizeof(struct xlx_ethlite), - .instance_init = xilinx_ethlite_init, - .class_init = xilinx_ethlite_class_init, +static const TypeInfo xilinx_ethlite_types[] = { + { + .name = TYPE_XILINX_ETHLITE, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(XlnxXpsEthLite), + .instance_init = xilinx_ethlite_init, + .class_init = xilinx_ethlite_class_init, + }, }; -static void xilinx_ethlite_register_types(void) -{ - type_register_static(&xilinx_ethlite_info); -} - -type_init(xilinx_ethlite_register_types) +DEFINE_TYPES(xilinx_ethlite_types) From patchwork Thu Nov 14 20:59:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 843196 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcc:0:b0:382:184f:390f with SMTP id e12csp504319wrc; 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Iglesias" , qemu-arm@nongnu.org, Richard Henderson , Thomas Huth , Anton Johansson , Bernhard Beschow , Alistair Francis , Paolo Bonzini , Gustavo Romero , =?utf-8?q?Marc-Andr=C3=A9_Lurea?= =?utf-8?q?u?= , Peter Maydell , Jason Wang , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , "Edgar E . Iglesias" Subject: [PATCH RESEND v2 05/19] hw/net/xilinx_ethlite: Correct maximum RX buffer size Date: Thu, 14 Nov 2024 21:59:56 +0100 Message-ID: <20241114210010.34502-6-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241114210010.34502-1-philmd@linaro.org> References: <20241114210010.34502-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=philmd@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The current max RX bufsize is set to 0x800. This is invalid, since it contains the MMIO registers region. Add the correct definition (valid for both TX & RX, see datasheet p. 20, Table 11 "XPS Ethernet Lite MAC Memory Map") and use it. Reviewed-by: Edgar E. Iglesias Signed-off-by: Philippe Mathieu-Daudé --- hw/net/xilinx_ethlite.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/hw/net/xilinx_ethlite.c b/hw/net/xilinx_ethlite.c index 0f59811c78..0df962cd22 100644 --- a/hw/net/xilinx_ethlite.c +++ b/hw/net/xilinx_ethlite.c @@ -3,6 +3,9 @@ * * Copyright (c) 2009 Edgar E. Iglesias. * + * DS580: https://docs.amd.com/v/u/en-US/xps_ethernetlite + * LogiCORE IP XPS Ethernet Lite Media Access Controller + * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights @@ -33,6 +36,7 @@ #include "trace.h" #define R_TX_BUF0 0 +#define BUFSZ_MAX 0x07e4 #define R_TX_LEN0 (0x07f4 / 4) #define R_TX_GIE0 (0x07f8 / 4) #define R_TX_CTRL0 (0x07fc / 4) @@ -195,7 +199,7 @@ static ssize_t eth_rx(NetClientState *nc, const uint8_t *buf, size_t size) return -1; } - if (size > (R_MAX - R_RX_BUF0 - rxbase) * 4) { + if (size >= BUFSZ_MAX) { trace_ethlite_pkt_size_too_big(size); return -1; } From patchwork Thu Nov 14 20:59:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 843200 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcc:0:b0:382:184f:390f with SMTP id e12csp505093wrc; Thu, 14 Nov 2024 13:03:16 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWiN/1XL9YZwjSxOmkPRzbpZ+Xr7FjG5xnmmo/+J2rb1sepCUvQi5Cc6h/6nl+4cdgygQ1FfQ==@linaro.org X-Google-Smtp-Source: AGHT+IF5dhPSxII6llwiS7Tfj6Qi0fkbS/j0rKM4hG0frLRxjX1okboBVS2eXjMe3wZdV9ZCrO4u X-Received: by 2002:ac8:5f0b:0:b0:461:190f:98ab with SMTP id d75a77b69052e-4636350bda0mr9116231cf.3.1731618195774; Thu, 14 Nov 2024 13:03:15 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1731618195; cv=none; d=google.com; s=arc-20240605; b=ANrOfvKEbzyelc73dmFK7AWAnWPHumqE3n6MftUw8IussmnBbU7At6ZzY9IoPI6fvG Gr5yDyfHr4Ck+Hk7UbCbU19kAOzcvDYLIWkIujpo5tPbILYw7YjHYEzcKARaEDIOmie0 X9F5bRKWOzLIfL6jz7j8CQSJjIGF3hLJ8sFzY9uVKHa4gHq9Zs4JDVFy4rb4q+0Knt+l 6c6BlFcdY090l4RPcjk8mjX1N6AzccISuRNJ56san/YLkQ94wJm2cezTdVhYr/C0M1Dc G3jV8cTMye/oqla4dHp+zbFTPGGSVNMAX/aCO5u8UHDoNGCie0JF9tlzp1Tc7gK92W2M SXjg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=w7oaVYUllzOyksXJ6qk0wfeCGOBTZK5l45Wvi+e1fAY=; fh=IRuGWMvTeecxgxjKSI7QmRflMkYktes0sVu/RVhAZQM=; b=X6zAdC9D/nLG4KO1n9lG30AsSyVlOQerghUzW1rZcfrRuaaclYcBbiomUrWwOzYzFl h3zHFwp8E+tWY+qWOCYyM7UKxubXTEgAaGfZG/2i6i/lcY478rCgVZwL4OA08HtW1LcN idgeLiHN1BQbkOp/CaSjm+it73GFNntjb4mCpOpjQrJK9yE6sBe68PrZC0G9pyLC0YDg S4lq++BGf2VDS67CQTImso9tkiSb1gld8BUy/zhhYiJFKPRX93AszR2302qcuugCxvyt wnzhgq72y/1J2Vu1nB+sGKReAJWJRLTxUUvkOqZ8Plu8nWVN5UtdabZ9Iw5nS+bxqvFC KKWg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="SQdtn/DO"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Iglesias" , qemu-arm@nongnu.org, Richard Henderson , Thomas Huth , Anton Johansson , Bernhard Beschow , Alistair Francis , Paolo Bonzini , Gustavo Romero , =?utf-8?q?Marc-Andr=C3=A9_Lurea?= =?utf-8?q?u?= , Peter Maydell , Jason Wang , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , "Edgar E . Iglesias" Subject: [PATCH RESEND v2 06/19] hw/net/xilinx_ethlite: Map MDIO registers (as unimplemented) Date: Thu, 14 Nov 2024 21:59:57 +0100 Message-ID: <20241114210010.34502-7-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241114210010.34502-1-philmd@linaro.org> References: <20241114210010.34502-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=philmd@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Rather than handling the MDIO registers as RAM, map them as unimplemented I/O within the device MR. The memory flat view becomes: (qemu) info mtree -f FlatView #0 Root memory region: system 0000000081000000-00000000810007e3 (prio 0, i/o): xlnx.xps-ethernetlite 00000000810007e4-00000000810007f3 (prio 0, i/o): ethlite.mdio 00000000810007f4-0000000081001fff (prio 0, i/o): xlnx.xps-ethernetlite @00000000000007f4 Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Edgar E. Iglesias --- hw/net/xilinx_ethlite.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/hw/net/xilinx_ethlite.c b/hw/net/xilinx_ethlite.c index 0df962cd22..8de3131408 100644 --- a/hw/net/xilinx_ethlite.c +++ b/hw/net/xilinx_ethlite.c @@ -28,15 +28,18 @@ #include "qemu/osdep.h" #include "qemu/module.h" #include "qom/object.h" +#include "qapi/error.h" #include "exec/tswap.h" #include "hw/sysbus.h" #include "hw/irq.h" #include "hw/qdev-properties.h" +#include "hw/misc/unimp.h" #include "net/net.h" #include "trace.h" #define R_TX_BUF0 0 #define BUFSZ_MAX 0x07e4 +#define A_MDIO_BASE 0x07e4 #define R_TX_LEN0 (0x07f4 / 4) #define R_TX_GIE0 (0x07f8 / 4) #define R_TX_CTRL0 (0x07fc / 4) @@ -73,6 +76,7 @@ struct XlnxXpsEthLite unsigned int txbuf; unsigned int rxbuf; + UnimplementedDeviceState mdio; uint32_t regs[R_MAX]; }; @@ -233,6 +237,14 @@ static void xilinx_ethlite_realize(DeviceState *dev, Error **errp) { XlnxXpsEthLite *s = XILINX_ETHLITE(dev); + object_initialize_child(OBJECT(dev), "ethlite.mdio", &s->mdio, + TYPE_UNIMPLEMENTED_DEVICE); + qdev_prop_set_string(DEVICE(&s->mdio), "name", "ethlite.mdio"); + qdev_prop_set_uint64(DEVICE(&s->mdio), "size", 4 * 4); + sysbus_realize(SYS_BUS_DEVICE(&s->mdio), &error_fatal); + memory_region_add_subregion(&s->mmio, A_MDIO_BASE, + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->mdio), 0)); + qemu_macaddr_default_if_unset(&s->conf.macaddr); s->nic = qemu_new_nic(&net_xilinx_ethlite_info, &s->conf, object_get_typename(OBJECT(dev)), dev->id, From patchwork Thu Nov 14 20:59:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 843209 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcc:0:b0:382:184f:390f with SMTP id e12csp506076wrc; Thu, 14 Nov 2024 13:05:10 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXVTy1kfHY08K2Fi4ba5L8trTWjtO6hVa325Kh+zFwvAOJNuVaU5QktxngC1LuYU2mj6lttrg==@linaro.org X-Google-Smtp-Source: AGHT+IG0Fhi++HdDlLuCn1XDpPFvtPbMZozbYHzqMH4w9GB8aPvQV5PVLqAI28aWQEBq9yfpzv5w X-Received: by 2002:a05:6808:f06:b0:3e6:2889:5fa7 with SMTP id 5614622812f47-3e7bc85401cmr369225b6e.27.1731618310673; Thu, 14 Nov 2024 13:05:10 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1731618310; cv=none; d=google.com; s=arc-20240605; b=VPKUTutN7t6mQ0g775nrj0K4FWUKmTHc4Wdv6mcwyQL4usT4sz5eQQIMOGfPQOYxlv 2u5cs2XX4UXrWjHEnUw8154cYA5uLWCd9qCI6SFiHPul78aQbr0ChtKK7fQLAUQlUFNp pkzGHcQMUIEhXDmb0diULf4W4/6cniI1/rBEzEmaHJEEGNDXkiJRadxsBQ3vOzkRcr6/ aclf3Sz/FqkYTJtMwzIHiEgP4k4GCAxBQzU8UmzSVT7z135yV2Ax/znHa3gIc4q+QPLq XLuCSuR71EdDkAjgo5YdJub/uRp9JWfmrdj2r2RNGvA4qEe7XdLdOrjsmBRYikaEHD+v 3iyQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=7vs9ivF9siaWRamWv2mgjjJCogSIQAiZCiYH/706wGI=; fh=IRuGWMvTeecxgxjKSI7QmRflMkYktes0sVu/RVhAZQM=; b=A6M0/3DJixW2v5lGgyFLDqj8CsH1Bocky2Iy+HUYIwKaic1yT8GUYFKOOgdG34u2ZO jc/7VhEm6s3/EsdX9UWtnBJf5zMh5p6ykvcGAZ93484a9Hvadq/lBV+gqU0g0vzmqfrc S9fX94G0+ARJLiZnJoVPvWI1N0jt0CrP93Vg3QeciLqZoMmTGPaZk2pEqJjpjwSs7CTo 0R66mlyBEdWGkSLVwnUvbxotbnDvyScxbBZNbyikL8BpNcrmerviX1qmB0v9AxoqWJaY zunqkTkv1doZrGS0a7ZvCuG0f+OyWXUSNjbCD2dDF46b/zkQ1XnZYjaoIzUFb66GCVZH 5l6w==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CES7arhh; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Iglesias" Subject: [PATCH RESEND v2 07/19] hw/net/xilinx_ethlite: Rename rxbuf -> port_index Date: Thu, 14 Nov 2024 21:59:58 +0100 Message-ID: <20241114210010.34502-8-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241114210010.34502-1-philmd@linaro.org> References: <20241114210010.34502-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=philmd@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org 'rxbuf' is the index of the dual port RAM used. Rename it as 'port_index'. Reviewed-by: Edgar E. Iglesias Signed-off-by: Philippe Mathieu-Daudé --- hw/net/xilinx_ethlite.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/hw/net/xilinx_ethlite.c b/hw/net/xilinx_ethlite.c index 8de3131408..7a14f4edea 100644 --- a/hw/net/xilinx_ethlite.c +++ b/hw/net/xilinx_ethlite.c @@ -73,8 +73,7 @@ struct XlnxXpsEthLite uint32_t c_tx_pingpong; uint32_t c_rx_pingpong; - unsigned int txbuf; - unsigned int rxbuf; + unsigned int port_index; /* dual port RAM index */ UnimplementedDeviceState mdio; uint32_t regs[R_MAX]; @@ -184,7 +183,7 @@ static const MemoryRegionOps eth_ops = { static bool eth_can_rx(NetClientState *nc) { XlnxXpsEthLite *s = qemu_get_nic_opaque(nc); - unsigned int rxbase = s->rxbuf * (0x800 / 4); + unsigned int rxbase = s->port_index * (0x800 / 4); return !(s->regs[rxbase + R_RX_CTRL0] & CTRL_S); } @@ -192,7 +191,7 @@ static bool eth_can_rx(NetClientState *nc) static ssize_t eth_rx(NetClientState *nc, const uint8_t *buf, size_t size) { XlnxXpsEthLite *s = qemu_get_nic_opaque(nc); - unsigned int rxbase = s->rxbuf * (0x800 / 4); + unsigned int rxbase = s->port_index * (0x800 / 4); /* DA filter. */ if (!(buf[0] & 0x80) && memcmp(&s->conf.macaddr.a[0], buf, 6)) @@ -215,7 +214,7 @@ static ssize_t eth_rx(NetClientState *nc, const uint8_t *buf, size_t size) } /* If c_rx_pingpong was set flip buffers. */ - s->rxbuf ^= s->c_rx_pingpong; + s->port_index ^= s->c_rx_pingpong; return size; } @@ -223,7 +222,7 @@ static void xilinx_ethlite_reset(DeviceState *dev) { XlnxXpsEthLite *s = XILINX_ETHLITE(dev); - s->rxbuf = 0; + s->port_index = 0; } static NetClientInfo net_xilinx_ethlite_info = { From patchwork Thu Nov 14 20:59:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 843197 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcc:0:b0:382:184f:390f with SMTP id e12csp504621wrc; Thu, 14 Nov 2024 13:02:27 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCUI6RzazhkE/qeh9APxTZfIKP7F66djNkbGDAmA6QObslJucwM+DCEoLcWpa9IUoj9swq61tw==@linaro.org X-Google-Smtp-Source: AGHT+IH7ttJcXFnM8JKjTszT5ZSziqCaf0St8YGABtHmBlLzzlR9YSmVXtZVEqtkvBLyTYBs2Hgu X-Received: by 2002:ac8:7fc6:0:b0:461:48f9:44eb with SMTP id d75a77b69052e-46363e23ccdmr3470391cf.25.1731618146819; Thu, 14 Nov 2024 13:02:26 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1731618146; cv=none; d=google.com; s=arc-20240605; b=PDGgYJSMY6a6dMyTG3FqOpYkTPRujb07QZ2B92XlL/3g7kGGMWEmVYnXy2oTURVF/e CQ1Zm+4mzGr7ogeXYplAFX68MK1mqjEP3HCbfkkzIaMHy6iCVwWM6chfLtGVr56uZg9M IYoYbdyr38f6olC7LM60nr+3ODsvmEbwkqHe1ZAWVBiCTbzj+Q8HMzTraalXDoe8an+S ktVjLbkFZRWA5KPI1+h5JHYTbkO/IYZSrBo6+bO4ztW5hPicJ1J508du5mDUAMB7ofur GKeh1/p/jtIWUXCeYyN2k76Vao1YZpN4DCAqo/upuXUNw/ivVBJG1gCiazvOC+WJJ1ZK 9wAQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=N6+gSXBoOBmz0VjYZ13ccRnCNyVzdwJCJ6CvUinNnmk=; fh=IRuGWMvTeecxgxjKSI7QmRflMkYktes0sVu/RVhAZQM=; b=Wp+4Zo1BLBvXxxhp35bd7XfwReejiQf2BP/9o5efE98HKXhNHd6H/KQLCEpjk9Tgw3 Pvj1IV9kUVYspqw31t9rTgViJOuw2Bpl1yd/vPpY0t1grdVw/9TihUZN7Yiug1rxC7Bd Ruy4JeunILr+0ScTOQj3ItcQC0B4PBmkgK+Z9wJW/10IAxUTPLMZHutxZvxkuTQKMG6y tbifXAg7+VMFrODiiLO/6uBivCHfk57y5/Pr/nogMQ2qN6WX5ZsEEZeeyKI87JgjEMRp ktu5QqLRzJCrYhU+aRNTRebSZfChGbIs42o/H9Xx9HnWGQBPG6vQsxziRQfaQ2frJwLb wTZg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PlE4oywo; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Iglesias" , qemu-arm@nongnu.org, Richard Henderson , Thomas Huth , Anton Johansson , Bernhard Beschow , Alistair Francis , Paolo Bonzini , Gustavo Romero , =?utf-8?q?Marc-Andr=C3=A9_Lurea?= =?utf-8?q?u?= , Peter Maydell , Jason Wang , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , "Edgar E . Iglesias" Subject: [PATCH RESEND v2 08/19] hw/net/xilinx_ethlite: Introduce txbuf_ptr() helper Date: Thu, 14 Nov 2024 21:59:59 +0100 Message-ID: <20241114210010.34502-9-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241114210010.34502-1-philmd@linaro.org> References: <20241114210010.34502-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=philmd@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org For a particular physical address within the EthLite MMIO range, addr_to_port_index() returns which port is accessed. txbuf_ptr() points to the beginning of a (RAM) TX buffer within the device state. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Edgar E. Iglesias --- hw/net/xilinx_ethlite.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/hw/net/xilinx_ethlite.c b/hw/net/xilinx_ethlite.c index 7a14f4edea..21ce2a112c 100644 --- a/hw/net/xilinx_ethlite.c +++ b/hw/net/xilinx_ethlite.c @@ -27,6 +27,7 @@ #include "qemu/osdep.h" #include "qemu/module.h" +#include "qemu/bitops.h" #include "qom/object.h" #include "qapi/error.h" #include "exec/tswap.h" @@ -87,6 +88,18 @@ static inline void eth_pulse_irq(XlnxXpsEthLite *s) } } +static unsigned addr_to_port_index(hwaddr addr) +{ + return extract64(addr, 11, 1); +} + +static void *txbuf_ptr(XlnxXpsEthLite *s, unsigned port_index) +{ + unsigned int rxbase = port_index * (0x800 / 4); + + return &s->regs[rxbase + R_TX_BUF0]; +} + static uint64_t eth_read(void *opaque, hwaddr addr, unsigned int size) { @@ -119,6 +132,7 @@ eth_write(void *opaque, hwaddr addr, uint64_t val64, unsigned int size) { XlnxXpsEthLite *s = opaque; + unsigned int port_index = addr_to_port_index(addr); unsigned int base = 0; uint32_t value = val64; @@ -132,12 +146,12 @@ eth_write(void *opaque, hwaddr addr, if ((value & (CTRL_P | CTRL_S)) == CTRL_S) { qemu_send_packet(qemu_get_queue(s->nic), - (void *) &s->regs[base], + txbuf_ptr(s, port_index), s->regs[base + R_TX_LEN0]); if (s->regs[base + R_TX_CTRL0] & CTRL_I) eth_pulse_irq(s); } else if ((value & (CTRL_P | CTRL_S)) == (CTRL_P | CTRL_S)) { - memcpy(&s->conf.macaddr.a[0], &s->regs[base], 6); + memcpy(&s->conf.macaddr.a[0], txbuf_ptr(s, port_index), 6); if (s->regs[base + R_TX_CTRL0] & CTRL_I) eth_pulse_irq(s); } From patchwork Thu Nov 14 21:00:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 843198 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcc:0:b0:382:184f:390f with SMTP id e12csp504832wrc; Thu, 14 Nov 2024 13:02:48 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXuvx1aHuTjlhc+yOs4yGSs/E4LCb31dwmBu7qbwJN6Pd8PKgGef/Pw5Tvc3srFqrjiiI0EbA==@linaro.org X-Google-Smtp-Source: AGHT+IHsbVfpaQStGp285N5uqDv4nkgE0pqz5J0GntniRaObquzeZTFwgynz5UPfZ1VaBjem/x6v X-Received: by 2002:a05:622a:1654:b0:461:2a3c:c1f with SMTP id d75a77b69052e-46363ec8e05mr3699331cf.52.1731618168385; Thu, 14 Nov 2024 13:02:48 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1731618168; cv=none; d=google.com; s=arc-20240605; b=C2I2pN785bXi/aa6k1yq8nG1Yt2y0/BoLuXQiIVkglqH6zl21SIaV/pBDNvxlb+DB3 jTxDEE5N0NLtfWbbSzH3/LPgkgTVihJkxeG2XO3nnC3RLEE9gWrLJhP57BQanEObJy53 gl7dpPKJnC3ng375f2mRDlTddKR/5Ckv14NQb97rprNfzhhKlJoIH5P4RGyUgYPwhk1G 4K9eXGynDQ5RisS9WrQh7Bn0ycVTo2RJZdN+ag3flaJOzPWXlL6rE1uE1vEWZ9bXQE7w m/rL6yJR7SuFL7hBmP/cNDKnv3+StdGllDAfcxwnfYeu9WWojvGe+2lGHeQr0CBDt+F/ ZN2A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=dRoZ7cwroZSiGL3yaDx0dNBCN/zDvjhHMaiZQ6yO+wI=; fh=IRuGWMvTeecxgxjKSI7QmRflMkYktes0sVu/RVhAZQM=; b=iz6PUDcXKCJSnvLv2jiyqIf2SJfjzyh9xJXXzPp6Rwd00yIOwcP9hhGixINeaBA1J6 MnU+1LCDfcrx6oUrAf9VobUm5PKAYV3sr5usXWA1CUxFFjtHnyB2l6I9mpw/Z+LBfxeh TGFJ5GRQWyAsd/wbOLH7E7oABXpdHwqEI7NMZSsFwx0WEPmDqo5c4fHWqDggwVThY2IT y+0Jp80HN4ZFNzrwEUFPOavU02723PevfzmJKWM+RJaNsZh/UUCxecPfkF8uz4G4BQk8 P0PQzeQp9zkw3U2A92l+fqc3kHP5/qkS4kh7gIsYJq1dpAetwsWMEfDgWJKo3meg+UeM 1VSg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dNBagkX5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Iglesias" , qemu-arm@nongnu.org, Richard Henderson , Thomas Huth , Anton Johansson , Bernhard Beschow , Alistair Francis , Paolo Bonzini , Gustavo Romero , =?utf-8?q?Marc-Andr=C3=A9_Lurea?= =?utf-8?q?u?= , Peter Maydell , Jason Wang , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , "Edgar E . Iglesias" Subject: [PATCH RESEND v2 09/19] hw/net/xilinx_ethlite: Introduce rxbuf_ptr() helper Date: Thu, 14 Nov 2024 22:00:00 +0100 Message-ID: <20241114210010.34502-10-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241114210010.34502-1-philmd@linaro.org> References: <20241114210010.34502-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=philmd@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org rxbuf_ptr() points to the beginning of a (RAM) RX buffer within the device state. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Edgar E. Iglesias --- hw/net/xilinx_ethlite.c | 40 ++++++++++++++++++++++++++++++---------- 1 file changed, 30 insertions(+), 10 deletions(-) diff --git a/hw/net/xilinx_ethlite.c b/hw/net/xilinx_ethlite.c index 21ce2a112c..a993cb8bb9 100644 --- a/hw/net/xilinx_ethlite.c +++ b/hw/net/xilinx_ethlite.c @@ -60,6 +60,13 @@ #define CTRL_P 0x2 #define CTRL_S 0x1 +typedef struct XlnxXpsEthLitePort +{ + struct { + uint32_t rx_ctrl; + } reg; +} XlnxXpsEthLitePort; + #define TYPE_XILINX_ETHLITE "xlnx.xps-ethernetlite" OBJECT_DECLARE_SIMPLE_TYPE(XlnxXpsEthLite, XILINX_ETHLITE) @@ -77,6 +84,7 @@ struct XlnxXpsEthLite unsigned int port_index; /* dual port RAM index */ UnimplementedDeviceState mdio; + XlnxXpsEthLitePort port[2]; uint32_t regs[R_MAX]; }; @@ -100,10 +108,18 @@ static void *txbuf_ptr(XlnxXpsEthLite *s, unsigned port_index) return &s->regs[rxbase + R_TX_BUF0]; } +static void *rxbuf_ptr(XlnxXpsEthLite *s, unsigned port_index) +{ + unsigned int rxbase = port_index * (0x800 / 4); + + return &s->regs[rxbase + R_RX_BUF0]; +} + static uint64_t eth_read(void *opaque, hwaddr addr, unsigned int size) { XlnxXpsEthLite *s = opaque; + unsigned port_index = addr_to_port_index(addr); uint32_t r = 0; addr >>= 2; @@ -115,9 +131,12 @@ eth_read(void *opaque, hwaddr addr, unsigned int size) case R_TX_LEN1: case R_TX_CTRL1: case R_TX_CTRL0: + r = s->regs[addr]; + break; + case R_RX_CTRL1: case R_RX_CTRL0: - r = s->regs[addr]; + r = s->port[port_index].reg.rx_ctrl; break; default: @@ -167,7 +186,9 @@ eth_write(void *opaque, hwaddr addr, if (!(value & CTRL_S)) { qemu_flush_queued_packets(qemu_get_queue(s->nic)); } - /* fall through */ + s->port[port_index].reg.rx_ctrl = value; + break; + case R_TX_LEN0: case R_TX_LEN1: case R_TX_GIE0: @@ -197,22 +218,21 @@ static const MemoryRegionOps eth_ops = { static bool eth_can_rx(NetClientState *nc) { XlnxXpsEthLite *s = qemu_get_nic_opaque(nc); - unsigned int rxbase = s->port_index * (0x800 / 4); - return !(s->regs[rxbase + R_RX_CTRL0] & CTRL_S); + return !(s->port[s->port_index].reg.rx_ctrl & CTRL_S); } static ssize_t eth_rx(NetClientState *nc, const uint8_t *buf, size_t size) { XlnxXpsEthLite *s = qemu_get_nic_opaque(nc); - unsigned int rxbase = s->port_index * (0x800 / 4); + unsigned int port_index = s->port_index; /* DA filter. */ if (!(buf[0] & 0x80) && memcmp(&s->conf.macaddr.a[0], buf, 6)) return size; - if (s->regs[rxbase + R_RX_CTRL0] & CTRL_S) { - trace_ethlite_pkt_lost(s->regs[R_RX_CTRL0]); + if (s->port[port_index].reg.rx_ctrl & CTRL_S) { + trace_ethlite_pkt_lost(s->port[port_index].reg.rx_ctrl); return -1; } @@ -220,10 +240,10 @@ static ssize_t eth_rx(NetClientState *nc, const uint8_t *buf, size_t size) trace_ethlite_pkt_size_too_big(size); return -1; } - memcpy(&s->regs[rxbase + R_RX_BUF0], buf, size); + memcpy(rxbuf_ptr(s, port_index), buf, size); - s->regs[rxbase + R_RX_CTRL0] |= CTRL_S; - if (s->regs[R_RX_CTRL0] & CTRL_I) { + s->port[port_index].reg.rx_ctrl |= CTRL_S; + if (s->port[port_index].reg.rx_ctrl & CTRL_I) { eth_pulse_irq(s); } From patchwork Thu Nov 14 21:00:01 2024 Content-Type: text/plain; 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Iglesias" , qemu-arm@nongnu.org, Richard Henderson , Thomas Huth , Anton Johansson , Bernhard Beschow , Alistair Francis , Paolo Bonzini , Gustavo Romero , =?utf-8?q?Marc-Andr=C3=A9_Lurea?= =?utf-8?q?u?= , Peter Maydell , Jason Wang , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , "Edgar E . Iglesias" Subject: [PATCH RESEND v2 10/19] hw/net/xilinx_ethlite: Access TX_GIE register for each port Date: Thu, 14 Nov 2024 22:00:01 +0100 Message-ID: <20241114210010.34502-11-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241114210010.34502-1-philmd@linaro.org> References: <20241114210010.34502-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=philmd@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Rather than accessing the registers within the mixed RAM/MMIO region as indexed register, declare a per-port TX_GIE. This will help to map the RAM as RAM (keeping MMIO as MMIO) in few commits. Previous s->regs[R_TX_GIE0] and s->regs[R_TX_GIE1] are now unused. Not a concern, this array will soon disappear. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Edgar E. Iglesias --- hw/net/xilinx_ethlite.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/hw/net/xilinx_ethlite.c b/hw/net/xilinx_ethlite.c index a993cb8bb9..36ac8097af 100644 --- a/hw/net/xilinx_ethlite.c +++ b/hw/net/xilinx_ethlite.c @@ -63,6 +63,8 @@ typedef struct XlnxXpsEthLitePort { struct { + uint32_t tx_gie; + uint32_t rx_ctrl; } reg; } XlnxXpsEthLitePort; @@ -91,7 +93,7 @@ struct XlnxXpsEthLite static inline void eth_pulse_irq(XlnxXpsEthLite *s) { /* Only the first gie reg is active. */ - if (s->regs[R_TX_GIE0] & GIE_GIE) { + if (s->port[0].reg.tx_gie & GIE_GIE) { qemu_irq_pulse(s->irq); } } @@ -127,6 +129,9 @@ eth_read(void *opaque, hwaddr addr, unsigned int size) switch (addr) { case R_TX_GIE0: + r = s->port[port_index].reg.tx_gie; + break; + case R_TX_LEN0: case R_TX_LEN1: case R_TX_CTRL1: @@ -191,10 +196,13 @@ eth_write(void *opaque, hwaddr addr, case R_TX_LEN0: case R_TX_LEN1: - case R_TX_GIE0: s->regs[addr] = value; break; + case R_TX_GIE0: + s->port[port_index].reg.tx_gie = value; + break; + default: s->regs[addr] = tswap32(value); break; From patchwork Thu Nov 14 21:00:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 843211 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcc:0:b0:382:184f:390f with SMTP id e12csp506314wrc; Thu, 14 Nov 2024 13:05:38 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVG5jPzn1GbNi0I3Z0om5VRtqLMx8K5qAqdyiDqkrPUNEk2LOWbWP/PddmHlPh8FiIMBnKmRg==@linaro.org X-Google-Smtp-Source: AGHT+IFfmZH5xqnm05ALp6HFka6qHRS41okpVG0GOvHX8NrvYXHzbtTP9Jk6oP2bFPRX8l5gjBTd X-Received: by 2002:a05:622a:2b0e:b0:45d:82a0:5028 with SMTP id d75a77b69052e-46363df181bmr3409821cf.1.1731618338672; Thu, 14 Nov 2024 13:05:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1731618338; cv=none; d=google.com; s=arc-20240605; b=AVsB4+Y795u+cJ5sjzXgwtuLoq3VXmWIDEKTU7Cud6OSnkbACsTSetQlTpZ0SuQO4N cVrV9rP9ohoDEMk6l26qO9KCqYHsj595jG0NNe3FmekLdgV4IwoibHpp7UYvaVctqg9g 13O0YbQbO1uCHlC1mhkALlY9S7ZLlF4XvdDUCEAoC5IROGhO/fSH9iY8o9nZVeAMo4Br cDHtl+sa7gTbsLLITvS8lPC1zo1xQTNkHiCw5VFRkGO6ryTkSKZh9iwgaVmMxnIEwkdA qLz1qdwohHBKM7wci1zcguK8+BYIzZ5Lc2CGIyoG8BWjsXhnSraiuEE7iX5XKd2feLp5 dYNQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=trKZIqBS/vvTexwy29kgOKpXSiuRtzrN3KiHsscp0eY=; fh=IRuGWMvTeecxgxjKSI7QmRflMkYktes0sVu/RVhAZQM=; b=ihYSKCOrlU2FU++uCHVsbNXlLzF6rLTKs1BD4qHKtK95VOnYxOcxR3llzxb2PzLYK9 931UE3DM4t8NAZTGIgNU9SFVHH4Y1zi7FIPUyEUS5T8UhBVt8qqasco/UUJO9Gys63a2 myI19mT3LmKXkIM9T2x5cZcL47xaMqwiaRaI3Tnezi82PScEzlaYG0Ay4mfWDeolwxLC oRlOl/Tbv4RdG5NjFibxGohipg1OZzpZlg2LTE7UtfgHWjFYRdVqMEO7ZYVlFbTobZi1 ykWXAvxsujwVFCcOWlJt9M15PUYxRjEzWJM4NSH/VIf86kIvv5Knuve6OQtGmf7ea+Wb 6K5w==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=UOncNcMa; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Iglesias" , qemu-arm@nongnu.org, Richard Henderson , Thomas Huth , Anton Johansson , Bernhard Beschow , Alistair Francis , Paolo Bonzini , Gustavo Romero , =?utf-8?q?Marc-Andr=C3=A9_Lurea?= =?utf-8?q?u?= , Peter Maydell , Jason Wang , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , "Edgar E . Iglesias" Subject: [PATCH RESEND v2 11/19] hw/net/xilinx_ethlite: Access TX_LEN register for each port Date: Thu, 14 Nov 2024 22:00:02 +0100 Message-ID: <20241114210010.34502-12-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241114210010.34502-1-philmd@linaro.org> References: <20241114210010.34502-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=philmd@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Rather than accessing the registers within the mixed RAM/MMIO region as indexed register, declare a per-port TX_LEN. This will help to map the RAM as RAM (keeping MMIO as MMIO) in few commits. Previous s->regs[R_TX_LEN0] and s->regs[R_TX_LEN1] are now unused. Not a concern, this array will soon disappear. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Edgar E. Iglesias --- hw/net/xilinx_ethlite.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/hw/net/xilinx_ethlite.c b/hw/net/xilinx_ethlite.c index 36ac8097af..06da940303 100644 --- a/hw/net/xilinx_ethlite.c +++ b/hw/net/xilinx_ethlite.c @@ -63,6 +63,7 @@ typedef struct XlnxXpsEthLitePort { struct { + uint32_t tx_len; uint32_t tx_gie; uint32_t rx_ctrl; @@ -134,6 +135,9 @@ eth_read(void *opaque, hwaddr addr, unsigned int size) case R_TX_LEN0: case R_TX_LEN1: + r = s->port[port_index].reg.tx_len; + break; + case R_TX_CTRL1: case R_TX_CTRL0: r = s->regs[addr]; @@ -171,7 +175,7 @@ eth_write(void *opaque, hwaddr addr, if ((value & (CTRL_P | CTRL_S)) == CTRL_S) { qemu_send_packet(qemu_get_queue(s->nic), txbuf_ptr(s, port_index), - s->regs[base + R_TX_LEN0]); + s->port[port_index].reg.tx_len); if (s->regs[base + R_TX_CTRL0] & CTRL_I) eth_pulse_irq(s); } else if ((value & (CTRL_P | CTRL_S)) == (CTRL_P | CTRL_S)) { @@ -196,7 +200,7 @@ eth_write(void *opaque, hwaddr addr, case R_TX_LEN0: case R_TX_LEN1: - s->regs[addr] = value; + s->port[port_index].reg.tx_len = value; break; case R_TX_GIE0: From patchwork Thu Nov 14 21:00:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 843210 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcc:0:b0:382:184f:390f with SMTP id e12csp506278wrc; Thu, 14 Nov 2024 13:05:35 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWzOg9ELp2i5UduPx97+xR3jckSvRmiVAFPGPNfXbjWVbuSRaKKXjKYefAeznvlRVirvPCHpA==@linaro.org X-Google-Smtp-Source: AGHT+IHLoyUrpO6meNZjQAu5oYueKCMCZChgFC57x03fVQc0Ezzhl9sMOg7BBvoznxZtl0uMH3o7 X-Received: by 2002:a05:6122:1d47:b0:50d:39aa:7881 with SMTP id 71dfb90a1353d-51477c9a10fmr964514e0c.0.1731618334880; Thu, 14 Nov 2024 13:05:34 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1731618334; cv=none; d=google.com; s=arc-20240605; b=MXnDXQ7Slt1IsiXkd3UHU661/ZtLUi5o7iN2lyn3wWw5OxRG324BS37czrXkIE3uCv bxLdgxAnHpkY0xB3HzuOP3GURYqRw9hFHzTq81GDz6IVytvWgbADRviOKDlTkQba6k9O eer4+F0WC5pfCVaj9NjW92nzF1JUFsa43ypB2J8EVC/X7dnbaitCFPjFE17GfeHlf2lM GuGdf4u0qOJ7aDlommG9m3tiVry1DSeZbHuD9pwhZ76BOBMqYL8wI/fXfvOYDGQYKrmj Gp6SOZM3Mv/xXBgZrrYBqftXPYYZbWrzoiBbATQW8eHR1XT5/etx4JbOba2n12aqAp64 WtwA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=b8zvUlfKjuVL1gQONPCLSNzp6FDlA5idGOeDaT6LkvA=; fh=IRuGWMvTeecxgxjKSI7QmRflMkYktes0sVu/RVhAZQM=; b=ZJybVHDEXL5aS//UE2GjEpfmZYOxtCmAnp992NHWVmlZe/BOmqmQYwzOWwcOwzsLdp QPb1pjYOuFPzZl8B+s8j12wWPqZQl5sxfZcG5Pr93QaKGk2p/9igmN+PCpgjv38qxW0l hMnkfhunS7azQKEYTKumQqFCqBu1tAmn1sJkGR2KKkQYcw4u/KLghr7F4/R8yKdmIPH+ Yh06wCPDzJqHdCbcoOhZJQBhOeq3kHoANXaR4NfuDv1fqC3YD4andGqQbG86qeLv9XMU 9qJn15G553l691eCm24f5p5Cc7WabVHeouyEDfDrdl+6XZT1woVAxq2Z7PWxpNur55Kh SYQA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=fwqkHPne; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Iglesias" , qemu-arm@nongnu.org, Richard Henderson , Thomas Huth , Anton Johansson , Bernhard Beschow , Alistair Francis , Paolo Bonzini , Gustavo Romero , =?utf-8?q?Marc-Andr=C3=A9_Lurea?= =?utf-8?q?u?= , Peter Maydell , Jason Wang , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , "Edgar E . Iglesias" Subject: [PATCH RESEND v2 12/19] hw/net/xilinx_ethlite: Access TX_CTRL register for each port Date: Thu, 14 Nov 2024 22:00:03 +0100 Message-ID: <20241114210010.34502-13-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241114210010.34502-1-philmd@linaro.org> References: <20241114210010.34502-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=philmd@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Rather than accessing the registers within the mixed RAM/MMIO region as indexed register, declare a per-port TX_CTRL. This will help to map the RAM as RAM (keeping MMIO as MMIO) in few commits. Previous s->regs[R_TX_CTRL0] and s->regs[R_TX_CTRL1] are now unused. Not a concern, this array will soon disappear. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Edgar E. Iglesias --- hw/net/xilinx_ethlite.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/hw/net/xilinx_ethlite.c b/hw/net/xilinx_ethlite.c index 06da940303..674f805d76 100644 --- a/hw/net/xilinx_ethlite.c +++ b/hw/net/xilinx_ethlite.c @@ -65,6 +65,7 @@ typedef struct XlnxXpsEthLitePort struct { uint32_t tx_len; uint32_t tx_gie; + uint32_t tx_ctrl; uint32_t rx_ctrl; } reg; @@ -140,7 +141,7 @@ eth_read(void *opaque, hwaddr addr, unsigned int size) case R_TX_CTRL1: case R_TX_CTRL0: - r = s->regs[addr]; + r = s->port[port_index].reg.tx_ctrl; break; case R_RX_CTRL1: @@ -161,7 +162,6 @@ eth_write(void *opaque, hwaddr addr, { XlnxXpsEthLite *s = opaque; unsigned int port_index = addr_to_port_index(addr); - unsigned int base = 0; uint32_t value = val64; addr >>= 2; @@ -169,24 +169,23 @@ eth_write(void *opaque, hwaddr addr, { case R_TX_CTRL0: case R_TX_CTRL1: - if (addr == R_TX_CTRL1) - base = 0x800 / 4; - if ((value & (CTRL_P | CTRL_S)) == CTRL_S) { qemu_send_packet(qemu_get_queue(s->nic), txbuf_ptr(s, port_index), s->port[port_index].reg.tx_len); - if (s->regs[base + R_TX_CTRL0] & CTRL_I) + if (s->port[port_index].reg.tx_ctrl & CTRL_I) { eth_pulse_irq(s); + } } else if ((value & (CTRL_P | CTRL_S)) == (CTRL_P | CTRL_S)) { memcpy(&s->conf.macaddr.a[0], txbuf_ptr(s, port_index), 6); - if (s->regs[base + R_TX_CTRL0] & CTRL_I) + if (s->port[port_index].reg.tx_ctrl & CTRL_I) { eth_pulse_irq(s); + } } /* We are fast and get ready pretty much immediately so we actually never flip the S nor P bits to one. */ - s->regs[addr] = value & ~(CTRL_P | CTRL_S); + s->port[port_index].reg.tx_ctrl = value & ~(CTRL_P | CTRL_S); break; /* Keep these native. */ From patchwork Thu Nov 14 21:00:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 843201 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcc:0:b0:382:184f:390f with SMTP id e12csp505117wrc; Thu, 14 Nov 2024 13:03:18 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCW6/HEtV57bk+s+QhTGA0Iuxhh5PR+NleNJBHuAlPj1Zi+San65U0FeZbHWIZVokXFXuA8jOA==@linaro.org X-Google-Smtp-Source: AGHT+IH44bEtP7a8hs1HriE3UkwN2vBze3TPeOepJ7dixWdFNegASyAFg1xLUk2nbimRDXeFHhAO X-Received: by 2002:a05:622a:1791:b0:463:60a9:74ba with SMTP id d75a77b69052e-46363ec10afmr3379541cf.55.1731618198468; Thu, 14 Nov 2024 13:03:18 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1731618198; cv=none; d=google.com; s=arc-20240605; b=R7Z9TutkSNdNFygJX1ydCPJ/EBnzSE8i88JJaWqBYCG4fV2jNco/hhlyJNcmYLVd6j qlNv51eQCtNzFZHecc3HRj/+7BIT1VYFTYKgzHddUCljY1AQXb5o9eMWr23b/vub3Sjb J9EKV85m1e9vpEXTMkz0pKX0IDzzdDOn70Rm+hYzEPQNmcxqvzeqD3XrsVEU42FFhPqh I8fQmkKOXFdSZV7VpN8+qH0pURmyuZvwK0vdpn2G0FRz0Lnm2h9tAI8L3rKK2JKkfk1d Iih3JglGfEMHGvZ9tD/IWRcpHnJaob8lIwVYqVrvi0UUVMK41dTtm/cHPECHsWVrl7MU JBHg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=LMLXteKzNxHurRj29HFY+TepUdXjvjn4u+eJ/Foyx5Y=; fh=IRuGWMvTeecxgxjKSI7QmRflMkYktes0sVu/RVhAZQM=; b=UEggstRh1EgmBaQReAxa5QweKZox6ytmhnPK/WeSx7WZlRgIL2EWEQI7GafWyO7B4f vCwTVc2bHBzjVTT/put/82gi1pj39ReWTzrnw9+pQbwu+YhwI44FEKnexeen7mf1LsBi puex1N71eAfkU0jShV4p+9l4fVGmcUWezTkkVznSL5sR3KoDhxH4D2bL8fIHPBUtzGky CpOxTrw2xvwL/AxpgzxquWMFBGhTR/p2+AIbZ12cFETEebtok9EWXS4hTcGoSVTxQj5V vR9ciCNJsaK5IUoPSRF+r7JxJOsBLNbINXY/iyHJ1tpb2CZVCK5JpdepEoiUopKmOKBk xKIw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=QXR8PiYR; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Iglesias" , qemu-arm@nongnu.org, Richard Henderson , Thomas Huth , Anton Johansson , Bernhard Beschow , Alistair Francis , Paolo Bonzini , Gustavo Romero , =?utf-8?q?Marc-Andr=C3=A9_Lurea?= =?utf-8?q?u?= , Peter Maydell , Jason Wang , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , "Edgar E . Iglesias" Subject: [PATCH RESEND v2 13/19] hw/net/xilinx_ethlite: Map RX_CTRL as MMIO Date: Thu, 14 Nov 2024 22:00:04 +0100 Message-ID: <20241114210010.34502-14-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241114210010.34502-1-philmd@linaro.org> References: <20241114210010.34502-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=philmd@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Declare RX registers as MMIO region, split it out of the current mixed RAM/MMIO region. The memory flat view becomes: (qemu) info mtree -f FlatView #0 Root memory region: system 0000000081000000-00000000810007e3 (prio 0, i/o): xlnx.xps-ethernetlite 00000000810007e4-00000000810007f3 (prio 0, i/o): ethlite.mdio 00000000810007f4-00000000810017fb (prio 0, i/o): xlnx.xps-ethernetlite @00000000000007f4 00000000810017fc-00000000810017ff (prio 0, i/o): ethlite.rx[0]io 0000000081001800-0000000081001ffb (prio 0, i/o): xlnx.xps-ethernetlite @0000000000001800 0000000081001ffc-0000000081001fff (prio 0, i/o): ethlite.rx[1]io Reviewed-by: Edgar E. Iglesias Signed-off-by: Philippe Mathieu-Daudé --- hw/net/xilinx_ethlite.c | 82 +++++++++++++++++++++++++++++++++-------- 1 file changed, 67 insertions(+), 15 deletions(-) diff --git a/hw/net/xilinx_ethlite.c b/hw/net/xilinx_ethlite.c index 674f805d76..d8f5a06182 100644 --- a/hw/net/xilinx_ethlite.c +++ b/hw/net/xilinx_ethlite.c @@ -49,11 +49,16 @@ #define R_TX_CTRL1 (0x0ffc / 4) #define R_RX_BUF0 (0x1000 / 4) -#define R_RX_CTRL0 (0x17fc / 4) +#define A_RX_BASE0 0x17fc #define R_RX_BUF1 (0x1800 / 4) -#define R_RX_CTRL1 (0x1ffc / 4) +#define A_RX_BASE1 0x1ffc #define R_MAX (0x2000 / 4) +enum { + RX_CTRL = 0, + RX_MAX +}; + #define GIE_GIE 0x80000000 #define CTRL_I 0x8 @@ -62,6 +67,8 @@ typedef struct XlnxXpsEthLitePort { + MemoryRegion rxio; + struct { uint32_t tx_len; uint32_t tx_gie; @@ -119,6 +126,55 @@ static void *rxbuf_ptr(XlnxXpsEthLite *s, unsigned port_index) return &s->regs[rxbase + R_RX_BUF0]; } +static uint64_t port_rx_read(void *opaque, hwaddr addr, unsigned int size) +{ + XlnxXpsEthLite *s = opaque; + unsigned port_index = addr_to_port_index(addr); + uint32_t r = 0; + + switch (addr >> 2) { + case RX_CTRL: + r = s->port[port_index].reg.rx_ctrl; + break; + default: + g_assert_not_reached(); + } + + return r; +} + +static void port_rx_write(void *opaque, hwaddr addr, uint64_t value, + unsigned int size) +{ + XlnxXpsEthLite *s = opaque; + unsigned port_index = addr_to_port_index(addr); + + switch (addr >> 2) { + case RX_CTRL: + if (!(value & CTRL_S)) { + qemu_flush_queued_packets(qemu_get_queue(s->nic)); + } + s->port[port_index].reg.rx_ctrl = value; + break; + default: + g_assert_not_reached(); + } +} + +static const MemoryRegionOps eth_portrx_ops = { + .read = port_rx_read, + .write = port_rx_write, + .endianness = DEVICE_NATIVE_ENDIAN, + .impl = { + .min_access_size = 4, + .max_access_size = 4, + }, + .valid = { + .min_access_size = 4, + .max_access_size = 4, + }, +}; + static uint64_t eth_read(void *opaque, hwaddr addr, unsigned int size) { @@ -144,11 +200,6 @@ eth_read(void *opaque, hwaddr addr, unsigned int size) r = s->port[port_index].reg.tx_ctrl; break; - case R_RX_CTRL1: - case R_RX_CTRL0: - r = s->port[port_index].reg.rx_ctrl; - break; - default: r = tswap32(s->regs[addr]); break; @@ -189,14 +240,6 @@ eth_write(void *opaque, hwaddr addr, break; /* Keep these native. */ - case R_RX_CTRL0: - case R_RX_CTRL1: - if (!(value & CTRL_S)) { - qemu_flush_queued_packets(qemu_get_queue(s->nic)); - } - s->port[port_index].reg.rx_ctrl = value; - break; - case R_TX_LEN0: case R_TX_LEN1: s->port[port_index].reg.tx_len = value; @@ -289,6 +332,15 @@ static void xilinx_ethlite_realize(DeviceState *dev, Error **errp) memory_region_add_subregion(&s->mmio, A_MDIO_BASE, sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->mdio), 0)); + for (unsigned i = 0; i < 2; i++) { + memory_region_init_io(&s->port[i].rxio, OBJECT(dev), + ð_portrx_ops, s, + i ? "ethlite.rx[1]io" : "ethlite.rx[0]io", + 4 * RX_MAX); + memory_region_add_subregion(&s->mmio, i ? A_RX_BASE1 : A_RX_BASE0, + &s->port[i].rxio); + } + qemu_macaddr_default_if_unset(&s->conf.macaddr); s->nic = qemu_new_nic(&net_xilinx_ethlite_info, &s->conf, object_get_typename(OBJECT(dev)), dev->id, From patchwork Thu Nov 14 21:00:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 843205 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcc:0:b0:382:184f:390f with SMTP id e12csp505855wrc; Thu, 14 Nov 2024 13:04:44 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXDY+GSR0+6qekhqtwF7essPcR+itsQOjb2Ci9ktv75FdZfSpO2CH+a1sEQub2/PYZQ1rplTA==@linaro.org X-Google-Smtp-Source: AGHT+IGtJW2QHqz14zXmXo3M8BUdREEX60L0jl5fmwn5VF3sHNY3ub4F2tL9ot+AImczUQl8OO51 X-Received: by 2002:a05:6830:618c:b0:718:9c03:d216 with SMTP id 46e09a7af769-71a7794717bmr507581a34.15.1731618284105; Thu, 14 Nov 2024 13:04:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1731618284; cv=none; d=google.com; s=arc-20240605; b=h4YaHw/cZlAgj1NUnweytpil4FBxdAbJlyBJ4tHrbXNVdgX53fSxV2scNRageSPgcr if/wygNvRzFWnwanvg/gNjwEcBCR7Mp5qK8FQp/kohkfL2zIlsAl4tYIBGUWNtnh8/SD c0y8NQdqPVjk0MqlvWBPvkhWQGIJAmqT8ikk/YGkh0YdWKk0IE3XbwL0gRSu7I+okEqR thwKOuae05w/eEInh8sIdTpQuaFsBs1M9SnK/mAJ1+K1p1PHPPBSWm/mCQnnO49Afqes g+6qew0GeCRoHDDsQ98Z02V28OcvBfTAu2UtjXXlSPwBQe+mxoJx8LV6uo3FwlhQX9OE j2Sg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=WHsXd+6nklg/Fen/qM8UGXgjnDFu4CazQunEUxBn5NI=; fh=IRuGWMvTeecxgxjKSI7QmRflMkYktes0sVu/RVhAZQM=; b=k9Va+3si9/w0T2LXKuJxZQrXrdq2mjGWzZBsOyYDjrrNzxuByrRIpYgLUwKbtV1Y9G b/xuKZYyWPF9MdDfJEOqDlpIFS4tqs+2uhvUPzA03MsOzCQtyuRJrQtnKwq+FU/Xq2Y6 erq7NH3EmdQjFNgXi25JXB6rTEUQ1MnkS5yBvJaleEwBvq3JRDFLBRMl4tz9o/bPzMRz pmNjJwbu72EdpH7PkSsS/7hfIscg9hONVIFTInntDJ/nM4KAl/e/Qa7ZAvWEavtMagYv TjDVxVzGQo+slm0nJJERRKsIUUw791r5weKYTOa6EcJOQ1dpNm8/gyWGa5LSojgD5A0N 7Zkw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Mb9848ZR; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Iglesias" , qemu-arm@nongnu.org, Richard Henderson , Thomas Huth , Anton Johansson , Bernhard Beschow , Alistair Francis , Paolo Bonzini , Gustavo Romero , =?utf-8?q?Marc-Andr=C3=A9_Lurea?= =?utf-8?q?u?= , Peter Maydell , Jason Wang , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , "Edgar E . Iglesias" Subject: [PATCH RESEND v2 14/19] hw/net/xilinx_ethlite: Map TX_LEN as MMIO Date: Thu, 14 Nov 2024 22:00:05 +0100 Message-ID: <20241114210010.34502-15-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241114210010.34502-1-philmd@linaro.org> References: <20241114210010.34502-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=philmd@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Declare TX registers as MMIO region, split it out of the current mixed RAM/MMIO region. The memory flat view becomes: (qemu) info mtree -f FlatView #0 Root memory region: system 0000000081000000-00000000810007e3 (prio 0, i/o): xlnx.xps-ethernetlite 00000000810007e4-00000000810007f3 (prio 0, i/o): ethlite.mdio 00000000810007f4-00000000810007f7 (prio 0, i/o): ethlite.tx[0]io 00000000810007f8-0000000081000ff3 (prio 0, i/o): xlnx.xps-ethernetlite @00000000000007f8 0000000081000ff4-0000000081000ff7 (prio 0, i/o): ethlite.tx[1]io 0000000081000ff8-00000000810017fb (prio 0, i/o): xlnx.xps-ethernetlite @0000000000000ff8 00000000810017fc-00000000810017ff (prio 0, i/o): ethlite.rx[0]io 0000000081001800-0000000081001ffb (prio 0, i/o): xlnx.xps-ethernetlite @0000000000001800 0000000081001ffc-0000000081001fff (prio 0, i/o): ethlite.rx[1]io Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Edgar E. Iglesias --- hw/net/xilinx_ethlite.c | 73 ++++++++++++++++++++++++++++++++++------- 1 file changed, 61 insertions(+), 12 deletions(-) diff --git a/hw/net/xilinx_ethlite.c b/hw/net/xilinx_ethlite.c index d8f5a06182..b105fb7524 100644 --- a/hw/net/xilinx_ethlite.c +++ b/hw/net/xilinx_ethlite.c @@ -41,11 +41,11 @@ #define R_TX_BUF0 0 #define BUFSZ_MAX 0x07e4 #define A_MDIO_BASE 0x07e4 -#define R_TX_LEN0 (0x07f4 / 4) +#define A_TX_BASE0 0x07f4 #define R_TX_GIE0 (0x07f8 / 4) #define R_TX_CTRL0 (0x07fc / 4) #define R_TX_BUF1 (0x0800 / 4) -#define R_TX_LEN1 (0x0ff4 / 4) +#define A_TX_BASE1 0x0ff4 #define R_TX_CTRL1 (0x0ffc / 4) #define R_RX_BUF0 (0x1000 / 4) @@ -54,6 +54,11 @@ #define A_RX_BASE1 0x1ffc #define R_MAX (0x2000 / 4) +enum { + TX_LEN = 0, + TX_MAX +}; + enum { RX_CTRL = 0, RX_MAX @@ -67,6 +72,7 @@ enum { typedef struct XlnxXpsEthLitePort { + MemoryRegion txio; MemoryRegion rxio; struct { @@ -126,6 +132,52 @@ static void *rxbuf_ptr(XlnxXpsEthLite *s, unsigned port_index) return &s->regs[rxbase + R_RX_BUF0]; } +static uint64_t port_tx_read(void *opaque, hwaddr addr, unsigned int size) +{ + XlnxXpsEthLite *s = opaque; + unsigned port_index = addr_to_port_index(addr); + uint32_t r = 0; + + switch (addr >> 2) { + case TX_LEN: + r = s->port[port_index].reg.tx_len; + break; + default: + g_assert_not_reached(); + } + + return r; +} + +static void port_tx_write(void *opaque, hwaddr addr, uint64_t value, + unsigned int size) +{ + XlnxXpsEthLite *s = opaque; + unsigned port_index = addr_to_port_index(addr); + + switch (addr >> 2) { + case TX_LEN: + s->port[port_index].reg.tx_len = value; + break; + default: + g_assert_not_reached(); + } +} + +static const MemoryRegionOps eth_porttx_ops = { + .read = port_tx_read, + .write = port_tx_write, + .endianness = DEVICE_NATIVE_ENDIAN, + .impl = { + .min_access_size = 4, + .max_access_size = 4, + }, + .valid = { + .min_access_size = 4, + .max_access_size = 4, + }, +}; + static uint64_t port_rx_read(void *opaque, hwaddr addr, unsigned int size) { XlnxXpsEthLite *s = opaque; @@ -190,11 +242,6 @@ eth_read(void *opaque, hwaddr addr, unsigned int size) r = s->port[port_index].reg.tx_gie; break; - case R_TX_LEN0: - case R_TX_LEN1: - r = s->port[port_index].reg.tx_len; - break; - case R_TX_CTRL1: case R_TX_CTRL0: r = s->port[port_index].reg.tx_ctrl; @@ -240,11 +287,6 @@ eth_write(void *opaque, hwaddr addr, break; /* Keep these native. */ - case R_TX_LEN0: - case R_TX_LEN1: - s->port[port_index].reg.tx_len = value; - break; - case R_TX_GIE0: s->port[port_index].reg.tx_gie = value; break; @@ -333,6 +375,13 @@ static void xilinx_ethlite_realize(DeviceState *dev, Error **errp) sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->mdio), 0)); for (unsigned i = 0; i < 2; i++) { + memory_region_init_io(&s->port[i].txio, OBJECT(dev), + ð_porttx_ops, s, + i ? "ethlite.tx[1]io" : "ethlite.tx[0]io", + 4 * TX_MAX); + memory_region_add_subregion(&s->mmio, i ? A_TX_BASE1 : A_TX_BASE0, + &s->port[i].txio); + memory_region_init_io(&s->port[i].rxio, OBJECT(dev), ð_portrx_ops, s, i ? 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Iglesias" , qemu-arm@nongnu.org, Richard Henderson , Thomas Huth , Anton Johansson , Bernhard Beschow , Alistair Francis , Paolo Bonzini , Gustavo Romero , =?utf-8?q?Marc-Andr=C3=A9_Lurea?= =?utf-8?q?u?= , Peter Maydell , Jason Wang , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , "Edgar E . Iglesias" Subject: [PATCH RESEND v2 15/19] hw/net/xilinx_ethlite: Map TX_GIE as MMIO Date: Thu, 14 Nov 2024 22:00:06 +0100 Message-ID: <20241114210010.34502-16-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241114210010.34502-1-philmd@linaro.org> References: <20241114210010.34502-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::230; envelope-from=philmd@linaro.org; helo=mail-lj1-x230.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Add TX_GIE to the TX registers MMIO region. Before TX_GIE1 was accessed as RAM, with no effect. Now it is accessed as MMIO, also without any effect. The memory flat view becomes: (qemu) info mtree -f FlatView #0 Root memory region: system 0000000081000000-00000000810007e3 (prio 0, i/o): xlnx.xps-ethernetlite 00000000810007e4-00000000810007f3 (prio 0, i/o): ethlite.mdio 00000000810007f4-00000000810007fb (prio 0, i/o): ethlite.tx[0]io 00000000810007fc-0000000081000ff3 (prio 0, i/o): xlnx.xps-ethernetlite @00000000000007fc 0000000081000ff4-0000000081000ffb (prio 0, i/o): ethlite.tx[1]io 0000000081000ffc-00000000810017fb (prio 0, i/o): xlnx.xps-ethernetlite @0000000000000ffc 00000000810017fc-00000000810017ff (prio 0, i/o): ethlite.rx[0]io 0000000081001800-0000000081001ffb (prio 0, i/o): xlnx.xps-ethernetlite @0000000000001800 0000000081001ffc-0000000081001fff (prio 0, i/o): ethlite.rx[1]io Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Edgar E. Iglesias --- hw/net/xilinx_ethlite.c | 17 +++++++---------- 1 file changed, 7 insertions(+), 10 deletions(-) diff --git a/hw/net/xilinx_ethlite.c b/hw/net/xilinx_ethlite.c index b105fb7524..038e81dcae 100644 --- a/hw/net/xilinx_ethlite.c +++ b/hw/net/xilinx_ethlite.c @@ -42,7 +42,6 @@ #define BUFSZ_MAX 0x07e4 #define A_MDIO_BASE 0x07e4 #define A_TX_BASE0 0x07f4 -#define R_TX_GIE0 (0x07f8 / 4) #define R_TX_CTRL0 (0x07fc / 4) #define R_TX_BUF1 (0x0800 / 4) #define A_TX_BASE1 0x0ff4 @@ -56,6 +55,7 @@ enum { TX_LEN = 0, + TX_GIE = 1, TX_MAX }; @@ -142,6 +142,9 @@ static uint64_t port_tx_read(void *opaque, hwaddr addr, unsigned int size) case TX_LEN: r = s->port[port_index].reg.tx_len; break; + case TX_GIE: + r = s->port[port_index].reg.tx_gie; + break; default: g_assert_not_reached(); } @@ -159,6 +162,9 @@ static void port_tx_write(void *opaque, hwaddr addr, uint64_t value, case TX_LEN: s->port[port_index].reg.tx_len = value; break; + case TX_GIE: + s->port[port_index].reg.tx_gie = value; + break; default: g_assert_not_reached(); } @@ -238,10 +244,6 @@ eth_read(void *opaque, hwaddr addr, unsigned int size) switch (addr) { - case R_TX_GIE0: - r = s->port[port_index].reg.tx_gie; - break; - case R_TX_CTRL1: case R_TX_CTRL0: r = s->port[port_index].reg.tx_ctrl; @@ -286,11 +288,6 @@ eth_write(void *opaque, hwaddr addr, s->port[port_index].reg.tx_ctrl = value & ~(CTRL_P | CTRL_S); break; - /* Keep these native. */ - case R_TX_GIE0: - s->port[port_index].reg.tx_gie = value; - break; - default: s->regs[addr] = tswap32(value); break; From patchwork Thu Nov 14 21:00:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 843204 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcc:0:b0:382:184f:390f with SMTP id e12csp505833wrc; Thu, 14 Nov 2024 13:04:41 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWh1pPU+5oaCwl8TeHMWtm9Rd/RHyIIw2EUWQ0A4RVZbb8n1W/ywi7bjyVDnR+jg8vM7CTRtQ==@linaro.org X-Google-Smtp-Source: AGHT+IGk9k4oTeirr6J6PsZXjrxrdosGuXSqk8J4hS3i2sg2HnKZwi6LsaydsT4mDeVm9EBdorz1 X-Received: by 2002:a05:6214:5541:b0:6d3:6542:848c with SMTP id 6a1803df08f44-6d3fac11f99mr8240156d6.1.1731618281608; Thu, 14 Nov 2024 13:04:41 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1731618281; cv=none; d=google.com; s=arc-20240605; b=fglg12N6i3QET3D6cEZrHSu1RXdF1/soUzblAcwYLz7l3jJel8mFlkKE1/Fu1ew4IG DL5e3EbD9xpx6NeV+g1htIevXEsmbJHPrQfK+eW5CkKibyZSGZOWYINEQkQlqBN+YXOJ 113VARttKSTj49+yIe+NDyO73ihGr8LUgpwFq3LuY+HY35SkXyF4seXl2nSdcJeHMgtU 0fQaHHBmnFYWPD8hlIfkGbJotFIBIu28G6mIRlmKTMNvJXkXEn0Qs+0PY+wGcTesz2js iUjFkE75VF2ARw1mL+eFOT1tIj9tuir1fB9rtUIFBCTXJx8No9fRsde0B588JeYAYrwU iw5w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=YrNmzpyBj8jJaMk8J310GpURg0YUYlZP1LiDoI08wTo=; fh=IRuGWMvTeecxgxjKSI7QmRflMkYktes0sVu/RVhAZQM=; b=HeXIsM5fjf3NMT/MMlzDfbzDcGul/iqdBH/ddMPoZzbQmHLC8XTomy2Z0JoEcmdYBS sohiu94mPqhP71HV/cra5hHQoYrt4rg/7SCCPoD7CZKjv4ppAoCBtlF5am67/7pTAuy2 iSL65k1ZK8nzGpGcAuBfoey3pkzxfdU+N5TMBT+th1LDP6AUeHDzaQ1dG4HXSBuqnZAu lkvLKlsc2hF+DbyaWRUz5cqsEA3BZWXzKQWqXmjOsBvSHbZrEqBrtJkv744gkdS73Zs2 0HDrDAkl10I3TOeAbraIGibr1Dr1LvoH3OuR6EJE0SWWALGYEbzbMWHA3P08PJgS3H1W WeFg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=v3XrjUf9; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Iglesias" , qemu-arm@nongnu.org, Richard Henderson , Thomas Huth , Anton Johansson , Bernhard Beschow , Alistair Francis , Paolo Bonzini , Gustavo Romero , =?utf-8?q?Marc-Andr=C3=A9_Lurea?= =?utf-8?q?u?= , Peter Maydell , Jason Wang , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , "Edgar E . Iglesias" Subject: [PATCH RESEND v2 16/19] hw/net/xilinx_ethlite: Map TX_CTRL as MMIO Date: Thu, 14 Nov 2024 22:00:07 +0100 Message-ID: <20241114210010.34502-17-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241114210010.34502-1-philmd@linaro.org> References: <20241114210010.34502-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=philmd@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Add TX_CTRL to the TX registers MMIO region. The memory flat view becomes: (qemu) info mtree -f FlatView #0 Root memory region: system 0000000081000000-00000000810007e3 (prio 0, i/o): xlnx.xps-ethernetlite 00000000810007e4-00000000810007f3 (prio 0, i/o): ethlite.mdio 00000000810007f4-00000000810007ff (prio 0, i/o): ethlite.tx[0]io 0000000081000800-0000000081000ff3 (prio 0, i/o): xlnx.xps-ethernetlite @0000000000000800 0000000081000ff4-0000000081000fff (prio 0, i/o): ethlite.tx[1]io 0000000081001000-00000000810017fb (prio 0, i/o): xlnx.xps-ethernetlite @0000000000001000 00000000810017fc-00000000810017ff (prio 0, i/o): ethlite.rx[0]io 0000000081001800-0000000081001ffb (prio 0, i/o): xlnx.xps-ethernetlite @0000000000001800 0000000081001ffc-0000000081001fff (prio 0, i/o): ethlite.rx[1]io Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Edgar E. Iglesias --- hw/net/xilinx_ethlite.c | 54 ++++++++++++++++++----------------------- 1 file changed, 24 insertions(+), 30 deletions(-) diff --git a/hw/net/xilinx_ethlite.c b/hw/net/xilinx_ethlite.c index 038e81dcae..c710857cfd 100644 --- a/hw/net/xilinx_ethlite.c +++ b/hw/net/xilinx_ethlite.c @@ -42,10 +42,8 @@ #define BUFSZ_MAX 0x07e4 #define A_MDIO_BASE 0x07e4 #define A_TX_BASE0 0x07f4 -#define R_TX_CTRL0 (0x07fc / 4) #define R_TX_BUF1 (0x0800 / 4) #define A_TX_BASE1 0x0ff4 -#define R_TX_CTRL1 (0x0ffc / 4) #define R_RX_BUF0 (0x1000 / 4) #define A_RX_BASE0 0x17fc @@ -56,6 +54,7 @@ enum { TX_LEN = 0, TX_GIE = 1, + TX_CTRL = 2, TX_MAX }; @@ -145,6 +144,9 @@ static uint64_t port_tx_read(void *opaque, hwaddr addr, unsigned int size) case TX_GIE: r = s->port[port_index].reg.tx_gie; break; + case TX_CTRL: + r = s->port[port_index].reg.tx_ctrl; + break; default: g_assert_not_reached(); } @@ -165,6 +167,26 @@ static void port_tx_write(void *opaque, hwaddr addr, uint64_t value, case TX_GIE: s->port[port_index].reg.tx_gie = value; break; + case TX_CTRL: + if ((value & (CTRL_P | CTRL_S)) == CTRL_S) { + qemu_send_packet(qemu_get_queue(s->nic), + txbuf_ptr(s, port_index), + s->port[port_index].reg.tx_len); + if (s->port[port_index].reg.tx_ctrl & CTRL_I) { + eth_pulse_irq(s); + } + } else if ((value & (CTRL_P | CTRL_S)) == (CTRL_P | CTRL_S)) { + memcpy(&s->conf.macaddr.a[0], txbuf_ptr(s, port_index), 6); + if (s->port[port_index].reg.tx_ctrl & CTRL_I) { + eth_pulse_irq(s); + } + } + /* + * We are fast and get ready pretty much immediately + * so we actually never flip the S nor P bits to one. + */ + s->port[port_index].reg.tx_ctrl = value & ~(CTRL_P | CTRL_S); + break; default: g_assert_not_reached(); } @@ -237,18 +259,12 @@ static uint64_t eth_read(void *opaque, hwaddr addr, unsigned int size) { XlnxXpsEthLite *s = opaque; - unsigned port_index = addr_to_port_index(addr); uint32_t r = 0; addr >>= 2; switch (addr) { - case R_TX_CTRL1: - case R_TX_CTRL0: - r = s->port[port_index].reg.tx_ctrl; - break; - default: r = tswap32(s->regs[addr]); break; @@ -261,33 +277,11 @@ eth_write(void *opaque, hwaddr addr, uint64_t val64, unsigned int size) { XlnxXpsEthLite *s = opaque; - unsigned int port_index = addr_to_port_index(addr); uint32_t value = val64; addr >>= 2; switch (addr) { - case R_TX_CTRL0: - case R_TX_CTRL1: - if ((value & (CTRL_P | CTRL_S)) == CTRL_S) { - qemu_send_packet(qemu_get_queue(s->nic), - txbuf_ptr(s, port_index), - s->port[port_index].reg.tx_len); - if (s->port[port_index].reg.tx_ctrl & CTRL_I) { - eth_pulse_irq(s); - } - } else if ((value & (CTRL_P | CTRL_S)) == (CTRL_P | CTRL_S)) { - memcpy(&s->conf.macaddr.a[0], txbuf_ptr(s, port_index), 6); - if (s->port[port_index].reg.tx_ctrl & CTRL_I) { - eth_pulse_irq(s); - } - } - - /* We are fast and get ready pretty much immediately so - we actually never flip the S nor P bits to one. */ - s->port[port_index].reg.tx_ctrl = value & ~(CTRL_P | CTRL_S); - break; - default: s->regs[addr] = tswap32(value); break; From patchwork Thu Nov 14 21:00:08 2024 Content-Type: text/plain; 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Iglesias" , qemu-arm@nongnu.org, Richard Henderson , Thomas Huth , Anton Johansson , Bernhard Beschow , Alistair Francis , Paolo Bonzini , Gustavo Romero , =?utf-8?q?Marc-Andr=C3=A9_Lurea?= =?utf-8?q?u?= , Peter Maydell , Jason Wang , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , "Edgar E . Iglesias" Subject: [PATCH RESEND v2 17/19] hw/net/xilinx_ethlite: Map the RAM buffer as RAM memory region Date: Thu, 14 Nov 2024 22:00:08 +0100 Message-ID: <20241114210010.34502-18-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241114210010.34502-1-philmd@linaro.org> References: <20241114210010.34502-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philmd@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Rather than using I/O registers for RAM buffer, having to swap endianness back and forth (because the core memory layer automatically swaps endiannes for us), declare the buffers as RAM regions. The "xlnx.xps-ethernetlite" MR doesn't have any more I/O regions. Remove the now unused s->regs[] array. The memory flat view becomes: FlatView #0 Root memory region: system 0000000081000000-00000000810007e3 (prio 0, ram): ethlite.tx[0]buf 00000000810007e4-00000000810007f3 (prio 0, i/o): ethlite.mdio 00000000810007f4-00000000810007ff (prio 0, i/o): ethlite.tx[0]io 0000000081000800-0000000081000fe3 (prio 0, ram): ethlite.tx[1]buf 0000000081000ff4-0000000081000fff (prio 0, i/o): ethlite.tx[1]io 0000000081001000-00000000810017e3 (prio 0, ram): ethlite.rx[0]buf 00000000810017fc-00000000810017ff (prio 0, i/o): ethlite.rx[0]io 0000000081001800-0000000081001fe3 (prio 0, ram): ethlite.rx[1]buf 0000000081001ffc-0000000081001fff (prio 0, i/o): ethlite.rx[1]io Reported-by: Paolo Bonzini Reviewed-by: Edgar E. Iglesias Signed-off-by: Philippe Mathieu-Daudé --- hw/net/xilinx_ethlite.c | 81 +++++++++-------------------------------- 1 file changed, 17 insertions(+), 64 deletions(-) diff --git a/hw/net/xilinx_ethlite.c b/hw/net/xilinx_ethlite.c index c710857cfd..0d445653b2 100644 --- a/hw/net/xilinx_ethlite.c +++ b/hw/net/xilinx_ethlite.c @@ -2,6 +2,7 @@ * QEMU model of the Xilinx Ethernet Lite MAC. * * Copyright (c) 2009 Edgar E. Iglesias. + * Copyright (c) 2024 Linaro, Ltd * * DS580: https://docs.amd.com/v/u/en-US/xps_ethernetlite * LogiCORE IP XPS Ethernet Lite Media Access Controller @@ -30,7 +31,6 @@ #include "qemu/bitops.h" #include "qom/object.h" #include "qapi/error.h" -#include "exec/tswap.h" #include "hw/sysbus.h" #include "hw/irq.h" #include "hw/qdev-properties.h" @@ -38,18 +38,12 @@ #include "net/net.h" #include "trace.h" -#define R_TX_BUF0 0 #define BUFSZ_MAX 0x07e4 #define A_MDIO_BASE 0x07e4 #define A_TX_BASE0 0x07f4 -#define R_TX_BUF1 (0x0800 / 4) #define A_TX_BASE1 0x0ff4 - -#define R_RX_BUF0 (0x1000 / 4) #define A_RX_BASE0 0x17fc -#define R_RX_BUF1 (0x1800 / 4) #define A_RX_BASE1 0x1ffc -#define R_MAX (0x2000 / 4) enum { TX_LEN = 0, @@ -73,6 +67,8 @@ typedef struct XlnxXpsEthLitePort { MemoryRegion txio; MemoryRegion rxio; + MemoryRegion txbuf; + MemoryRegion rxbuf; struct { uint32_t tx_len; @@ -101,7 +97,6 @@ struct XlnxXpsEthLite UnimplementedDeviceState mdio; XlnxXpsEthLitePort port[2]; - uint32_t regs[R_MAX]; }; static inline void eth_pulse_irq(XlnxXpsEthLite *s) @@ -119,16 +114,12 @@ static unsigned addr_to_port_index(hwaddr addr) static void *txbuf_ptr(XlnxXpsEthLite *s, unsigned port_index) { - unsigned int rxbase = port_index * (0x800 / 4); - - return &s->regs[rxbase + R_TX_BUF0]; + return memory_region_get_ram_ptr(&s->port[port_index].txbuf); } static void *rxbuf_ptr(XlnxXpsEthLite *s, unsigned port_index) { - unsigned int rxbase = port_index * (0x800 / 4); - - return &s->regs[rxbase + R_RX_BUF0]; + return memory_region_get_ram_ptr(&s->port[port_index].rxbuf); } static uint64_t port_tx_read(void *opaque, hwaddr addr, unsigned int size) @@ -255,53 +246,6 @@ static const MemoryRegionOps eth_portrx_ops = { }, }; -static uint64_t -eth_read(void *opaque, hwaddr addr, unsigned int size) -{ - XlnxXpsEthLite *s = opaque; - uint32_t r = 0; - - addr >>= 2; - - switch (addr) - { - default: - r = tswap32(s->regs[addr]); - break; - } - return r; -} - -static void -eth_write(void *opaque, hwaddr addr, - uint64_t val64, unsigned int size) -{ - XlnxXpsEthLite *s = opaque; - uint32_t value = val64; - - addr >>= 2; - switch (addr) - { - default: - s->regs[addr] = tswap32(value); - break; - } -} - -static const MemoryRegionOps eth_ops = { - .read = eth_read, - .write = eth_write, - .endianness = DEVICE_NATIVE_ENDIAN, - .impl = { - .min_access_size = 4, - .max_access_size = 4, - }, - .valid = { - .min_access_size = 4, - .max_access_size = 4 - } -}; - static bool eth_can_rx(NetClientState *nc) { XlnxXpsEthLite *s = qemu_get_nic_opaque(nc); @@ -357,6 +301,9 @@ static void xilinx_ethlite_realize(DeviceState *dev, Error **errp) { XlnxXpsEthLite *s = XILINX_ETHLITE(dev); + memory_region_init(&s->mmio, OBJECT(dev), + "xlnx.xps-ethernetlite", 0x2000); + object_initialize_child(OBJECT(dev), "ethlite.mdio", &s->mdio, TYPE_UNIMPLEMENTED_DEVICE); qdev_prop_set_string(DEVICE(&s->mdio), "name", "ethlite.mdio"); @@ -366,6 +313,10 @@ static void xilinx_ethlite_realize(DeviceState *dev, Error **errp) sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->mdio), 0)); for (unsigned i = 0; i < 2; i++) { + memory_region_init_ram(&s->port[i].txbuf, OBJECT(dev), + i ? "ethlite.tx[1]buf" : "ethlite.tx[0]buf", + BUFSZ_MAX, &error_abort); + memory_region_add_subregion(&s->mmio, 0x0800 * i, &s->port[i].txbuf); memory_region_init_io(&s->port[i].txio, OBJECT(dev), ð_porttx_ops, s, i ? "ethlite.tx[1]io" : "ethlite.tx[0]io", @@ -373,6 +324,11 @@ static void xilinx_ethlite_realize(DeviceState *dev, Error **errp) memory_region_add_subregion(&s->mmio, i ? A_TX_BASE1 : A_TX_BASE0, &s->port[i].txio); + memory_region_init_ram(&s->port[i].rxbuf, OBJECT(dev), + i ? "ethlite.rx[1]buf" : "ethlite.rx[0]buf", + BUFSZ_MAX, &error_abort); + memory_region_add_subregion(&s->mmio, 0x1000 + 0x0800 * i, + &s->port[i].rxbuf); memory_region_init_io(&s->port[i].rxio, OBJECT(dev), ð_portrx_ops, s, i ? "ethlite.rx[1]io" : "ethlite.rx[0]io", @@ -393,9 +349,6 @@ static void xilinx_ethlite_init(Object *obj) XlnxXpsEthLite *s = XILINX_ETHLITE(obj); sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); - - memory_region_init_io(&s->mmio, obj, ð_ops, s, - "xlnx.xps-ethernetlite", R_MAX * 4); sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); } From patchwork Thu Nov 14 21:00:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 843207 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcc:0:b0:382:184f:390f with SMTP id e12csp506028wrc; Thu, 14 Nov 2024 13:05:03 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWjzVQZZF65g3WrZ5GoDTvNRvIXBp1Z8Px1svPOhD6ePJ/FV7ywkiCm7L2lO5oCLm44uqDUsg==@linaro.org X-Google-Smtp-Source: AGHT+IFdnjwtOjggiMxmGKLmXourCrXiRn76UpSyIIIqe8xaDqdhecWlxfDYz4dGH5AEVmDtjGFd X-Received: by 2002:a05:6358:728d:b0:1c3:8f64:add6 with SMTP id e5c5f4694b2df-1c6cd0a32fcmr70668655d.3.1731618303201; Thu, 14 Nov 2024 13:05:03 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1731618303; cv=none; d=google.com; s=arc-20240605; b=Sp5yITbk9ADpOK8CNfdrJOoFReycAT8b9aT9ZIfPXXHroNqXbwm1MBmeLMF2EWsUjG iiNBPauBs9D2Vyx8delw5KCI53pJ+hmOKX07fnWUiUgn/0naI7fAd79i11dBrmWiyVtf yQvRHzI9tvU/oKYTSXMnie8C5Kd+ZCnBRKVfaDPbNdSfaEr3Zw63r9/MlgcX+5YtLMF2 7se1k8oQKWSVIyPNtsyVih1nO1haFi8x2mfB06nQp7aW6XdlGAQTWCIuKyDW3qLQ6zCR r/mzFWryuZxUMfAsAvWnST/nl7hJJOxpP++XUakeKFf3q/o0KUZBVf1EzfjomNWinN4i HKKg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=8xMxbLuqYUOAO97RnSz2IGo3OvTtmoe9G2YVBXewgY0=; fh=IRuGWMvTeecxgxjKSI7QmRflMkYktes0sVu/RVhAZQM=; b=Gj4HWqAiBIS56JEU1jRpJVs5EHe8Fzujmmt14CqSAcKpldUIhfmFSuVpmPEsWGfLEV 6+hHb3KDuZeiWuQMojEPPDBVe768XoViSttZWXbgYDFRi2NWlWJ4+qEV5/hk7Ez15WpA GKSQg0xSi/90hapYqPrzcMNa8BgdDny6wzRO9NTTmzDcypKM+hpQRwp6sov+lkDznGAE jwDPiliV+Og8Pt99tMgAUYmWxzhOar6ziuJ70hQG4pvvcCdSQds5OwehW5kH2m7bQa08 MRSlJ6VtCkumHa70ScuBL1DUa4DSA0gXHHDu1+0s0JpqRD4xuS/a35DZtFkjk9WCZANo QYUA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=aqOqZqyY; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Iglesias" , qemu-arm@nongnu.org, Richard Henderson , Thomas Huth , Anton Johansson , Bernhard Beschow , Alistair Francis , Paolo Bonzini , Gustavo Romero , =?utf-8?q?Marc-Andr=C3=A9_Lurea?= =?utf-8?q?u?= , Peter Maydell , Jason Wang , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , "Edgar E . Iglesias" Subject: [PATCH RESEND v2 18/19] hw/net/xilinx_ethlite: Rename 'mmio' MR as 'container' Date: Thu, 14 Nov 2024 22:00:09 +0100 Message-ID: <20241114210010.34502-19-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241114210010.34502-1-philmd@linaro.org> References: <20241114210010.34502-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=philmd@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Having all its address range mapped by subregions, s->mmio MemoryRegion effectively became a container. Rename it as 'container' for clarity. Reviewed-by: Edgar E. Iglesias Signed-off-by: Philippe Mathieu-Daudé --- hw/net/xilinx_ethlite.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/hw/net/xilinx_ethlite.c b/hw/net/xilinx_ethlite.c index 0d445653b2..5f1ff7b712 100644 --- a/hw/net/xilinx_ethlite.c +++ b/hw/net/xilinx_ethlite.c @@ -86,7 +86,7 @@ struct XlnxXpsEthLite { SysBusDevice parent_obj; - MemoryRegion mmio; + MemoryRegion container; qemu_irq irq; NICState *nic; NICConf conf; @@ -301,7 +301,7 @@ static void xilinx_ethlite_realize(DeviceState *dev, Error **errp) { XlnxXpsEthLite *s = XILINX_ETHLITE(dev); - memory_region_init(&s->mmio, OBJECT(dev), + memory_region_init(&s->container, OBJECT(dev), "xlnx.xps-ethernetlite", 0x2000); object_initialize_child(OBJECT(dev), "ethlite.mdio", &s->mdio, @@ -309,31 +309,31 @@ static void xilinx_ethlite_realize(DeviceState *dev, Error **errp) qdev_prop_set_string(DEVICE(&s->mdio), "name", "ethlite.mdio"); qdev_prop_set_uint64(DEVICE(&s->mdio), "size", 4 * 4); sysbus_realize(SYS_BUS_DEVICE(&s->mdio), &error_fatal); - memory_region_add_subregion(&s->mmio, A_MDIO_BASE, + memory_region_add_subregion(&s->container, A_MDIO_BASE, sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->mdio), 0)); for (unsigned i = 0; i < 2; i++) { memory_region_init_ram(&s->port[i].txbuf, OBJECT(dev), i ? "ethlite.tx[1]buf" : "ethlite.tx[0]buf", BUFSZ_MAX, &error_abort); - memory_region_add_subregion(&s->mmio, 0x0800 * i, &s->port[i].txbuf); + memory_region_add_subregion(&s->container, 0x0800 * i, &s->port[i].txbuf); memory_region_init_io(&s->port[i].txio, OBJECT(dev), ð_porttx_ops, s, i ? "ethlite.tx[1]io" : "ethlite.tx[0]io", 4 * TX_MAX); - memory_region_add_subregion(&s->mmio, i ? A_TX_BASE1 : A_TX_BASE0, + memory_region_add_subregion(&s->container, i ? A_TX_BASE1 : A_TX_BASE0, &s->port[i].txio); memory_region_init_ram(&s->port[i].rxbuf, OBJECT(dev), i ? "ethlite.rx[1]buf" : "ethlite.rx[0]buf", BUFSZ_MAX, &error_abort); - memory_region_add_subregion(&s->mmio, 0x1000 + 0x0800 * i, + memory_region_add_subregion(&s->container, 0x1000 + 0x0800 * i, &s->port[i].rxbuf); memory_region_init_io(&s->port[i].rxio, OBJECT(dev), ð_portrx_ops, s, i ? "ethlite.rx[1]io" : "ethlite.rx[0]io", 4 * RX_MAX); - memory_region_add_subregion(&s->mmio, i ? A_RX_BASE1 : A_RX_BASE0, + memory_region_add_subregion(&s->container, i ? A_RX_BASE1 : A_RX_BASE0, &s->port[i].rxio); } @@ -349,7 +349,7 @@ static void xilinx_ethlite_init(Object *obj) XlnxXpsEthLite *s = XILINX_ETHLITE(obj); sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); - sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->container); } static Property xilinx_ethlite_properties[] = { From patchwork Thu Nov 14 21:00:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 843203 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcc:0:b0:382:184f:390f with SMTP id e12csp505847wrc; Thu, 14 Nov 2024 13:04:43 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCUvMpH24b4GD82bNOwQsKCS/VXk7ww+iejQjgvQHiHWRth5y462bPbmX8yfAE/MOMFky2v3rg==@linaro.org X-Google-Smtp-Source: AGHT+IFWCh+s0qd/wYanYoOUih6wjQ1Kz8DeI8fP/dKaM9OXNaQfsCvkqA9UqGy+QGOlVFv2G8aq X-Received: by 2002:a05:6122:65aa:b0:50d:53ab:3d0c with SMTP id 71dfb90a1353d-5147853ff1cmr580128e0c.2.1731618282853; Thu, 14 Nov 2024 13:04:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1731618282; cv=none; d=google.com; s=arc-20240605; b=MFUcIaaTGFzfgDLW4NZ4pqCnHRu0WGnvkEBXgEmemDz2zXf88NkSX+NBQAiA6qE/Lg z4X5xOKv0m0Md9Nmp0jnbOzMs+l/nLn4W4tOtX4Op2viiY18YokjPN94xn37JS0HrPuT 0qsLl1zSpCiKsgR15N/glJ44It3bv2Mr1N2N7HOoTtdR65ZpXf6Sbw96NgiDtCMvHEzj 9y9CbkCxQCQ/XopzmLs9WWaIuwUOLQ83bZ5buAVEVGB2z67t19lTE1z71V81VI4KKUp+ DAMzqNfm3paQQPSLQPMwBjx5rXCd9rpwXIRNqzuLkLftiQnNJGuJQjk6IbnaJCPELeIP +qvw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Nb6BGc20Jrn3ivl3e3d8GrejdUgzYW7qbVEFEk+JhnM=; fh=5jk8UxAyCIlFm5FJTrcugn+mYgKxg5oCAlh/+aIwL9w=; b=jzXQfn1FDsDwCeDE1aGwK+etRPW9SmC3bl+BF3pDdXBEBcbnoRbAyyAtKhrvvcxGq8 7L+qeAR76pofaSUSk4tEcTO8DNYHmRR6/WCZP2Yx/+RHgCHmQOiBUqktULYp3ZpScZGb CbHM6W0DbPzTbP3mgVVD70t92L6CWKes+MtxS9DcR0UTi10Fjm5WIY44nTqYbMxEScmk YTvEdHikaQxrCJVnz4KObLS5S3+02pT57V82G95guMqJ+yQP0ILYz+ObXFYfLC7XdtgF pgRRn9egwfqU5hN3Bsr97VZGXDOn7PVaL0cgt894ZaQMVoRY6UWbvBWhOHZQDZZ1oUCu wPJQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=cVQVwNdC; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Iglesias" , qemu-arm@nongnu.org, Richard Henderson , Thomas Huth , Anton Johansson , Bernhard Beschow , Alistair Francis , Paolo Bonzini , Gustavo Romero , =?utf-8?q?Marc-Andr=C3=A9_Lurea?= =?utf-8?q?u?= , Peter Maydell , Jason Wang , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH RESEND v2 19/19] hw/net/xilinx_ethlite: Map RESERVED I/O as unimplemented Date: Thu, 14 Nov 2024 22:00:10 +0100 Message-ID: <20241114210010.34502-20-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241114210010.34502-1-philmd@linaro.org> References: <20241114210010.34502-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philmd@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In order to track access to reserved I/O space, use yet another UnimplementedDevice covering the whole device memory range. Mapped with lower priority (-1). The memory flat view becomes: (qemu) info mtree -f FlatView #0 Root memory region: system 0000000081000000-00000000810007e3 (prio 0, ram): ethlite.tx[0]buf 00000000810007e4-00000000810007f3 (prio 0, i/o): ethlite.mdio 00000000810007f4-00000000810007ff (prio 0, i/o): ethlite.tx[0]io 0000000081000800-0000000081000fe3 (prio 0, ram): ethlite.tx[1]buf 0000000081000fe4-0000000081000ff3 (prio -1, i/o): ethlite.reserved @0000000000000fe4 0000000081000ff4-0000000081000fff (prio 0, i/o): ethlite.tx[1]io 0000000081001000-00000000810017e3 (prio 0, ram): ethlite.rx[0]buf 00000000810017e4-00000000810017fb (prio -1, i/o): ethlite.reserved @00000000000017e4 00000000810017fc-00000000810017ff (prio 0, i/o): ethlite.rx[0]io 0000000081001800-0000000081001fe3 (prio 0, ram): ethlite.rx[1]buf 0000000081001fe4-0000000081001ffb (prio -1, i/o): ethlite.reserved @0000000000001fe4 0000000081001ffc-0000000081001fff (prio 0, i/o): ethlite.rx[1]io Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alex Bennée --- hw/net/xilinx_ethlite.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/hw/net/xilinx_ethlite.c b/hw/net/xilinx_ethlite.c index 5f1ff7b712..1be38c44dd 100644 --- a/hw/net/xilinx_ethlite.c +++ b/hw/net/xilinx_ethlite.c @@ -95,6 +95,7 @@ struct XlnxXpsEthLite uint32_t c_rx_pingpong; unsigned int port_index; /* dual port RAM index */ + UnimplementedDeviceState rsvd; UnimplementedDeviceState mdio; XlnxXpsEthLitePort port[2]; }; @@ -304,6 +305,16 @@ static void xilinx_ethlite_realize(DeviceState *dev, Error **errp) memory_region_init(&s->container, OBJECT(dev), "xlnx.xps-ethernetlite", 0x2000); + object_initialize_child(OBJECT(dev), "ethlite.reserved", &s->rsvd, + TYPE_UNIMPLEMENTED_DEVICE); + qdev_prop_set_string(DEVICE(&s->rsvd), "name", "ethlite.reserved"); + qdev_prop_set_uint64(DEVICE(&s->rsvd), "size", + memory_region_size(&s->container)); + sysbus_realize(SYS_BUS_DEVICE(&s->rsvd), &error_fatal); + memory_region_add_subregion_overlap(&s->container, 0, + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->rsvd), 0), + -1); + object_initialize_child(OBJECT(dev), "ethlite.mdio", &s->mdio, TYPE_UNIMPLEMENTED_DEVICE); qdev_prop_set_string(DEVICE(&s->mdio), "name", "ethlite.mdio");