From patchwork Mon Dec 9 14:08:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 181030 Delivered-To: patch@linaro.org Received: by 2002:a92:3001:0:0:0:0:0 with SMTP id x1csp4399115ile; Mon, 9 Dec 2019 06:12:06 -0800 (PST) X-Google-Smtp-Source: APXvYqxDyCTH8dD+ca3p5oKgENOApXMKoS7IsXgBAgfkzmRYHj4uXm0BkhoP4PmYhJf/XCHQQCj8 X-Received: by 2002:a9d:4c12:: with SMTP id l18mr21713848otf.140.1575900723973; Mon, 09 Dec 2019 06:12:03 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1575900723; cv=none; d=google.com; s=arc-20160816; b=bDoUqiw+mbRhNpOOFsTESCS4nPVMiCz9ABMOEHx0gExTJ7fnsdQ1rxkG45efIFyEhG zWix8CJFS2J/R2Tw3G8E/qE68Bqon9c6+6326njnUhnhBFynJABz1PArxrN4EovSazJS bHGhgkZ6/fmbzPYRuiMuM5Q/eROTCayoMrooS5nBJQKKtr6Gnf6uENg0yKT6dIPaCaVK pCGvauFuyfO1PjZo1CVFLRozZC/csgBXxgnWrYoAftug6GhNh2KxnGIuaGS46M9q1FM5 5x+faYUuy5zT0tjzgZg/53Rvs8QcoFrr0b02SdDeTOaDAr7BHEJ/0xjHsLFe387wjhTV yxYw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from; bh=xEbLeRMXnJIO3NswPIdYACcnzTAnteoUjh3bNAxlGUM=; b=ZczCWJLOeOWbbbNRtDc3LbcvRWwqAGVlGWO0zU1HOUcohWrwgFmZuFOPIPrpFj1baj //6sJT5InK2LoMN8cuHwudG76Lw+maMB+7Z6zyIWHJZPwnPOalN9gM6OSym1NW8FV9OD zlMhlNmcuPm43ZpnWwVwqLjSu7m4K2Q/2FGLHzb4NOzsIEbYiZJ1KPjpFMfW2oM/h+8b LyrSdyyqO/SIIBYtTv5aeqMxP4eUebVFnG53DQLAfqNSs2uim5ZJmT1q2XzEmDKU2Vvq I0DzxVamQQQiCp6CyJP1FBE8MUepdxe5j2dLDrpqFbHizGYbrOWMPrkmbVPLm8VCZ10V u2Sw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 14si12013794oie.181.2019.12.09.06.12.03; Mon, 09 Dec 2019 06:12:03 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727894AbfLIOMC (ORCPT + 27 others); Mon, 9 Dec 2019 09:12:02 -0500 Received: from szxga05-in.huawei.com ([45.249.212.191]:7198 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727572AbfLIOLy (ORCPT ); Mon, 9 Dec 2019 09:11:54 -0500 Received: from DGGEMS412-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id B5CB71F1F54802B1C6EE; Mon, 9 Dec 2019 22:11:49 +0800 (CST) Received: from localhost.localdomain (10.69.192.58) by DGGEMS412-HUB.china.huawei.com (10.3.19.212) with Microsoft SMTP Server id 14.3.439.0; Mon, 9 Dec 2019 22:11:41 +0800 From: John Garry To: , , CC: , , , , , , , John Garry Subject: [PATCH v2 1/3] mtd: spi-nor: hisi-sfc: Try to provide some clarity on which SFC we are Date: Mon, 9 Dec 2019 22:08:08 +0800 Message-ID: <1575900490-74467-2-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1575900490-74467-1-git-send-email-john.garry@huawei.com> References: <1575900490-74467-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.69.192.58] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The driver is for the HiSilicon FMC (Flash Memory Controller), which supports SPI NOR in addition other memory technologies, like SPI NAND. Indeed, the naming in the driver is a little inappropriate, especially considering that there is already another HiSilicon SPI NOR flash controller (which I believe the FMC is derived from). Since we now want to provide software support for this other HiSilicon controller, update code comments to at least try to make it clear that this driver is for the FMC. Signed-off-by: John Garry --- drivers/mtd/spi-nor/Kconfig | 4 ++-- drivers/mtd/spi-nor/hisi-sfc.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) -- 2.17.1 diff --git a/drivers/mtd/spi-nor/Kconfig b/drivers/mtd/spi-nor/Kconfig index f237fcdf7f86..c1eda67d1ad2 100644 --- a/drivers/mtd/spi-nor/Kconfig +++ b/drivers/mtd/spi-nor/Kconfig @@ -46,11 +46,11 @@ config SPI_CADENCE_QUADSPI Flash as an MTD device. config SPI_HISI_SFC - tristate "Hisilicon SPI-NOR Flash Controller(SFC)" + tristate "Hisilicon FMC SPI-NOR Flash Controller(SFC)" depends on ARCH_HISI || COMPILE_TEST depends on HAS_IOMEM help - This enables support for hisilicon SPI-NOR flash controller. + This enables support for HiSilicon FMC SPI-NOR flash controller. config SPI_MTK_QUADSPI tristate "MediaTek Quad SPI controller" diff --git a/drivers/mtd/spi-nor/hisi-sfc.c b/drivers/mtd/spi-nor/hisi-sfc.c index a1258216f89d..6db964bf3b0e 100644 --- a/drivers/mtd/spi-nor/hisi-sfc.c +++ b/drivers/mtd/spi-nor/hisi-sfc.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-or-later /* - * HiSilicon SPI Nor Flash Controller Driver + * HiSilicon FMC SPI-NOR flash controller driver * * Copyright (c) 2015-2016 HiSilicon Technologies Co., Ltd. */ From patchwork Mon Dec 9 14:08:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 181028 Delivered-To: patch@linaro.org Received: by 2002:a92:3001:0:0:0:0:0 with SMTP id x1csp4398877ile; Mon, 9 Dec 2019 06:11:57 -0800 (PST) X-Google-Smtp-Source: APXvYqwt4Bz5CTKGjeLSkntxFE1ntZ0Lee2P3UjQTpRqc5LSvY0cF6qpYcIXFWCZt5Len3NwxCIz X-Received: by 2002:a05:6830:22e3:: with SMTP id t3mr20714497otc.193.1575900717180; Mon, 09 Dec 2019 06:11:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1575900717; cv=none; d=google.com; s=arc-20160816; b=Mmd7lzTYgEo61rl/0BHzs22SgSOGLARs0W+D0cmvkDUzK4WYPJREkz2B9Hm5R9Xqct FgAi47LkiMlWyYBmLBKLzdjXFh5/oBl8heVxKjWvEyEw4vCBWYHnzEcDayoFDQ5jFRZ2 pr4OMRLCaXL9Eku7uT4PqIUDCOAmZXDBPc5R6xL/8q2tGO742ZUoKAc6zFnWFfEbOhlL Lhj9w0OYQmtdTJk0EwYGC9UzGnoRI/82dedhbRKeaX6/QAJeSNwgY1dqEcLxyYfqDtGZ ulQMFl/bHR2p5lGezCFhnBrXusZTUKHs2zZ1HiQGMENOcG7Y8ZhwtfxCR91Y+r/ie9JK kqtg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from; bh=slZxxK8D2gs/2U5C28iGDvxzRiK+iBfKe9DcHmkYwj0=; b=HeRJ7ji8YcTMD1DNYBiNWA/NQchMwa1+ot/284D4qo/ZXc/vM8kyR0n5Yp5FzaBgKD gF93ZZgYPDudsxNahHRr3uIeMg4Q0R+a1HVBBnvcmlJcmDFhAPMmKR11DCQgDXcBkUFy cQiGFLc5bWPWA0cqCGVUnNsbg3upmX2kpVek939uWhvHnQuXTc+bb4yfQ4Kg6op6TcDc TqO7AjGy2Kg/PCzHoEPtgtbjA2LGLwXye1b3qIP7EZfX1ZnMhQhzcxwktXmmfYWh3MDh Lwt1UBTtZA4A77Q8cSJ3AanbVT9b6bUB5VOOLMt/Mw/6I6Bt5Q4Sdat5BcedzmPyu77f mK9A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id v1si12618040otq.141.2019.12.09.06.11.56; Mon, 09 Dec 2019 06:11:57 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727859AbfLIOL4 (ORCPT + 27 others); Mon, 9 Dec 2019 09:11:56 -0500 Received: from szxga05-in.huawei.com ([45.249.212.191]:7199 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727643AbfLIOLx (ORCPT ); Mon, 9 Dec 2019 09:11:53 -0500 Received: from DGGEMS412-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id BB2D8E31A48C72F3A273; Mon, 9 Dec 2019 22:11:49 +0800 (CST) Received: from localhost.localdomain (10.69.192.58) by DGGEMS412-HUB.china.huawei.com (10.3.19.212) with Microsoft SMTP Server id 14.3.439.0; Mon, 9 Dec 2019 22:11:41 +0800 From: John Garry To: , , CC: , , , , , , , John Garry Subject: [PATCH v2 2/3] spi: Add HiSilicon v3xx SPI NOR flash controller driver Date: Mon, 9 Dec 2019 22:08:09 +0800 Message-ID: <1575900490-74467-3-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1575900490-74467-1-git-send-email-john.garry@huawei.com> References: <1575900490-74467-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.69.192.58] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add the driver for the HiSilicon v3xx SPI NOR flash controller, commonly found in hi16xx chipsets. This is a different controller than that in drivers/mtd/spi-nor/hisi-sfc.c; indeed, the naming for that driver is poor, since it is really known as FMC, and can support other memory technologies. The driver module name is "hisi-sfc-v3xx", as recommended by HW designer, being an attempt to provide a distinct name - v3xx being the unique controller versioning. Only ACPI firmware is supported. DMA is not supported, and we just use polling mode for operation completion notification. The driver uses the SPI MEM OPs. Signed-off-by: John Garry --- drivers/spi/Kconfig | 9 + drivers/spi/Makefile | 1 + drivers/spi/spi-hisi-sfc-v3xx.c | 284 ++++++++++++++++++++++++++++++++ 3 files changed, 294 insertions(+) create mode 100644 drivers/spi/spi-hisi-sfc-v3xx.c -- 2.17.1 diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 870f7797b56b..d6ed0c355954 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -281,6 +281,15 @@ config SPI_FSL_QUADSPI This controller does not support generic SPI messages. It only supports the high-level SPI memory interface. +config SPI_HISI_SFC_V3XX + tristate "HiSilicon SPI-NOR Flash Controller for Hi16XX chipsets" + depends on (ARM64 && ACPI) || COMPILE_TEST + depends on HAS_IOMEM + select CONFIG_MTD_SPI_NOR + help + This enables support for HiSilicon v3xx SPI-NOR flash controller + found in hi16xx chipsets. + config SPI_NXP_FLEXSPI tristate "NXP Flex SPI controller" depends on ARCH_LAYERSCAPE || HAS_IOMEM diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index bb49c9e6d0a0..9b65ec5afc5e 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -48,6 +48,7 @@ obj-$(CONFIG_SPI_FSL_LPSPI) += spi-fsl-lpspi.o obj-$(CONFIG_SPI_FSL_QUADSPI) += spi-fsl-qspi.o obj-$(CONFIG_SPI_FSL_SPI) += spi-fsl-spi.o obj-$(CONFIG_SPI_GPIO) += spi-gpio.o +obj-$(CONFIG_SPI_HISI_SFC_V3XX) += spi-hisi-sfc-v3xx.o obj-$(CONFIG_SPI_IMG_SPFI) += spi-img-spfi.o obj-$(CONFIG_SPI_IMX) += spi-imx.o obj-$(CONFIG_SPI_LANTIQ_SSC) += spi-lantiq-ssc.o diff --git a/drivers/spi/spi-hisi-sfc-v3xx.c b/drivers/spi/spi-hisi-sfc-v3xx.c new file mode 100644 index 000000000000..4cf8fc80a7b7 --- /dev/null +++ b/drivers/spi/spi-hisi-sfc-v3xx.c @@ -0,0 +1,284 @@ +// SPDX-License-Identifier: GPL-2.0-only +// +// HiSilicon SPI NOR V3XX Flash Controller Driver for hi16xx chipsets +// +// Copyright (c) 2019 HiSilicon Technologies Co., Ltd. +// Author: John Garry + +#include +#include +#include +#include +#include +#include +#include +#include + +#define HISI_SFC_V3XX_VERSION (0x1f8) + +#define HISI_SFC_V3XX_CMD_CFG (0x300) +#define HISI_SFC_V3XX_CMD_CFG_DATA_CNT_OFF 9 +#define HISI_SFC_V3XX_CMD_CFG_RW_MSK BIT(8) +#define HISI_SFC_V3XX_CMD_CFG_DATA_EN_MSK BIT(7) +#define HISI_SFC_V3XX_CMD_CFG_DUMMY_CNT_OFF 4 +#define HISI_SFC_V3XX_CMD_CFG_ADDR_EN_MSK BIT(3) +#define HISI_SFC_V3XX_CMD_CFG_CS_SEL_OFF 1 +#define HISI_SFC_V3XX_CMD_CFG_START_MSK BIT(0) +#define HISI_SFC_V3XX_CMD_INS (0x308) +#define HISI_SFC_V3XX_CMD_ADDR (0x30c) +#define HISI_SFC_V3XX_CMD_DATABUF0 (0x400) + +struct hisi_sfc_v3xx_host { + struct device *dev; + void __iomem *regbase; + int max_cmd_dword; +}; + +#define HISI_SFC_V3XX_WAIT_TIMEOUT_US 1000000 +#define HISI_SFC_V3XX_WAIT_POLL_INTERVAL_US 10 + +static int hisi_sfc_v3xx_wait_cmd_idle(struct hisi_sfc_v3xx_host *host) +{ + u32 reg; + + return readl_poll_timeout(host->regbase + HISI_SFC_V3XX_CMD_CFG, reg, + !(reg & HISI_SFC_V3XX_CMD_CFG_START_MSK), + HISI_SFC_V3XX_WAIT_POLL_INTERVAL_US, + HISI_SFC_V3XX_WAIT_TIMEOUT_US); +} + +static int hisi_sfc_v3xx_adjust_op_size(struct spi_mem *mem, + struct spi_mem_op *op) +{ + struct spi_device *spi = mem->spi; + struct hisi_sfc_v3xx_host *host; + uintptr_t addr = (uintptr_t)op->data.buf.in; + int max_byte_count; + + host = spi_controller_get_devdata(spi->master); + + max_byte_count = host->max_cmd_dword * 4; + + if (!IS_ALIGNED(addr, 4) && op->data.nbytes >= 4) + op->data.nbytes = 4 - (addr % 4); + else if (op->data.nbytes > max_byte_count) + op->data.nbytes = max_byte_count; + + return 0; +} + +/* + * memcpy_{to,from}io doesn't gurantee 32b accesses - which we require for the + * DATABUF registers -so use __io{read,write}32_copy when possible. For + * trailing bytes, copy them byte-by-byte from the DATABUF register, as we + * can't clobber outside the source/dest buffer. + * + * For efficient data read/write, we try to put any start 32b unaligned data + * into a separate transaction in hisi_sfc_v3xx_adjust_op_size(). + */ +static void hisi_sfc_v3xx_read_databuf(struct hisi_sfc_v3xx_host *host, + u8 *to, unsigned int len) +{ + void __iomem *from; + int i; + + from = host->regbase + HISI_SFC_V3XX_CMD_DATABUF0; + + if (IS_ALIGNED((uintptr_t)to, 4)) { + int words = len / 4; + + __ioread32_copy(to, from, words); + + len -= words * 4; + if (len) { + u32 val; + + to += words * 4; + from += words * 4; + + val = __raw_readl(from); + + for (i = 0; i < len; i++, val >>= 8, to++) + *to = (u8)val; + } + } else { + for (i = 0; i < DIV_ROUND_UP(len, 4); i++, from += 4) { + u32 val = __raw_readl(from); + int j; + + for (j = 0; j < 4 && (j + (i * 4) < len); + to++, val >>= 8, j++) + *to = (u8)val; + } + } +} + +static void hisi_sfc_v3xx_write_databuf(struct hisi_sfc_v3xx_host *host, + const u8 *from, unsigned int len) +{ + void __iomem *to; + int i; + + to = host->regbase + HISI_SFC_V3XX_CMD_DATABUF0; + + if (IS_ALIGNED((uintptr_t)from, 4)) { + int words = len / 4; + + __iowrite32_copy(to, from, words); + + len -= words * 4; + if (len) { + u32 val = 0; + + to += words * 4; + from += words * 4; + + for (i = 0; i < len; i++, from++) + val |= *from << i * 8; + __raw_writel(val, to); + } + + } else { + for (i = 0; i < DIV_ROUND_UP(len, 4); i++, to += 4) { + u32 val = 0; + int j; + + for (j = 0; j < 4 && (j + (i * 4) < len); + from++, j++) + val |= *from << j * 8; + __raw_writel(val, to); + } + } +} + +static int hisi_sfc_v3xx_generic_exec_op(struct hisi_sfc_v3xx_host *host, + const struct spi_mem_op *op, + u8 chip_select) +{ + int ret, len = op->data.nbytes; + u32 config = 0; + + if (op->addr.nbytes) + config |= HISI_SFC_V3XX_CMD_CFG_ADDR_EN_MSK; + + if (op->data.dir != SPI_MEM_NO_DATA) { + config |= (len - 1) << HISI_SFC_V3XX_CMD_CFG_DATA_CNT_OFF; + config |= HISI_SFC_V3XX_CMD_CFG_DATA_EN_MSK; + } + + if (op->data.dir == SPI_MEM_DATA_OUT) + hisi_sfc_v3xx_write_databuf(host, op->data.buf.out, len); + else if (op->data.dir == SPI_MEM_DATA_IN) + config |= HISI_SFC_V3XX_CMD_CFG_RW_MSK; + + config |= op->dummy.nbytes << HISI_SFC_V3XX_CMD_CFG_DUMMY_CNT_OFF | + chip_select << HISI_SFC_V3XX_CMD_CFG_CS_SEL_OFF | + HISI_SFC_V3XX_CMD_CFG_START_MSK; + + writel(op->addr.val, host->regbase + HISI_SFC_V3XX_CMD_ADDR); + writel(op->cmd.opcode, host->regbase + HISI_SFC_V3XX_CMD_INS); + + writel(config, host->regbase + HISI_SFC_V3XX_CMD_CFG); + + ret = hisi_sfc_v3xx_wait_cmd_idle(host); + if (ret) + return ret; + + if (op->data.dir == SPI_MEM_DATA_IN) + hisi_sfc_v3xx_read_databuf(host, op->data.buf.in, len); + + return 0; +} + +static int hisi_sfc_v3xx_exec_op(struct spi_mem *mem, + const struct spi_mem_op *op) +{ + struct hisi_sfc_v3xx_host *host; + struct spi_device *spi = mem->spi; + u8 chip_select = spi->chip_select; + + host = spi_controller_get_devdata(spi->master); + + return hisi_sfc_v3xx_generic_exec_op(host, op, chip_select); +} + +static const struct spi_controller_mem_ops hisi_sfc_v3xx_mem_ops = { + .adjust_op_size = hisi_sfc_v3xx_adjust_op_size, + .exec_op = hisi_sfc_v3xx_exec_op, +}; + +static int hisi_sfc_v3xx_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct hisi_sfc_v3xx_host *host; + struct spi_controller *ctlr; + u32 version; + int ret; + + ctlr = spi_alloc_master(&pdev->dev, sizeof(*host)); + if (!ctlr) + return -ENOMEM; + + ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | + SPI_TX_DUAL | SPI_TX_QUAD; + + host = spi_controller_get_devdata(ctlr); + host->dev = dev; + + platform_set_drvdata(pdev, host); + + host->regbase = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(host->regbase)) { + ret = PTR_ERR(host->regbase); + goto err_put_master; + } + + ctlr->bus_num = -1; + ctlr->num_chipselect = 1; + ctlr->mem_ops = &hisi_sfc_v3xx_mem_ops; + + version = readl(host->regbase + HISI_SFC_V3XX_VERSION); + + switch (version) { + case 0x351: + host->max_cmd_dword = 64; + break; + default: + host->max_cmd_dword = 16; + break; + } + + ret = devm_spi_register_controller(dev, ctlr); + if (ret) + goto err_put_master; + + dev_info(&pdev->dev, "hw version 0x%x\n", version); + + return 0; + +err_put_master: + spi_master_put(ctlr); + return ret; +} + +#if IS_ENABLED(CONFIG_ACPI) +static const struct acpi_device_id hisi_sfc_v3xx_acpi_ids[] = { + {"HISI0341", 0}, + {} +}; +MODULE_DEVICE_TABLE(acpi, hisi_sfc_v3xx_acpi_ids); +#endif + +static struct platform_driver hisi_sfc_v3xx_spi_driver = { + .driver = { + .name = "hisi-sfc-v3xx", + .acpi_match_table = ACPI_PTR(hisi_sfc_v3xx_acpi_ids), + }, + .probe = hisi_sfc_v3xx_probe, +}; + +module_platform_driver(hisi_sfc_v3xx_spi_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("John Garry "); +MODULE_DESCRIPTION("HiSilicon SPI NOR V3XX Flash Controller Driver for hi16xx chipsets"); From patchwork Mon Dec 9 14:08:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 181029 Delivered-To: patch@linaro.org Received: by 2002:a92:3001:0:0:0:0:0 with SMTP id x1csp4399007ile; Mon, 9 Dec 2019 06:12:02 -0800 (PST) X-Google-Smtp-Source: APXvYqzXdUL8QYkNUWyUL8OUYP8V09tMmHQbTfIKDDVtlq8DpV/2ZhFln2RTEbQa58fSwFmT9MPV X-Received: by 2002:a05:6808:2d8:: with SMTP id a24mr9091891oid.88.1575900721966; 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[209.132.180.67]) by mx.google.com with ESMTP id 14si12013794oie.181.2019.12.09.06.12.01; Mon, 09 Dec 2019 06:12:01 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727496AbfLIOMA (ORCPT + 27 others); Mon, 9 Dec 2019 09:12:00 -0500 Received: from szxga05-in.huawei.com ([45.249.212.191]:7201 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727388AbfLIOLy (ORCPT ); Mon, 9 Dec 2019 09:11:54 -0500 Received: from DGGEMS412-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id C681C7ADE8329B6A8CE4; Mon, 9 Dec 2019 22:11:49 +0800 (CST) Received: from localhost.localdomain (10.69.192.58) by DGGEMS412-HUB.china.huawei.com (10.3.19.212) with Microsoft SMTP Server id 14.3.439.0; Mon, 9 Dec 2019 22:11:42 +0800 From: John Garry To: , , CC: , , , , , , , John Garry Subject: [PATCH v2 3/3] MAINTAINERS: Add a maintainer for the HiSilicon v3xx SFC driver Date: Mon, 9 Dec 2019 22:08:10 +0800 Message-ID: <1575900490-74467-4-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1575900490-74467-1-git-send-email-john.garry@huawei.com> References: <1575900490-74467-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.69.192.58] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Set John Garry @ Huawei as the maintainer. Signed-off-by: John Garry --- MAINTAINERS | 6 ++++++ 1 file changed, 6 insertions(+) -- 2.17.1 diff --git a/MAINTAINERS b/MAINTAINERS index bd5847e802de..8c119bd4f687 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -7492,6 +7492,12 @@ S: Supported F: drivers/scsi/hisi_sas/ F: Documentation/devicetree/bindings/scsi/hisilicon-sas.txt +HISILICON V3XX SPI NOR FLASH Controller Driver +M: John Garry +W: http://www.hisilicon.com +S: Maintained +F: drivers/spi/spi-hisi-sfc-v3xx.c + HISILICON QM AND ZIP Controller DRIVER M: Zhou Wang L: linux-crypto@vger.kernel.org