From patchwork Mon Dec 9 09:21:37 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 180992 Delivered-To: patch@linaro.org Received: by 2002:a92:3001:0:0:0:0:0 with SMTP id x1csp4097809ile; Mon, 9 Dec 2019 01:21:03 -0800 (PST) X-Google-Smtp-Source: APXvYqxtiHEgqGGTZl0fF7ufPcyfAPDuIspaqZ8OYEVX5/nvQkd6p0ROPOdKCp15P22CmaGM8gt/ X-Received: by 2002:aca:5785:: with SMTP id l127mr22564044oib.168.1575883263560; Mon, 09 Dec 2019 01:21:03 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1575883263; cv=none; d=google.com; s=arc-20160816; b=VvwOK3+cYmmAxZTJJUEfjylMK45aFEU1nhP3t8M4Rm8oCK876diF7XDZHy1+91/vy4 2T5p19NfU+QAyXNYe3vczvkHuK1Fzt+EJRiD1cvEdwcN7qGeIpFLQaONOFLp4vDZc12s tBAXZ3MUHE1PLie9Fv70x8PfgMMScSwtHUI5U4vCzliUO4pR4ZsPaPxFurdiZQrbHbdb P/bFu3uw6icfIf4eDIsmNdwta6CG1PPBOvtIGOr8heGapG5cn1299KyPlyIxasmPTvfk NhKn/zJjJy9iuWbqbVTvHRixbP1qJ639K1lt52KowprgKQqtLygrtAoOfFWpJP2ppKC/ rl1A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=56IRQZ6d0HNeeygqitauo27pEYK2FxxPjAg9EHDISc4=; b=Ff6/cLJDiiA6GdgOJ1rPbcnuycVdtS7P5U67gbQP0QTJxBr5c/a3Qb4G34seY9OHUf SPLxnMefS5y3ydsFvdwGJmprPAfofbbl8Uc+90j1+rTGXDHRRUGP9dva53OgZTn8h/H3 a1H7IItTONjMIhAGHrBayX6vE1d+l3rBrhp2SPdN1NKNmSYJCjW2NYbx3o1wkiGOLWze R/9qIADvFu0Q9nMy/1OHPN/aMf3GSBQW2zHteF08uzTNoctpPx6G/IwYTVTY4vbo+gJ1 vyUzLQ0FzmTvo0380E4S12NG3Ib9W42hiyloAzidUp7x+kKVCB7oOb9GxscH6wjEwbMC 1kwA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="p/b8yFb5"; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id l26si11922379oti.152.2019.12.09.01.21.03; Mon, 09 Dec 2019 01:21:03 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="p/b8yFb5"; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727573AbfLIJVB (ORCPT + 8 others); Mon, 9 Dec 2019 04:21:01 -0500 Received: from fllv0015.ext.ti.com ([198.47.19.141]:54396 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727565AbfLIJVB (ORCPT ); Mon, 9 Dec 2019 04:21:01 -0500 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id xB99KqHh100845; Mon, 9 Dec 2019 03:20:52 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1575883252; bh=56IRQZ6d0HNeeygqitauo27pEYK2FxxPjAg9EHDISc4=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=p/b8yFb5ni6WQ+9TItu9Nc1t1cFNlLFGunswdWZvQzaKbIdzdD3hSOI2SBXzUlDlX gEDmViCotjtX1awimeDHlJ+zEAD0T4Sm1E+02YbrfvWmvF4wqO5MTkI2+30pHqSpsV Bm1TNTbt//17B3uTtQP+4WZECdicQvskyufBwKkM= Received: from DLEE104.ent.ti.com (dlee104.ent.ti.com [157.170.170.34]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id xB99KqEd063246 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 9 Dec 2019 03:20:52 -0600 Received: from DLEE113.ent.ti.com (157.170.170.24) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Mon, 9 Dec 2019 03:20:52 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Mon, 9 Dec 2019 03:20:52 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id xB99Kcd1087697; Mon, 9 Dec 2019 03:20:49 -0600 From: Kishon Vijay Abraham I To: Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , Arnd Bergmann , Andrew Murray CC: , , , , Kishon Vijay Abraham I Subject: [PATCH 03/13] PCI: cadence: Add support to use custom read and write accessors Date: Mon, 9 Dec 2019 14:51:37 +0530 Message-ID: <20191209092147.22901-4-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191209092147.22901-1-kishon@ti.com> References: <20191209092147.22901-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add support to use custom read and write accessors. Platforms that doesn't support half word or byte access or any other constraint while accessing registers can use this feature to populate custom read and write accessors. These custom accessors are used for both standard register access and configuration space register access. This is in preparation for adding PCIe support in TI's J721E SoC which uses Cadence PCIe core. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/cadence/pcie-cadence.h | 99 +++++++++++++++++-- 1 file changed, 90 insertions(+), 9 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h index a2b28b912ca4..d0d91c69fa1d 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.h +++ b/drivers/pci/controller/cadence/pcie-cadence.h @@ -223,6 +223,11 @@ enum cdns_pcie_msg_routing { MSG_ROUTING_GATHER, }; +struct cdns_pcie_ops { + u32 (*read)(void __iomem *addr, int size); + void (*write)(void __iomem *addr, int size, u32 value); +}; + /** * struct cdns_pcie - private data for Cadence PCIe controller drivers * @reg_base: IO mapped register base @@ -239,7 +244,7 @@ struct cdns_pcie { int phy_count; struct phy **phy; struct device_link **link; - const struct cdns_pcie_common_ops *ops; + const struct cdns_pcie_ops *ops; }; /** @@ -301,21 +306,47 @@ struct cdns_pcie_ep { /* Register access */ static inline void cdns_pcie_writeb(struct cdns_pcie *pcie, u32 reg, u8 value) { + void __iomem *addr = pcie->reg_base + reg; + + if (pcie->ops && pcie->ops->write) { + pcie->ops->write(addr, 0x1, value); + return; + } + writeb(value, pcie->reg_base + reg); } static inline void cdns_pcie_writew(struct cdns_pcie *pcie, u32 reg, u16 value) { + void __iomem *addr = pcie->reg_base + reg; + + if (pcie->ops && pcie->ops->write) { + pcie->ops->write(addr, 0x2, value); + return; + } + writew(value, pcie->reg_base + reg); } static inline void cdns_pcie_writel(struct cdns_pcie *pcie, u32 reg, u32 value) { + void __iomem *addr = pcie->reg_base + reg; + + if (pcie->ops && pcie->ops->write) { + pcie->ops->write(addr, 0x4, value); + return; + } + writel(value, pcie->reg_base + reg); } static inline u32 cdns_pcie_readl(struct cdns_pcie *pcie, u32 reg) { + void __iomem *addr = pcie->reg_base + reg; + + if (pcie->ops && pcie->ops->read) + return pcie->ops->read(addr, 0x4); + return readl(pcie->reg_base + reg); } @@ -323,47 +354,97 @@ static inline u32 cdns_pcie_readl(struct cdns_pcie *pcie, u32 reg) static inline void cdns_pcie_rp_writeb(struct cdns_pcie *pcie, u32 reg, u8 value) { - writeb(value, pcie->reg_base + CDNS_PCIE_RP_BASE + reg); + void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg; + + if (pcie->ops && pcie->ops->write) { + pcie->ops->write(addr, 0x1, value); + return; + } + + writeb(value, addr); } static inline void cdns_pcie_rp_writew(struct cdns_pcie *pcie, u32 reg, u16 value) { - writew(value, pcie->reg_base + CDNS_PCIE_RP_BASE + reg); + void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg; + + if (pcie->ops && pcie->ops->write) { + pcie->ops->write(addr, 0x2, value); + return; + } + + writew(value, addr); } /* Endpoint Function register access */ static inline void cdns_pcie_ep_fn_writeb(struct cdns_pcie *pcie, u8 fn, u32 reg, u8 value) { - writeb(value, pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg); + void __iomem *addr = pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg; + + if (pcie->ops && pcie->ops->write) { + pcie->ops->write(addr, 0x1, value); + return; + } + + writeb(value, addr); } static inline void cdns_pcie_ep_fn_writew(struct cdns_pcie *pcie, u8 fn, u32 reg, u16 value) { - writew(value, pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg); + void __iomem *addr = pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg; + + if (pcie->ops && pcie->ops->write) { + pcie->ops->write(addr, 0x2, value); + return; + } + + writew(value, addr); } static inline void cdns_pcie_ep_fn_writel(struct cdns_pcie *pcie, u8 fn, u32 reg, u32 value) { - writel(value, pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg); + void __iomem *addr = pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg; + + if (pcie->ops && pcie->ops->write) { + pcie->ops->write(addr, 0x4, value); + return; + } + + writel(value, addr); } static inline u8 cdns_pcie_ep_fn_readb(struct cdns_pcie *pcie, u8 fn, u32 reg) { - return readb(pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg); + void __iomem *addr = pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg; + + if (pcie->ops && pcie->ops->read) + return pcie->ops->read(addr, 0x1); + + return readb(addr); } static inline u16 cdns_pcie_ep_fn_readw(struct cdns_pcie *pcie, u8 fn, u32 reg) { - return readw(pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg); + void __iomem *addr = pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg; + + if (pcie->ops && pcie->ops->read) + return pcie->ops->read(addr, 0x2); + + return readw(addr); } static inline u32 cdns_pcie_ep_fn_readl(struct cdns_pcie *pcie, u8 fn, u32 reg) { - return readl(pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg); + void __iomem *addr = pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg; + + if (pcie->ops && pcie->ops->read) + return pcie->ops->read(addr, 0x4); + + return readl(addr); } #ifdef CONFIG_PCIE_CADENCE_HOST From patchwork Mon Dec 9 09:21:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 180995 Delivered-To: patch@linaro.org Received: by 2002:a92:3001:0:0:0:0:0 with SMTP id x1csp4097962ile; Mon, 9 Dec 2019 01:21:12 -0800 (PST) X-Google-Smtp-Source: APXvYqwkG49ZaUdXqYuv/VUEHlxlUnPzUk1r3SOlyD8REd40uoK1WdWMP/KfFwzgoktgAosD8Y9L X-Received: by 2002:aca:5a45:: with SMTP id o66mr23890836oib.114.1575883272588; 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[209.132.180.67]) by mx.google.com with ESMTP id n23si11847075otf.265.2019.12.09.01.21.12; Mon, 09 Dec 2019 01:21:12 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=GVZ2NItQ; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727625AbfLIJVL (ORCPT + 8 others); Mon, 9 Dec 2019 04:21:11 -0500 Received: from lelv0142.ext.ti.com ([198.47.23.249]:59902 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727619AbfLIJVK (ORCPT ); Mon, 9 Dec 2019 04:21:10 -0500 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id xB99L3NC046038; Mon, 9 Dec 2019 03:21:03 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1575883263; bh=f4oXcQEVxFFKqAFQ41+Ixwr9LBwG0bHt8f5qwBY+dkI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=GVZ2NItQK/iNov5YRB2xmesxldtYQDIUEG0D09p3eDs/8gqwkHUBxrZFzkSog+oth wwcXafHTl1wpJjLE8g/bCMS0O8ob/UJpBkQULG4voHAKTClZdHlN2Bvp8RMmIoI674 6SGPukoDkujgh4rTS2ZyvMq9i9WWhBNorP22Ch18= Received: from DLEE105.ent.ti.com (dlee105.ent.ti.com [157.170.170.35]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTP id xB99L2au127280; Mon, 9 Dec 2019 03:21:03 -0600 Received: from DLEE110.ent.ti.com (157.170.170.21) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Mon, 9 Dec 2019 03:21:02 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Mon, 9 Dec 2019 03:21:02 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id xB99Kcd4087697; Mon, 9 Dec 2019 03:20:59 -0600 From: Kishon Vijay Abraham I To: Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , Arnd Bergmann , Andrew Murray CC: , , , , Kishon Vijay Abraham I Subject: [PATCH 06/13] PCI: cadence: Allow pci_host_bridge to have custom pci_ops Date: Mon, 9 Dec 2019 14:51:40 +0530 Message-ID: <20191209092147.22901-7-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191209092147.22901-1-kishon@ti.com> References: <20191209092147.22901-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Certain platforms like TI's J721E allows only 32-bit configuration space access. In such cases pci_generic_config_read and pci_generic_config_write cannot be used. Add support in Cadence core to let pci_host_bridge have custom pci_ops. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/cadence/pcie-cadence-host.c | 7 ++++--- drivers/pci/controller/cadence/pcie-cadence.h | 8 ++++++++ 2 files changed, 12 insertions(+), 3 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c index 0929554f5a81..2efc33b1cade 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-host.c +++ b/drivers/pci/controller/cadence/pcie-cadence-host.c @@ -12,8 +12,8 @@ #include "pcie-cadence.h" -static void __iomem *cdns_pci_map_bus(struct pci_bus *bus, unsigned int devfn, - int where) +void __iomem *cdns_pci_map_bus(struct pci_bus *bus, unsigned int devfn, + int where) { struct pci_host_bridge *bridge = pci_find_host_bridge(bus); struct cdns_pcie_rc *rc = pci_host_bridge_priv(bridge); @@ -289,7 +289,8 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc) list_splice_init(&resources, &bridge->windows); bridge->dev.parent = dev; bridge->busnr = pcie->bus; - bridge->ops = &cdns_pcie_host_ops; + if (!bridge->ops) + bridge->ops = &cdns_pcie_host_ops; bridge->map_irq = of_irq_parse_and_map_pci; bridge->swizzle_irq = pci_common_swizzle; diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h index 5171d0da37da..c879dd3d2893 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.h +++ b/drivers/pci/controller/cadence/pcie-cadence.h @@ -472,11 +472,19 @@ static inline bool cdns_pcie_is_link_up(struct cdns_pcie *pcie) #ifdef CONFIG_PCIE_CADENCE_HOST int cdns_pcie_host_setup(struct cdns_pcie_rc *rc); +void __iomem *cdns_pci_map_bus(struct pci_bus *bus, unsigned int devfn, + int where); #else static inline int cdns_pcie_host_setup(struct cdns_pcie_rc *rc) { return 0; } + +static inline void __iomem *cdns_pci_map_bus(struct pci_bus *bus, + unsigned int devfn, + int where) +{ +} #endif #ifdef CONFIG_PCIE_CADENCE_EP