From patchwork Mon Dec 9 09:21:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 180990 Delivered-To: patch@linaro.org Received: by 2002:a92:3001:0:0:0:0:0 with SMTP id x1csp4097714ile; Mon, 9 Dec 2019 01:20:56 -0800 (PST) X-Google-Smtp-Source: APXvYqxeLsHMlz3RHG2eRWOpQxsgAENhA4jlMsW61cNIZJ5JehZFQiXDStdd4BWQXiv9AuiELKFw X-Received: by 2002:a9d:7f12:: with SMTP id j18mr21533185otq.17.1575883256396; Mon, 09 Dec 2019 01:20:56 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1575883256; cv=none; d=google.com; s=arc-20160816; b=xWEI9LdAZAHgHpDpl31kpXxR5Yqg/Hinx+6Ni190ntBl2/Ln3YVGbTM+9CZHZjiIV5 bmOVKkTYPMRzzVwwt4tYx2tGwW2bZNC+7yR3olk5APAXka/OLYawNm+45P6YEueINGPl 1IwD4oIbqt4GkIhDOJQ8Tetau11NFdA3uIiHif0StxTv9OsQzp7Z82flrRCJ+7I7avp0 nlAH3km5vlpukZjJtTTNdB9nCmwyGI1qSewTHas2HgC60TLQWeDtRzWgxgLncsIfg4yd Wyq95K+18JHIRdPiTB2YUaH34rdwNcDcadUF4a5WyVnHkLJl1R8hfe3abzpjbdSY7RyX k5Fg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=62DDuOo04TbPHTLK9JrEpoRquiITZMIbCCFCFJ1RQQY=; b=O8QHa/UFvtISOD7mVkIcS8P/I9HqJBsS56bjTIxDMuokASYVr5Mc1ql5U9lqEvcVV/ XXJ9mpA6rFKCLMkFJA0oxzfIQGyWsGpHk9SANVMK8+k/4g/BeCTiuOOs0tSAuG7Lo0zk Hn+Q3Rny3SSHWgaM67n+9bKeoDRTSPZbcHCHKvc9GJGKOjoGzK0IIWB5oWqHUs4451Pv x0FSSfseJE719Pd2J2UYPzET29NDOsiFAe2xqlzDu7M+0BVvNHlu59BgIjzvy/Zn6Th2 VjUOSqBbvx4J6ovMdIg/HSYjAjennpw33v2nC8RHx2PjgeRRyAOS0ll8B/Vn+tx6PR7K GwwQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=oGNJxuWx; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id p14si12178607ota.71.2019.12.09.01.20.56; Mon, 09 Dec 2019 01:20:56 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=oGNJxuWx; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727547AbfLIJUz (ORCPT + 4 others); Mon, 9 Dec 2019 04:20:55 -0500 Received: from lelv0143.ext.ti.com ([198.47.23.248]:49456 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726377AbfLIJUz (ORCPT ); Mon, 9 Dec 2019 04:20:55 -0500 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id xB99Kjdq025907; Mon, 9 Dec 2019 03:20:45 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1575883245; bh=62DDuOo04TbPHTLK9JrEpoRquiITZMIbCCFCFJ1RQQY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=oGNJxuWxlJcrpHirekmw8baxM8dsTpm6PIFpTWEjjXFR264jSha0vgPsUBB2J1QVi ZTKnY8N6Dm+SEUPVAdYdLNQy8+ffHCnndTI+0J4xOUb8pDx+tV3zU5izjD1Dt97xqH kAfEWj3Z89HI8y3ng21NM4XfZ0RAzweFn2QRRpXQ= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id xB99KjoV062979 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 9 Dec 2019 03:20:45 -0600 Received: from DFLE111.ent.ti.com (10.64.6.32) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Mon, 9 Dec 2019 03:20:45 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Mon, 9 Dec 2019 03:20:45 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id xB99Kccx087697; Mon, 9 Dec 2019 03:20:42 -0600 From: Kishon Vijay Abraham I To: Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , Arnd Bergmann , Andrew Murray CC: , , , , Kishon Vijay Abraham I Subject: [PATCH 01/13] PCI: cadence: Remove stray "pm_runtime_put_sync()" in error path Date: Mon, 9 Dec 2019 14:51:35 +0530 Message-ID: <20191209092147.22901-2-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191209092147.22901-1-kishon@ti.com> References: <20191209092147.22901-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org commit bd22885aa188f135fd9 ("PCI: cadence: Refactor driver to use as a core library") while refactoring the Cadence PCIe driver to be used as library, removed pm_runtime_get_sync() from cdns_pcie_ep_setup() and cdns_pcie_host_setup() but missed to remove the corresponding pm_runtime_put_sync() in the error path. Fix it here. Fixes: commit bd22885aa188f135fd9 ("PCI: cadence: Refactor driver to use as a core library") Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/cadence/pcie-cadence-ep.c | 2 -- drivers/pci/controller/cadence/pcie-cadence-host.c | 2 -- 2 files changed, 4 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/cadence/pcie-cadence-ep.c b/drivers/pci/controller/cadence/pcie-cadence-ep.c index 1c173dad67d1..560f22b4d165 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-ep.c +++ b/drivers/pci/controller/cadence/pcie-cadence-ep.c @@ -473,7 +473,5 @@ int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep) pci_epc_mem_exit(epc); err_init: - pm_runtime_put_sync(dev); - return ret; } diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c index 9b1c3966414b..ccf55e143e1d 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-host.c +++ b/drivers/pci/controller/cadence/pcie-cadence-host.c @@ -275,7 +275,5 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc) pci_free_resource_list(&resources); err_init: - pm_runtime_put_sync(dev); - return ret; } From patchwork Mon Dec 9 09:21:36 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 180991 Delivered-To: patch@linaro.org Received: by 2002:a92:3001:0:0:0:0:0 with SMTP id x1csp4097762ile; Mon, 9 Dec 2019 01:21:00 -0800 (PST) X-Google-Smtp-Source: APXvYqzzQ0hR2gMuXl7KNC1b5frlIUe2+/6gY5p5zIq3oR4phCh1DaOuU+qvcviKWoyzI04yb3xP X-Received: by 2002:aca:120e:: with SMTP id 14mr21971224ois.135.1575883260218; Mon, 09 Dec 2019 01:21:00 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1575883260; cv=none; d=google.com; s=arc-20160816; b=kZpOncZVxBhHxhbOM0ghqwiB8jbe0I4jjoOdthqGt67v4FgNjLDqb1ZVMRP5JnpSIY v/mZYXPgkcuyouKtUN5rad1lXhRY+EGRhte4vH44xDSH+5GQAxBn+0GWLDoH0aBnIJ04 Q9o647Y3l+AGzlyAi0YHhJARXtSgnj1dkbcxsz7T9ENa3EMTzL23xcEYsWBR047dx8ca gB9u3DUbh6ME2ozSFjXcDGeZaOMgROIc0DQJXky7AV2ZHAmGaT0gP8OakCnJTpnL8rOg 8VYK8bOGW8c1CWd3xlm06Qm0KHKstGo7jHAOE6tShvXBesvhwMNjDPzeJT9/tYckYe3r O5lg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=Rc8YT4TU+I5HtgVac7UO4Rq0QTyfIQpD6Hq6n/QrUS8=; b=UC95RoPH1SiGwMQklgDs499KbRJGzgRJflhwHjPa88qbkpN9zt9ebducLjFLLPAOn7 ++OENXnwWwiJarzPdfHBx8Y8Ec1izqQ85Atd2w+Il9psN2V2BGbr3/FaIox7+3W29jYK x61h2/5b5nASowH9CTiqQlbS0KrMDJsgKDSxzKBVQ7uZUfP5/w+QPGBNtctv+OzfUjwF tt+10HxGVGZO2SeF+7gLnmkhglZE4AdWXaTZnVVHjv+jz8QhsnC3S+aWTyKEKjNu62xe aMNsTSNZxcITnURKvN2LEjGdK9k86du3Ec9PtId4ZZa/yF6gVyPLxkt37fjzbS6Zl25V BjAw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=VHiW7Jil; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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This is useful to get an aligned register address when a device allows only word access and doesn't allow half word or byte access. Signed-off-by: Kishon Vijay Abraham I --- include/linux/kernel.h | 1 + 1 file changed, 1 insertion(+) -- 2.17.1 diff --git a/include/linux/kernel.h b/include/linux/kernel.h index 3adcb39fa6f5..888ad70a80aa 100644 --- a/include/linux/kernel.h +++ b/include/linux/kernel.h @@ -34,6 +34,7 @@ #define ALIGN_DOWN(x, a) __ALIGN_KERNEL((x) - ((a) - 1), (a)) #define __ALIGN_MASK(x, mask) __ALIGN_KERNEL_MASK((x), (mask)) #define PTR_ALIGN(p, a) ((typeof(p))ALIGN((unsigned long)(p), (a))) +#define PTR_ALIGN_DOWN(p, a) ((typeof(p))ALIGN_DOWN((unsigned long)(p), (a))) #define IS_ALIGNED(x, a) (((x) & ((typeof(x))(a) - 1)) == 0) /* generic data direction definitions */ From patchwork Mon Dec 9 09:21:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 180997 Delivered-To: patch@linaro.org Received: by 2002:a92:3001:0:0:0:0:0 with SMTP id x1csp4098086ile; Mon, 9 Dec 2019 01:21:22 -0800 (PST) X-Google-Smtp-Source: APXvYqwBEhGKLjg4Ai9gEHnYOY+jWMNcrrdpdxp5r15q7ZAnQMjPP9i0DWTZnf0T/8dhs6Kh1xxm X-Received: by 2002:aca:5582:: with SMTP id j124mr22287751oib.20.1575883282387; Mon, 09 Dec 2019 01:21:22 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1575883282; cv=none; d=google.com; s=arc-20160816; b=PuMIhvb3c3jze2LgT4yk0T5ymEV8NCFuKgQnXLOc1gIAHg4sJQ5r8+I2u5pk5ffoiI N/masTrekm7lq4A7s6qh4yQiKYt5uTRQoeT4OqLRb81AKALFUoVIzbcmAw9u7Taa4VNX owrbFVaESAsKOhcrBegQaEKxZ+mRfn6WAK+SK4kdYExHEJR0MtG8t0L3WHGmifjBnR/O roGHH3j5Baf8EOoiPx58SNTwPv0Qg2ucBVKykxJqil63fBjQZluAJIrqgN92fr2WO40/ F8dbiSUHYR/poXDqvBtPyj3/emBODAP2qGRrhTgdzel+GDatdnmqfCe/u7Id0D1i5R2T y3qg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=YobrPQ65XL9eRBwZXhJ3WyYimyOjvLKJGFnM3tEfmto=; b=WhtoVsU92aeZczUOKh0ch39whX64dtIfnMDH0kMj7HvJ3QSl50NzIxUaa1QxMHGVLg CqdBnLWTClklu4PFOjF5Pt/xw1Z1xF8akGwXMPSGyX+yEfgeJdy0L68Pe0vkMnOlcF9q HN6qbrpQB7mfFYEYpWJ2z9qneyApwDR9k4OHwAjnXqPS6XJlJXJ9CRUo5M+mN8VduiQt Tifu1F67t1c5Ua9zBTuKO8wE9Xov/KuWm2KsLgNJAJNkvfD6ynteodBmuJuxrhKsEbf/ zxAp8JBW/n95JVd1NpRIP5YHWJmPTQ+mlFHqHaOZVTfJ3ldKPqSyF6mszAPUWUMSzi9D 3TQw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=XotwPxFc; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id x7si11420552oia.165.2019.12.09.01.21.22; Mon, 09 Dec 2019 01:21:22 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=XotwPxFc; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727666AbfLIJVU (ORCPT + 4 others); Mon, 9 Dec 2019 04:21:20 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:49950 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727619AbfLIJVT (ORCPT ); Mon, 9 Dec 2019 04:21:19 -0500 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id xB99LCe6080946; Mon, 9 Dec 2019 03:21:12 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1575883272; bh=YobrPQ65XL9eRBwZXhJ3WyYimyOjvLKJGFnM3tEfmto=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=XotwPxFcTCJ+IQk3kLoL1x6tP2aCnh35v9/evsXiBBpMO53mriTy6h/QESs6ybOw3 6gsGvsyXSPXk2skQt97w28lsZKSHJpXBmhS2PpGhl/Ks9Zn4a59hLT3yYmOEYqr7Nk ecBg+wwoZkbFxO6a6xcJovjv2wf0HVWNHz+ciLa0= Received: from DLEE105.ent.ti.com (dlee105.ent.ti.com [157.170.170.35]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id xB99LCeB005933 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 9 Dec 2019 03:21:12 -0600 Received: from DLEE102.ent.ti.com (157.170.170.32) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Mon, 9 Dec 2019 03:21:12 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Mon, 9 Dec 2019 03:21:12 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id xB99Kcd7087697; Mon, 9 Dec 2019 03:21:09 -0600 From: Kishon Vijay Abraham I To: Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , Arnd Bergmann , Andrew Murray CC: , , , , Kishon Vijay Abraham I Subject: [PATCH 09/13] dt-bindings: PCI: Add host mode dt-bindings for TI's J721E SoC Date: Mon, 9 Dec 2019 14:51:43 +0530 Message-ID: <20191209092147.22901-10-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191209092147.22901-1-kishon@ti.com> References: <20191209092147.22901-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Add host mode dt-bindings for TI's J721E SoC. Cc: Rob Herring Signed-off-by: Kishon Vijay Abraham I --- .../bindings/pci/ti,j721e-pci-host.yaml | 161 ++++++++++++++++++ 1 file changed, 161 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml -- 2.17.1 diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml new file mode 100644 index 000000000000..96184e1f419f --- /dev/null +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml @@ -0,0 +1,161 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/pci/ti,j721e-pci-host.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: TI J721E PCI Host (PCIe Wrapper) + +maintainers: + - Kishon Vijay Abraham I + +properties: + compatible: + enum: + - ti,j721e-pcie-host + + reg: + maxItems: 4 + + reg-names: + items: + - const: intd_cfg + - const: user_cfg + - const: reg + - const: cfg + + ti,syscon-pcie-ctrl: + description: Phandle to the SYSCON entry required for configuring PCIe mode + and link speed. + allOf: + - $ref: /schemas/types.yaml#/definitions/phandle + + max-link-speed: + minimum: 1 + maximum: 3 + + num-lanes: + minimum: 1 + maximum: 2 + + power-domains: + maxItems: 1 + + clocks: + maxItems: 1 + description: clock-specifier to represent input to the PCIe + + clock-names: + items: + - const: fck + + "#address-cells": + const: 3 + + "#size-cells": + const: 2 + + bus-range: + description: Range of bus numbers associated with this controller. + + cdns,max-outbound-regions: + description: As defined in + Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt + allOf: + - $ref: /schemas/types.yaml#/definitions/int32 + - enum: [16] + + cdns,no-bar-match-nbits: + description: As defined in + Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt + allOf: + - $ref: /schemas/types.yaml#/definitions/int32 + - enum: [64] + + vendor-id: + const: 0x104c + description: As defined in + Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt + + device-id: + const: 0xb00d + description: As defined in + Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt + + msi-map: true + + dma-coherent: + description: Indicates that the PCIe IP block can ensure the coherency + + ranges: true + + reset-gpios: + description: GPIO specifier for the PERST# signal + + phys: + description: As defined in + Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt + + phy-names: + description: As defined in + Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt + +required: + - compatible + - reg + - reg-names + - ti,syscon-pcie-ctrl + - max-link-speed + - num-lanes + - power-domains + - clocks + - clock-names + - "#address-cells" + - "#size-cells" + - bus-range + - cdns,max-outbound-regions + - cdns,no-bar-match-nbits + - vendor-id + - device-id + - msi-map + - dma-coherent + - ranges + - reset-gpios + - phys + - phy-names + +examples: + - | + #include + #include + + + pcie0_rc: pcie@2900000 { + compatible = "ti,j721e-pcie-host"; + reg = <0x00 0x02900000 0x00 0x1000>, + <0x00 0x02907000 0x00 0x400>, + <0x00 0x0d000000 0x00 0x00800000>, + <0x00 0x10000000 0x00 0x00001000>; + reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; + ti,syscon-pcie-ctrl = <&pcie0_ctrl>; + max-link-speed = <3>; + num-lanes = <2>; + power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 239 1>; + clock-names = "fck"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0xf>; + cdns,max-outbound-regions = <16>; + cdns,no-bar-match-nbits = <64>; + vendor-id = /bits/ 16 <0x104c>; + device-id = /bits/ 16 <0xb00d>; + msi-map = <0x0 &gic_its 0x0 0x10000>; + dma-coherent; + reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>; + phys = <&serdes0_pcie_link>; + phy-names = "pcie_phy"; + ranges = <0x01000000 0x0 0x10001000 0x00 0x10001000 0x0 0x0010000>, + <0x02000000 0x0 0x10011000 0x00 0x10011000 0x0 0x7fef000>; + };