From patchwork Thu Nov 7 23:38:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Elliot Berman X-Patchwork-Id: 842173 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 302D51F12F5; Thu, 7 Nov 2024 23:38:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731022739; cv=none; b=OkjIbpPWu3+T1gBtd3/IsLkBXID1eEJ9t3HwhRUyuGhtF65dZOt5ANi1w3tZjtWYSXmF+dfnJbsfuZHfx/QPaVEqerGHDe2WEop37tq4/SniDnz02+6WXQ4OrPVOPDf16mmr3CsGbElslkoGVkLWX69h6I32U0KlVUyLFlWbwwE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731022739; c=relaxed/simple; bh=M/2l4Xl3vNkDGlj6NTJzFIntJYAf5PgZgQw7T79na90=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=ay8T4Oqe7hKPYy4H2Tt1UuJ2DxlE8vxEMLw5EyZCBV8kGQGocpdjLhL9sDXoZe8Ow3Nh8E4q5GL/jgEXmGpNr+F0lLKJN0JhG24YQYbxx0ZYlMOGf7DnEgo14/zI2qzPuwsVFSWWN8wttvUx44PK/2lsFlaUgXWfKhonxzCjiqI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=k5IlWviW; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="k5IlWviW" Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4A7Max5X013457; Thu, 7 Nov 2024 23:38:36 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= pGBcDJ4w4CXpuMx4u9qwtTgF3ku4Pb+02npBfURg4es=; b=k5IlWviWC/fh+7Rj W/Sg4l9vpjGWZAK449JwA1MpFKQXpqY2DRS8R/iV6+tzdKRPLSIgxBZ7jbDiqmc0 L9q/Zo8AMOxzi3q7CDLzXTLD5hqZ4UCwXUQY2/cromnEUpyG9TXellfknbwZHKPS BXt8Gbt9/Jh/N67C5Jp9hVOYnsJqNp2wd5kVm8mOtW3+XPnGB9LrecwhGxXweI+j 8FCZZfpN4sPTTZB51kZS+xHhGBEbaEDQKi06ZMked1pe55RPv+OumKE/UnlyQoD0 vGS/uGK63WSGhYRQ1DcE3WoRLZfvrSJMqeQinCZZ8HMj9oOPMFLQDTY+TCyoDeAA Pt7kNg== Received: from nasanppmta04.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 42s6gjg43x-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 07 Nov 2024 23:38:36 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4A7NcZRP027964 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 7 Nov 2024 23:38:35 GMT Received: from hu-eberman-lv.qualcomm.com (10.49.16.6) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 7 Nov 2024 15:38:35 -0800 From: Elliot Berman Date: Thu, 7 Nov 2024 15:38:25 -0800 Subject: [PATCH v8 1/6] dt-bindings: power: reset: Convert mode-.* properties to array Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20241107-arm-psci-system_reset2-vendor-reboots-v8-1-e8715fa65cb5@quicinc.com> References: <20241107-arm-psci-system_reset2-vendor-reboots-v8-0-e8715fa65cb5@quicinc.com> In-Reply-To: <20241107-arm-psci-system_reset2-vendor-reboots-v8-0-e8715fa65cb5@quicinc.com> To: Bjorn Andersson , Sebastian Reichel , Rob Herring , Conor Dooley , Vinod Koul , Andy Yan , Lorenzo Pieralisi , "Mark Rutland" , Bartosz Golaszewski , Arnd Bergmann , "Olof Johansson" , Catalin Marinas , "Will Deacon" , , "Krzysztof Kozlowski" , Konrad Dybcio , Konrad Dybcio CC: Satya Durga Srinivasu Prabhala , Melody Olvera , Shivendra Pratap , , , , Florian Fainelli , Stephen Boyd , , , Elliot Berman X-Mailer: b4 0.14.2 X-ClientProxiedBy: nalasex01c.na.qualcomm.com (10.47.97.35) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 0iaJ7uWxrUvvrwWEH4l2LUaICDmH65-W X-Proofpoint-ORIG-GUID: 0iaJ7uWxrUvvrwWEH4l2LUaICDmH65-W X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 clxscore=1015 suspectscore=0 adultscore=0 mlxscore=0 malwarescore=0 impostorscore=0 spamscore=0 phishscore=0 bulkscore=0 lowpriorityscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411070184 PSCI reboot mode will map a mode name to multiple magic values instead of just one. Convert the mode-.* property to an array. Users of the reboot-mode schema will need to specify the maxItems of the mode-.* properties. Existing users will all be 1. Reviewed-by: Rob Herring (Arm) Signed-off-by: Elliot Berman --- .../devicetree/bindings/power/reset/nvmem-reboot-mode.yaml | 4 ++++ Documentation/devicetree/bindings/power/reset/qcom,pon.yaml | 7 +++++++ Documentation/devicetree/bindings/power/reset/reboot-mode.yaml | 4 ++-- .../devicetree/bindings/power/reset/syscon-reboot-mode.yaml | 4 ++++ 4 files changed, 17 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/power/reset/nvmem-reboot-mode.yaml b/Documentation/devicetree/bindings/power/reset/nvmem-reboot-mode.yaml index 627f8a6078c299e32e4bc7597509a6ef52d119d7..7f5f94673e9c248302bbd70378a19f0d25906b7c 100644 --- a/Documentation/devicetree/bindings/power/reset/nvmem-reboot-mode.yaml +++ b/Documentation/devicetree/bindings/power/reset/nvmem-reboot-mode.yaml @@ -31,6 +31,10 @@ properties: allOf: - $ref: reboot-mode.yaml# +patternProperties: + "^mode-.*$": + maxItems: 1 + required: - compatible - nvmem-cells diff --git a/Documentation/devicetree/bindings/power/reset/qcom,pon.yaml b/Documentation/devicetree/bindings/power/reset/qcom,pon.yaml index fc8105a7b9b268df5cb08ad32cde26c50ea955ce..3da3d02a669089af037f9492c64e0304c714b523 100644 --- a/Documentation/devicetree/bindings/power/reset/qcom,pon.yaml +++ b/Documentation/devicetree/bindings/power/reset/qcom,pon.yaml @@ -54,6 +54,10 @@ required: - compatible - reg +patternProperties: + "^mode-.*$": + maxItems: 1 + unevaluatedProperties: false allOf: @@ -75,6 +79,9 @@ allOf: reg-names: items: - const: pon + else: + patternProperties: + "^mode-.*$": false # Special case for pm8941, which doesn't store reset mode - if: diff --git a/Documentation/devicetree/bindings/power/reset/reboot-mode.yaml b/Documentation/devicetree/bindings/power/reset/reboot-mode.yaml index ad0a0b95cec1267c8e479556aebf99cca653a2d9..3ddac06cec7277789b066d8426ea77d293298fac 100644 --- a/Documentation/devicetree/bindings/power/reset/reboot-mode.yaml +++ b/Documentation/devicetree/bindings/power/reset/reboot-mode.yaml @@ -28,13 +28,13 @@ description: | properties: mode-normal: - $ref: /schemas/types.yaml#/definitions/uint32 + $ref: /schemas/types.yaml#/definitions/uint32-array description: Default value to set on a reboot if no command was provided. patternProperties: "^mode-.*$": - $ref: /schemas/types.yaml#/definitions/uint32 + $ref: /schemas/types.yaml#/definitions/uint32-array additionalProperties: true diff --git a/Documentation/devicetree/bindings/power/reset/syscon-reboot-mode.yaml b/Documentation/devicetree/bindings/power/reset/syscon-reboot-mode.yaml index b6acff199cdecea08c1243ed5e8ad71240d65e9a..79ffc78b23eaf913dcb43964d083b78befe76890 100644 --- a/Documentation/devicetree/bindings/power/reset/syscon-reboot-mode.yaml +++ b/Documentation/devicetree/bindings/power/reset/syscon-reboot-mode.yaml @@ -32,6 +32,10 @@ properties: allOf: - $ref: reboot-mode.yaml# +patternProperties: + "^mode-.*$": + maxItems: 1 + unevaluatedProperties: false required: From patchwork Thu Nov 7 23:38:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Elliot Berman X-Patchwork-Id: 842174 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 302711EC015; Thu, 7 Nov 2024 23:38:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731022739; cv=none; b=GVq+o8PdGEIVFZyMLTr6vkiQZi4jkhEEUUeLB2wMnC6pIR+sRbOLuNqHwLFF0W+9x0WHDX9sQTRwMo6FtuiMVsNDcgpL0nKXQtS+pmcJqXCR5vRlpDYjGmyvmE8QsofAQZcVTGdKEC8kXcpPSmbmQQylY8OqoJDAXcQjLbfNtu4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731022739; c=relaxed/simple; bh=nw0IPJa6Yl8GLoi3oLMtGxvSfaCGz2wBhI23D41K+lQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=RNaoxQMCPgJ69gSniEcuFF+uX0l9X7mD2Y6LVsKwM07GiSWhS1EsPWZii4ZigqpwIAZgsGv24EMlGkyoT3TSOmgnfRFBjgrjunpA8RE8nIM8Xre0IXj5Sw+1PZJzi0z7DtYQaf1PyEvsPEtkSAaHE2OSZg6pkJN5PGWHxcg9w/4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=IFxf3s+m; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="IFxf3s+m" Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4A7Mb3UE000666; Thu, 7 Nov 2024 23:38:37 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= usuKKwc+EgHlEUqNp9S754v7FG/4Mwhu4ISmoEEUfas=; b=IFxf3s+mMyC8kBtt wxJwV0ZQFnrMCZGq7ZStYVeDyKdX8BIliXNZqtNalipt6LbDbOM0xVuh7b9oJq0j K3CEaAKDrnWxQxSFr2faV32CO1lQdFf7ykmzx6dMPELnm0ufibrjB1ROU4tKpQnR CDqE0qLr0ak4x7GcIxMwAJvygysqkp3kM2zZbhzdiAjBGQjX9fnHu5s8ahss59/q omOupJca09WQrmkaeL9Lhu6ptsyigS0+4tXWVL89X8R4qRCYMa3LITj5gCp0fxVk ugSH7GBE6VwZnD66skXvhvhYMmfZbkemSmaiixt4At+cJmBylA7Sx3+laVvCgDbF dk4JOQ== Received: from nasanppmta02.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 42s6gk83nm-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 07 Nov 2024 23:38:37 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4A7Ncax5006853 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 7 Nov 2024 23:38:36 GMT Received: from hu-eberman-lv.qualcomm.com (10.49.16.6) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 7 Nov 2024 15:38:35 -0800 From: Elliot Berman Date: Thu, 7 Nov 2024 15:38:26 -0800 Subject: [PATCH v8 2/6] dt-bindings: arm: Document reboot mode magic Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20241107-arm-psci-system_reset2-vendor-reboots-v8-2-e8715fa65cb5@quicinc.com> References: <20241107-arm-psci-system_reset2-vendor-reboots-v8-0-e8715fa65cb5@quicinc.com> In-Reply-To: <20241107-arm-psci-system_reset2-vendor-reboots-v8-0-e8715fa65cb5@quicinc.com> To: Bjorn Andersson , Sebastian Reichel , Rob Herring , Conor Dooley , Vinod Koul , Andy Yan , Lorenzo Pieralisi , "Mark Rutland" , Bartosz Golaszewski , Arnd Bergmann , "Olof Johansson" , Catalin Marinas , "Will Deacon" , , "Krzysztof Kozlowski" , Konrad Dybcio , Konrad Dybcio CC: Satya Durga Srinivasu Prabhala , Melody Olvera , Shivendra Pratap , , , , Florian Fainelli , Stephen Boyd , , , Elliot Berman X-Mailer: b4 0.14.2 X-ClientProxiedBy: nalasex01c.na.qualcomm.com (10.47.97.35) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: VG-zuR7SpKHayHDb7hBwgofTMdYdJGst X-Proofpoint-ORIG-GUID: VG-zuR7SpKHayHDb7hBwgofTMdYdJGst X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 mlxlogscore=999 mlxscore=0 clxscore=1015 suspectscore=0 spamscore=0 malwarescore=0 impostorscore=0 lowpriorityscore=0 adultscore=0 priorityscore=1501 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411070184 Add bindings to describe vendor-specific reboot modes. Values here correspond to valid parameters to vendor-specific reset types in PSCI SYSTEM_RESET2 call. Reviewed-by: Rob Herring (Arm) Signed-off-by: Elliot Berman --- Documentation/devicetree/bindings/arm/psci.yaml | 43 +++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/psci.yaml b/Documentation/devicetree/bindings/arm/psci.yaml index cbb012e217ab80c1ca88e611e7acc06c6d56fad0..5e07c62fe5d74a8d001f6b8a8c9e777f43f3113f 100644 --- a/Documentation/devicetree/bindings/arm/psci.yaml +++ b/Documentation/devicetree/bindings/arm/psci.yaml @@ -98,6 +98,27 @@ properties: [1] Kernel documentation - ARM idle states bindings Documentation/devicetree/bindings/cpu/idle-states.yaml + reset-types: + type: object + $ref: /schemas/power/reset/reboot-mode.yaml# + unevaluatedProperties: false + properties: + # "mode-normal" is just SYSTEM_RESET + mode-normal: false + patternProperties: + "^mode-.*$": + minItems: 1 + maxItems: 2 + description: | + Describes a vendor-specific reset type. The string after "mode-" + maps a reboot mode to the parameters in the PSCI SYSTEM_RESET2 call. + + Parameters are named mode-xxx = , where xxx + is the name of the magic reboot mode, type is the lower 31 bits + of the reset_type, and, optionally, the cookie value. If the cookie + is not provided, it is defaulted to zero. + The 31st bit (vendor-resets) will be implicitly set by the driver. + patternProperties: "^power-domain-": $ref: /schemas/power/power-domain.yaml# @@ -137,6 +158,15 @@ allOf: required: - cpu_off - cpu_on + - if: + not: + properties: + compatible: + contains: + const: arm,psci-1.0 + then: + properties: + reset-types: false additionalProperties: false @@ -261,4 +291,17 @@ examples: domain-idle-states = <&CLUSTER_RET>, <&CLUSTER_PWRDN>; }; }; + + - |+ + + // Case 5: SYSTEM_RESET2 vendor resets + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + + reset-types { + mode-edl = <0>; + mode-bootloader = <1 2>; + }; + }; ... From patchwork Thu Nov 7 23:38:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Elliot Berman X-Patchwork-Id: 841431 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 05EB7198E99; Thu, 7 Nov 2024 23:38:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731022739; cv=none; b=IQdLRWkb3OTDFNS0UIyv4D2XWKz0B/s2BMiWvQyIBrbvyyTDPtH0CMct8ViRLfquXdP0xlnLsSUro9KnFd8Q6wm837b8JxOpOFfEShRGJVlxHMBgsh5WZyMruG1i+AIFv31d1Kp8tb0qyVJMqvZHCs2Ya1azHS2wpIcOv4Asj9E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731022739; c=relaxed/simple; bh=UvIBqvOu1X+VXL8CJcPTJQuOWo2CyVpboy2Ngf5M+s0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=JKRLUYmu2sZ8n8UHglV/JXmTuU7bcxhakJe+r/Y1hYipq0PQJc7+tsWAZK9YmgyCoSJYeW36zC7SqmGx7mEv9A+bjtqwHERghtXp9myA4YXlYkHmrTTH/gybhLw7Z/t4jkEriqxpsMbbmF/6wZ/O9LzmMfGydD0xOu1YJhOoLew= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=CUzNq7Qg; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="CUzNq7Qg" Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4A7Mao7D014240; Thu, 7 Nov 2024 23:38:38 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= Zsx7v6mZz0Yust6nOGUIR9FH41kMyWKZVOzppJtcOVE=; b=CUzNq7Qgsb9Lte1I Y5CUB5kIbzyJ6tyaOnHlN//Z7+rbVCYlprnLcUOUIpjdnVUfLl7kxjO/gsAvWvd+ 34+veVwN3hX5/QtNridlN+VeDYNemqNOF/mAftdWYFDeaFKG8+L0WG681DzosNAV 0Tyjt+6+kSlYS4VEv0Vr08DqMRZIQ5QTrwHiJvv5J97mwiGJcDWT/8WZcXb9h8DS sa8cxktkA1XlliCG1fPP/uxyQIFuy1ZaG+omA4S8PGip+BeTcbpw1+dCCBMGS1wv p3iUxVRqULHpVIUewDCTWekqcmq+vWLlCQaTlFbEtA0JHkMWCldbmhBVcScpzeMM JD5kmQ== Received: from nasanppmta03.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 42s6gd03vn-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 07 Nov 2024 23:38:38 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4A7NcbS6025285 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 7 Nov 2024 23:38:37 GMT Received: from hu-eberman-lv.qualcomm.com (10.49.16.6) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 7 Nov 2024 15:38:36 -0800 From: Elliot Berman Date: Thu, 7 Nov 2024 15:38:27 -0800 Subject: [PATCH v8 3/6] firmware: psci: Read and use vendor reset types Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20241107-arm-psci-system_reset2-vendor-reboots-v8-3-e8715fa65cb5@quicinc.com> References: <20241107-arm-psci-system_reset2-vendor-reboots-v8-0-e8715fa65cb5@quicinc.com> In-Reply-To: <20241107-arm-psci-system_reset2-vendor-reboots-v8-0-e8715fa65cb5@quicinc.com> To: Bjorn Andersson , Sebastian Reichel , Rob Herring , Conor Dooley , Vinod Koul , Andy Yan , Lorenzo Pieralisi , "Mark Rutland" , Bartosz Golaszewski , Arnd Bergmann , "Olof Johansson" , Catalin Marinas , "Will Deacon" , , "Krzysztof Kozlowski" , Konrad Dybcio , Konrad Dybcio CC: Satya Durga Srinivasu Prabhala , Melody Olvera , Shivendra Pratap , , , , Florian Fainelli , Stephen Boyd , , , Elliot Berman X-Mailer: b4 0.14.2 X-ClientProxiedBy: nalasex01c.na.qualcomm.com (10.47.97.35) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: G0K7UiDRRX9KFTNJHhfxQRMH6gAwCaz8 X-Proofpoint-ORIG-GUID: G0K7UiDRRX9KFTNJHhfxQRMH6gAwCaz8 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 bulkscore=0 mlxscore=0 priorityscore=1501 clxscore=1015 spamscore=0 lowpriorityscore=0 phishscore=0 mlxlogscore=999 suspectscore=0 adultscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411070184 SoC vendors have different types of resets and are controlled through various registers. For instance, Qualcomm chipsets can reboot to a "download mode" that allows a RAM dump to be collected. Another example is they also support writing a cookie that can be read by bootloader during next boot. PSCI offers a mechanism, SYSTEM_RESET2, for these vendor reset types to be implemented without requiring drivers for every register/cookie. Add support in PSCI to statically map reboot mode commands from userspace to a vendor reset and cookie value using the device tree. A separate initcall is needed to parse the devicetree, instead of using psci_dt_init because mm isn't sufficiently set up to allocate memory. Reboot mode framework is close but doesn't quite fit with the design and requirements for PSCI SYSTEM_RESET2. Some of these issues can be solved but doesn't seem reasonable in sum: 1. reboot mode registers against the reboot_notifier_list, which is too early to call SYSTEM_RESET2. PSCI would need to remember the reset type from the reboot-mode framework callback and use it psci_sys_reset. 2. reboot mode assumes only one cookie/parameter is described in the device tree. SYSTEM_RESET2 uses 2: one for the type and one for cookie. 3. psci cpuidle driver already registers a driver against the arm,psci-1.0 compatible. Refactoring would be needed to have both a cpuidle and reboot-mode driver. Tested-by: Florian Fainelli Signed-off-by: Elliot Berman Reviewed-by: Stephen Boyd --- drivers/firmware/psci/psci.c | 104 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 104 insertions(+) diff --git a/drivers/firmware/psci/psci.c b/drivers/firmware/psci/psci.c index 2328ca58bba61fdb677ac20a1a7447882cd0cf22..e60e3f8749c5a6732c51d23a2c1f453361132d9a 100644 --- a/drivers/firmware/psci/psci.c +++ b/drivers/firmware/psci/psci.c @@ -79,6 +79,14 @@ struct psci_0_1_function_ids get_psci_0_1_function_ids(void) static u32 psci_cpu_suspend_feature; static bool psci_system_reset2_supported; +struct psci_reset_param { + const char *mode; + u32 reset_type; + u32 cookie; +}; +static struct psci_reset_param *psci_reset_params __ro_after_init; +static size_t num_psci_reset_params __ro_after_init; + static inline bool psci_has_ext_power_state(void) { return psci_cpu_suspend_feature & @@ -305,9 +313,38 @@ static int get_set_conduit_method(const struct device_node *np) return 0; } +static void psci_vendor_system_reset2(const char *cmd) +{ + unsigned long ret; + size_t i; + + for (i = 0; i < num_psci_reset_params; i++) { + if (!strcmp(psci_reset_params[i].mode, cmd)) { + ret = invoke_psci_fn(PSCI_FN_NATIVE(1_1, SYSTEM_RESET2), + psci_reset_params[i].reset_type, + psci_reset_params[i].cookie, 0); + /* + * if vendor reset fails, log it and fall back to + * architecture reset types + */ + pr_err("failed to perform reset \"%s\": %ld\n", cmd, + (long)ret); + return; + } + } +} + static int psci_sys_reset(struct notifier_block *nb, unsigned long action, void *data) { + /* + * try to do the vendor system_reset2 + * If the reset fails or there wasn't a match on the command, + * fall back to architectural resets + */ + if (data && num_psci_reset_params) + psci_vendor_system_reset2(data); + if ((reboot_mode == REBOOT_WARM || reboot_mode == REBOOT_SOFT) && psci_system_reset2_supported) { /* @@ -750,6 +787,73 @@ static const struct of_device_id psci_of_match[] __initconst = { {}, }; +#define REBOOT_PREFIX "mode-" + +static int __init psci_init_system_reset2_modes(void) +{ + const size_t len = strlen(REBOOT_PREFIX); + struct psci_reset_param *param; + struct device_node *psci_np __free(device_node) = NULL; + struct device_node *np __free(device_node) = NULL; + struct property *prop; + size_t count = 0; + u32 magic[2]; + int num; + + if (!psci_system_reset2_supported) + return 0; + + psci_np = of_find_matching_node(NULL, psci_of_match); + if (!psci_np) + return 0; + + np = of_find_node_by_name(psci_np, "reset-types"); + if (!np) + return 0; + + for_each_property_of_node(np, prop) { + if (strncmp(prop->name, REBOOT_PREFIX, len)) + continue; + num = of_property_count_u32_elems(np, prop->name); + if (num != 1 && num != 2) + continue; + + count++; + } + + param = psci_reset_params = + kcalloc(count, sizeof(*psci_reset_params), GFP_KERNEL); + if (!psci_reset_params) + return -ENOMEM; + + for_each_property_of_node(np, prop) { + if (strncmp(prop->name, REBOOT_PREFIX, len)) + continue; + + param->mode = kstrdup_const(prop->name + len, GFP_KERNEL); + if (!param->mode) + continue; + + num = of_property_read_variable_u32_array(np, prop->name, magic, + 1, ARRAY_SIZE(magic)); + if (num < 0) { + pr_warn("Failed to parse vendor reboot mode %s\n", + param->mode); + kfree_const(param->mode); + continue; + } + + /* Force reset type to be in vendor space */ + param->reset_type = PSCI_1_1_RESET_TYPE_VENDOR_START | magic[0]; + param->cookie = num > 1 ? magic[1] : 0; + param++; + num_psci_reset_params++; + } + + return 0; +} +arch_initcall(psci_init_system_reset2_modes); + int __init psci_dt_init(void) { struct device_node *np; From patchwork Thu Nov 7 23:38:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Elliot Berman X-Patchwork-Id: 841430 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 303291F4269; Thu, 7 Nov 2024 23:38:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731022739; cv=none; b=SnD2z+tdB4jwaix+GSERwQR0xL2N1VEpmMZ7BPIDLp+Gf3X3JBe7m4LN1ly2Ore9FSHgkmm7abTuCCL5ERYW3ZLouXHjYcazJKPL90cAQ3tXmr7cjUnTEG+1kHlgaADAvsbDLVuLQY+9vGdp8RncyxB3PtKN9m0md3zVikSMSsY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731022739; c=relaxed/simple; bh=7EO0qLNxt6YhqxBz0rV9UYU/huKFfEEAsG2HrEJFCWI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=dRX9Z7Uwayv/k3UPsBzWn+HpOXBb9TxVfTMifwDTYM2bJ1pJ+TPoj9payxidvQB6dP0X8Mvpe7k7PAX7Za2DZHpNHIu9o9QErFKuOvFn2mDDGRdRCBa5/qomVot4o2R9CJPkDIDtbFYZRA052kQR/PV6J8JL828hGjYUDbWRk0E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=HxBtEeUZ; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="HxBtEeUZ" Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4A7MaxlT021233; Thu, 7 Nov 2024 23:38:39 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= XbNsxJCIYTQRHc/L8A5AxsoN1XJdMZhzG+/ZhH275aY=; b=HxBtEeUZhNflcKsC 5pqilBj79WMKJFGl5CYpFmz5MZobS2dV9jrTU+Av3ftRVGHFfggNRHKzAcSqPSxg FeWsUO9BiIbSRZQhyku2arkc0L4X4SPZfGgJtIfNv6i6jb7oNJlHq2npVkELKgv9 yhwiPilkJCIsFYz6AJIZ0Vue644gRchYLjPonqk8fyOe/KBxEU3f+KK4A+93qdp7 qT5aVUMgb7kh4/F2AuFpMyX+e2RQX3IxKjwSkrKvnipaI619UqnydjK5L7BH2W7n 3u2SaLfG/YNudrLtPxqIa9M515OATuEwsLnaCWz/Ye800o+3nSNRiZLBMRwHxMBe 1uUDaA== Received: from nasanppmta04.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 42s6gh83ug-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 07 Nov 2024 23:38:38 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4A7NccUJ027982 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 7 Nov 2024 23:38:38 GMT Received: from hu-eberman-lv.qualcomm.com (10.49.16.6) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 7 Nov 2024 15:38:37 -0800 From: Elliot Berman Date: Thu, 7 Nov 2024 15:38:28 -0800 Subject: [PATCH v8 4/6] arm64: dts: qcom: qcm6490-idp: Add PSCI SYSTEM_RESET2 types Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20241107-arm-psci-system_reset2-vendor-reboots-v8-4-e8715fa65cb5@quicinc.com> References: <20241107-arm-psci-system_reset2-vendor-reboots-v8-0-e8715fa65cb5@quicinc.com> In-Reply-To: <20241107-arm-psci-system_reset2-vendor-reboots-v8-0-e8715fa65cb5@quicinc.com> To: Bjorn Andersson , Sebastian Reichel , Rob Herring , Conor Dooley , Vinod Koul , Andy Yan , Lorenzo Pieralisi , "Mark Rutland" , Bartosz Golaszewski , Arnd Bergmann , "Olof Johansson" , Catalin Marinas , "Will Deacon" , , "Krzysztof Kozlowski" , Konrad Dybcio , Konrad Dybcio CC: Satya Durga Srinivasu Prabhala , Melody Olvera , Shivendra Pratap , , , , Florian Fainelli , Stephen Boyd , , , Elliot Berman X-Mailer: b4 0.14.2 X-ClientProxiedBy: nalasex01c.na.qualcomm.com (10.47.97.35) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: xf1J7enr0aBTbmSxNv1sUC3Em7y46Jhv X-Proofpoint-GUID: xf1J7enr0aBTbmSxNv1sUC3Em7y46Jhv X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 adultscore=0 malwarescore=0 clxscore=1015 spamscore=0 lowpriorityscore=0 phishscore=0 mlxscore=0 impostorscore=0 priorityscore=1501 bulkscore=0 mlxlogscore=828 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411070184 qcm6490-idp firmware supports vendor-defined SYSTEM_RESET2 types. Describe the reset types: "bootloader" will cause device to reboot and stop in the bootloader's fastboot mode. "edl" will cause device to reboot into "emergency download mode", which permits loading images via the Firehose protocol. Co-developed-by: Shivendra Pratap Signed-off-by: Shivendra Pratap Reviewed-by: Konrad Dybcio Signed-off-by: Elliot Berman --- arch/arm64/boot/dts/qcom/qcm6490-idp.dts | 7 +++++++ arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 +- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts index a0668f767e4bf9c8a749adf180dc65f785eb389e..9c141244a7b23cff4c1e85b952c28208b2ad40b7 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts @@ -617,6 +617,13 @@ &pon_resin { status = "okay"; }; +&psci { + reset-types { + mode-bootloader = <0x10001 0x2>; + mode-edl = <0 0x1>; + }; +}; + &qupv3_id_0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 3d8410683402fd4c03c5c2951721938fff20fc77..5360d0e51a65874be86c0a6ad7bed612bcb44e81 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -850,7 +850,7 @@ pmu { interrupts = ; }; - psci { + psci: psci { compatible = "arm,psci-1.0"; method = "smc"; From patchwork Thu Nov 7 23:38:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Elliot Berman X-Patchwork-Id: 841429 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6B0331F4FA9; Thu, 7 Nov 2024 23:38:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731022740; cv=none; b=iCY7AUOpkDJDae5FXLEsNlxuCWQKNZUviR/PN+UXCL7jY2cerCau823zjBvu1/W+6gxk5e2dFHA71p/97Tc0KQseuBsv4d1Jw4/DQrRRRf84X8h7alaKrpze+PKhhjf18iUVzKC37/lwqUioYvr9PWyFTZZXYgQ+iU5IBgF3GgA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731022740; c=relaxed/simple; bh=CRl4sp5W1H5HCBEEE9ZitP6r+tmfklHAzHiiBvISpBs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=XQqa+mlWZ2UZnn1doniMm3mTSSUtB9n3H5nyxEF9LniDbK0UJ++Asp0CnSrRFCYzfixlllN+AwcnUGtsmji8wuwWgVisp3CO2f4Rr7hnZyIBVsrbjQHtFD3gncWbWsrlVoUVTowev/Zwe7OtKbetPjUhavMxiWR17260pNIXqIU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=cwx4+ttz; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="cwx4+ttz" Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4A7MbQFj021503; Thu, 7 Nov 2024 23:38:39 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= A6mw8karyIFLki/rxMpwPqRRLujrN+gCUVJx1EPH0tU=; b=cwx4+ttz+yPACV1l RQlMFM45fSxJ/PISEGP8UzYpebM+uMuj/WdM3kzVM9ZiP33b7YkVd0ZmT/up93rR v3i41uweA3i6JDeu8iALlg4STV1iTb4SgRiq5TBPsgwPCfC+cnhu6QoIi0WR/tb+ vGePsO1fZ2SXyyUpGYLpg7Qg+Jo9xkmv4MBRtz8trH9xi5qjC+J9yuuUTxaIYKyU hoWXCLCNWOOCywBpQbC6XDTt+5uNGrCynKv/XXW13ENfJB7hOn9QIy5fA9BMGooV Zi07Rsm3DL0PdaZf+a1tiMQo0MXCBXsNJFgG6CdFb9bQgCWbK36JRMOYpJ8QJ4IZ L/XoUg== Received: from nasanppmta03.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 42s6gh83uh-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 07 Nov 2024 23:38:39 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4A7NccPJ025300 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 7 Nov 2024 23:38:38 GMT Received: from hu-eberman-lv.qualcomm.com (10.49.16.6) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 7 Nov 2024 15:38:38 -0800 From: Elliot Berman Date: Thu, 7 Nov 2024 15:38:29 -0800 Subject: [PATCH v8 5/6] arm64: dts: qcom: qcs6490-rb3gen2: Add PSCI SYSTEM_RESET2 types Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20241107-arm-psci-system_reset2-vendor-reboots-v8-5-e8715fa65cb5@quicinc.com> References: <20241107-arm-psci-system_reset2-vendor-reboots-v8-0-e8715fa65cb5@quicinc.com> In-Reply-To: <20241107-arm-psci-system_reset2-vendor-reboots-v8-0-e8715fa65cb5@quicinc.com> To: Bjorn Andersson , Sebastian Reichel , Rob Herring , Conor Dooley , Vinod Koul , Andy Yan , Lorenzo Pieralisi , "Mark Rutland" , Bartosz Golaszewski , Arnd Bergmann , "Olof Johansson" , Catalin Marinas , "Will Deacon" , , "Krzysztof Kozlowski" , Konrad Dybcio , Konrad Dybcio CC: Satya Durga Srinivasu Prabhala , Melody Olvera , Shivendra Pratap , , , , Florian Fainelli , Stephen Boyd , , , Elliot Berman X-Mailer: b4 0.14.2 X-ClientProxiedBy: nalasex01c.na.qualcomm.com (10.47.97.35) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: c9X-a9BpD_uP9I0gjRSqqGhLZtqKDIyF X-Proofpoint-GUID: c9X-a9BpD_uP9I0gjRSqqGhLZtqKDIyF X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 adultscore=0 malwarescore=0 clxscore=1015 spamscore=0 lowpriorityscore=0 phishscore=0 mlxscore=0 impostorscore=0 priorityscore=1501 bulkscore=0 mlxlogscore=806 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411070184 qcs6490-rb3gen2 firmware supports vendor-defined SYSTEM_RESET2 types. Describe the reset types: "bootloader" will cause device to reboot and stop in the bootloader's fastboot mode. "edl" will cause device to reboot into "emergency download mode", which permits loading images via the Firehose protocol. Signed-off-by: Elliot Berman Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index 0d45662b8028bff475024cff37c33e01d2ee251b..67d453c5b089aadb7b6f965e6ff7a29290963079 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -688,6 +688,13 @@ &pmk8350_rtc { status = "okay"; }; +&psci { + reset-types { + mode-bootloader = <0x10001 0x2>; + mode-edl = <0 0x1>; + }; +}; + &qupv3_id_0 { status = "okay"; }; From patchwork Thu Nov 7 23:38:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Elliot Berman X-Patchwork-Id: 842175 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 424FF1EE000; Thu, 7 Nov 2024 23:38:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731022738; cv=none; b=o9EVpaKLnMAewEcUnqE7MERg+LuR0u8Yp21LwksJguVinpTKMWQ0l1I5G1+80gHau1awBLtc3sIea40Mw2rElh5VZSyq0LccZGdFso0QyXLJ7or+zW6OM6H1giknjntAFvnaG+my35kj+pNg2xn6kj9eGzQZJylFq1ni5h/cgqg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731022738; c=relaxed/simple; bh=kayrvux8BhemWIVBDX8P8yW3cgvSbun4j3/DheCN7Oc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=P4GhRWRpVGcY6Di1+9gw1DbqiB406l6xiIYXMtqNAtpzhjd/pBuiZzU+FT5Sx0C9dYUsGL5ogjbR3c/A8tOwTspQIHf22Zax2QYl20hUXHW9sdZOj12rp5FdaY0Y4VMTsBL1aVWvamyQYQ/OxwFTH52GlVDGbRNNHZdx4vE6FUs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=CxRoRrph; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="CxRoRrph" Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4A7Mbewh012723; Thu, 7 Nov 2024 23:38:41 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= XCtmy0HxXe0b8tYyb4jInNsE60r7b6EEJpK4qRncReU=; b=CxRoRrphrXUaYC8Y cf1zEtmshlB1CtrflMR3uYeuQ+5pxgq1MA0UKz1BNfPjL54gKNAaGA2wl0Rejck5 TGaionutzmwqIrd6q8DDkiVuq0jLRIDVdOlTteuqkBiuaQvQJTgOWuIPpUw6A6JF JumxF1e+U9NJzQNTNjxQGRCB1cV4BCHyXvFwkzQnO3zy97hRtpjLf5R/q6LFmfjS mrDY8vyahMd/lAxuhkGiuml/3bNykmHfGkXR3AzlpnGlI6vsHzM2GZbQWnLyGsJr mBAe0BRxADQhMOkTcDuc7aSgJWZRdmvAyZMDHBCFgtAjq64LaVlkYGILOF0vVCB4 w8tGFQ== Received: from nasanppmta02.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 42s6gm03tu-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 07 Nov 2024 23:38:40 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4A7Ncdw6006876 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 7 Nov 2024 23:38:39 GMT Received: from hu-eberman-lv.qualcomm.com (10.49.16.6) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 7 Nov 2024 15:38:38 -0800 From: Elliot Berman Date: Thu, 7 Nov 2024 15:38:30 -0800 Subject: [PATCH v8 6/6] arm64: dts: qcom: sa8775p-ride: Add PSCI SYSTEM_RESET2 types Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20241107-arm-psci-system_reset2-vendor-reboots-v8-6-e8715fa65cb5@quicinc.com> References: <20241107-arm-psci-system_reset2-vendor-reboots-v8-0-e8715fa65cb5@quicinc.com> In-Reply-To: <20241107-arm-psci-system_reset2-vendor-reboots-v8-0-e8715fa65cb5@quicinc.com> To: Bjorn Andersson , Sebastian Reichel , Rob Herring , Conor Dooley , Vinod Koul , Andy Yan , Lorenzo Pieralisi , "Mark Rutland" , Bartosz Golaszewski , Arnd Bergmann , "Olof Johansson" , Catalin Marinas , "Will Deacon" , , "Krzysztof Kozlowski" , Konrad Dybcio , Konrad Dybcio CC: Satya Durga Srinivasu Prabhala , Melody Olvera , Shivendra Pratap , , , , Florian Fainelli , Stephen Boyd , , , Elliot Berman X-Mailer: b4 0.14.2 X-ClientProxiedBy: nalasex01c.na.qualcomm.com (10.47.97.35) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: RVklIsCqsrNkHx21Ja7Z-a2NTjjatmZU X-Proofpoint-GUID: RVklIsCqsrNkHx21Ja7Z-a2NTjjatmZU X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=860 spamscore=0 suspectscore=0 adultscore=0 bulkscore=0 impostorscore=0 mlxscore=0 phishscore=0 clxscore=1015 lowpriorityscore=0 malwarescore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411070184 sa8775p-ride firmware supports vendor-defined SYSTEM_RESET2 types. Describe the reset types: "bootloader" will cause device to reboot and stop in the bootloader's fastboot mode. "edl" will cause device to reboot into "emergency download mode", which permits loading images via the Firehose protocol. Co-developed-by: Shivendra Pratap Signed-off-by: Shivendra Pratap Signed-off-by: Elliot Berman --- arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi | 7 +++++++ arch/arm64/boot/dts/qcom/sa8775p.dtsi | 2 +- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi b/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi index 2a6170623ea95ad34625b7eb3b729a3e1018f99a..9e8cc21873338f5aaf289df0acde6576d425d6e5 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi @@ -498,6 +498,13 @@ &pmm8654au_3_gpios { "GNSS_BOOT_MODE"; }; +&psci { + reset-types { + mode-bootloader = <0x10001 0x2>; + mode-edl = <0 0x1>; + }; +}; + &qupv3_id_1 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 23f1b2e5e62471396d8dd5eaf5ecb23e01a5e458..dd36eea80f7c5ca39ae7bd5dec7f469d4f69775f 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -329,7 +329,7 @@ pmu { interrupts = ; }; - psci { + psci: psci { compatible = "arm,psci-1.0"; method = "smc"; };