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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id r7sm21969662pfg.34.2019.12.07.12.22.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Dec 2019 12:22:15 -0800 (PST) From: Bjorn Andersson To: Andy Gross , Bjorn Andersson Cc: Kishon Vijay Abraham I , Rob Herring , Mark Rutland , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, vinod.koul@linaro.org Subject: [PATCH 2/2] arm64: dts: qcom: msm8996: Use generic QMP driver for UFS Date: Sat, 7 Dec 2019 12:21:47 -0800 Message-Id: <20191207202147.2314248-3-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191207202147.2314248-1-bjorn.andersson@linaro.org> References: <20191207202147.2314248-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org With support for the MSM8996 UFS PHY added to the common QMP driver, migrate the DTS to use the common QMP binding. Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 33 +++++++++++++++------------ 1 file changed, 18 insertions(+), 15 deletions(-) -- 2.24.0 diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index c9c6efbbcc01..d0f2544ccf5b 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -1323,27 +1323,30 @@ spmi_bus: qcom,spmi@400f000 { #interrupt-cells = <4>; }; - ufsphy: phy@627000 { - compatible = "qcom,msm8996-ufs-phy-qmp-14nm"; - reg = <0x627000 0xda8>; - reg-names = "phy_mem"; - #phy-cells = <0>; + ufs_phy: phy@627000 { + compatible = "qcom,msm8996-qmp-ufs-phy"; + reg = <0x00627000 0x1c4>; + #address-cells = <1>; + #size-cells = <1>; + ranges; vdda-phy-supply = <&pm8994_l28>; vdda-pll-supply = <&pm8994_l12>; - - vdda-phy-max-microamp = <18380>; - vdda-pll-max-microamp = <9440>; - vddp-ref-clk-supply = <&pm8994_l25>; - vddp-ref-clk-max-microamp = <100>; - vddp-ref-clk-always-on; - clock-names = "ref_clk_src", "ref_clk"; - clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, - <&gcc GCC_UFS_CLKREF_CLK>; + clocks = <&gcc GCC_UFS_CLKREF_CLK>; + clock-names = "ref"; + resets = <&ufshc 0>; + reset-names = "ufsphy"; status = "disabled"; + + ufs_phy_lane: lanes@627400 { + reg = <0x627400 0x12c>, + <0x627600 0x200>, + <0x627c00 0x1b4>; + #phy-cells = <0>; + }; }; ufshc: ufshc@624000 { @@ -1351,7 +1354,7 @@ ufshc: ufshc@624000 { reg = <0x624000 0x2500>; interrupts = ; - phys = <&ufsphy>; + phys = <&ufs_phy_lane>; phy-names = "ufsphy"; vcc-supply = <&pm8994_l20>;