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Mon, 04 Nov 2024 16:20:59 +0000 Received: from NALASPPMTA05.qualcomm.com (NALASPPMTA05.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 4A4GKwMW000890; Mon, 4 Nov 2024 16:20:59 GMT Received: from hu-devc-lv-u22-c.qualcomm.com (hu-uchalich-lv.qualcomm.com [10.81.89.1]) by NALASPPMTA05.qualcomm.com (PPS) with ESMTPS id 4A4GKwEe000887 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 04 Nov 2024 16:20:58 +0000 Received: by hu-devc-lv-u22-c.qualcomm.com (Postfix, from userid 4184210) id C475F641; Mon, 4 Nov 2024 08:20:58 -0800 (PST) From: Unnathi Chalicheemala To: Bjorn Andersson , Konrad Dybcio Cc: Unnathi Chalicheemala , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, kernel@quicinc.com Subject: [PATCH v3 1/2] firmware: qcom_scm: Add API to get waitqueue IRQ info Date: Mon, 4 Nov 2024 08:20:55 -0800 Message-Id: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: u4QeLECsrL5cXaKaauxBWa27DPpgG6VQ X-Proofpoint-GUID: u4QeLECsrL5cXaKaauxBWa27DPpgG6VQ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 malwarescore=0 priorityscore=1501 phishscore=0 clxscore=1015 mlxscore=0 impostorscore=0 bulkscore=0 mlxlogscore=999 adultscore=0 suspectscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411040138 Bootloader and firmware for SM8650 and older chipsets expect node name as "qcom_scm", in order to patch the wait queue IRQ information. However, DeviceTree uses node name "scm" and this mismatch prevents firmware from correctly identifying waitqueue IRQ information. Waitqueue IRQ is used for signaling between secure and non-secure worlds. To resolve this, introduce qcom_scm_get_waitq_irq() that'll get the hardware IRQ number to be used from firmware instead of relying on data provided by devicetree, thereby bypassing the DeviceTree node name mismatch. This hardware IRQ number is converted to a Linux IRQ number using newly defined fill_irq_fwspec_params(). This Linux IRQ number is then supplied to the threaded_irq call. Signed-off-by: Unnathi Chalicheemala --- drivers/firmware/qcom/qcom_scm.c | 52 +++++++++++++++++++++++++++++++- drivers/firmware/qcom/qcom_scm.h | 1 + 2 files changed, 52 insertions(+), 1 deletion(-) diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_scm.c index 10986cb11ec0..ec1205474a3a 100644 --- a/drivers/firmware/qcom/qcom_scm.c +++ b/drivers/firmware/qcom/qcom_scm.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -35,6 +36,11 @@ static u32 download_mode; +#define GIC_SPI_BASE 32 +#define GIC_MAX_SPI 1019 // SPIs in GICv3 spec range from 32..1019 +#define GIC_ESPI_BASE 4096 +#define GIC_MAX_ESPI 5119 // ESPIs in GICv3 spec range from 4096..5119 + struct qcom_scm { struct device *dev; struct clk *core_clk; @@ -1830,6 +1836,50 @@ bool qcom_scm_is_available(void) } EXPORT_SYMBOL_GPL(qcom_scm_is_available); +static int qcom_scm_fill_irq_fwspec_params(struct irq_fwspec *fwspec, u32 virq) +{ + if (virq >= GIC_SPI_BASE && virq <= GIC_SPI_MAX) { + fwspec->param[0] = GIC_SPI; + fwspec->param[1] = virq - GIC_SPI_BASE; + } else if (virq >= GIC_ESPI_BASE && virq <= GIC_ESPI_MAX) { + fwspec->param[0] = GIC_ESPI; + fwspec->param[1] = virq - GIC_ESPI_BASE; + } else { + WARN(1, "Unexpected virq: %d\n", virq); + return -ENXIO; + } + fwspec->param[2] = IRQ_TYPE_EDGE_RISING; + fwspec->param_count = 3; + + return 0; +} + +static int qcom_scm_get_waitq_irq(void) +{ + int ret; + u32 hwirq; + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_WAITQ, + .cmd = QCOM_SCM_WAITQ_GET_INFO, + .owner = ARM_SMCCC_OWNER_SIP + }; + struct qcom_scm_res res; + struct irq_fwspec fwspec; + + ret = qcom_scm_call_atomic(__scm->dev, &desc, &res); + if (ret) + return ret; + + fwspec.fwnode = of_node_to_fwnode(__scm->dev->of_node); + hwirq = res.result[1] & GENMASK(15, 0); + ret = qcom_scm_fill_irq_fwspec_params(&fwspec, hwirq); + if (ret) + return ret; + ret = irq_create_fwspec_mapping(&fwspec); + + return ret; +} + static int qcom_scm_assert_valid_wq_ctx(u32 wq_ctx) { /* FW currently only supports a single wq_ctx (zero). @@ -1986,7 +2036,7 @@ static int qcom_scm_probe(struct platform_device *pdev) /* Let all above stores be available after this */ smp_store_release(&__scm, scm); - irq = platform_get_irq_optional(pdev, 0); + irq = qcom_scm_get_waitq_irq(); if (irq < 0) { if (irq != -ENXIO) return irq; diff --git a/drivers/firmware/qcom/qcom_scm.h b/drivers/firmware/qcom/qcom_scm.h index 685b8f59e7a6..ab0f88f5f777 100644 --- a/drivers/firmware/qcom/qcom_scm.h +++ b/drivers/firmware/qcom/qcom_scm.h @@ -143,6 +143,7 @@ struct qcom_tzmem_pool *qcom_scm_get_tzmem_pool(void); #define QCOM_SCM_SVC_WAITQ 0x24 #define QCOM_SCM_WAITQ_RESUME 0x02 #define QCOM_SCM_WAITQ_GET_WQ_CTX 0x03 +#define QCOM_SCM_WAITQ_GET_INFO 0x04 #define QCOM_SCM_SVC_GPU 0x28 #define QCOM_SCM_SVC_GPU_INIT_REGS 0x01 From patchwork Mon Nov 4 16:20:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Unnathi Chalicheemala X-Patchwork-Id: 840595 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1C6C61C233A; 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Mon, 04 Nov 2024 16:21:00 +0000 (GMT) Received: from pps.filterd (NALASPPMTA02.qualcomm.com [127.0.0.1]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTP id 4A4GL0uV003698; Mon, 4 Nov 2024 16:21:00 GMT Received: from pps.reinject (localhost [127.0.0.1]) by NALASPPMTA02.qualcomm.com (PPS) with ESMTPS id 42nd5m2srr-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 04 Nov 2024 16:20:59 +0000 Received: from NALASPPMTA02.qualcomm.com (NALASPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 4A4GKtDD003631; Mon, 4 Nov 2024 16:20:59 GMT Received: from hu-devc-lv-u22-c.qualcomm.com (hu-uchalich-lv.qualcomm.com [10.81.89.1]) by NALASPPMTA02.qualcomm.com (PPS) with ESMTPS id 4A4GKxb7003688 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 04 Nov 2024 16:20:59 +0000 Received: by hu-devc-lv-u22-c.qualcomm.com (Postfix, from userid 4184210) id 7E8FD641; Mon, 4 Nov 2024 08:20:59 -0800 (PST) From: Unnathi Chalicheemala To: Bjorn Andersson , Konrad Dybcio Cc: Unnathi Chalicheemala , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, kernel@quicinc.com Subject: [PATCH v3 2/2] firmware: qcom_scm: Support multiple waitq contexts Date: Mon, 4 Nov 2024 08:20:56 -0800 Message-Id: <3fe8739458227081d43f00746fe527bc4f8fd8b5.1730735881.git.quic_uchalich@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: smGKiLN9Ug4JX3_UM7O_U7UHJ_fzyLQI X-Proofpoint-GUID: smGKiLN9Ug4JX3_UM7O_U7UHJ_fzyLQI X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 bulkscore=0 mlxscore=0 spamscore=0 lowpriorityscore=0 adultscore=0 malwarescore=0 suspectscore=0 priorityscore=1501 clxscore=1015 mlxlogscore=999 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411040138 Currently, only a single waitqueue context exists, with waitqueue id zero. Multi-waitqueue mechanism is added in firmware to support the case when multiple VMs make SMC calls or single VM making multiple calls on same CPU. When VMs make SMC call, firmware will allocate waitqueue context assuming the SMC call to be a blocking call. SMC calls that cannot acquire resources are returned to sleep in the calling VM. When resource is available, VM will be notified to wake sleeping thread and resume SMC call. SM8650 firmware can allocate two such waitq contexts so create these two waitqueue contexts. Unique waitqueue contexts are supported by a dynamically sized array where each unique wq_ctx is associated with a struct completion variable for easy lookup. To get the number of waitqueue contexts directly from firmware, qcom_scm_query_waitq_cnt() is introduced. On older targets which support only a single waitqueue, wq_cnt is set to 1 as SCM call for query_waitq_cnt() is not implemented for single waitqueue case. Signed-off-by: Unnathi Chalicheemala --- drivers/firmware/qcom/qcom_scm.c | 75 ++++++++++++++++++++++---------- 1 file changed, 53 insertions(+), 22 deletions(-) diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_scm.c index ec1205474a3a..a93157917f79 100644 --- a/drivers/firmware/qcom/qcom_scm.c +++ b/drivers/firmware/qcom/qcom_scm.c @@ -47,7 +47,7 @@ struct qcom_scm { struct clk *iface_clk; struct clk *bus_clk; struct icc_path *path; - struct completion waitq_comp; + struct completion *waitq; struct reset_controller_dev reset; /* control access to the interconnect path */ @@ -57,6 +57,7 @@ struct qcom_scm { u64 dload_mode_addr; struct qcom_tzmem_pool *mempool; + unsigned int wq_cnt; }; struct qcom_scm_current_perm_info { @@ -1854,6 +1855,26 @@ static int qcom_scm_fill_irq_fwspec_params(struct irq_fwspec *fwspec, u32 virq) return 0; } +static int qcom_scm_query_waitq_count(void) +{ + int ret; + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_WAITQ, + .cmd = QCOM_SCM_WAITQ_GET_INFO, + .owner = ARM_SMCCC_OWNER_SIP + }; + struct qcom_scm_res res; + + if (!__qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_WAITQ, QCOM_SCM_WAITQ_GET_INFO)) + return 1; + + ret = qcom_scm_call_atomic(__scm->dev, &desc, &res); + if (ret) + return ret; + + return res.result[0] & GENMASK(7, 0); +} + static int qcom_scm_get_waitq_irq(void) { int ret; @@ -1880,42 +1901,40 @@ static int qcom_scm_get_waitq_irq(void) return ret; } -static int qcom_scm_assert_valid_wq_ctx(u32 wq_ctx) +static struct completion *qcom_scm_get_completion(u32 wq_ctx) { - /* FW currently only supports a single wq_ctx (zero). - * TODO: Update this logic to include dynamic allocation and lookup of - * completion structs when FW supports more wq_ctx values. - */ - if (wq_ctx != 0) { - dev_err(__scm->dev, "Firmware unexpectedly passed non-zero wq_ctx\n"); - return -EINVAL; - } + struct completion *wq; - return 0; + if (WARN_ON_ONCE((wq_ctx >= __scm->wq_cnt)) + return ERR_PTR(-EINVAL); + + wq = &__scm->waitq[wq_ctx]; + + return wq; } int qcom_scm_wait_for_wq_completion(u32 wq_ctx) { - int ret; + struct completion *wq; - ret = qcom_scm_assert_valid_wq_ctx(wq_ctx); - if (ret) - return ret; + wq = qcom_scm_get_completion(wq_ctx); + if (IS_ERR(wq)) + return PTR_ERR(wq); - wait_for_completion(&__scm->waitq_comp); + wait_for_completion(wq); return 0; } static int qcom_scm_waitq_wakeup(unsigned int wq_ctx) { - int ret; + struct completion *wq; - ret = qcom_scm_assert_valid_wq_ctx(wq_ctx); - if (ret) - return ret; + wq = qcom_scm_get_completion(wq_ctx); + if (IS_ERR(wq)) + return PTR_ERR(wq); - complete(&__scm->waitq_comp); + complete(wq); return 0; } @@ -2001,7 +2020,19 @@ static int qcom_scm_probe(struct platform_device *pdev) if (ret < 0) return ret; - init_completion(&scm->waitq_comp); + ret = qcom_scm_query_waitq_count(); + if (ret < 0) + return ret; + + scm->wq_cnt = ret; + + scm->waitq = devm_kcalloc(&pdev->dev, scm->wq_cnt, sizeof(*scm->waitq), GFP_KERNEL); + if (!scm->waitq) + return -ENOMEM; + + for (i = 0; i < scm->wq_cnt; i++) + init_completion(&scm->waitq[i]); + mutex_init(&scm->scm_bw_lock); scm->path = devm_of_icc_get(&pdev->dev, NULL);