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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id k5sm4128256pju.14.2019.12.03.15.42.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Dec 2019 15:42:47 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 1/4] target/arm: Add ID_AA64MMFR2_EL1 Date: Tue, 3 Dec 2019 15:42:41 -0800 Message-Id: <20191203234244.9124-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191203234244.9124-1-richard.henderson@linaro.org> References: <20191203234244.9124-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Add definitions for all of the fields, up to ARMv8.5. Convert the existing RESERVED register to a full register. Query KVM for the value of the register for the host. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 17 +++++++++++++++++ target/arm/helper.c | 4 ++-- target/arm/kvm64.c | 2 ++ 3 files changed, 21 insertions(+), 2 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/cpu.h b/target/arm/cpu.h index d403dc5947..cdf6caf869 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -864,6 +864,7 @@ struct ARMCPU { uint64_t id_aa64pfr1; uint64_t id_aa64mmfr0; uint64_t id_aa64mmfr1; + uint64_t id_aa64mmfr2; } isar; uint32_t midr; uint32_t revidr; @@ -1778,6 +1779,22 @@ FIELD(ID_AA64MMFR1, PAN, 20, 4) FIELD(ID_AA64MMFR1, SPECSEI, 24, 4) FIELD(ID_AA64MMFR1, XNX, 28, 4) +FIELD(ID_AA64MMFR2, CNP, 0, 4) +FIELD(ID_AA64MMFR2, UAO, 4, 4) +FIELD(ID_AA64MMFR2, LSM, 8, 4) +FIELD(ID_AA64MMFR2, IESB, 12, 4) +FIELD(ID_AA64MMFR2, VARANGE, 16, 4) +FIELD(ID_AA64MMFR2, CCIDX, 20, 4) +FIELD(ID_AA64MMFR2, NV, 24, 4) +FIELD(ID_AA64MMFR2, ST, 28, 4) +FIELD(ID_AA64MMFR2, AT, 32, 4) +FIELD(ID_AA64MMFR2, IDS, 36, 4) +FIELD(ID_AA64MMFR2, FWB, 40, 4) +FIELD(ID_AA64MMFR2, TTL, 48, 4) +FIELD(ID_AA64MMFR2, BBM, 52, 4) +FIELD(ID_AA64MMFR2, EVT, 56, 4) +FIELD(ID_AA64MMFR2, E0PD, 60, 4) + FIELD(ID_DFR0, COPDBG, 0, 4) FIELD(ID_DFR0, COPSDBG, 4, 4) FIELD(ID_DFR0, MMAPDBG, 8, 4) diff --git a/target/arm/helper.c b/target/arm/helper.c index f1eab4fb28..70f2db5447 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6825,11 +6825,11 @@ void register_cp_regs_for_features(ARMCPU *cpu) .access = PL1_R, .type = ARM_CP_CONST, .accessfn = access_aa64_tid3, .resetvalue = cpu->isar.id_aa64mmfr1 }, - { .name = "ID_AA64MMFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, + { .name = "ID_AA64MMFR2_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 2, .access = PL1_R, .type = ARM_CP_CONST, .accessfn = access_aa64_tid3, - .resetvalue = 0 }, + .resetvalue = cpu->isar.id_aa64mmfr2 }, { .name = "ID_AA64MMFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 3, .access = PL1_R, .type = ARM_CP_CONST, diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 876184b8fe..482e7fdfbb 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -549,6 +549,8 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) ARM64_SYS_REG(3, 0, 0, 7, 0)); err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr1, ARM64_SYS_REG(3, 0, 0, 7, 1)); + err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr2, + ARM64_SYS_REG(3, 0, 0, 7, 2)); /* * Note that if AArch32 support is not present in the host, From patchwork Tue Dec 3 23:42:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 180782 Delivered-To: patch@linaro.org Received: by 2002:a92:3001:0:0:0:0:0 with SMTP id x1csp2222377ile; Tue, 3 Dec 2019 15:57:21 -0800 (PST) X-Google-Smtp-Source: APXvYqwnrUROSB571RYOdNPth8CTPyZq6SvIi0V8UJ7wX1VGZHIbQqHa3hQCvPKt13kHL8LSuzic X-Received: by 2002:a50:d849:: with SMTP id v9mr942165edj.105.1575417440934; Tue, 03 Dec 2019 15:57:20 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1575417440; cv=none; d=google.com; s=arc-20160816; b=AlnY3RsMgK4R3ScaIeu3rToaiJwnyCsnebG6JpkMok8aTbWouXlXD29BIlNScahjB5 ID5RfLX/qPXwKjg/Ee6elb/53HwHtfMtkpZ+oA2uFsgfQ3wOQi6mXg+0rwSm3uOEDLbB tXn8nik8yO7DrZ8plCIu2FtiRKn3UDVRE1iZ+rHAw+EZBHSG4pKc43+sn0g6Qr5rFzJa Vg9P1LeTUFNqR1fjeJZd6Q33jPUYk16g+W7R7JmhdGSDtPoqZACU4yTzbTd5ZdHbpwEn CJi1nHChTkVQBTPkxpiZb8VhKzkbFOnuoIF152o+DJxCPWTbtGp9sYlmXPRrUX8gNG2q JOzA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:references:in-reply-to :message-id:date:subject:to:from:dkim-signature; bh=7MVIDNVevAOck6qQcN8WApev5jEl5Rubg+oXUTbOUTk=; b=I0eaIFjKYePYTr6ZOX7rPGbG8SXjs7b2fSq0sAFrod5iR18pJcIGNkigS88RqXlWhy tamDhUKGAxljDrASByHobHbMjLwIrhrWL9zfblPybJgtoRIbKsT/dI1LShHXgoh0rDn5 j7LzEemDlZFjvyYJAn2cdWFOzMBuc8iPR2kRrmJ2IruGXXfKpT3K8i73k9D0wbAAmnFZ sQxgr5VvZD92UC+YD6jY3NIfnx1I5etqPoOI8w/gO2ra2nwgVrj+9stR8nFEos9T8+IL OEgXoygelW849XrdNJCjwzZXqwL9nup1yLhDFQumN7ay/OrS+VOoesVSpZs0nmhJcSEr UJhA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=P4ZZiAfx; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id k5sm4128256pju.14.2019.12.03.15.42.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Dec 2019 15:42:48 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 2/4] target/arm: Update MSR access to UAO Date: Tue, 3 Dec 2019 15:42:42 -0800 Message-Id: <20191203234244.9124-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191203234244.9124-1-richard.henderson@linaro.org> References: <20191203234244.9124-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::52b X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/cpu.h | 6 ++++++ target/arm/helper.c | 21 +++++++++++++++++++++ target/arm/translate-a64.c | 14 ++++++++++++++ 3 files changed, 41 insertions(+) -- 2.17.1 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index cdf6caf869..dd284ba5c7 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1228,6 +1228,7 @@ void pmu_init(ARMCPU *cpu); #define PSTATE_IL (1U << 20) #define PSTATE_SS (1U << 21) #define PSTATE_PAN (1U << 22) +#define PSTATE_UAO (1U << 23) #define PSTATE_V (1U << 28) #define PSTATE_C (1U << 29) #define PSTATE_Z (1U << 30) @@ -3598,6 +3599,11 @@ static inline bool isar_feature_aa64_ats1e1(const ARMISARegisters *id) return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >= 2; } +static inline bool isar_feature_aa64_uao(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, UAO) != 0; +} + static inline bool isar_feature_aa64_bti(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0; diff --git a/target/arm/helper.c b/target/arm/helper.c index 70f2db5447..8941a6c10f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4131,6 +4131,17 @@ static void aa64_pan_write(CPUARMState *env, const ARMCPRegInfo *ri, env->pstate = (env->pstate & ~PSTATE_PAN) | (value & PSTATE_PAN); } +static uint64_t aa64_uao_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return env->pstate & PSTATE_UAO; +} + +static void aa64_uao_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + env->pstate = (env->pstate & ~PSTATE_UAO) | (value & PSTATE_UAO); +} + static CPAccessResult aa64_cacheop_access(CPUARMState *env, const ARMCPRegInfo *ri, bool isread) @@ -7464,6 +7475,16 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, ats1cp_reginfo); } #endif + if (cpu_isar_feature(aa64_uao, cpu)) { + static const ARMCPRegInfo uao_reginfo[] = { + { .name = "UAO", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 4, + .type = ARM_CP_NO_RAW, .access = PL1_RW, + .readfn = aa64_uao_read, .writefn = aa64_uao_write, }, + REGINFO_SENTINEL + }; + define_arm_cp_regs(cpu, uao_reginfo); + } if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu)) { static const ARMCPRegInfo vhe_reginfo[] = { diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 7f5a68106b..2b6846ef01 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1601,6 +1601,20 @@ static void handle_msr_i(DisasContext *s, uint32_t insn, s->base.is_jmp = DISAS_NEXT; break; + case 0x03: /* UAO */ + if (!dc_isar_feature(aa64_uao, s) || s->current_el == 0) { + goto do_unallocated; + } + if (crm & 1) { + set_pstate_bits(PSTATE_UAO); + } else { + clear_pstate_bits(PSTATE_UAO); + } + t1 = tcg_const_i32(s->current_el); + gen_helper_rebuild_hflags_a64(cpu_env, t1); + tcg_temp_free_i32(t1); + break; + case 0x04: /* PAN */ if (!dc_isar_feature(aa64_pan, s) || s->current_el == 0) { goto do_unallocated; From patchwork Tue Dec 3 23:42:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 180779 Delivered-To: patch@linaro.org Received: by 2002:a92:3001:0:0:0:0:0 with SMTP id x1csp2214390ile; Tue, 3 Dec 2019 15:47:43 -0800 (PST) X-Google-Smtp-Source: APXvYqw8GVbxTIoaVmOlaUiAotdW2uMiasYHuH7hsXR2x4K3L3Powf+7qmAd8yq8n1QCVBHSapdw X-Received: by 2002:a17:906:e94:: with SMTP id p20mr1699052ejf.57.1575416863446; Tue, 03 Dec 2019 15:47:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1575416863; cv=none; d=google.com; s=arc-20160816; b=id/U89iYqRUj8fib0d6H9/mp6lEatsxuUlDwatDyoWq+wPji9edi3C5LM/ZAq0C/3y BlYZjdW0Mppnz83jjb/HKf64ZkF809kAjFsB6+dzwRbpUL6WO6h6lE5wJmtK/1KoXTA/ pWMSU4WwkMpxPtARyumfLtVNWnebAx8LXVi9gkiviBdZ8jZXLbz+e4K6ahp+K5NZ8Am9 ILNkYiw1iO437clQaHQt/ipi4Ev1e8i9qOT4eCoibBoh7TvqhUWqn5AEsGYxRZ7O+dak e3ugoPfH7FPDdaL/9yx7os+ygOd1qO2EeGPEJnBqQMu5yFA+P68ly5kzFa6IJ2k0Du9h HPXw== ARC-Message-Signature: i=1; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id k5sm4128256pju.14.2019.12.03.15.42.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Dec 2019 15:42:49 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 3/4] target/arm: Implement UAO semantics Date: Tue, 3 Dec 2019 15:42:43 -0800 Message-Id: <20191203234244.9124-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191203234244.9124-1-richard.henderson@linaro.org> References: <20191203234244.9124-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We need only override the current condition under which TBFLAG_A64.UNPRIV is set. Signed-off-by: Richard Henderson --- target/arm/helper.c | 41 +++++++++++++++++++++-------------------- 1 file changed, 21 insertions(+), 20 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/helper.c b/target/arm/helper.c index 8941a6c10f..6d7a8349b5 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -12050,28 +12050,29 @@ static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, } /* Compute the condition for using AccType_UNPRIV for LDTR et al. */ - /* TODO: ARMv8.2-UAO */ - switch (mmu_idx) { - case ARMMMUIdx_EL10_1: - case ARMMMUIdx_EL10_1_PAN: - case ARMMMUIdx_SE1: - case ARMMMUIdx_SE1_PAN: - /* TODO: ARMv8.3-NV */ - flags = FIELD_DP32(flags, TBFLAG_A64, UNPRIV, 1); - break; - case ARMMMUIdx_EL20_2: - case ARMMMUIdx_EL20_2_PAN: - /* TODO: ARMv8.4-SecEL2 */ - /* - * Note that EL20_2 is gated by HCR_EL2.E2H == 1, but EL20_0 is - * gated by HCR_EL2. == '11', and so is LDTR. - */ - if (env->cp15.hcr_el2 & HCR_TGE) { + if (!(env->pstate & PSTATE_UAO)) { + switch (mmu_idx) { + case ARMMMUIdx_EL10_1: + case ARMMMUIdx_EL10_1_PAN: + case ARMMMUIdx_SE1: + case ARMMMUIdx_SE1_PAN: + /* TODO: ARMv8.3-NV */ flags = FIELD_DP32(flags, TBFLAG_A64, UNPRIV, 1); + break; + case ARMMMUIdx_EL20_2: + case ARMMMUIdx_EL20_2_PAN: + /* TODO: ARMv8.4-SecEL2 */ + /* + * Note that EL20_2 is gated by HCR_EL2.E2H == 1, but EL20_0 is + * gated by HCR_EL2. == '11', and so is LDTR. + */ + if (env->cp15.hcr_el2 & HCR_TGE) { + flags = FIELD_DP32(flags, TBFLAG_A64, UNPRIV, 1); + } + break; + default: + break; } - break; - default: - break; } return rebuild_hflags_common(env, fp_el, mmu_idx, flags); From patchwork Tue Dec 3 23:42:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 180781 Delivered-To: patch@linaro.org Received: by 2002:a92:3001:0:0:0:0:0 with SMTP id x1csp2217912ile; Tue, 3 Dec 2019 15:52:09 -0800 (PST) X-Google-Smtp-Source: APXvYqwpU76BxQSB1CChSopHJmZy18OI8AvI3p1FclcTQSlMQuEDLO160pfqOk5Kkh7kcyYvtXoI X-Received: by 2002:a05:620a:4e8:: with SMTP id b8mr112614qkh.182.1575417129526; Tue, 03 Dec 2019 15:52:09 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1575417129; cv=none; d=google.com; s=arc-20160816; b=XnK8b45hCWJjk4q6obu5cqOkotGZeOxwgSQG5ss9uORVWFM8gVXO/UeYWjBk9zhY0P NQEcINdUpT2JZ1Ylb3z2t5VBgBAYjUNO7aafRhvxFrU2+9TtEESzHXjmRAUZIuYh6T8l yACi5kwJ4C+crGEccNWWFBzi9jnKy3ncqNXoGFvAvclVAU8+6IFrqFFhGXPr3k68Qq+Z Ou0hkXDIyqBdJ4PQo05rDko+Jra1HztqHAHijHWlS3K4ZfQdqmn2vkJzwzEo50Iegtvq 93vXLbHR1zXaolvOryTxctVCQjmzKy09xABYufP55WIQfEm08DWRdFm91xUnuMUXf8Rz I0vA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:references:in-reply-to :message-id:date:subject:to:from:dkim-signature; bh=LDEaaXMkISHBRBQq2wWOEn0yi/1F+Nwrnq77hCMsb2U=; b=bKCp4nVlibJCgFwGa1YmqZqctd9GitaQ2vMWCfNZoplyNFfaWZUd9xNBWKrj+DCQKM tZtmfgeZWT5rkm1tkNTl7riMCwF+oQBtwxCBovsqQTEbKGKC+I/PXcYoJ2kEFyCaQ3Se de0IS7kMMDHjNSOfbigBlbYcLd2h9g0Tt5HIaTYDM8DruJMxvKRPifmEzaI1e7xmMzvm zEEBtYKyKfG3YpLqu+PjMyfwk2Hhx9XyLEvxAxE38+dAeH2ZxiwmgKXKYpvpidPwSP3i SJgDnMgazA3OfRH6rnAM0vrHKta+++wuZ2uDUJZtSIjYxae3VcOJ/1MIz0J7IMTKZ9xy 3RCA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="bT2K3/kC"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id k5sm4128256pju.14.2019.12.03.15.42.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Dec 2019 15:42:51 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 4/4] target/arm: Enable ARMv8.2-UAO in -cpu max Date: Tue, 3 Dec 2019 15:42:44 -0800 Message-Id: <20191203234244.9124-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191203234244.9124-1-richard.henderson@linaro.org> References: <20191203234244.9124-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/cpu64.c | 4 ++++ 1 file changed, 4 insertions(+) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 9399253b4c..03377084e3 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -674,6 +674,10 @@ static void aarch64_max_initfn(Object *obj) t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* ATS1E1 */ cpu->isar.id_aa64mmfr1 = t; + t = cpu->isar.id_aa64mmfr2; + t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); + cpu->isar.id_aa64mmfr2 = t; + /* Replicate the same data to the 32-bit id registers. */ u = cpu->isar.id_isar5; u = FIELD_DP32(u, ID_ISAR5, AES, 2); /* AES + PMULL */