From patchwork Fri Oct 25 15:03:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 838455 Received: from mail-lf1-f44.google.com (mail-lf1-f44.google.com [209.85.167.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9A66918870B for ; Fri, 25 Oct 2024 15:03:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.44 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729868639; cv=none; b=Tygtmo4VN6h5DAOZtrZI4n2T1DTupyIwBwaRHJb7B0oppFU9yPBK1gMWwrhyuZKXiu4buyjSHQFLyQ6H7JsogqLiJFfqSmKCy2y5kJN4IjpUmoAFuQfEfCZv0B2BHqZckf8RcAbZ1hDnKSP+2cm/IrcYmDxKhCxt/LfVdO3X/ts= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729868639; c=relaxed/simple; bh=xfoORnG7BJgpYsszuYcVMwpN0RRab8ojk9gSAD6d/zQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=kZ/uZzW1whoCALk3ABvZdOWjVlIwhf2qmcEkDpnFXzRm9VDFL2Vh5kO+bcYs5mLgRA49bTVm6nGLbwbY2omW/VjcMKKfAdujbEOa1BMfywhAXu43CfD4d9DHrB41HkqTLbiCpdvU14NdyoznqgWbD8R6cZq3Vk9XqDxOgMeumig= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=B+7f2XCD; arc=none smtp.client-ip=209.85.167.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="B+7f2XCD" Received: by mail-lf1-f44.google.com with SMTP id 2adb3069b0e04-53a007743e7so2662084e87.1 for ; Fri, 25 Oct 2024 08:03:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1729868636; x=1730473436; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=vBMgQWjciUW4UHYAr1mygReqy4wqLPHJvE0xLDCFl18=; b=B+7f2XCDbXC9VkLlCJO7eOhlicgVIzWbgaaNbeF6kT6fa6F/QbcT0jH9GnojaR8tKC H23BkqduDUVCkNV9dPUe4i7GbIAtTX/JDV0GYXIk4sDhAXbIM85Hf9V1CXH4sWE6M56p L57di7/7piCyMb/AoLhZhodRAx4tZC8WqZ8K4DbK5n4a9ADWqL13Xqa0XKW9AHyU9lfM S2b1l1gT5Sb6Z1ec7iebACFkD7QDHTg47eyo8yLGubKxf97z0jDI3xKuRre/QfbiximM XWOa2huxBzcgaM17AuEB+4BuicGuK3t/SjreJ39AposWO0k4+Dkh4XseVsOjBQnS7JGZ kAMQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729868636; x=1730473436; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vBMgQWjciUW4UHYAr1mygReqy4wqLPHJvE0xLDCFl18=; b=XTmVvIHewcFAqZ7ANGrs0nkAi1L/qSeJvM6QoBoxqu4ybeW0Lubm3EX2I9z24Xv65g M/lZVofcvORWvcvZyK/gXfZ0M2KfIsQKFXKgrz5iFE3vn6Xdf/dv4vHmDdIgmbbBGzLZ WpK03KJtDHrmF2ilYsv0SL0mmcneI6h2EIeLbGjdnkWkMnvEWGejEXgPWp9dLKSKs1uZ Bc/sudRnJhLTtGuFQ9XxTpEjoART5QLkAJloCRlz2i/8aQvR/ka83waM175YFdEkh8xT eCXsGzqik9MBAoeRBRYuVFw+7l3v2WnKHPxqmj7FIuJljGWMMQ6j9PrhL/Xt+9vRmVy7 kpFA== X-Gm-Message-State: AOJu0Yz1LoFiPeMgMeXB3sMhCUwUiLsuNF0ieCFXEleakWlOUVm4jPQ7 ZGbdW7pxgTGnH9HY/EIAwPHyd7zzDk4NTqWK1QjRgP5Lw3VmiTpVcCiptEZcvtA= X-Google-Smtp-Source: AGHT+IHw33o6Q6BEaMaaqtnQ0f21ONG+7koUkJlYb5gDEIHecgviYqz+I+hT7AyKKDix7j48FckOaw== X-Received: by 2002:a05:6512:2344:b0:539:f8c7:4211 with SMTP id 2adb3069b0e04-53b1a33e6a7mr5295180e87.26.1729868635566; Fri, 25 Oct 2024 08:03:55 -0700 (PDT) Received: from [127.0.1.1] (2001-14ba-a0c3-3a00-70b-e6fc-b322-6a1b.rev.dnainternet.fi. [2001:14ba:a0c3:3a00:70b:e6fc:b322:6a1b]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-53b2e10a915sm209542e87.12.2024.10.25.08.03.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Oct 2024 08:03:54 -0700 (PDT) From: Dmitry Baryshkov Date: Fri, 25 Oct 2024 18:03:35 +0300 Subject: [PATCH v3 01/11] dt-bindings: clock: qcom,rpmhcc: Add SAR2130P compatible Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241025-sar2130p-clocks-v3-1-48f1842fd156@linaro.org> References: <20241025-sar2130p-clocks-v3-0-48f1842fd156@linaro.org> In-Reply-To: <20241025-sar2130p-clocks-v3-0-48f1842fd156@linaro.org> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das , Neil Armstrong , Philipp Zabel , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=907; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=xfoORnG7BJgpYsszuYcVMwpN0RRab8ojk9gSAD6d/zQ=; b=owEBbQKS/ZANAwAKARTbcu2+gGW4AcsmYgBnG7NSkS5DbNLl9SXHQKahpCgXEmSAddeHRTCAY OLsGm3v0nqJAjMEAAEKAB0WIQRdB85SOKWMgfgVe+4U23LtvoBluAUCZxuzUgAKCRAU23LtvoBl uC1+D/950ATdnQeApqf1ew/BSm4GNQ8lbW7sSMJSXhEJZHW9UumPK01hVEcevcI3+XsB+rbQdOO xRiQLSSyBum7A8r6xoNcVU7FGqBhA0v4w2uhdRN7jFDS5ml0Ch9FL6XPgngmclkk3BZUYUg2Vqd ScksYYHqjtPq2HjDylgVdb99i1CC3Y4KIQV5x6BM5v8YcrZTcgyR0+DRvNOe1auo+ZQ+CwOoNCJ wKaEzYHXUtaZKfUs1GzqyqXe5Al0scWORygKzp5ZksjRfoU3BwmEEKlXOFN6IlNs7Mexkl4elSi C3rRH8CcjPzYKZzqgRWq4NlxdRWjg/+INj/y8/M5YIn/XBfkw3VNGx+BU3IeAh9kf11AUxsQdP3 hrAB3UwNSbm3iPNmqLyls4k3gRgGkOAEPdmsHjif4sBDS+aLm7cBsRHZ8D34jlV+lvt9icrDm0O lyc9LoCJCHQGawojo0Qk64PZDCXEqrxSwf6EWATCL16ZUuVTIliPemz4lTa0ETUuHcFy1soRHq0 ZEew9pz+3CNXzE8fNgsCQdw819skQkp0qG+F0fdUa2b4mXhE8Q8v3DJEmIFmIsRGJJW9S8hGiDB cTfQr+7JMVHET8qGpI1Dgp5cgsgAwAXOIYYbUbOHyVRECNQul21cgoc24VNMybTuiuU/jFiWAW2 N51BhYYiQAKfsBQ== X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Document compatible for RPMh clock controller on SAR2130P platform. Acked-by: Krzysztof Kozlowski Signed-off-by: Dmitry Baryshkov --- Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml b/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml index ca857942ed6c08cd4b906f18f6a48631da59ce9a..a561a306b947a6933e33033f913328e7c74114bf 100644 --- a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml @@ -19,6 +19,7 @@ properties: enum: - qcom,qdu1000-rpmh-clk - qcom,sa8775p-rpmh-clk + - qcom,sar2130p-rpmh-clk - qcom,sc7180-rpmh-clk - qcom,sc7280-rpmh-clk - qcom,sc8180x-rpmh-clk From patchwork Fri Oct 25 15:03:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 838454 Received: from mail-lf1-f47.google.com (mail-lf1-f47.google.com [209.85.167.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CA55A209F57 for ; Fri, 25 Oct 2024 15:04:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729868646; cv=none; b=OXDrzpoNLBsVMcSLpk4RLKFjOmGGh6V2t7DYyAbLJ/gMc27bFLfsXe0lEJhkK/hloVXjsKqTk/dEv4daLbHDbwAnJLzqfCRQBsNz1ek7x9rsderB4g//NCZjaz4w1q0AqJK17puQFi+vSayKzppeviIvXXZibG/SXtMe46tVOZo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729868646; c=relaxed/simple; bh=mHXA679fTLSBfLWh8pBmR4AEa9V2nbcklgPIdka6VnY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=BDv4RGN3C0UpuituwyeHvUQyiNG5czOC2jED/6MFslmdoX5H+2pBGgyv+eVO6GOwRg6Ntzd2/GxvaseOMK6Zqz3Evwk/8ygPiusi3nJeYPFFOlblLWcHVB9/+/6Ey2+GH251JW1KvqWzwYf+iubUD+7ipKWxoyjkVc4neK9tFEk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=g3nrBNY9; arc=none smtp.client-ip=209.85.167.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="g3nrBNY9" Received: by mail-lf1-f47.google.com with SMTP id 2adb3069b0e04-53a0c160b94so2582588e87.2 for ; Fri, 25 Oct 2024 08:04:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1729868641; x=1730473441; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=Yljl+967ibX2I7aSbp1Ln8dspkbFoWgzBqO671H8u2g=; b=g3nrBNY9zmK9Yo+Odc+0gHmAvx+6h3uyNPia5WebrEYtliJCbhJi24DGvYD423bvYL dmc6/8ceSZLmGpAdKnNHLDhqaT6mHnk+bXHhMObimtigBQd8eo6CsWDYOJ6v8NnJEmOX hGsM7U52yr7BU1PL9hB9zjYp8uj1bsqZuzVtc4tEfrYKJVDtfm161leMdpwK2Z2EgeVH BjY6bhvtXtEPMrLm1Msnx2LOsgCVkwKXYpcwcSHoBBnlWsQ3yeAdv2+nnipSQCQDzzgy SQnaIb/37udVqKGcMMaySsvoF9Rb4Ooq/t/qI3RA8+AO+ZzMqTNJtDEu7TuY6V7fkwd7 t8/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729868641; x=1730473441; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Yljl+967ibX2I7aSbp1Ln8dspkbFoWgzBqO671H8u2g=; b=Wh2R+R7miGgZ0Yaql1lVp5L0X+mywlS/NMIL31OgDtgCLECzi7zxkn6f3m8ljglQJV Z2zLyXQ1nImCkVSopGgIks78h1LWern5TN7K42p7yGJx6Z4i8D51u1urqhZiPNK4QZqz 8ecpAsshD7w/BQTEjLQSLF6T2CnisJgfksogOBVxG+rzCYkzxrCq5SxPwMPo1JI9oLJ2 Pbe6X/sQ90f5NbFXoqu2Flpi0xSJkw5TIY9IUpyDbmUmTfEZe1exnmGhFMiWE0RK76ez D6U/iL2lGPXhXnSrt7rgPEYdx7P7lFLm0pkecesPkRJsRulU5V4ropyybhnfa5dsDxoM +lHw== X-Gm-Message-State: AOJu0Yzm/LT7e1GzU2HP5UR7JrawMJJyuJF6S2HRxgAt+T95FVHTYYeL FhbSCv6HN9FOTzIFDMTzSiukiQKE+XrK1uCSlJfGAzmf4U5cliIpcTlsNwevnVA= X-Google-Smtp-Source: AGHT+IGRdVgNIQNl7U761e1+szjrsqjcP0+l1q+achwbWKzkFkLd8qICXqlF0ukCjOl5ZqZ44TuiTQ== X-Received: by 2002:a05:6512:3f17:b0:535:645b:fb33 with SMTP id 2adb3069b0e04-53b1a2f21b5mr5072553e87.2.1729868640664; Fri, 25 Oct 2024 08:04:00 -0700 (PDT) Received: from [127.0.1.1] (2001-14ba-a0c3-3a00-70b-e6fc-b322-6a1b.rev.dnainternet.fi. [2001:14ba:a0c3:3a00:70b:e6fc:b322:6a1b]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-53b2e10a915sm209542e87.12.2024.10.25.08.03.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Oct 2024 08:03:59 -0700 (PDT) From: Dmitry Baryshkov Date: Fri, 25 Oct 2024 18:03:37 +0300 Subject: [PATCH v3 03/11] dt-bindings: clock: qcom,sm8550-tcsr: Add SAR2130P compatible Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241025-sar2130p-clocks-v3-3-48f1842fd156@linaro.org> References: <20241025-sar2130p-clocks-v3-0-48f1842fd156@linaro.org> In-Reply-To: <20241025-sar2130p-clocks-v3-0-48f1842fd156@linaro.org> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das , Neil Armstrong , Philipp Zabel , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=992; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=mHXA679fTLSBfLWh8pBmR4AEa9V2nbcklgPIdka6VnY=; b=owEBbQKS/ZANAwAKARTbcu2+gGW4AcsmYgBnG7NTNKoQ4rWqeM/jEqOVW9ZOebj6juoiFbSKC oo+Oh5dE8yJAjMEAAEKAB0WIQRdB85SOKWMgfgVe+4U23LtvoBluAUCZxuzUwAKCRAU23LtvoBl uLVYD/4hrM1vmtXA2QPfaA51PEgQK1wH3OoQeoXsH9h/YcrVZqsLL9R2bGPGhvBnZ8XcUhs18Oz ft+VyfR2VS0CGDXwJBOREEl/5KYqsD/tff0oNWQiFn6LvLYbCpr7BYpuiaNdQRyjleeeEm2Dip/ +a/1oNNIeTmNmxqFC1cb3KGr6i7sqCoTO/fK6wctIXe1LU3mcETHCwOrENzU/De4kK4pBmR5EUE YtHkrYAJUFcx2LOPoIFDOhW36rG1quJ4Kpd79jkEW7DuVn0FVqXu1fRi8qGGFev2YBHMe+o8UW9 inLQ11/EB3DVx2T/dlwJcxLXOhRlZ/LTVLqM4DW/rfZ0eUnUK3PZ/O/VCAJH7xSX8KMMRehAcDn Mp8+RffetNEUmkiasBCSHbOLfA45ZW+iCP2G8qa2U4EKnc+3rVEjGENpUoYUwuTO3syBkDrbUCO KKu9i89Uh1hj4wUp/tfS7dHtA9WQzymQi2UX97Pc1FecTg1GZ3PH1ISp6Gv2qUQtupqiunLp8oU WD4tPZzhHQedUjaMp/9KvGCfx63iP9fVeXWvYwlifqYZcuaDGYX9ucGaAk+R8W4Ep8B01qd1jzU Mv4ThPBUYvQIB5Z+yrzGpUGdMdGORe7YJ92kKG6Z/mTpd+ITJ4BhMOxe7RUg/NbNL06lbm1QEOD 4o1o3LI+uPgqkqA== X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Document compatible for the TCSR Clock Controller on SAR2130P platform. It is mostly compatible with the SM8550, except that it doesn't provide UFS clocks. Acked-by: Krzysztof Kozlowski Signed-off-by: Dmitry Baryshkov --- Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml index 48fdd562d7439424ebf4cc7ff43cc0c381bde524..3b546deb514af2ffe35d80337335509e8f6a559d 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml @@ -21,6 +21,7 @@ properties: compatible: items: - enum: + - qcom,sar2130p-tcsr - qcom,sm8550-tcsr - qcom,sm8650-tcsr - qcom,x1e80100-tcsr From patchwork Fri Oct 25 15:03:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 838453 Received: from mail-lf1-f54.google.com (mail-lf1-f54.google.com [209.85.167.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9495F20D4EA for ; Fri, 25 Oct 2024 15:04:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729868649; cv=none; b=qi8KofYwD+m0lr4LJAHh1T0L5lczEaIyw7wR+80YBJe/MuTBLcp1bPUPtWcoRtDSV4hdStIXQr03LjBHZLQBwuE8iBae/IYZ7weptoZWw1HSkf4ccMJkOY5FoHyCgzH/NGrOdDI/ICuhjDQRIcyvePmJRvtqnEqqQzqyBs+ZPJ0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729868649; c=relaxed/simple; bh=doO/a916moGA8DWgcEw9MEXPijwB7ll6ZA8YQOQZTOA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=WewON3O8MMoI1aPX0/ml9x/kwFya2iwsFZkUguWAR5x9GYgueYPM/9F4Rz5BU9iRm+o7AydA4d6GhOjhUFcSeOWweTq9AULqlhMk1IzPDSuVOlg+UXxTs6EkiUxlPYkoif1kpuLIOtPTNwM9N9qjs9udphauCT4DyT4mJN3t7uA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=OhTB/rAx; arc=none smtp.client-ip=209.85.167.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="OhTB/rAx" Received: by mail-lf1-f54.google.com with SMTP id 2adb3069b0e04-539ebb5a20aso2266807e87.2 for ; Fri, 25 Oct 2024 08:04:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1729868645; x=1730473445; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=Et/ChhQ8OUXatHb7KnUo7g0jzZYAGHhogo25hpK7iKY=; b=OhTB/rAxSlK9XXUYM1OYQUCdI/bidx8s4kkD54bRq7tD/CpM0fuMuURXMSrluHls2/ HxgHWn22+6QKvUWT72QTXNe9cNVed4yZ82ChW6k4YkhDWrM27JINRww9ldHPWKFOgTi2 5oCmjdirMk1VmtnoqjHQfz+SxLkq2FlJnNsI8FJWm20QPfrhMP/pKSawiXkqmuyvz3AK qlmrvK3KIcGHOnMAkYDCsyrxY01ycf/IdY5xeom9YAq8xcttZS8S35+RxbIDT1bBU4Ue pssuR4kTQKWstLyx2HRU4M9u10OyjT4eScWial8kCyAMHpEMZ2KuP5d9HgHNAFPTlPlC dCvw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729868645; x=1730473445; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Et/ChhQ8OUXatHb7KnUo7g0jzZYAGHhogo25hpK7iKY=; b=OIDJAUlXMEEe7iOtoZ0cpmQ2zG3f39RoLmjsTYg0qNOGU7nThBS8eB2jHYY7W7KLBW q4HLdkG3rn+4PvHWk3Rxnq+oZmgLUjAq89Otjw+1Jr+0ayp9gdXiXlALBUOkfgQ+FsAW q4HaEvn3S7Y2aoLTFFiRfTYhObYyk/ACLdGAJzePZpF4jbFzkwklsF89GDP4ZSfXt0QM CBa2ILdkz1v3CaxOInF0CvKwXn9RvCylyVan8Cg7aZmZOaJeidyWnmuCOt/ZfM5ir+xS pN3C6sb4ch4Xwiy/dDhd5jxyUS1ZH+TlIz0+Udt5PKlP5Ff+cMGv0qxs4s4hQdlCzUkd wiFw== X-Gm-Message-State: AOJu0YwUFrNvQBrFHg+OATHrx7k4dZhhtWYr/hw/j6DM62gh5EraqgGk nZQfo+msvSpO4fcL1GqLMXufecXDkhUurk0LIlYkUU41hJcZoTvThpoZB31ka8Q= X-Google-Smtp-Source: AGHT+IGtY1qTkN15xcNE0g0BfiJop+L6FB6xIVMg1QDWDxk47fxYONTxiCffT+2S+uNDPx5qh5Mcew== X-Received: by 2002:a05:6512:159d:b0:530:e323:b1d0 with SMTP id 2adb3069b0e04-53b1a2f4d2dmr5736485e87.9.1729868643167; Fri, 25 Oct 2024 08:04:03 -0700 (PDT) Received: from [127.0.1.1] (2001-14ba-a0c3-3a00-70b-e6fc-b322-6a1b.rev.dnainternet.fi. [2001:14ba:a0c3:3a00:70b:e6fc:b322:6a1b]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-53b2e10a915sm209542e87.12.2024.10.25.08.04.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Oct 2024 08:04:02 -0700 (PDT) From: Dmitry Baryshkov Date: Fri, 25 Oct 2024 18:03:39 +0300 Subject: [PATCH v3 05/11] dt-bindings: clk: qcom,sm8450-gpucc: add SAR2130P compatibles Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241025-sar2130p-clocks-v3-5-48f1842fd156@linaro.org> References: <20241025-sar2130p-clocks-v3-0-48f1842fd156@linaro.org> In-Reply-To: <20241025-sar2130p-clocks-v3-0-48f1842fd156@linaro.org> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das , Neil Armstrong , Philipp Zabel , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio , Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3379; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=U8SwElc6O/aMG3Pi0A0hWuxY5S0AlYAxeI/Vjj5b5Qw=; b=owEBbQKS/ZANAwAKARTbcu2+gGW4AcsmYgBnG7NTltGGykly5DZ7ohu+6Sy0FnciNQ9ys7G1K I/GA3gowEuJAjMEAAEKAB0WIQRdB85SOKWMgfgVe+4U23LtvoBluAUCZxuzUwAKCRAU23LtvoBl uAyBD/9n5aFPGXGGrvd4VTK+ArYu1hNwnakVHkgvI2tCYpiMs9PMPY2b97yCz94brmzscDLgDFP u6ggwrCA0eYoHy+0VQSAJO07Q5yqW/YvsUzBMnMUl68YWfWPnBjYMpASaFrA3jKyVPFshfi+aiU Vzmq7eZqna4h0hAELcg/12O+1U9eZ30BN3T0+VcvzOE1MfzQ0QZ8prDF9ky9Si3DyoA9Au041s3 s6IQ+w6zL4fSKTbeAGUfGEPpvTcGoTl5nCradIVS107dYo8vBVxYGwWanikJlfItCPDabSidJp/ svtlGGwMuvCLTbIxtYpXLBx0IcBN7YWIcQN57RScGpCmEdUML4ukD6xIPgWkEFBZvgaVkJJMZab erwxsDn5D98NSTFnIL0m5bSuSGENZFterU86YzanetFf/WYMHFGbukeQikceOqKDtmUIXCLId2w uqwf82PfZcv+d+xWX5tbZEMDNeGyExsvMKzMl4umIAxPQqyC6ejG0lItesV37/zQibbQnqXFj2l kO2xqXsaqVql3hh2VU13e56pKgxaIDn1jnRObMgU2yqprTE+1wipdeddJBStA64ghvkYYaEbkcI 9/4WZzLtP6mrq3q0uOqwAhxu6KAuL7RtXapzgQGkMlH5sfaTy6sfhapPSCiz8nSNd2AZlmHLbAM n1FZbI9fxJr68Zw== X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A From: Konrad Dybcio Expand qcom,sm8450-gpucc bindings to include SAR2130P. Signed-off-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski Signed-off-by: Dmitry Baryshkov --- .../bindings/clock/qcom,sm8450-gpucc.yaml | 2 ++ include/dt-bindings/clock/qcom,sar2130p-gpucc.h | 33 ++++++++++++++++++++++ include/dt-bindings/reset/qcom,sar2130p-gpucc.h | 14 +++++++++ 3 files changed, 49 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml index b9d29e4f65ded538c0ac8caae5acb541c9f01f41..5c65f5ecf0f387f30ae70a8f2b25d292f6092133 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml @@ -14,6 +14,7 @@ description: | domains on Qualcomm SoCs. See also:: + include/dt-bindings/clock/qcom,sar2130p-gpucc.h include/dt-bindings/clock/qcom,sm4450-gpucc.h include/dt-bindings/clock/qcom,sm8450-gpucc.h include/dt-bindings/clock/qcom,sm8550-gpucc.h @@ -24,6 +25,7 @@ description: | properties: compatible: enum: + - qcom,sar2130p-gpucc - qcom,sm4450-gpucc - qcom,sm8450-gpucc - qcom,sm8475-gpucc diff --git a/include/dt-bindings/clock/qcom,sar2130p-gpucc.h b/include/dt-bindings/clock/qcom,sar2130p-gpucc.h new file mode 100644 index 0000000000000000000000000000000000000000..a2204369110a585394d175193dce8bf9f63439d2 --- /dev/null +++ b/include/dt-bindings/clock/qcom,sar2130p-gpucc.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved + * Copyright (c) 2024, Linaro Limited + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SAR2130P_H +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SAR2130P_H + +/* GPU_CC clocks */ +#define GPU_CC_AHB_CLK 0 +#define GPU_CC_CRC_AHB_CLK 1 +#define GPU_CC_CX_FF_CLK 2 +#define GPU_CC_CX_GMU_CLK 3 +#define GPU_CC_CXO_AON_CLK 4 +#define GPU_CC_CXO_CLK 5 +#define GPU_CC_FF_CLK_SRC 6 +#define GPU_CC_GMU_CLK_SRC 7 +#define GPU_CC_GX_GMU_CLK 8 +#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 9 +#define GPU_CC_HUB_AON_CLK 10 +#define GPU_CC_HUB_CLK_SRC 11 +#define GPU_CC_HUB_CX_INT_CLK 12 +#define GPU_CC_MEMNOC_GFX_CLK 13 +#define GPU_CC_PLL0 14 +#define GPU_CC_PLL1 15 +#define GPU_CC_SLEEP_CLK 16 + +/* GDSCs */ +#define GPU_GX_GDSC 0 +#define GPU_CX_GDSC 1 + +#endif diff --git a/include/dt-bindings/reset/qcom,sar2130p-gpucc.h b/include/dt-bindings/reset/qcom,sar2130p-gpucc.h new file mode 100644 index 0000000000000000000000000000000000000000..99ba5f092e2a43fb7b7b2a9f78d9ac4ae0bfea18 --- /dev/null +++ b/include/dt-bindings/reset/qcom,sar2130p-gpucc.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2024, Linaro Limited + */ + +#ifndef _DT_BINDINGS_RESET_QCOM_GPU_CC_SAR2130P_H +#define _DT_BINDINGS_RESET_QCOM_GPU_CC_SAR2130P_H + +#define GPUCC_GPU_CC_GX_BCR 0 +#define GPUCC_GPU_CC_ACD_BCR 1 +#define GPUCC_GPU_CC_GX_ACD_IROOT_BCR 2 + +#endif From patchwork Fri Oct 25 15:03:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 838452 Received: from mail-lf1-f45.google.com (mail-lf1-f45.google.com [209.85.167.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D7E5A20F3E0 for ; Fri, 25 Oct 2024 15:04:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729868653; cv=none; b=fR9Q5Y+g/bDI36PNeAGoYf6pMn8X6q9AZoL8r3GYImIKpWV8dRad/+TWWUOJYrHSZ/Gjr44TG5p3cquM9QZxw5CBPr+sHZHLMWkt6KhNV6yzvCGKWuOXAIVtB5PkB3gMwEfho3snO14Bq4Jfh/hdG58dTq4h89fwstd1mcXEq5M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729868653; c=relaxed/simple; bh=L1rjSA7hLRyjlIeLPYAhbgLNuAgpRygH7wmtCWHxdlw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=sVNtRkDnHV9/sU2DhSL36aAnciIMArG+rXdCbGNzzN1OeJxnFJTv44e8pMC0+DxgHQKAdvwo70b3ptQP5StRZ3alYgk0ZHmBKV88HGIRphN+KKCje4LuGQr0dXtQpJHgrHwvP8SK0bPouQ2yCyuAyTBE0ErDuGh31NhQyld6cvc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=VdffLGuX; arc=none smtp.client-ip=209.85.167.45 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="VdffLGuX" Received: by mail-lf1-f45.google.com with SMTP id 2adb3069b0e04-539f2b95775so2509594e87.1 for ; Fri, 25 Oct 2024 08:04:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1729868648; x=1730473448; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=cx/7E6yuzJaG4XgFatO59KTwh6rhD+wMbHNfceiybZI=; b=VdffLGuXYiM8BRtTTB1f8WgM7rLZdFs/SzyFIt4YTOQ6pojd6xhXBqZHwoWNFQzkzL XNG4vzqOjcEERnPaSA5MmPtnqJQEKf0dD0o7EUIbQbBsydjhcjsWuY/KXTKxolMYh7tb zrZe6MS0kuvDuIn/dEjuxB0ufC/1FUWlXy+SZ9XXPiu8F2PRi63A31rB8kxojnIIYx+x K5OSIiKyhst8EUmNaF/Bx8gJP1+v9awRD0zlPMUxsfkI5n3rSsfHSxbm/CpVRt6nN6KZ ejm7ptKW/FQGYFI7aTiRa/SkBTErNghVc8cEEFhjrJfSwFn9hmHL2nySCzdGDWuzI8YV 0g9g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729868648; x=1730473448; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cx/7E6yuzJaG4XgFatO59KTwh6rhD+wMbHNfceiybZI=; b=U9z0wPu5fQmYri1wXUdahCIaMHeDJ+KHv7AmhMpP3Xys1X4vKoa0ZtPd5qCddE5THH 00uVmlMeM2fWQ3DsBQUQhv0GqSWHdtFClWnEq69i4ySDBNaFvLhViUPMLAARdnpZuPh7 Pxm06KdNyH0gCBFimjnXrJ8GZJ1CTDUZ/bKdEXwSOTEZ1NtudF+D77CGeVo8RwEh3hfy GoDT8B6lMcmh4bseABxdcAEBqu9vZtJPEPp9CwNHHYfAkaYY8r/gGimFysx4ATgGipNh IJoA35Z93gmjxKZitVAMDB6v8Ncd+aydvPZKG0T7jQ0D1qiHiqCGmj+ergcoB7UWW5yA 2/XQ== X-Gm-Message-State: AOJu0Yx7qUoo849JdB5DZ+Ms+xmOg0fwrmneMHOCntvRPI4ToaXH/NHx VbT/R/zV90BHnObM/6HHLyJNUblHpytpTAV2/DAo4NAfnwFKysPJIyl/mck/sh8= X-Google-Smtp-Source: AGHT+IHKeGi7yAw1nrKsdQEKATmo/BeDQcLQH8PETHLOFHplqHMWV1kNi0431GoHQHIGePJg942nfQ== X-Received: by 2002:a05:6512:258c:b0:53b:1e9b:b073 with SMTP id 2adb3069b0e04-53b1e9bb2d6mr9019329e87.3.1729868647882; Fri, 25 Oct 2024 08:04:07 -0700 (PDT) Received: from [127.0.1.1] (2001-14ba-a0c3-3a00-70b-e6fc-b322-6a1b.rev.dnainternet.fi. [2001:14ba:a0c3:3a00:70b:e6fc:b322:6a1b]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-53b2e10a915sm209542e87.12.2024.10.25.08.04.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Oct 2024 08:04:07 -0700 (PDT) From: Dmitry Baryshkov Date: Fri, 25 Oct 2024 18:03:41 +0300 Subject: [PATCH v3 07/11] clk: qcom: rpmh: add support for SAR2130P Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241025-sar2130p-clocks-v3-7-48f1842fd156@linaro.org> References: <20241025-sar2130p-clocks-v3-0-48f1842fd156@linaro.org> In-Reply-To: <20241025-sar2130p-clocks-v3-0-48f1842fd156@linaro.org> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das , Neil Armstrong , Philipp Zabel , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1793; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=L1rjSA7hLRyjlIeLPYAhbgLNuAgpRygH7wmtCWHxdlw=; b=owEBbQKS/ZANAwAKARTbcu2+gGW4AcsmYgBnG7NUk3yWZdzVjPwVQa1LUVgaj+sDlUPqXdKm0 6q66y76nnWJAjMEAAEKAB0WIQRdB85SOKWMgfgVe+4U23LtvoBluAUCZxuzVAAKCRAU23LtvoBl uHmJEAC4U2gI4CvDeOJh7p/G2E3CyEJ6aT08SK/0Zud8/VQL6zEyXSEWFNbsNfEg2SaIeuChzce k3sRpy6BMKi/VULdMt5eT2C3e38FH5tcZeVyGpLii41BP3uoQnJSABuXKTEiyRb3b8yaB0fK7m7 99LEjfJEFfZB+f9A/pdSEXq+i5bsEFFkk8QcxZT3R3NzhWbDY4aNEBmvgXSPwgs116baWtZQWGg ON2ppeY8pgF+aPFy01U2Q8cfg4mhOLMhRlptbSHE1j80okXJ9A5t3MI79j4BHfG49KOWWub1IhE DWfOVt7ToMLNf3zyA0y2R5RtWjAezFMLLuCdDQX1Dd5SVs0c6jVGY8ybLw0s0eoj+P8tzFMmMEn 2oLCXsgDOAhPshVdU7gsgeJC4kAFakL4F7P2SADf60IsztOSoDzyj3cQNodshFWFK7oljZQfKWX bJFgCH97c48lNpvj2rRpvDYL1cQwdx5AZeW8enfjIAxXt4Ghi9fPtq1D0qjv54r/uk2S2uWpgpk cZgNk8FNGWXMH532pxg8nS0Gw5abGolKv5A37M9nE5otR/cW+XUcwXOSsHGSFrARz6WJLmkCdyj XgyDezZKMJRI5Avqe5OW2OJWyjfeGHXxgZNEji0V6DB0sDHFEmBdixrMGzPm4dzejw1hSLG6YWP AVTyDazzWU2KwVA== X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Define clocks as supported by the RPMh on the SAR2130P platform. It seems that on this platform RPMh models only CXO clock. Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/clk-rpmh.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c index 4acde937114af3d7fdc15f3d125a72d42d0fde21..eefc322ce367989f625f1285dcccddbdd8341a12 100644 --- a/drivers/clk/qcom/clk-rpmh.c +++ b/drivers/clk/qcom/clk-rpmh.c @@ -389,6 +389,18 @@ DEFINE_CLK_RPMH_BCM(ipa, "IP0"); DEFINE_CLK_RPMH_BCM(pka, "PKA0"); DEFINE_CLK_RPMH_BCM(qpic_clk, "QP0"); +static struct clk_hw *sar2130p_rpmh_clocks[] = { + [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div1.hw, + [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div1_ao.hw, + [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw, + [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw, +}; + +static const struct clk_rpmh_desc clk_rpmh_sar2130p = { + .clks = sar2130p_rpmh_clocks, + .num_clks = ARRAY_SIZE(sar2130p_rpmh_clocks), +}; + static struct clk_hw *sdm845_rpmh_clocks[] = { [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, @@ -880,6 +892,7 @@ static int clk_rpmh_probe(struct platform_device *pdev) static const struct of_device_id clk_rpmh_match_table[] = { { .compatible = "qcom,qdu1000-rpmh-clk", .data = &clk_rpmh_qdu1000}, { .compatible = "qcom,sa8775p-rpmh-clk", .data = &clk_rpmh_sa8775p}, + { .compatible = "qcom,sar2130p-rpmh-clk", .data = &clk_rpmh_sar2130p}, { .compatible = "qcom,sc7180-rpmh-clk", .data = &clk_rpmh_sc7180}, { .compatible = "qcom,sc8180x-rpmh-clk", .data = &clk_rpmh_sc8180x}, { .compatible = "qcom,sc8280xp-rpmh-clk", .data = &clk_rpmh_sc8280xp}, From patchwork Fri Oct 25 15:03:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 838451 Received: from mail-lf1-f43.google.com (mail-lf1-f43.google.com [209.85.167.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AEF55216213 for ; Fri, 25 Oct 2024 15:04:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729868662; cv=none; b=S2hfmpwqAtQ4T55RnaGKMozDLk0q/sJ88BSaLUwZ85SypPLdv6DrBdRlMAu3uZWgwjMDHMyiDJlJW3W6PA2F46355sWJLPhWkkgXJpMDCNf41algedazaUrE38682kz3arWeAEk3NKjeBBwHQ8os/SxF5cVY5Tzj+zzu1cg8MHI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729868662; c=relaxed/simple; bh=PgUHmFdy/8IXl2Ih12X3KfX+3gP6WyToyydVdAOKAoU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=F+BlWQwLjUxbn8kVbrn7oHBiyqK3SCEL2QbIXptP7+N+lurFh86j5r64vJl04WYryZoHK2Rp0Aqwfh6ns2lmFY7hbbvxMdK3ZiFazJH8I2NCTmvs+qy9qJf2PS0HASZzRvpqKX+USk93BAPV88Q106eh6SgiFuF1JUOG1+elU1U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=RabTfG0B; arc=none smtp.client-ip=209.85.167.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="RabTfG0B" Received: by mail-lf1-f43.google.com with SMTP id 2adb3069b0e04-539f0f9ee49so2312733e87.1 for ; Fri, 25 Oct 2024 08:04:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1729868658; x=1730473458; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=hhWjPDR01VyPmkS+g9wDQI09Awa9JCuuAq0juv5oCEE=; b=RabTfG0BR+nWok1btsY9Th6oYWgZPgp+V9rnVKIx7a/u54KqeJbLtk7D9XfkShe2bN TBDlWkYEPjV9LVhTLRITVrTwEt5UDDL0Yts80KGmL76tb92gpKBO2/KS1fLNWjunALe9 4YNQvNBBQjdOZ30mfquIfgy1Or1d3drn4XQEC9lQsNd8Ll1AF+eX5CG5W5A/81cYT/ux DNCt7Ps9D/PbuNtC5wnY5p5jaiPoXrCmp0d1nf0b5bFUpW7L1rsvEFyXCERuUwM1TSrI JBv8ka7cBM/uRvqcJGcBAwtIkROKJnOoQsOFgymo4G58wQyIadRBdiO/hZNdMlH9HNOl 5T0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729868658; x=1730473458; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hhWjPDR01VyPmkS+g9wDQI09Awa9JCuuAq0juv5oCEE=; b=l4sCNjUY3bFNcphKNSGloQKJN8LL9bKEeQLgJqOFfKLws9rOPCYuArz4lOW+iaq70x X4QN8t/rnZdtq8inXZd27t0Sj47xl3Bbnii6Glgsim8AyXV9MDw+KXcTjmzZXEoQRVE6 1Gs8Mo/FSSF1D8NHAmqOWB4AK7mZnBZXwzTbRstWMYtfAToI7IvPxmvz6xh2KXaPj8o8 Ad6fV9F5wK6xNwMM69TvgcJSdRy4qbZqJ09MZGA+S71YDYXq4Quu1CurSEsf6n77wJJf zIEesPgzhSZS/d08kU94W3yoHogL9Ht9doy02O0yNRE2ISdCYdYU1Lzsivjvs/+f538N 5W0Q== X-Gm-Message-State: AOJu0YwuhN0Y+gVgsYUzn0IbkVNg/88Rs5qhxw8yqZ15j6lBDZggSZ3y lVRExvPVGUEQWAblA4cPbWJxygtjd5yZ+MlP1D5PxzOAeWQrQkAR788rYraNalIST1ICII53dSx N X-Google-Smtp-Source: AGHT+IFOHPlSpj7S7IBeSaeF7wNAwH4f4/VKeIRCl0Jwww8I4AkoqFRn2jYxDvVmYbE1M8y3b15Hng== X-Received: by 2002:a05:6512:b0d:b0:539:e6bf:ca9a with SMTP id 2adb3069b0e04-53b23ddee9amr3805385e87.6.1729868656091; Fri, 25 Oct 2024 08:04:16 -0700 (PDT) Received: from [127.0.1.1] (2001-14ba-a0c3-3a00-70b-e6fc-b322-6a1b.rev.dnainternet.fi. [2001:14ba:a0c3:3a00:70b:e6fc:b322:6a1b]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-53b2e10a915sm209542e87.12.2024.10.25.08.04.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Oct 2024 08:04:15 -0700 (PDT) From: Dmitry Baryshkov Date: Fri, 25 Oct 2024 18:03:44 +0300 Subject: [PATCH v3 10/11] clk: qcom: dispcc-sm8550: enable support for SAR2130P Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241025-sar2130p-clocks-v3-10-48f1842fd156@linaro.org> References: <20241025-sar2130p-clocks-v3-0-48f1842fd156@linaro.org> In-Reply-To: <20241025-sar2130p-clocks-v3-0-48f1842fd156@linaro.org> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das , Neil Armstrong , Philipp Zabel , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3519; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=PgUHmFdy/8IXl2Ih12X3KfX+3gP6WyToyydVdAOKAoU=; b=owEBbQKS/ZANAwAKARTbcu2+gGW4AcsmYgBnG7NVYlZcvhzoMKoY5H1LFlgmkK6FmY6xs1MAb STi1P1SyAaJAjMEAAEKAB0WIQRdB85SOKWMgfgVe+4U23LtvoBluAUCZxuzVQAKCRAU23LtvoBl uI+DD/4/4hj/osuQWCSS5EZQYWUUV4eBOg4wnd1AxMKfk89HFVLsfGjPtQeSe6gELEX1cuhwhfH TFBPqU+8RXeGVJuizkphMQLlyRsf3HH89obJlXa0XybE6MUv7lcwfxQw4Yd0bwLLj+V/OTS8MUd yKib/I8IbGBodUlXjMjVgQuXwHgXvE5NLU8pJALQtsJkfELT6AKzS4xn0t4Yzm0SdSwHPCOWGnO zWiM6R14kXbXnB074tPHNiaiKWuvzKsCxTcU5jiBj0ixOf7CsZwXr7cSVD2EUQGbAP463+7vqp7 IMMl1UsICRUhyGx793L6OSZ4mFQu5kV0xQ/9C8DxXn6PsB5YFUi2GEi4KbY7BEh2Li/KHvQZxbg nEzYNngfclwUny1BpvStLbjx4KTbWb6gKun1wjioyyr9hyHCZ2Ep1WG6M/YvrhNkfejP8ZjGhgV rgElnz0s20LTsGo+5TnN9Hyq+5zkEjrGqjqGF9l1MoNtRbRc2Ld7g1TV4KYAMyO+yx1RjjXlAR2 TSYsiod0tWW84RRsNUXaecl0kIPjkoEDeF7ndm0yNDk+KBLpqn7prZtgF+YaMp1mW7pja9VB7I4 VsIibtn7RSxaRsbztxRCSU6IqhrN8NKfS+wIYHQJXF1rb2UWG2gVKR/wil3PHYjYGy89lBiV81s r0WfAH/ZM+9QayA== X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A The display clock controller on SAR2130P is very close to the clock controller on SM8550 (and SM8650). Reuse existing driver to add support for the controller on SAR2130P. Reviewed-by: Neil Armstrong Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/Kconfig | 4 ++-- drivers/clk/qcom/dispcc-sm8550.c | 18 ++++++++++++++++-- 2 files changed, 18 insertions(+), 4 deletions(-) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 0cb5d5a052744761c95a5c72047cd322ddb8e0fc..77a4139d222ec7dea87d63b24896324973e4838b 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -988,10 +988,10 @@ config SM_DISPCC_8450 config SM_DISPCC_8550 tristate "SM8550 Display Clock Controller" depends on ARM64 || COMPILE_TEST - depends on SM_GCC_8550 || SM_GCC_8650 + depends on SM_GCC_8550 || SM_GCC_8650 || SAR_GCC_2130P help Support for the display clock controller on Qualcomm Technologies, Inc - SM8550 or SM8650 devices. + SAR2130P, SM8550 or SM8650 devices. Say Y if you want to support display devices and functionality such as splash screen. diff --git a/drivers/clk/qcom/dispcc-sm8550.c b/drivers/clk/qcom/dispcc-sm8550.c index 7f9021ca0ecb0ef743a40bed1bb3d2cbcfa23dc7..e41d4104d77021cae6438886bcb7015469d86a9f 100644 --- a/drivers/clk/qcom/dispcc-sm8550.c +++ b/drivers/clk/qcom/dispcc-sm8550.c @@ -75,7 +75,7 @@ static struct pll_vco lucid_ole_vco[] = { { 249600000, 2000000000, 0 }, }; -static const struct alpha_pll_config disp_cc_pll0_config = { +static struct alpha_pll_config disp_cc_pll0_config = { .l = 0xd, .alpha = 0x6492, .config_ctl_val = 0x20485699, @@ -106,7 +106,7 @@ static struct clk_alpha_pll disp_cc_pll0 = { }, }; -static const struct alpha_pll_config disp_cc_pll1_config = { +static struct alpha_pll_config disp_cc_pll1_config = { .l = 0x1f, .alpha = 0x4000, .config_ctl_val = 0x20485699, @@ -594,6 +594,13 @@ static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = { { } }; +static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src_sar2130p[] = { + F(200000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), + F(325000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), + F(514000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), + { } +}; + static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src_sm8650[] = { F(19200000, P_BI_TCXO, 1, 0, 0), F(85714286, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), @@ -1750,6 +1757,7 @@ static struct qcom_cc_desc disp_cc_sm8550_desc = { }; static const struct of_device_id disp_cc_sm8550_match_table[] = { + { .compatible = "qcom,sar2130p-dispcc" }, { .compatible = "qcom,sm8550-dispcc" }, { .compatible = "qcom,sm8650-dispcc" }, { } @@ -1780,6 +1788,12 @@ static int disp_cc_sm8550_probe(struct platform_device *pdev) disp_cc_mdss_mdp_clk_src.freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src_sm8650; disp_cc_mdss_dptx1_usb_router_link_intf_clk.clkr.hw.init->parent_hws[0] = &disp_cc_mdss_dptx1_link_div_clk_src.clkr.hw; + } else if (of_device_is_compatible(pdev->dev.of_node, "qcom,sar2130p-dispcc")) { + disp_cc_pll0_config.l = 0x1f; + disp_cc_pll0_config.alpha = 0x4000; + disp_cc_pll0_config.user_ctl_val = 0x1; + disp_cc_pll1_config.user_ctl_val = 0x1; + disp_cc_mdss_mdp_clk_src.freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src_sar2130p; } clk_lucid_ole_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config); From patchwork Fri Oct 25 15:03:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 838450 Received: from mail-lf1-f50.google.com (mail-lf1-f50.google.com [209.85.167.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0207021621A for ; Fri, 25 Oct 2024 15:04:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729868664; cv=none; b=JbmGrGXltJiSz/oVnunZiizCF/3wEjswAbfE9/f0kecaYgjISuXvn+EkcZZPoupIzAN5eCOdcaEeno5r3L+4Oqhw8xNIb/Rcx1n5S1yBKYq6u6Sl+hjjiCpM+dIhLiFO2dcRjqBVr1rOZnW5xEETtDnbvcp+pXlLZ7TFqG48Y+o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729868664; c=relaxed/simple; bh=OIwivcEmms/RiYvRKS6a5BbzOR582S903YsWbbGK00c=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=OSidcQRJ3WS8ZyB4f8lXDLx7Q4/kx5AV/R8Po2rcaKL/q7EMg5Usr/XUXa1MjL/RZX4/R4mPJQd8VO3kVBol3nrdOphGmNnUpSb3KitqNlqGkljb7RYLJkbkuY0ihqeed+zqVssR70FIbM7hnIyQTmiCS824ym61eoq1ndLutRk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=u2zIwhdq; arc=none smtp.client-ip=209.85.167.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="u2zIwhdq" Received: by mail-lf1-f50.google.com with SMTP id 2adb3069b0e04-53a0c160b94so2583047e87.2 for ; Fri, 25 Oct 2024 08:04:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1729868657; x=1730473457; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=GzCy0S9O1o+dncbxhCc6FXPTS7r2JcJPH1XnGftO8Rc=; b=u2zIwhdq9Z0PehZTJFTlxhNTRLX4lqb3jmfC8FKQ7RcQYNk+1oMqBvTH4vEo/rTvJU lvr5IZNmC0ooA2PH/glFg5/alX5YuYD/cOV/TkWYwCbWJtsB2aXd03Db7mTMBAOcCHQr jFO2J7RLlj3SulDr1VJpz0gXxctCH23BZE8pckOZ6EfaCH9/qWvyPaJNQuC2jJtOzQvB K4iL0djOHk+j35Ic9Pn2qNbNVNBY4//g5QCUHpGCsNTGisek10h7JBV25KPIlP3Y72p8 OnDIf+B390aiucKMkQ0TqcT2OZ6fzJ/Kcg56CraSq8o8N/N7La0JKBPK9hMvuigR05lB kvCQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729868657; x=1730473457; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GzCy0S9O1o+dncbxhCc6FXPTS7r2JcJPH1XnGftO8Rc=; b=oJfEOg0EU0I/tkKZr9AQoGS6E4J6biiRUwq+L875OL7BQv/iqEJGzqoEvclFC8etoO ykBgE/pYK7IaACohOJovvwxBjFNHo2cOMTydlt1a0lkl+Br+udohcwOU1v9dEjYsF+un HWAN17rEktRkO2DPvIRBxXh6YMuIOxJQlpifyCIxBdcu8fDxz5wE+sK9FrUHAyT6fodV /DchRL63TSxQpUgw0zrIMkSNPeQ+Eir9mx9c94MnPFMBDGwKvEKvQioONWSUN2UBdEvi RIKmLM505yr4uXZIl5almYhHDcscYMYVDJDNUyumC2V8oK1j6OqMCAshO3sHcQKi+tBI 2r7Q== X-Gm-Message-State: AOJu0YztgjGQFwAWfVNM3ANwQwEEwWFo1sjczD5HReOgUlhfM8w3QiN9 Fleyw1WlrLoYUovTbFGrJtQZuOMBRXEr6tAALb6y564IhbU65fyMq0IfrsAybR8= X-Google-Smtp-Source: AGHT+IEwXYQDKB+25Fuv5k2e0Mx0F3nAq/uPsaoMjy11avdKUhyjHCiBB+awibzoiwdGUYXULseJQA== X-Received: by 2002:a05:6512:124f:b0:536:741a:6bad with SMTP id 2adb3069b0e04-53b1a2f2943mr5833853e87.12.1729868656983; Fri, 25 Oct 2024 08:04:16 -0700 (PDT) Received: from [127.0.1.1] (2001-14ba-a0c3-3a00-70b-e6fc-b322-6a1b.rev.dnainternet.fi. [2001:14ba:a0c3:3a00:70b:e6fc:b322:6a1b]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-53b2e10a915sm209542e87.12.2024.10.25.08.04.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Oct 2024 08:04:16 -0700 (PDT) From: Dmitry Baryshkov Date: Fri, 25 Oct 2024 18:03:45 +0300 Subject: [PATCH v3 11/11] clk: qcom: add SAR2130P GPU Clock Controller support Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241025-sar2130p-clocks-v3-11-48f1842fd156@linaro.org> References: <20241025-sar2130p-clocks-v3-0-48f1842fd156@linaro.org> In-Reply-To: <20241025-sar2130p-clocks-v3-0-48f1842fd156@linaro.org> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das , Neil Armstrong , Philipp Zabel , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=15878; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=0yBBilK2IS2kHAQ22Aavz62Y0H+bW+P6ui8CLW5p9Yg=; b=owEBbQKS/ZANAwAKARTbcu2+gGW4AcsmYgBnG7NWxgPYZtBOohH8r11AFjKBrxqhWh3DYDFjm xvDIR7APMyJAjMEAAEKAB0WIQRdB85SOKWMgfgVe+4U23LtvoBluAUCZxuzVgAKCRAU23LtvoBl uAghEACXu4zNsrSyxTa/ERw7JxYgGp9rpWhSTn3lLijk2aDpCM1B9SIagHaUcFd/3YBkJ0IGn0+ w9D+/Y/TN7BJH48/55S1kPGlfdOdD8OI7var+IfckC0lE8RNWJMV2TBZX6awATfA9rWKD+kA/yg LLqbELrgAGwWPLH4SovepvtRdsZa7dQeEm2U58yMhK2PmmC7O31Go8jyjR0yirgy/zEfib/CbhR ih2QapzPbGxrv0FypgWWFWjyaUUzjOrNx9LI/12IFKSy7tfEGTGtMWP3nGXCDfqwqezUBpk4jW9 P37eakofPUILl/+RsAAqL/5gmKABNP4hOGu6oH9EsMC5QZ5oN072aj+Y6aXCrXpudFJ0ZzZ5umV VB+m9dQdGnw/7vi6Kbx0NRGb9I4DrVUEUxgcoJukIEhY5/Vt3Ar039H8i/NJZLheI+QeY5/Esme jpDlG12kdStE63WmEaTCjWWNtOUSYieJqX59hCwsvz28FhmiV5qBsp7wjbKDl43cEbzBA7VZ6v/ uLbSse1MkLUM7ist4xKEzieIXzSBy6MZ/IcgYs3rtLZlWQD6Crm26AYBZ9LqRU1J+v/7lJlaqVU KOtPQW5KnjD5AqIAXFlVHx558qjN96Ef68feKzp+n1p5SgPyShYqF5U6ccb4KVy91ShKPwUli9c xGxzvM3WmsNax9A== X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A From: Konrad Dybcio Add support for the GPU Clock Controller as used on the SAR2130P and SAR1130P platforms. Signed-off-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/Kconfig | 9 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gpucc-sar2130p.c | 503 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 513 insertions(+) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 77a4139d222ec7dea87d63b24896324973e4838b..678b1ebd9785be066fc202dd7865a6c6ff342465 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -574,6 +574,15 @@ config SAR_GCC_2130P Say Y if you want to use peripheral devices such as UART, SPI, I2C, USB, SDCC, etc. +config SAR_GPUCC_2130P + tristate "SAR2130P Graphics clock controller" + select QCOM_GDSC + select SAR_GCC_2130P + help + Support for the graphics clock controller on SAR2130P devices. + Say Y if you want to support graphics controller devices and + functionality such as 3D graphics. + config SC_GCC_7180 tristate "SC7180 Global Clock Controller" select QCOM_GDSC diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 992192ea231c0b10fe81982c175302a6b782e2fd..c581e65f173c81aafe385a53ea8a5c07a4c3e32e 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -86,6 +86,7 @@ obj-$(CONFIG_SA_GCC_8775P) += gcc-sa8775p.o obj-$(CONFIG_SA_GPUCC_8775P) += gpucc-sa8775p.o obj-$(CONFIG_SA_VIDEOCC_8775P) += videocc-sa8775p.o obj-$(CONFIG_SAR_GCC_2130P) += gcc-sar2130p.o +obj-$(CONFIG_SAR_GPUCC_2130P) += gpucc-sar2130p.o obj-$(CONFIG_SC_GCC_7180) += gcc-sc7180.o obj-$(CONFIG_SC_GCC_7280) += gcc-sc7280.o obj-$(CONFIG_SC_GCC_8180X) += gcc-sc8180x.o diff --git a/drivers/clk/qcom/gpucc-sar2130p.c b/drivers/clk/qcom/gpucc-sar2130p.c new file mode 100644 index 0000000000000000000000000000000000000000..61be63fc30fd5d45a16197bc4b9110c787ec4110 --- /dev/null +++ b/drivers/clk/qcom/gpucc-sar2130p.c @@ -0,0 +1,503 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024, Linaro Limited + */ + +#include +#include +#include +#include +#include + +#include +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "common.h" +#include "gdsc.h" +#include "reset.h" + +enum { + DT_BI_TCXO, + DT_GPLL0_OUT_MAIN, + DT_GPLL0_OUT_MAIN_DIV, +}; + +enum { + P_BI_TCXO, + P_GPLL0_OUT_MAIN, + P_GPLL0_OUT_MAIN_DIV, + P_GPU_CC_PLL0_OUT_MAIN, + P_GPU_CC_PLL1_OUT_MAIN, +}; + +static const struct pll_vco lucid_ole_vco[] = { + { 249600000, 2000000000, 0 }, +}; + +/* 470MHz Configuration */ +static const struct alpha_pll_config gpu_cc_pll0_config = { + .l = 0x18, + .alpha = 0x7aaa, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00182261, + .config_ctl_hi1_val = 0x82aa299c, + .test_ctl_val = 0x00000000, + .test_ctl_hi_val = 0x00000003, + .test_ctl_hi1_val = 0x00009000, + .test_ctl_hi2_val = 0x00000034, + .user_ctl_val = 0x00000000, + .user_ctl_hi_val = 0x00000005, +}; + +static struct clk_alpha_pll gpu_cc_pll0 = { + .offset = 0x0, + .vco_table = lucid_ole_vco, + .num_vco = ARRAY_SIZE(lucid_ole_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_pll0", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +/* 440MHz Configuration */ +static const struct alpha_pll_config gpu_cc_pll1_config = { + .l = 0x16, + .alpha = 0xeaaa, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00182261, + .config_ctl_hi1_val = 0x82aa299c, + .test_ctl_val = 0x00000000, + .test_ctl_hi_val = 0x00000003, + .test_ctl_hi1_val = 0x00009000, + .test_ctl_hi2_val = 0x00000034, + .user_ctl_val = 0x00000000, + .user_ctl_hi_val = 0x00000005, +}; + +static struct clk_alpha_pll gpu_cc_pll1 = { + .offset = 0x1000, + .vco_table = lucid_ole_vco, + .num_vco = ARRAY_SIZE(lucid_ole_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_pll1", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct parent_map gpu_cc_parent_map_0[] = { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, +}; + +static const struct clk_parent_data gpu_cc_parent_data_0[] = { + { .index = DT_BI_TCXO }, + { .index = DT_GPLL0_OUT_MAIN }, + { .index = DT_GPLL0_OUT_MAIN_DIV }, +}; + +static const struct parent_map gpu_cc_parent_map_1[] = { + { P_BI_TCXO, 0 }, + { P_GPU_CC_PLL0_OUT_MAIN, 1 }, + { P_GPU_CC_PLL1_OUT_MAIN, 3 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, +}; + +static const struct clk_parent_data gpu_cc_parent_data_1[] = { + { .index = DT_BI_TCXO }, + { .hw = &gpu_cc_pll0.clkr.hw }, + { .hw = &gpu_cc_pll1.clkr.hw }, + { .index = DT_GPLL0_OUT_MAIN }, + { .index = DT_GPLL0_OUT_MAIN_DIV }, +}; + +static const struct parent_map gpu_cc_parent_map_2[] = { + { P_BI_TCXO, 0 }, + { P_GPU_CC_PLL1_OUT_MAIN, 3 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, +}; + +static const struct clk_parent_data gpu_cc_parent_data_2[] = { + { .index = DT_BI_TCXO }, + { .hw = &gpu_cc_pll1.clkr.hw }, + { .index = DT_GPLL0_OUT_MAIN }, + { .index = DT_GPLL0_OUT_MAIN_DIV }, +}; + +static const struct freq_tbl ftbl_gpu_cc_ff_clk_src[] = { + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_ff_clk_src = { + .cmd_rcgr = 0x9474, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gpu_cc_parent_map_0, + .freq_tbl = ftbl_gpu_cc_ff_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_ff_clk_src", + .parent_data = gpu_cc_parent_data_0, + .num_parents = ARRAY_SIZE(gpu_cc_parent_data_0), + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(220000000, P_GPU_CC_PLL1_OUT_MAIN, 2, 0, 0), + F(550000000, P_GPU_CC_PLL1_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_gmu_clk_src = { + .cmd_rcgr = 0x9318, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gpu_cc_parent_map_1, + .freq_tbl = ftbl_gpu_cc_gmu_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_gmu_clk_src", + .parent_data = gpu_cc_parent_data_1, + .num_parents = ARRAY_SIZE(gpu_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gpu_cc_hub_clk_src = { + .cmd_rcgr = 0x93ec, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gpu_cc_parent_map_2, + .freq_tbl = ftbl_gpu_cc_ff_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_hub_clk_src", + .parent_data = gpu_cc_parent_data_2, + .num_parents = ARRAY_SIZE(gpu_cc_parent_data_2), + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_branch gpu_cc_ahb_clk = { + .halt_reg = 0x911c, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x911c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &gpu_cc_hub_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_crc_ahb_clk = { + .halt_reg = 0x9120, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x9120, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_crc_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &gpu_cc_hub_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_ff_clk = { + .halt_reg = 0x914c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x914c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_cx_ff_clk", + .parent_hws = (const struct clk_hw*[]) { + &gpu_cc_ff_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_gmu_clk = { + .halt_reg = 0x913c, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x913c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_cx_gmu_clk", + .parent_hws = (const struct clk_hw*[]) { + &gpu_cc_gmu_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cxo_aon_clk = { + .halt_reg = 0x9004, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x9004, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_cxo_aon_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cxo_clk = { + .halt_reg = 0x9144, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x9144, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_cxo_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_gx_gmu_clk = { + .halt_reg = 0x90bc, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x90bc, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_gx_gmu_clk", + .parent_hws = (const struct clk_hw*[]) { + &gpu_cc_gmu_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_hub_aon_clk = { + .halt_reg = 0x93e8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x93e8, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_hub_aon_clk", + .parent_hws = (const struct clk_hw*[]) { + &gpu_cc_hub_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_hub_cx_int_clk = { + .halt_reg = 0x9148, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x9148, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_hub_cx_int_clk", + .parent_hws = (const struct clk_hw*[]) { + &gpu_cc_hub_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_memnoc_gfx_clk = { + .halt_reg = 0x9150, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x9150, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_memnoc_gfx_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = { + .halt_reg = 0x7000, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x7000, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_hlos1_vote_gpu_smmu_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_sleep_clk = { + .halt_reg = 0x9134, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x9134, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_sleep_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct gdsc gpu_cx_gdsc = { + .gdscr = 0x9108, + .gds_hw_ctrl = 0x953c, + .clk_dis_wait_val = 8, + .pd = { + .name = "gpu_cx_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = VOTABLE | RETAIN_FF_ENABLE, +}; + +static struct gdsc gpu_gx_gdsc = { + .gdscr = 0x905c, + .clamp_io_ctrl = 0x9504, + .resets = (unsigned int []){ GPUCC_GPU_CC_GX_BCR, + GPUCC_GPU_CC_ACD_BCR, + GPUCC_GPU_CC_GX_ACD_IROOT_BCR }, + .reset_count = 3, + .pd = { + .name = "gpu_gx_gdsc", + .power_on = gdsc_gx_do_nothing_enable, + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = CLAMP_IO | AON_RESET | SW_RESET, +}; + +static struct clk_regmap *gpu_cc_sar2130p_clocks[] = { + [GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr, + [GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr, + [GPU_CC_CX_FF_CLK] = &gpu_cc_cx_ff_clk.clkr, + [GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr, + [GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr, + [GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr, + [GPU_CC_FF_CLK_SRC] = &gpu_cc_ff_clk_src.clkr, + [GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr, + [GPU_CC_GX_GMU_CLK] = &gpu_cc_gx_gmu_clk.clkr, + [GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr, + [GPU_CC_HUB_AON_CLK] = &gpu_cc_hub_aon_clk.clkr, + [GPU_CC_HUB_CLK_SRC] = &gpu_cc_hub_clk_src.clkr, + [GPU_CC_HUB_CX_INT_CLK] = &gpu_cc_hub_cx_int_clk.clkr, + [GPU_CC_MEMNOC_GFX_CLK] = &gpu_cc_memnoc_gfx_clk.clkr, + [GPU_CC_PLL0] = &gpu_cc_pll0.clkr, + [GPU_CC_PLL1] = &gpu_cc_pll1.clkr, + [GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr, +}; + +static const struct qcom_reset_map gpu_cc_sar2130p_resets[] = { + [GPUCC_GPU_CC_ACD_BCR] = { 0x9358 }, + [GPUCC_GPU_CC_GX_ACD_IROOT_BCR] = { 0x958c }, + [GPUCC_GPU_CC_GX_BCR] = { 0x9058 }, +}; + +static struct gdsc *gpu_cc_sar2130p_gdscs[] = { + [GPU_CX_GDSC] = &gpu_cx_gdsc, + [GPU_GX_GDSC] = &gpu_gx_gdsc, +}; + +static const struct regmap_config gpu_cc_sar2130p_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0xa000, + .fast_io = true, +}; + +static const struct qcom_cc_desc gpu_cc_sar2130p_desc = { + .config = &gpu_cc_sar2130p_regmap_config, + .clks = gpu_cc_sar2130p_clocks, + .num_clks = ARRAY_SIZE(gpu_cc_sar2130p_clocks), + .resets = gpu_cc_sar2130p_resets, + .num_resets = ARRAY_SIZE(gpu_cc_sar2130p_resets), + .gdscs = gpu_cc_sar2130p_gdscs, + .num_gdscs = ARRAY_SIZE(gpu_cc_sar2130p_gdscs), +}; + +static const struct of_device_id gpu_cc_sar2130p_match_table[] = { + { .compatible = "qcom,sar2130p-gpucc" }, + { } +}; +MODULE_DEVICE_TABLE(of, gpu_cc_sar2130p_match_table); + +static int gpu_cc_sar2130p_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct regmap *regmap; + int ret; + + regmap = qcom_cc_map(pdev, &gpu_cc_sar2130p_desc); + if (IS_ERR(regmap)) + return dev_err_probe(dev, PTR_ERR(regmap), "Couldn't map GPU_CC\n"); + + clk_lucid_ole_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config); + clk_lucid_ole_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config); + + /* Keep some clocks always-on */ + qcom_branch_set_clk_en(regmap, 0x900c); /* GPU_CC_DEMET_CLK */ + + return qcom_cc_really_probe(dev, &gpu_cc_sar2130p_desc, regmap); +} + +static struct platform_driver gpu_cc_sar2130p_driver = { + .probe = gpu_cc_sar2130p_probe, + .driver = { + .name = "gpu_cc-sar2130p", + .of_match_table = gpu_cc_sar2130p_match_table, + }, +}; +module_platform_driver(gpu_cc_sar2130p_driver); + +MODULE_DESCRIPTION("QTI GPU_CC SAR2130P Driver"); +MODULE_LICENSE("GPL");