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Signed-off-by: Mario Limonciello --- arch/x86/include/asm/cpufeatures.h | 2 +- arch/x86/kernel/cpu/scattered.c | 2 +- drivers/cpufreq/amd-pstate.c | 2 +- tools/arch/x86/include/asm/cpufeatures.h | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index cea1ed82aeb48..424bb7ae8914a 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -472,7 +472,7 @@ #define X86_FEATURE_BHI_CTRL (21*32+ 2) /* BHI_DIS_S HW control available */ #define X86_FEATURE_CLEAR_BHB_HW (21*32+ 3) /* BHI_DIS_S HW control enabled */ #define X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT (21*32+ 4) /* Clear branch history at vmexit using SW loop */ -#define X86_FEATURE_FAST_CPPC (21*32 + 5) /* AMD Fast CPPC */ +#define X86_FEATURE_AMD_FAST_CPPC (21*32 + 5) /* Fast CPPC */ #define X86_FEATURE_HETERO_CORE_TOPOLOGY (21*32 + 6) /* Heterogeneous Core Topology */ /* diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c index 3bba55323163b..d7f2c19abce33 100644 --- a/arch/x86/kernel/cpu/scattered.c +++ b/arch/x86/kernel/cpu/scattered.c @@ -45,7 +45,7 @@ static const struct cpuid_bit cpuid_bits[] = { { X86_FEATURE_HW_PSTATE, CPUID_EDX, 7, 0x80000007, 0 }, { X86_FEATURE_CPB, CPUID_EDX, 9, 0x80000007, 0 }, { X86_FEATURE_PROC_FEEDBACK, CPUID_EDX, 11, 0x80000007, 0 }, - { X86_FEATURE_FAST_CPPC, CPUID_EDX, 15, 0x80000007, 0 }, + { X86_FEATURE_AMD_FAST_CPPC, CPUID_EDX, 15, 0x80000007, 0 }, { X86_FEATURE_MBA, CPUID_EBX, 6, 0x80000008, 0 }, { X86_FEATURE_SMBA, CPUID_EBX, 2, 0x80000020, 0 }, { X86_FEATURE_BMEC, CPUID_EBX, 3, 0x80000020, 0 }, diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 3c14962adeb22..2670bdcad6eda 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -844,7 +844,7 @@ static u32 amd_pstate_get_transition_delay_us(unsigned int cpu) transition_delay_ns = cppc_get_transition_latency(cpu); if (transition_delay_ns == CPUFREQ_ETERNAL) { - if (cpu_feature_enabled(X86_FEATURE_FAST_CPPC)) + if (cpu_feature_enabled(X86_FEATURE_AMD_FAST_CPPC)) return AMD_PSTATE_FAST_CPPC_TRANSITION_DELAY; else return AMD_PSTATE_TRANSITION_DELAY; diff --git a/tools/arch/x86/include/asm/cpufeatures.h b/tools/arch/x86/include/asm/cpufeatures.h index dd4682857c120..23698d0f4bb47 100644 --- a/tools/arch/x86/include/asm/cpufeatures.h +++ b/tools/arch/x86/include/asm/cpufeatures.h @@ -472,7 +472,7 @@ #define X86_FEATURE_BHI_CTRL (21*32+ 2) /* BHI_DIS_S HW control available */ #define X86_FEATURE_CLEAR_BHB_HW (21*32+ 3) /* BHI_DIS_S HW control enabled */ #define X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT (21*32+ 4) /* Clear branch history at vmexit using SW loop */ -#define X86_FEATURE_FAST_CPPC (21*32 + 5) /* AMD Fast CPPC */ +#define X86_FEATURE_AMD_FAST_CPPC (21*32 + 5) /* AMD Fast CPPC */ /* * BUG word(s) From patchwork Mon Oct 21 17:55:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 837331 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2052.outbound.protection.outlook.com [40.107.94.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5F1BC1F8936; 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Mon, 21 Oct 2024 12:56:42 -0500 From: Mario Limonciello To: Borislav Petkov CC: Thomas Gleixner , Ingo Molnar , "Dave Hansen" , "maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)" , "H . Peter Anvin" , "Rafael J . Wysocki" , "Gautham R . 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(82310400026)(1800799024)(36860700013)(7416014)(376014); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Oct 2024 17:56:44.2220 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1e570c69-355d-4e0b-e875-08dcf1f9b9a1 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000044A4.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB7908 X86_FEATURE_AMD_HETEROGENEOUS_CORES makes it clear this is an AMD feature and matches the APM value of HeterogeneousCores Suggested-by: Borislav Petkov Signed-off-by: Mario Limonciello --- arch/x86/include/asm/cpufeatures.h | 2 +- arch/x86/kernel/cpu/amd.c | 2 +- arch/x86/kernel/cpu/scattered.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 424bb7ae8914a..7f6c9fc465293 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -473,7 +473,7 @@ #define X86_FEATURE_CLEAR_BHB_HW (21*32+ 3) /* BHI_DIS_S HW control enabled */ #define X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT (21*32+ 4) /* Clear branch history at vmexit using SW loop */ #define X86_FEATURE_AMD_FAST_CPPC (21*32 + 5) /* Fast CPPC */ -#define X86_FEATURE_HETERO_CORE_TOPOLOGY (21*32 + 6) /* Heterogeneous Core Topology */ +#define X86_FEATURE_AMD_HETEROGENEOUS_CORES (21*32 + 6) /* Heterogeneous Core Topology */ /* * BUG word(s) diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index 8ad5f1385f0ec..0f533e6260d29 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -1223,7 +1223,7 @@ enum amd_core_type amd_get_core_type(void) core_type :4; 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Mon, 21 Oct 2024 12:56:42 -0500 From: Mario Limonciello To: Borislav Petkov CC: Thomas Gleixner , Ingo Molnar , "Dave Hansen" , "maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)" , "H . Peter Anvin" , "Rafael J . Wysocki" , "Gautham R . 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This flag is beneficial for processors with one or more CCDs and relies on x86_sched_itmt_flags(). Signed-off-by: Perry Yuan Co-developed-by: Mario Limonciello Signed-off-by: Mario Limonciello --- Rename to match correct x86 feature name --- arch/x86/kernel/smpboot.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c index 766f092dab80b..b5a8f0891135b 100644 --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -497,8 +497,9 @@ static int x86_cluster_flags(void) static int x86_die_flags(void) { - if (cpu_feature_enabled(X86_FEATURE_HYBRID_CPU)) - return x86_sched_itmt_flags(); + if (cpu_feature_enabled(X86_FEATURE_HYBRID_CPU) || + cpu_feature_enabled(X86_FEATURE_AMD_HETEROGENEOUS_CORES)) + return x86_sched_itmt_flags(); return 0; } From patchwork Mon Oct 21 17:55:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 837330 Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2046.outbound.protection.outlook.com [40.107.223.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AA05E1F893D; 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Mon, 21 Oct 2024 12:56:43 -0500 From: Mario Limonciello To: Borislav Petkov CC: Thomas Gleixner , Ingo Molnar , "Dave Hansen" , "maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)" , "H . Peter Anvin" , "Rafael J . Wysocki" , "Gautham R . Shenoy" , Mario Limonciello , Perry Yuan , Brijesh Singh , Peter Zijlstra , Li RongQing , "open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)" , "open list:ACPI" , "open list:AMD PSTATE DRIVER" Subject: [PATCH 4/4] x86/amd: Move AMD core type identification code Date: Mon, 21 Oct 2024 12:55:09 -0500 Message-ID: <20241021175509.2079-5-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241021175509.2079-1-mario.limonciello@amd.com> References: <20241021175509.2079-1-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF000044A4:EE_|PH7PR12MB9076:EE_ X-MS-Office365-Filtering-Correlation-Id: 56044947-3120-4ca8-76a1-08dcf1f9baf4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|376014|7416014|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: d5LazVxW/yNiCt6tsHr6KuDIdsPRiKtooMsyoZKKCbaTqD8DbiRHeqjtQtjSwV/DASZH6ZR7cOpnrxfFHnynp5ZcswXiq+imNR1I0Ek8a6Bfytss71kiXBmvltNdyl3aMC70UAczuK1rId88QH1rWuJ/Q+8qY3b2T2obdASncdG4gecojHHySakHxC8g1q+06xG35QtHVRYZIqR81gHIjd8T+uHBe9FSfVPLO2v3yXJmzPAYq31qfj1n/whnG3amC6Mah/r+0soB4jgICzKCTOFjqtCW0nqjP2st4YDPEYMQ4xtOuFaatAhR1ByPBek02NIaFx78BtagyPJuy0CLndlYoWqDCUmImCTzUEPIKyS46GZa1g6Xq8WWMJsJUrNtvNkxb4sMLtLtpJjoEpR6mwy+Ax2H2ynS3w76UUtn7m41VxqbAnVdfl0IBWZNGuo/eQ+xmZCFEGUR3RH6z9NvAE4it02CXwXi3wdn8vUDhDrgW3ozwBRwBjGqlKgcAi33AIhZJzP9AFOqAEeRy//GUob2F7E8QqpIKCmhSIvL+0CUio5PJRMVEljavqRyNYU7A0WIhuCBHKDXv9SQkUwZgkfd3c/ZXmZltw3CaLo7q46ucwVeTjik4bjVaKggnnFwymQ2F8t6ZwOAQliAU1WoyeM+Vgfl8kEd9/wqPc2IPSj0hE+PJo3mMAY6j/JBvqzTHcQE8JdqfJWtodQSDMTXxgHIajW5ZmuZBmnSzkGxvlXRbMjbNsEdxq+jGQfj3DlRaSlaiyIUmR+7H1tg5A/b3Yv0PVPfNsy31oXpmDtPdOlgcDtA6+NuW9Vbz3SVIY/TWoAG/8XEWQJZBZKfcPcwPAcz4rfkY/Fltc3Tjdurt6iplP4+J1sUNUxMwDvKrcpbQjKUQhHxHSdfpHasCqlu92qhuq2vy4WO1MgLdMHIA5pkGLZYTHCf6YMGrOnbTzfMrDgGkdTrPGjt1ktsa+kBrb63dZA9RNlJTNX4fHKj0idNEVSrvjXosUHjak2SeRGXekhaiZrWB2pIesB1/e2pT0pKK0lKHt7BxXAn9X1f1wgkoW2GsS++tTX+ZxH/mbu6BnqPITseufUc54kvvwQec2FYT5f7IYndu9KLxDH7TPUtLQpxf4PiNBVyHcd6F3h9VsShwB7M4QZ9YzhuoMYYonz174AIcGqy5owxW/lv0saqX3W75RMAH/cvwpXZcW8DM4LK8DoI+dReAf1TE0hy1ZwKTdLI/jhrhcIXwoe5UsmEf9rHEwCpniEfVds1AwzQ4MV175AdRyTWbYIddT3sowqwJ6e/QuWobUyhtp8/5GpWZ+7h+bYMGNZBFLNLep4i3YHdghBiS5BWdG1p3A67WcGf9WZ7xhR+9EaX9AA9+3Ri/hFTMk3poUhvZsMsbygaroG7JXGhAoJQrVPN17QSUQ== X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(1800799024)(376014)(7416014)(36860700013)(82310400026); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Oct 2024 17:56:46.4876 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 56044947-3120-4ca8-76a1-08dcf1f9baf4 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000044A4.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB9076 The enum used for AMD core type identification is AMD specific so it should only be in the definition for CONFIG_CPU_SUP_AMD. Move the enum into this scope and adjust function return types since enum amd_core_type won't be available in the non CONFIG_CPU_SUP_AMD case. Instead of a dedicated enum definition of no hetero support use -EINVAL. Suggested-by: Borislav Petkov Signed-off-by: Mario Limonciello --- arch/x86/include/asm/processor.h | 15 +++++++-------- arch/x86/kernel/acpi/cppc.c | 2 +- arch/x86/kernel/cpu/amd.c | 7 +++---- 3 files changed, 11 insertions(+), 13 deletions(-) diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h index d81a6efa81bb0..5b772036f6e83 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -691,15 +691,14 @@ static inline u32 per_cpu_l2c_id(unsigned int cpu) return per_cpu(cpu_info.topo.l2c_id, cpu); } +#ifdef CONFIG_CPU_SUP_AMD /* defined by CPUID_Fn80000026_EBX BIT [31:28] */ enum amd_core_type { - CPU_CORE_TYPE_NO_HETERO_SUP = -1, - CPU_CORE_TYPE_PERFORMANCE = 0, - CPU_CORE_TYPE_EFFICIENCY = 1, - CPU_CORE_TYPE_UNDEFINED = 2, + CPU_CORE_TYPE_PERFORMANCE, + CPU_CORE_TYPE_EFFICIENCY, + CPU_CORE_TYPE_UNDEFINED, }; -#ifdef CONFIG_CPU_SUP_AMD /* * Issue a DIV 0/1 insn to clear any division data from previous DIV * operations. @@ -711,13 +710,13 @@ static __always_inline void amd_clear_divider(void) } extern void amd_check_microcode(void); -extern enum amd_core_type amd_get_core_type(void); +extern int amd_get_core_type(void); #else static inline void amd_clear_divider(void) { } static inline void amd_check_microcode(void) { } -static inline enum amd_core_type amd_get_core_type(void) +static inline int amd_get_core_type(void) { - return CPU_CORE_TYPE_NO_HETERO_SUP; + return -EINVAL; } #endif diff --git a/arch/x86/kernel/acpi/cppc.c b/arch/x86/kernel/acpi/cppc.c index ca289e6ec82c9..e25494212d964 100644 --- a/arch/x86/kernel/acpi/cppc.c +++ b/arch/x86/kernel/acpi/cppc.c @@ -273,7 +273,7 @@ int amd_get_boost_ratio_numerator(unsigned int cpu, u64 *numerator) /* detect if running on heterogeneous design */ smp_call_function_single(cpu, amd_do_get_core_type, &core_type, 1); switch (core_type) { - case CPU_CORE_TYPE_NO_HETERO_SUP: + case -EINVAL: break; case CPU_CORE_TYPE_PERFORMANCE: /* use the max scale for performance cores */ diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index 0f533e6260d29..a0d17993d52ce 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -1211,10 +1211,9 @@ void amd_check_microcode(void) * Returns the CPU type [31:28] (i.e., performance or efficient) of * a CPU in the processor. * - * If the processor has no core type support, returns - * CPU_CORE_TYPE_NO_HETERO_SUP. + * If the processor has no core type support, returns -EINVAL. */ -enum amd_core_type amd_get_core_type(void) +int amd_get_core_type(void) { struct { u32 num_processors :16, @@ -1224,7 +1223,7 @@ enum amd_core_type amd_get_core_type(void) } props; if (!cpu_feature_enabled(X86_FEATURE_AMD_HETEROGENEOUS_CORES)) - return CPU_CORE_TYPE_NO_HETERO_SUP; + return -EINVAL; cpuid_leaf_reg(0x80000026, CPUID_EBX, &props); if (props.core_type >= CPU_CORE_TYPE_UNDEFINED)