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Shenoy" , "Mario Limonciello" , Perry Yuan , , , , , "Shyam Sundar S K" Subject: [PATCH v2 02/13] MAINTAINERS: Add maintainer entry for AMD Hardware Feedback Driver Date: Thu, 10 Oct 2024 14:36:54 -0500 Message-ID: <20241010193705.10362-3-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241010193705.10362-1-mario.limonciello@amd.com> References: <20241010193705.10362-1-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF000015C7:EE_|DS0PR12MB7605:EE_ X-MS-Office365-Filtering-Correlation-Id: 79fb3897-0cdc-4734-bbcd-08dce9630235 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|36860700013|376014|82310400026; X-Microsoft-Antispam-Message-Info: PyqoU+T+3ci+uuWXQVdL9V42YavydJ7APSqi+CFbLcDCV3wdHWl9VNx7VlIEsEFlSBNrEXp6KJQSfHwvsLI+GEYCVZV8p3hLZstInc2/8Ptjjhvtt9xJY+fP59w+LTiIp9iJFC2gFUbH/CQl7Kzfz/od2JYWX6cP/5lHvWN/K5WNhOmYvTVpsqtMuXXB40/6ieo7VIlxk9CCzSbugdKRr/Fjx7I0jrFW3tWRcfBHsh9MHeJSE2p+hIuYj3TaWaCzOU/YZO+BXrZ5Lr/kVXs5YzbL5lVo1MvvM88xkuoTT4iN9TJMZST2y3OwUkt0ZQFHRn36GOS1VnUQ0AONi96+nekwBkWrYoIfxDloyrOhkm1ABn+k94+LvydvVg/Jkj+TRsaHV3A9jKuWNOIWvOluhoIO1Ad88nIF9KWzTYLhuVynHZIcLltJgbqiO6Zg8mjzqwl5+KBYuUxnJ0H2rLj9LFqGvzts5RY1O8aQZMiqlQj6SBAvOP2atPmC+42rMOY2Q5K+oz0BZDctr/8k9Q1/wd8cr+sg0pmAsRN6qNzgOa5HSccOjiy9wfhVbpKhT35oBa8vpW5ot7VrPRyD+XaPN2R0y/vzb3+A1UyqW6z0xlWmIJBSCX/97juHqgAVf1iUjPibEsXSWQ0T72DPYb1uz8B6z4GQEEcevxvFL5pRfqLYH7sDuStEgqR+Zr6eebRUhvcF9uNhHgxr5zaYgmy6U3upTwm3rnKGb5HKKSLmGROML5yUmMdqWHVafY4FDyK0MnaF1HcmbjKs67cHZs7MOiwLplTX2rku6b2PJU0qETMuk6wt4GTxu3CDct70Mc3Q/sLRuN3igh5oE+JpJ6yXk4D9205gOCs9OcpprhwJ+B14pCELJEosRt6njWQh69AztH/koFrdjHTkluRCUZ26YrnjlNZQhSm6Ug8Ct6Hyfo47V4TKC4i4ryHcyQ0abQqUeoikv5DgVYSrVM31KDjslp9E2yyEPtCq+ENlt8LF6A0t9iwFyv2+mwKYku9R41pQKLY+9p/JFOje+JA0MWNAy3k1SZvcFTXVJPSFdYurrWlDI7UEw2g+GjvkvmrDiw/DcpBp5mjg7ZmyzwO5b2LrbTBemUD6v70jk4urK0g5MElOvlLTCh7vEzkBAO00UFtKcy7pCiL0RkNunRTGJchOXAoSh5LRkeosR9wegT8M1Rsa2BMHgxbOXN9fW6Owb5wqKa9+8wW4yzlUyMo581DiJJnfivisBzTBo1QpvZ0Dc9qUpV6oqoYLkxtDgoWTIhdCEsJ9MuNqrpAYsXjFdNDLbocbJWgDrGjN0EiV+DLhjrX+qd9pOJXC/we8HdCT2jW8 X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(1800799024)(36860700013)(376014)(82310400026); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Oct 2024 19:37:42.6940 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 79fb3897-0cdc-4734-bbcd-08dce9630235 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF000015C7.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7605 Introduce the `amd_hfi` driver into the MAINTAINERS file. The driver will support AMD Heterogeneous Core design which provides hardware feedback to the OS scheduler. Moving forward, Mario will be responsible for the maintenance and Perry will assist on review of patches related to this driver. Signed-off-by: Mario Limonciello --- v2: * Make Perry Reviewer instead of Maintainer, he asked me to take over this series. --- MAINTAINERS | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index a097afd76ded..90094e064d94 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1083,6 +1083,15 @@ F: arch/x86/include/asm/amd_hsmp.h F: arch/x86/include/uapi/asm/amd_hsmp.h F: drivers/platform/x86/amd/hsmp.c +AMD HETERO CORE HARDWARE FEEDBACK DRIVER +M: Mario Limonciello +R: Perry Yuan +L: platform-driver-x86@vger.kernel.org +S: Supported +B: https://gitlab.freedesktop.org/drm/amd/-/issues +F: Documentation/arch/x86/amd-hfi.rst +F: drivers/platform/x86/amd/hfi/ + AMD IOMMU (AMD-VI) M: Joerg Roedel R: Suravee Suthikulpanit From patchwork Thu Oct 10 19:36:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 834424 Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10on2077.outbound.protection.outlook.com [40.107.93.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 56CB41E1330; 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Thu, 10 Oct 2024 14:37:41 -0500 From: Mario Limonciello To: Borislav Petkov , Hans de Goede , =?utf-8?q?Ilpo_J=C3=A4rvinen?= CC: , "Gautham R . Shenoy" , "Mario Limonciello" , Perry Yuan , , , , , "Shyam Sundar S K" Subject: [PATCH v2 03/13] x86/cpufeatures: add X86_FEATURE_WORKLOAD_CLASS feature bit Date: Thu, 10 Oct 2024 14:36:55 -0500 Message-ID: <20241010193705.10362-4-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241010193705.10362-1-mario.limonciello@amd.com> References: <20241010193705.10362-1-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF000015C7:EE_|SN7PR12MB7855:EE_ X-MS-Office365-Filtering-Correlation-Id: 6b330fe6-0e08-4f34-c7db-08dce96302e3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|36860700013|1800799024|376014|82310400026; X-Microsoft-Antispam-Message-Info: 9Jup9iaUe/+PRvznZ5mUpPO0+CxH8WTbEPvRYq+eltDhmxvm3fpTX7+Unea1ZGyVq8B+n79cgb4AJZLPWJH5DyovI8vLEKNm0Zqyp/NU+IF3qNOaRg8TK8wp2lkBlCAo3LoRYPMG1s/fZM2gdW/iM0Qcjs4MV5tzKC4+OCCevPYCGPx7cEEdg/4bQ8cEXksk0ZuEDCEmZZM/yXp6IULzAcZPLuqmG15BMs4efJpjFS4zcjhmoqSa0EG8OCo1KL4EfZBG7Miu2D44yO8Ep8aCkeTgRipeTemCkvi0xGatH423gHNWy7cxdHF0ghlFeAz+4UZkLCYmw3PQryDJNF3cSIH2Y+WC/NKd0ZJgmybsy34kv8+/w0RxM4YlqnxNo4/YfS+ncf+bA3Jz6T5h64nUb2cwugyiQlOZEnSMvp2dnOya2e51x6uiLm9VrP/9KUXNYdDDuqYfGbddVChVqBXz57hNYYC6NrWFxHx+VmbAOlw8MT3ihyv67JS307ZnidVqXyA4afVUFQY2P4P6b8kpkgXse3GDRX9S2rpQy2pTP+lp4y5fsRTC2uMaPimoc1GjYAtqtQlW+SyC3oY5sUmwiY7wSb9ixK9IMZrP/SkHdjgybON680f8qKR1F2EsfoqF0tWnXdhnM6aMvngUF3RYLhDpTBLUv84P2BH24xs0GzZLxV8I4pN4fLq7LbG4innLJOsY3K7u1YeCVhCoFoKjHVBo+0SO4z8FqbQ4Ci4z+J++QlPpDQeY/c2kT/m9pk1nlKn/VOAX/ekTsKHxI0e+M3XhFQLkDr7F6prMHypKz9yuyuQixzHoR2daFLp7Vxu8WWYA7jRKGmffcHFTPX2i9LRHfG8PYkliOtuFf0T1GoIixtpvQ4hfgEviTwnWNooXXydFkrWFwznzBBOPR6OYZPYyLZhJyCHfVlstlINhMSf84yDLrxOJ81sato2uCia+KAv44RIG1/5PXaZmKIHO5LlYBDjgm7PskytevltRJ7Sp8Ut+Gq0Klzmj20F2tt5xq6PKXR49VZ3zalmNLqmljUwgggl8drJGK0/BTpE8PsSyMku3ywUM3yruVXRcMlaqiryYcZudatwaQBkNS3Uy06fVym+fsaBU54ah+n0OhK2wpAjp0lvbPQJe2lO+7rdC0TGiNTGTOQ+1LUmS3nFWU69rd1ryfo3tUEVaItY+dWI/4wnHEnkw0dWkBgwSOVtesqmxYEesuXgwszgltVmQXU+lLAZP4mTufN/t8Ow9pVr64+LYzhjlxezO6PdJWdARBNg3hT+K1e9XVlAorYG9YqbYY4zJ73QSiDTeAS9AlKw1aHnEu5nJeIa8m7mS0n8H3OkTGjKd2xADDmDO6ZbjKlY3ONH5WD9+bwEdzX0lX0bD5Ttjom+7w1TSA/rDozDs X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(36860700013)(1800799024)(376014)(82310400026); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Oct 2024 19:37:43.8502 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6b330fe6-0e08-4f34-c7db-08dce96302e3 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF000015C7.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7855 From: Perry Yuan Add new feature bit that indicates support for workload based heuristic feedback to OS for scheduling decisions. When the bit set, threads are classified during runtime into enumerated classes. The classes represent thread performance/power characteristics that may benefit from special scheduling behaviors. Signed-off-by: Perry Yuan Signed-off-by: Mario Limonciello --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/kernel/cpu/scattered.c | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index cea1ed82aeb4..3e8e67b8ec7a 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -474,6 +474,7 @@ #define X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT (21*32+ 4) /* Clear branch history at vmexit using SW loop */ #define X86_FEATURE_FAST_CPPC (21*32 + 5) /* AMD Fast CPPC */ #define X86_FEATURE_HETERO_CORE_TOPOLOGY (21*32 + 6) /* Heterogeneous Core Topology */ +#define X86_FEATURE_WORKLOAD_CLASS (21*32 + 7) /* Workload Classification */ /* * BUG word(s) diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c index 3bba55323163..b6547bab9e23 100644 --- a/arch/x86/kernel/cpu/scattered.c +++ b/arch/x86/kernel/cpu/scattered.c @@ -49,6 +49,7 @@ static const struct cpuid_bit cpuid_bits[] = { { X86_FEATURE_MBA, CPUID_EBX, 6, 0x80000008, 0 }, { X86_FEATURE_SMBA, CPUID_EBX, 2, 0x80000020, 0 }, { X86_FEATURE_BMEC, CPUID_EBX, 3, 0x80000020, 0 }, + { X86_FEATURE_WORKLOAD_CLASS, CPUID_EAX, 22, 0x80000021, 0 }, { X86_FEATURE_PERFMON_V2, CPUID_EAX, 0, 0x80000022, 0 }, { X86_FEATURE_AMD_LBR_V2, CPUID_EAX, 1, 0x80000022, 0 }, { X86_FEATURE_AMD_LBR_PMC_FREEZE, CPUID_EAX, 2, 0x80000022, 0 }, From patchwork Thu Oct 10 19:36:57 2024 Content-Type: text/plain; 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Shenoy" , "Mario Limonciello" , Perry Yuan , , , , , "Shyam Sundar S K" , Perry Yuan Subject: [PATCH v2 05/13] platform/x86: hfi: Introduce AMD Hardware Feedback Interface Driver Date: Thu, 10 Oct 2024 14:36:57 -0500 Message-ID: <20241010193705.10362-6-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241010193705.10362-1-mario.limonciello@amd.com> References: <20241010193705.10362-1-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF000015C7:EE_|MN2PR12MB4359:EE_ X-MS-Office365-Filtering-Correlation-Id: 20e8579c-eec8-45ef-6e48-08dce96303cd X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|376014|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: IqVBRPWC+6p75ZRovi3I7gpbbF6B6TWVmGTay70dB40lHP99usghIYxD1yu4wqB/V8Ejuw6sD5jFqykwHAnToHQF1FwGKTnn4c+jQFe/RyxVVRYp2WXOb5H13gKzKuS8PgpjlfMRPq8qC6GDLJz7imPw91QTHlbEVdhEhdAUQFjHhZu5Aclk/4V+GA54v6yICO9dYoKyLAWRrc0baKZbuHkVTHmI3zjbF8ouooQrfYAESYfh5+uHjvhFQDeOe9p9YHb2bQ45ohQtLit56fkUSY75sK45csE/Xnt+m6F4wO12uq4Csa65CP1WXOj5XhaWhWllWQY7VItZ8B4b2i0CqEXbH9Uq89FBIm0ct7bPF0yfkWB2JMvCMaFj9AAphc6K57dcgwia96D3Ei6Kg9Qukwc+EPguryh+vFuKnNBqObFWtODAVF8VuH+MlVCFW1TzgIgSz0IueAY+eWmjWFdBoAZvVg1c4eJ2y+0pSm6rxm1MW6XM4pmWon/36QN4oKL+eQRW0zGGL6XwdK31tXoFoZw11ERpwK8nocR6y0n2xJEWnSw/vsNF8m63XgfoSJw2IvYOor0oNiBXTtsPv/BgZzNhNDRu4kS4fk+pM7yrcFp2dsVojCFoVcLpmBvSS63L2QkIxTRvQYBBmKDCFunbT2jPGZ0DBP5vz+Eho/53Tez/I0c89EaHFbQQyn3Qwog0HDLdzuEk5sLN4HNv6udU/gOjhix6XZvwGBZR4wducxCVIpKAjKhRf6Lyp47e5FTptdT+0sj6cqxoIKj9PUNjG2QgWPwtm4zd0g55C9lRbHeLGQdidD2qr72PWzZBqtzyGDYXrbtT8tziURSpL7Nofa8f31pniUYh68gtjUxPLcH7fJO8hX6L6Ugfq76f+pfXab8z0R0SmVLO35V0wLDOWOEn/8M6mrqz+Nf1i2E3rYSVPnJIJVKdSvMZou1UmdRocKe4IpSgna3ojc6VdOth0ynFv1ijcFEPkFRQrojsK+/wlkW7YnjL12zXJ773ebkF2I6MsYjhCOMznpt4lkR2vC2nOiKUjN1HlSnCNbTSRA3GQ2yXLEsDdV3t8eo55KZ7dAWfxNTxC4wHnB3s62kQWN/hFkrLnPPVlrGIpTSK0kSp3Lp2VSlpWfrJUrnW+n7SmTnYVYwzsywz1trL85SZ/OnJBcUJOg99ppjZ0+cnu1CdCCs21Rc0+nhvKwysrUf7SvbwPH8mr1y5KDGQTtFCyLwiJW1axQlQhk/prAlrH0+MPW0hjsyT9V1EPNhZtrUJEiFBcbNGmyP1wjYGCmrxPIO+5A/byYEdFgZ3OSP7XtY3v8OvfRNPN5UC/jOwqKoZ9ag1JNG8mTmzqHzmeCDp3o/U4LT8dCFu4pLCmHj0rREbLB3VzCd9XcfBZUgl4g6U X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(1800799024)(376014)(36860700013)(82310400026); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Oct 2024 19:37:45.3815 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 20e8579c-eec8-45ef-6e48-08dce96303cd X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF000015C7.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4359 From: Perry Yuan The AMD Heterogeneous core design and Hardware Feedback Interface (HFI) provide behavioral classification and a dynamically updated ranking table for the scheduler to use when choosing cores for tasks. There are two CPU core types defined: `Classic Core` and `Dense Core`. "Classic" cores are the standard performance cores, while "Dense" cores are optimized for area and efficiency. Heterogeneous compute refers to CPU implementations that are comprised of more than one architectural class, each with two capabilities. This means each CPU reports two separate capabilities: "perf" and "eff". Each capability lists all core ranking numbers between 0 and 255, where a higher number represents a higher capability. Heterogeneous systems can also extend to more than two architectural classes. The purpose of the scheduling feedback mechanism is to provide information to the operating system scheduler in real time, allowing the scheduler to direct threads to the optimal core during task scheduling. All core ranking data are provided by the BIOS via a shared memory ranking table, which the driver reads and uses to update core capabilities to the scheduler. When the hardware updates the table, it generates a platform interrupt to notify the OS to read the new ranking table. Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537 Signed-off-by: Perry Yuan Co-developed-by: Mario Limonciello Signed-off-by: Mario Limonciello --- v2: * Drop unnecessary select * Make tristate instead of bool * Drop error messages * Drop unnecessary function declarations for init * Fix cleanup for amd_hfi_exit() * Drop unnecessary variables for upcoming features --- drivers/platform/x86/amd/Kconfig | 1 + drivers/platform/x86/amd/Makefile | 1 + drivers/platform/x86/amd/hfi/Kconfig | 20 +++ drivers/platform/x86/amd/hfi/Makefile | 7 ++ drivers/platform/x86/amd/hfi/hfi.c | 169 ++++++++++++++++++++++++++ 5 files changed, 198 insertions(+) create mode 100644 drivers/platform/x86/amd/hfi/Kconfig create mode 100644 drivers/platform/x86/amd/hfi/Makefile create mode 100644 drivers/platform/x86/amd/hfi/hfi.c diff --git a/drivers/platform/x86/amd/Kconfig b/drivers/platform/x86/amd/Kconfig index f88682d36447..c3f69dbe3037 100644 --- a/drivers/platform/x86/amd/Kconfig +++ b/drivers/platform/x86/amd/Kconfig @@ -5,6 +5,7 @@ source "drivers/platform/x86/amd/pmf/Kconfig" source "drivers/platform/x86/amd/pmc/Kconfig" +source "drivers/platform/x86/amd/hfi/Kconfig" config AMD_HSMP tristate "AMD HSMP Driver" diff --git a/drivers/platform/x86/amd/Makefile b/drivers/platform/x86/amd/Makefile index dcec0a46f8af..2676fc81fee5 100644 --- a/drivers/platform/x86/amd/Makefile +++ b/drivers/platform/x86/amd/Makefile @@ -9,3 +9,4 @@ amd_hsmp-y := hsmp.o obj-$(CONFIG_AMD_HSMP) += amd_hsmp.o obj-$(CONFIG_AMD_PMF) += pmf/ obj-$(CONFIG_AMD_WBRF) += wbrf.o +obj-$(CONFIG_AMD_HFI) += hfi/ diff --git a/drivers/platform/x86/amd/hfi/Kconfig b/drivers/platform/x86/amd/hfi/Kconfig new file mode 100644 index 000000000000..08051cd4f74d --- /dev/null +++ b/drivers/platform/x86/amd/hfi/Kconfig @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# AMD Hardware Feedback Interface Driver +# + +config AMD_HFI + bool "AMD Hetero Core Hardware Feedback Driver" + depends on ACPI + depends on CPU_SUP_AMD + help + Select this option to enable the AMD Heterogeneous Core Hardware Feedback Interface. If + selected, hardware provides runtime thread classification guidance to the operating system + on the performance and energy efficiency capabilities of each heterogeneous CPU core. + These capabilities may vary due to the inherent differences in the core types and can + also change as a result of variations in the operating conditions of the system such + as power and thermal limits. If selected, the kernel relays updates in heterogeneous + CPUs' capabilities to userspace, allowing for more optimal task scheduling and + resource allocation, leveraging the diverse set of cores available. + + diff --git a/drivers/platform/x86/amd/hfi/Makefile b/drivers/platform/x86/amd/hfi/Makefile new file mode 100644 index 000000000000..672c6ac106e9 --- /dev/null +++ b/drivers/platform/x86/amd/hfi/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# AMD Hardware Feedback Interface Driver +# + +obj-$(CONFIG_AMD_HFI) += amd_hfi.o +amd_hfi-objs := hfi.o diff --git a/drivers/platform/x86/amd/hfi/hfi.c b/drivers/platform/x86/amd/hfi/hfi.c new file mode 100644 index 000000000000..da2e667107e8 --- /dev/null +++ b/drivers/platform/x86/amd/hfi/hfi.c @@ -0,0 +1,169 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * AMD Hardware Feedback Interface Driver + * + * Copyright (C) 2024 Advanced Micro Devices, Inc. All Rights Reserved. + * + * Author: Perry Yuan + * + */ + +#define pr_fmt(fmt) "amd-hfi: " fmt + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define AMD_HFI_DRIVER "amd_hfi" +#define AMD_HETERO_CPUID_27 0x80000027 +static struct platform_device *device; + +struct amd_hfi_data { + const char *name; + struct device *dev; + struct mutex lock; +}; + +struct amd_hfi_classes { + u32 perf; + u32 eff; +} __packed; + +/** + * struct amd_hfi_cpuinfo - HFI workload class info per CPU + * @cpu: cpu index + * @cpus: mask of cpus associated with amd_hfi_cpuinfo + * @class_index: workload class ID index + * @nr_class: max number of workload class supported + * @amd_hfi_classes: current cpu workload class ranking data + * + * Parameters of a logical processor linked with hardware feedback class + */ +struct amd_hfi_cpuinfo { + int cpu; + cpumask_var_t cpus; + s16 class_index; + u8 nr_class; + struct amd_hfi_classes *amd_hfi_classes; +}; + +static DEFINE_PER_CPU(struct amd_hfi_cpuinfo, amd_hfi_cpuinfo) = {.class_index = -1}; + +static int amd_hfi_alloc_class_data(struct platform_device *pdev) +{ + struct amd_hfi_cpuinfo *hfi_cpuinfo; + struct device *dev = &pdev->dev; + int idx; + int nr_class_id; + + nr_class_id = cpuid_eax(AMD_HETERO_CPUID_27); + if (nr_class_id < 0 || nr_class_id > 255) { + dev_warn(dev, "failed to get supported class number from CPUID %d\n", + AMD_HETERO_CPUID_27); + return -EINVAL; + } + + for_each_possible_cpu(idx) { + hfi_cpuinfo = per_cpu_ptr(&amd_hfi_cpuinfo, idx); + hfi_cpuinfo->amd_hfi_classes = devm_kmalloc(dev, nr_class_id * + sizeof(struct amd_hfi_classes), GFP_KERNEL); + if (!hfi_cpuinfo->amd_hfi_classes) + return -ENOMEM; + + hfi_cpuinfo->nr_class = nr_class_id; + } + + return 0; +} + +static void amd_hfi_remove(struct platform_device *pdev) +{ + struct amd_hfi_data *dev = platform_get_drvdata(pdev); + + mutex_destroy(&dev->lock); +} + +static const struct acpi_device_id amd_hfi_platform_match[] = { + { "AMDI0104", 0}, + { } +}; +MODULE_DEVICE_TABLE(acpi, amd_hfi_platform_match); + +static int amd_hfi_probe(struct platform_device *pdev) +{ + struct amd_hfi_data *amd_hfi_data; + int ret; + + if (!acpi_match_device(amd_hfi_platform_match, &pdev->dev)) + return -ENODEV; + + amd_hfi_data = devm_kzalloc(&pdev->dev, sizeof(*amd_hfi_data), GFP_KERNEL); + if (!amd_hfi_data) + return -ENOMEM; + + amd_hfi_data->dev = &pdev->dev; + + mutex_init(&amd_hfi_data->lock); + platform_set_drvdata(pdev, amd_hfi_data); + + /* alloc data array for hardware feedback class data */ + ret = amd_hfi_alloc_class_data(pdev); + if (ret) + goto out; + +out: + return ret; +} + +static struct platform_driver amd_hfi_driver = { + .driver = { + .name = AMD_HFI_DRIVER, + .owner = THIS_MODULE, + .acpi_match_table = ACPI_PTR(amd_hfi_platform_match), + }, + .probe = amd_hfi_probe, + .remove_new = amd_hfi_remove, +}; + +static int __init amd_hfi_init(void) +{ + int ret; + + if (acpi_disabled || + !boot_cpu_has(X86_FEATURE_HETERO_CORE_TOPOLOGY) || + !boot_cpu_has(X86_FEATURE_WORKLOAD_CLASS)) + return -ENODEV; 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Thu, 10 Oct 2024 14:37:45 -0500 From: Mario Limonciello To: Borislav Petkov , Hans de Goede , =?utf-8?q?Ilpo_J=C3=A4rvinen?= CC: , "Gautham R . Shenoy" , "Mario Limonciello" , Perry Yuan , , , , , "Shyam Sundar S K" , Perry Yuan Subject: [PATCH v2 07/13] platform/x86: hfi: init per-cpu scores for each class Date: Thu, 10 Oct 2024 14:36:59 -0500 Message-ID: <20241010193705.10362-8-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241010193705.10362-1-mario.limonciello@amd.com> References: <20241010193705.10362-1-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF000015CB:EE_|MW6PR12MB8950:EE_ X-MS-Office365-Filtering-Correlation-Id: dd2b95ba-8501-4405-825b-08dce96304dd X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|36860700013|82310400026|376014; X-Microsoft-Antispam-Message-Info: VuHKUbOqUXK/SY1GAN47n3CoyxEyIDQGYnjIeGlqfI2DAllETF1Sm/JQ9RkXkyeFZLBo5wiG8kA5h8Ks27aohp6ppe/wzfirCy2XQ9Dpm2sxp+VH50+sSULowSpylKcnXEa3zFyVoAuZ16QsFwWAHJADGV8I51avUbO+aWGeqet92C2r6Zh44uTlPomrMUz6uZT1ubeZXPxU9Q3xt11KGdN7rcmOyKuvNkZkGSb81m1lIIAVDeD7YF5ZmD+mejg3LlS0IPPW9x45Js1AFmoVUAxGfHF0mHYh2Jpu1xwxUEzh6TbLtN1FfWfoiTM/SXM/KbSBspOsJvD41v6XYfKt3DgTHtSbCuzwQPdWmYDNVrYyCYzaVCgZMNOkylTlVSH8UPuWNrRYjF0z8glTC7bNMr+xW9CaeRNhfk33BpusWlSl03B7Hs/zn/AFtkkRNhhoDBc2IqfR0RlMmv03sPuW3xgrfnrxg4fQU5RKR2qKfa+i92h4gJh+j+f00CMLuXI7ME2gz2dY9wVQTNDsdTAWiua3wKXp7EJGDK6r0G0HN5n3rGGjtCjtnFABYWkKK1gHjgyyyaDnKyBAx2hetLsKhrP5gZlzpnMrZ/kFuz5qIbRe+WizFlyztyUy7YO58aX1KZgjHNJGrrNHSe8o1TgP3qxetaXSvxmP9NYk5oEO9w7ZtPr40sDwJELf8IqB4v4w2Mee/7iAs2/NJPnltwcsq02KU1gxZKEqIFWRogjV3Z28jC4SaIxhZUUr8eDcurHgG8eIF09HCX0qd/zpvf3nOvDOR+O5XM7+7Bzqvxd/CNTJXVDRV05kKRwn79cjvFO412MuycCutuICOMN7/30wYTBA73g/i4E17jnBucjiOELZ8PXWRC+LjkearrncrNOzq6ePCIEgKjCqD5i+ZixnnnDHfy4QOLcCgaWOAA7ca7DNjJ1YME9yaSG44LtPgzrZ60T1d3MBQ9iKWbOXV5Bo+dIVNU4qN3Tdx+LDqhCeWG7D52m0PNAoFVYXdp6HcsWZnay0c1ToosuEK7HBD3W5q1jB410wH6BB2guHJqENT/VAvr3dE7HvvuJpfj1ce0ehl02Ow7VJx7JUJg8gcbyvIEhGjFnGI/7fAL1HS9CLwnof7q6hbArufuzX98wjQNw7kNF46V3qd+YkccMxrsGV3fOPLiGhrQl7baMjZ+LFiyIs5mB+0JMAz0Ep0oRZk6y87jywnKHqvej24J7qs9q+woPGGedgDfphI4MIrs/gIYFjHtog8bMzNagn1Go1aHE/jiKs1hbgaartMbSovJ+vclO/WpFLlZsPEMv/NfaRiZOOTmjT4IOHYUuC1l/JiM4Q8Po/Y2TxZ2ozP+aYWQoWQVqqb0LovMWRdneRepS65+prI4EEmIGULV56QcMp48/5 X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(1800799024)(36860700013)(82310400026)(376014); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Oct 2024 19:37:47.1646 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: dd2b95ba-8501-4405-825b-08dce96304dd X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF000015CB.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW6PR12MB8950 From: Perry Yuan Initialize per cpu score `amd_hfi_ipcc_scores` which store energy score and performance score data for each class. `Classic core` and `Dense core` are ranked according to those values as energy efficiency capability or performance capability. OS scheduler will pick cores from the ranking list on each class ID for the thread which provide the class id got from hardware feedback interface. Signed-off-by: Perry Yuan Co-developed-by: Mario Limonciello Signed-off-by: Mario Limonciello --- v2: * Rework --- drivers/platform/x86/amd/hfi/hfi.c | 32 ++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/drivers/platform/x86/amd/hfi/hfi.c b/drivers/platform/x86/amd/hfi/hfi.c index 10651399cf75..c0065ba0ed18 100644 --- a/drivers/platform/x86/amd/hfi/hfi.c +++ b/drivers/platform/x86/amd/hfi/hfi.c @@ -119,6 +119,8 @@ struct amd_hfi_cpuinfo { static DEFINE_PER_CPU(struct amd_hfi_cpuinfo, amd_hfi_cpuinfo) = {.class_index = -1}; +static DEFINE_MUTEX(hfi_cpuinfo_lock); + static int find_cpu_index_by_apicid(unsigned int target_apicid) { int cpu_index; @@ -233,6 +235,31 @@ static void amd_hfi_remove(struct platform_device *pdev) mutex_destroy(&dev->lock); } +static int amd_set_hfi_ipcc_score(struct amd_hfi_cpuinfo *hfi_cpuinfo, int cpu) +{ + for (int i = 0; i < hfi_cpuinfo->nr_class; i++) + WRITE_ONCE(hfi_cpuinfo->ipcc_scores[i], + hfi_cpuinfo->amd_hfi_classes[i].perf); + + return 0; +} + +static int update_hfi_ipcc_scores(struct amd_hfi_data *amd_hfi_data) +{ + int cpu; + int ret; + + for_each_online_cpu(cpu) { + struct amd_hfi_cpuinfo *hfi_cpuinfo = per_cpu_ptr(&amd_hfi_cpuinfo, cpu); + + ret = amd_set_hfi_ipcc_score(hfi_cpuinfo, cpu); + if (ret) + return ret; + } + + return 0; +} + static int amd_hfi_metadata_parser(struct platform_device *pdev, struct amd_hfi_data *amd_hfi_data) { @@ -330,6 +357,11 @@ static int amd_hfi_probe(struct platform_device *pdev) if (ret) goto out; + /* set up IPCC scores */ + ret = update_hfi_ipcc_scores(amd_hfi_data); + if (ret) + goto out; + out: return ret; } From patchwork Thu Oct 10 19:37:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 834421 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2068.outbound.protection.outlook.com [40.107.94.68]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5D90C1EABA6; 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Thu, 10 Oct 2024 14:37:48 -0500 From: Mario Limonciello To: Borislav Petkov , Hans de Goede , =?utf-8?q?Ilpo_J=C3=A4rvinen?= CC: , "Gautham R . Shenoy" , "Mario Limonciello" , Perry Yuan , , , , , "Shyam Sundar S K" Subject: [PATCH v2 10/13] x86/cpu: Enable SD_ASYM_PACKING for DIE Domain on AMD Processors Date: Thu, 10 Oct 2024 14:37:02 -0500 Message-ID: <20241010193705.10362-11-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241010193705.10362-1-mario.limonciello@amd.com> References: <20241010193705.10362-1-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF000015CA:EE_|CY8PR12MB7413:EE_ X-MS-Office365-Filtering-Correlation-Id: 3aff80c1-5765-407f-a541-08dce96306c4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|36860700013|376014|82310400026|1800799024; X-Microsoft-Antispam-Message-Info: y6Q3fReQxGnsgimihTNYp/nH+hMgGz4wVVIOamIxwK1sDF8pwuzXCtdujcrlIfeBkPrwlQTtkGIwyQ8fyos0pOJMB4Gp/TlPrg8wCOCR0eoIGGIKCj+YJlbOpmD8YKquP8f/6eW8PDS//zLiG67N2oZ5w2037vHkKUaZdmlEoN9ePCZuPIRc5ANW60iRw0r8xqhAjhgUQDrOqUm0zqttadPCVkDLHliRyA+TrBgbmT8Hi4JnSYHcTU5vtDWrAStcKlCjfL1N6vfo4KjMDgcHy7nBjmcgGRAhq4+MZY9Fb1jkp8/7NSTye0G+sg1kgzaXWfIBFOBnb1O+ZSSMaCCiLaVrvsQe7Y8Na8qUeqihBRui2QehdyiAT8tZUsOJktJw1Vw775rnUN3+3UXh4tpQPLruF95GSX3RplFVg9fguE+0tsekidzt7ruYyCFG5PtrZZhUBO100nj8+R31Qze9QqwbXpDsJT+Lx+dUkWODhI5LQHZHKmMzHMSSyIBQplz5lHB2GYp0Lv8Gqryf6iV85KObhq0m0ht6TkZ0A45NWuhrFHGiqABvDNC2j8qMgFnh80jsbRX3+GuiFPhoGwV4T2Gd88c2k6ngVexgoxO2bboDzPVoo/sbPEG3sCN+McHGDOx0PCDOeZe51gqsVR/jttbtyZ67qz6op+Xw+R2RihXelIuqd92PvHNJfFhweGGv/VaIbRmHKGdINqRLc9XHrh5/QqdCz3lY9EIQm+FHmkvEOyOYBmJrimGGFXJxVSmapiCOvly3WuZpInveaSqyXL/d4BEri8j9VVNS/J2mZ8giMZLvOotugFxE7KrxQEQOflFFYlTrUlG0FTt0T++qWQwpnksr74HjqGaQLfb1uOSOjjEYkV5KNxt7rUsH8adcmlaFpmBAZnI/EJa1+ORW4SYqVPVvYtloajfCBIEFRoCdbl8+7W1wPkaq3RDcwBOEQdggg8KkschV0NpSZmlm1BaFbjiwdncLS7Tqp+wQcdu6NoIGKSTo4sfBdXjS5+Vz0TdpjYDw48lnxeJY1bxbfct73ZFe0jjpj8XauNfuBkZHr+EGllFZjvRFo8ym3WzMjBOA1qNGHkQps3Qfv4r2xxpeXPxIt+tW41F78GRbaLCyBhYFq0foZek7tMVQy6fJ8LeK2UmdsOnZGznrqW7qFC+4PYFoAD3oa5clvhNL0qszzzkVHncasCjk0ZabeQfk8H13t8KLzAMz/tQxezvQtdu/AsUYe05PbsY2WiJ/BKIw45M/uYlbM8wgGhITi/bbej/bSne8nXobd31l+hHnInG/T3XvzwmImDATVxseSCjSrQMIoixiAkSQjqZ2U8pXNT2WDyL8UeRjycbRHt6FTE5sUCsNmC1/wUKbNk2bCWjgOXFB2AOeiS4QsZCfbW2M X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(36860700013)(376014)(82310400026)(1800799024); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Oct 2024 19:37:50.3571 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3aff80c1-5765-407f-a541-08dce96306c4 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF000015CA.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7413 From: Perry Yuan Enable the SD_ASYM_PACKING domain flag for the DIE domain on AMD heterogeneous processors. This flag is beneficial for processors with one or more CCDs and relies on x86_sched_itmt_flags(). Signed-off-by: Perry Yuan Signed-off-by: Mario Limonciello --- v2: * Whitespace --- arch/x86/kernel/smpboot.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c index 766f092dab80..c01bb75d0375 100644 --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -497,8 +497,9 @@ static int x86_cluster_flags(void) static int x86_die_flags(void) { - if (cpu_feature_enabled(X86_FEATURE_HYBRID_CPU)) - return x86_sched_itmt_flags(); + if (cpu_feature_enabled(X86_FEATURE_HYBRID_CPU) || + cpu_feature_enabled(X86_FEATURE_HETERO_CORE_TOPOLOGY)) + return x86_sched_itmt_flags(); return 0; } From patchwork Thu Oct 10 19:37:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 834422 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2082.outbound.protection.outlook.com [40.107.94.82]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 209971E8837; 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Thu, 10 Oct 2024 14:37:49 -0500 From: Mario Limonciello To: Borislav Petkov , Hans de Goede , =?utf-8?q?Ilpo_J=C3=A4rvinen?= CC: , "Gautham R . Shenoy" , "Mario Limonciello" , Perry Yuan , , , , , "Shyam Sundar S K" Subject: [PATCH v2 11/13] x86/process: Clear hardware feedback history for AMD processors Date: Thu, 10 Oct 2024 14:37:03 -0500 Message-ID: <20241010193705.10362-12-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241010193705.10362-1-mario.limonciello@amd.com> References: <20241010193705.10362-1-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF000015CA:EE_|SA1PR12MB7175:EE_ X-MS-Office365-Filtering-Correlation-Id: a1071107-5749-43ec-3008-08dce9630874 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|36860700013|1800799024|376014|82310400026; X-Microsoft-Antispam-Message-Info: 5vUuDEVW5M+9u4+LIAaZNJQB1TBRQH8bSKmjTWpL9gxBUtW3z/1ng4+8ur9gcZWLlNAq3v96KJOaZ+DIuZRIf2gSwrK1i5cq/pYy9xMcxOc+ekdwOJXt8jdyrCMtTXgVrbnPtLylPbloyjIzqPR/6nmksOGAWaGNBDqZ1P08TkHVRV66VWvgnLJGxvj2IVbTFlmA2fGWafodGV7MDBzv6W+BDx/zC5Fikcalx2+oeMTXf611YrBzAqQkIkVpWAtCiEO7jaZczgIEsO9NkpEO7t406yaUN2MUC2TH3ObQ1/UF2Fvzrz3m/GvwNRfG/vqujUZRyDFdstGsz8QhFjq6ihxlfsXAA1Els9jJ01dlo2y236DdBmx3Zepuc/Bp2mZHpqS/BtCPFIGxJH6SehoDtcL43c/3+T7tVfxTDww29vgS2/w8AAyebXm7eknS72/hfDj2oKS6XDFV5GBHOGCf+bOZaYsBtXHWOtV8yTPwgcOibfI8GK3dtfwfmCQc+o3pU4CRf28+jMnnWnHqzbSE6BD7kjjmjOgH3zQaumyx86SyP+sB09yhDjqGfRXSP1AxBuMbKoAw4d50v6bc2NTemaPrTHFoWxMUTkAEgKA/KCrlWauBY1nVbUUu1u+WFG39z7/jQAB+EfD5tFtk8BH3u2L/tIKXXrzKcTZq1NjPuN+hdmb8C4/tofEDpBxWqeg41NaApuDzC3/T17y0ZceCLJ4/5fAlMLRzMRyOuj9InZqB6wrlkGpRwSMbwfFEE9T1xIoNMDM5+L2WSy5taFnUA1uAu5rMLNq1LK/jDHuznoF9DGCYVEomyZmKMzh/DH2PZEA0lIhide90Vf0xlhHI2tP08K/8n4TbtZ3Ntwlk/xgU/L+r/ipJ+ELGT9EIBx9AZ17miAgmoh2d6nFcwj1JgUUMW8T7dFud7Ll0TktaEexqtRjz5NeLXMpbpIFQx5LwZ/QJonrzzjm2EDn4DJqxycjpOZZYMSGYP6xNgX3zi8EZp/DGL7BIqRLpyG/k8qh2mZ4LywBh6Yk3R3rcA2ZBajZRNWcPdHXleHRrf8EHN3mJIW9nwH6PM4dZUZhLozfsdUkqcwX3DuymZxt3skuBbZ3SaciT1uA02AXJBhFDfRl4WHe8H/S8ah+aD8OhSMX4RAV5iTTrT2ZUxZpb5R5rVVbBLr2IAfHNFu2uJjtero6eUlA8j/GWBxE1twvdTUZAUP0gw03nDyzh5v1vZzd/icxfjq6lIUFguNRx/3qMAw6oFAT73DzUKRtr7OO2u5s/z4jrB736C+2ZBGXE5JXv1ZMuF0j4JDv0DEjH2W7DyoN1VSH1ye8JzepsFuYiICNUvQVDYwBT8IExaKf9MX9nIoZvCbRkppCJeiFCoi7J8xtFsVtgCMhHejFtO5QRJiFa X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(36860700013)(1800799024)(376014)(82310400026); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Oct 2024 19:37:53.0602 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a1071107-5749-43ec-3008-08dce9630874 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF000015CA.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB7175 From: Perry Yuan Incorporate a mechanism within the context switching code to reset the hardware history for AMD processors. Specifically, when a task is switched in, the class ID was read and reset the hardware workload classification history of CPU firmware and then it start to trigger workload classification for the next running thread. Signed-off-by: Perry Yuan Co-developed-by: Mario Limonciello Signed-off-by: Mario Limonciello --- v2: * Fix function name * Use static keys --- arch/x86/include/asm/hreset.h | 6 ++++++ arch/x86/kernel/cpu/common.c | 15 +++++++++++++++ arch/x86/kernel/process_32.c | 3 +++ arch/x86/kernel/process_64.c | 3 +++ 4 files changed, 27 insertions(+) create mode 100644 arch/x86/include/asm/hreset.h diff --git a/arch/x86/include/asm/hreset.h b/arch/x86/include/asm/hreset.h new file mode 100644 index 000000000000..ae1f72602bbd --- /dev/null +++ b/arch/x86/include/asm/hreset.h @@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_X86_HRESET_H + +void reset_hardware_history_hetero(void); + +#endif /* _ASM_X86_HRESET_H */ diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 07a34d723505..887821e97e54 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -57,6 +57,7 @@ #include #include #include +#include #include #include #include @@ -403,6 +404,7 @@ static const unsigned long cr4_pinned_mask = X86_CR4_SMEP | X86_CR4_SMAP | X86_C X86_CR4_FSGSBASE | X86_CR4_CET | X86_CR4_FRED; static DEFINE_STATIC_KEY_FALSE_RO(cr_pinning); static unsigned long cr4_pinned_bits __ro_after_init; +static DEFINE_STATIC_KEY_FALSE_RO(hardware_history_features); void native_write_cr0(unsigned long val) { @@ -481,6 +483,12 @@ void cr4_init(void) this_cpu_write(cpu_tlbstate.cr4, cr4); } +static void __init setup_hreset(struct cpuinfo_x86 *c) +{ + if (cpu_feature_enabled(X86_FEATURE_WORKLOAD_CLASS)) + static_key_enable_cpuslocked(&hardware_history_features.key); +} + /* * Once CPU feature detection is finished (and boot params have been * parsed), record any of the sensitive CR bits that are set, and @@ -1844,6 +1852,7 @@ static void identify_cpu(struct cpuinfo_x86 *c) setup_smep(c); setup_smap(c); setup_umip(c); + setup_hreset(c); /* Enable FSGSBASE instructions if available. */ if (cpu_has(c, X86_FEATURE_FSGSBASE)) { @@ -2410,3 +2419,9 @@ void __init arch_cpu_finalize_init(void) */ mem_encrypt_init(); } + +__always_inline void reset_hardware_history_hetero(void) +{ + if (static_branch_unlikely(&hardware_history_features)) + wrmsrl(AMD_WORKLOAD_HRST, 0x1); +} diff --git a/arch/x86/kernel/process_32.c b/arch/x86/kernel/process_32.c index 0917c7f25720..6a3a1339f7a7 100644 --- a/arch/x86/kernel/process_32.c +++ b/arch/x86/kernel/process_32.c @@ -52,6 +52,7 @@ #include #include #include +#include #include #include "process.h" @@ -213,6 +214,8 @@ __switch_to(struct task_struct *prev_p, struct task_struct *next_p) /* Load the Intel cache allocation PQR MSR. */ resctrl_sched_in(next_p); + reset_hardware_history_hetero(); + return prev_p; } diff --git a/arch/x86/kernel/process_64.c b/arch/x86/kernel/process_64.c index 226472332a70..ea7f765c6262 100644 --- a/arch/x86/kernel/process_64.c +++ b/arch/x86/kernel/process_64.c @@ -54,6 +54,7 @@ #include #include #include +#include #include #include #include @@ -709,6 +710,8 @@ __switch_to(struct task_struct *prev_p, struct task_struct *next_p) /* Load the Intel cache allocation PQR MSR. */ resctrl_sched_in(next_p); + reset_hardware_history_hetero(); + return prev_p; }