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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20c1396948dsm14351765ad.225.2024.10.05.08.25.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 05 Oct 2024 08:25:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@kernel.org, peter.maydell@linaro.org, alex.bennee@linaro.org, linux-parisc@vger.kernel.org, qemu-arm@nongnu.org Subject: [PATCH 01/20] accel/tcg: Assert noreturn from write-only page for atomics Date: Sat, 5 Oct 2024 08:25:32 -0700 Message-ID: <20241005152551.307923-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241005152551.307923-1-richard.henderson@linaro.org> References: <20241005152551.307923-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org There should be no "just in case"; the page is already in the tlb, and known to be not readable. Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 117b516739..fd6459b695 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1852,10 +1852,9 @@ static void *atomic_mmu_lookup(CPUState *cpu, vaddr addr, MemOpIdx oi, /* * Since we don't support reads and writes to different * addresses, and we do have the proper page loaded for - * write, this shouldn't ever return. But just in case, - * handle via stop-the-world. + * write, this shouldn't ever return. */ - goto stop_the_world; + g_assert_not_reached(); } /* Collect tlb flags for read. */ tlb_addr |= tlbe->addr_read; From patchwork Sat Oct 5 15:25:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 832979 Delivered-To: patch@linaro.org Received: by 2002:adf:8b52:0:b0:367:895a:4699 with SMTP id v18csp1256258wra; Sat, 5 Oct 2024 08:29:00 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCX/vFILC6FMYmowq1DoznIFTp3yEFehmLQpQpuaYxwuZfQVema+C8PjPG9dPRS95KmztPtSfg==@linaro.org X-Google-Smtp-Source: AGHT+IGAHun1YYk45gMHgvYGK7vj6LBgfQCta9WlFhbk7maKqf8LYl7UPEZWE+1/4Rqfus8twai7 X-Received: by 2002:a05:620a:2407:b0:7a9:a6a7:dc2e with SMTP id af79cd13be357-7ae6f441a7emr1010284985a.26.1728142140666; Sat, 05 Oct 2024 08:29:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1728142140; cv=none; d=google.com; s=arc-20240605; b=Plas2yhVrvb0Q/V9bMRBi7PXZsBiQLyVZcjTVZL1+WI4N00SxUV47/5eVnZ2ULu8e8 MgPzfvWIbUPU/r20p4jKXlCNIQd67fNCEmqg3/Rm9WlIdOcSk0GCdZYx/4XBiZT0GL9h x5XC+XPm3rqWbDTSwRe5Hm0sUUxiCFtxVDOfi5DKddznfkyYuNYElve33N1lKw7nBVmp FfcAVv1wPnUFj4pIpeS+n3pPwPJFeSF+NgiOvauPPWmF/trdpO0Y8KkKkd8mxUMOMDoC lyLq0OzO8Bg5QNIvBQcJtFgNWi/+XZnlmPTV/gB0ZOdxEJS0qXGiS+Mp97zjAOwb5mSY AbuA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=wBthGFf8BfR2i4dob959bB47CFsEJX0Mf+aRMHd0jM4=; fh=rQg8EQ8KH04w/0VkDYF6/ktgEyHJ2dqn1eatHCfBaLw=; b=aZdR9LIf8F0dugaec6jrlqgppcxujC9tn9yrRoPogmESUEuuI3gx8Td2Ld3lyydPHs F3xVEwPF0z++Vc0PvnImHzEdP3gslvfh14+rTvv91lwpVc4scry9xssOMqDP0TuU5JkX FihNAPiQBekp6E9YxYvFlq4DXq8PB51WTKc4mLxCBvYNmR29lBut/0X+n25qz9HDVnP8 CwOm4PD+zbJ1dyWI6vdRz03Ivv/u1C6svwinv7bY40gQ9vXXbY4j+LD2Hg+5pXCsezVO X1OE5T35apgJqOaHDpKAMicTdWWhD5qY64XMY+Lh76mALmCCZmESQoHEjIhfr88T7Tsd QwVw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NRxMumqh; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20c1396948dsm14351765ad.225.2024.10.05.08.25.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 05 Oct 2024 08:25:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@kernel.org, peter.maydell@linaro.org, alex.bennee@linaro.org, linux-parisc@vger.kernel.org, qemu-arm@nongnu.org Subject: [PATCH 02/20] accel/tcg: Expand tlb_fill for 3 callers Date: Sat, 5 Oct 2024 08:25:33 -0700 Message-ID: <20241005152551.307923-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241005152551.307923-1-richard.henderson@linaro.org> References: <20241005152551.307923-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- accel/tcg/cputlb.c | 33 ++++++++++----------------------- 1 file changed, 10 insertions(+), 23 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index fd6459b695..58960969f4 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1220,25 +1220,6 @@ void tlb_set_page(CPUState *cpu, vaddr addr, prot, mmu_idx, size); } -/* - * Note: tlb_fill() can trigger a resize of the TLB. This means that all of the - * caller's prior references to the TLB table (e.g. CPUTLBEntry pointers) must - * be discarded and looked up again (e.g. via tlb_entry()). - */ -static void tlb_fill(CPUState *cpu, vaddr addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - bool ok; - - /* - * This is not a probe, so only valid return is success; failure - * should result in exception + longjmp to the cpu loop. - */ - ok = cpu->cc->tcg_ops->tlb_fill(cpu, addr, size, - access_type, mmu_idx, false, retaddr); - assert(ok); -} - static inline void cpu_unaligned_access(CPUState *cpu, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) @@ -1631,7 +1612,10 @@ static bool mmu_lookup1(CPUState *cpu, MMULookupPageData *data, if (!tlb_hit(tlb_addr, addr)) { if (!victim_tlb_hit(cpu, mmu_idx, index, access_type, addr & TARGET_PAGE_MASK)) { - tlb_fill(cpu, addr, data->size, access_type, mmu_idx, ra); + bool ok = cpu->cc->tcg_ops->tlb_fill(cpu, addr, data->size, + access_type, mmu_idx, + false, ra); + assert(ok); maybe_resized = true; index = tlb_index(cpu, mmu_idx, addr); entry = tlb_entry(cpu, mmu_idx, addr); @@ -1833,8 +1817,10 @@ static void *atomic_mmu_lookup(CPUState *cpu, vaddr addr, MemOpIdx oi, if (!tlb_hit(tlb_addr, addr)) { if (!victim_tlb_hit(cpu, mmu_idx, index, MMU_DATA_STORE, addr & TARGET_PAGE_MASK)) { - tlb_fill(cpu, addr, size, - MMU_DATA_STORE, mmu_idx, retaddr); + bool ok = cpu->cc->tcg_ops->tlb_fill(cpu, addr, size, + MMU_DATA_STORE, mmu_idx, + false, retaddr); + assert(ok); index = tlb_index(cpu, mmu_idx, addr); tlbe = tlb_entry(cpu, mmu_idx, addr); } @@ -1848,7 +1834,8 @@ static void *atomic_mmu_lookup(CPUState *cpu, vaddr addr, MemOpIdx oi, * but addr_read will only be -1 if PAGE_READ was unset. */ if (unlikely(tlbe->addr_read == -1)) { - tlb_fill(cpu, addr, size, MMU_DATA_LOAD, mmu_idx, retaddr); + cpu->cc->tcg_ops->tlb_fill(cpu, addr, size, MMU_DATA_LOAD, + mmu_idx, false, retaddr); /* * Since we don't support reads and writes to different * addresses, and we do have the proper page loaded for From patchwork Sat Oct 5 15:25:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 832977 Delivered-To: patch@linaro.org Received: by 2002:adf:8b52:0:b0:367:895a:4699 with SMTP id v18csp1256196wra; Sat, 5 Oct 2024 08:28:44 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVGZ9ARi2URAjJdR9kAWv1TanoLbJfjzrvizlyXlk5chgJhL4yzvCKLKLP4VTXtECgJgAMHew==@linaro.org X-Google-Smtp-Source: AGHT+IH1WevLPVfrAhQoB/ZzytLnMNjm3TCO9UWbMK7k/IDWzuqLPJGTtsxlhI80MJ0DR4hQNs6p X-Received: by 2002:a05:620a:4588:b0:7ae:4b83:daf2 with SMTP id af79cd13be357-7ae6f493bd8mr1021771285a.61.1728142124194; Sat, 05 Oct 2024 08:28:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1728142124; cv=none; d=google.com; s=arc-20240605; b=PrG87Y9ru6XGx0Y7oPwg20TA4i4p+8Ubwq3tEBiDvPitTQpBgrRdoZMVPAshUr34u8 2ZksFMVCdsUXaHNUNcY8u4WsNKXXztv2z/jIP5Sxjly5+iPrR20pUeJPthXgK9gJJYmy Q41EltFl1uwqmDxeEA1krApC+oQeVwYNoR4CPl9hh1q5bg/Z6x42f3eOXRRoBKNWj/nQ lCDLg3tf8+iYmk1cZPxqMhKcgzjQ+71Z/zbw9R3/sFvjj/IaxYBd6Sp2scchNEcOvg3o IIWe/I70HglJzCoyaVEjmquRzczry1JwS60NvwdG/xwZDPkZPADBDNOWcxrVDOHgRsAu VcgQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=js9k8IR/cEhAqGc5dKpCioG/n/UgV+piB56d5dg8Aiw=; fh=rQg8EQ8KH04w/0VkDYF6/ktgEyHJ2dqn1eatHCfBaLw=; b=bVaxvNzbcDDr4752czaBC9oehSEAUoGbkCzHT8s9m1eLhTl/y+8wMnx+0Auy9OMffi re/VXNCDDlr1DNC+m11SxHHsnXt5IsT4FBzIGITJ0ZIZFOLpnJLOm3rDfKxLmrxqE3cR w6RDXaAQPmHPsDpGgxmQfDHWjlMI8T71J6pFs5kuV34j3KlXPV/bpAa8sApk3NknTYxY kOahM45ASBEuS8utLOVC0u6DdMac584SqcKd1apDhADYJkT49byBlaxcfUhcaUr53M7i 818XxkomazNtk/eH9ZdD5v6A3bxo+uftFGj5lCVWKTyCy+QOqfE2JoUYfYH9EjuhF+s2 7zyA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=UBDojHq+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20c1396948dsm14351765ad.225.2024.10.05.08.25.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 05 Oct 2024 08:25:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@kernel.org, peter.maydell@linaro.org, alex.bennee@linaro.org, linux-parisc@vger.kernel.org, qemu-arm@nongnu.org Subject: [PATCH 03/20] include/exec/memop: Move get_alignment_bits from tcg.h Date: Sat, 5 Oct 2024 08:25:34 -0700 Message-ID: <20241005152551.307923-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241005152551.307923-1-richard.henderson@linaro.org> References: <20241005152551.307923-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This function is specific to MemOp, not TCG in general. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- include/exec/memop.h | 23 +++++++++++++++++++++++ include/tcg/tcg.h | 23 ----------------------- 2 files changed, 23 insertions(+), 23 deletions(-) diff --git a/include/exec/memop.h b/include/exec/memop.h index f881fe7af4..97720a8ee7 100644 --- a/include/exec/memop.h +++ b/include/exec/memop.h @@ -170,4 +170,27 @@ static inline bool memop_big_endian(MemOp op) return (op & MO_BSWAP) == MO_BE; } +/** + * get_alignment_bits + * @memop: MemOp value + * + * Extract the alignment size from the memop. + */ +static inline unsigned get_alignment_bits(MemOp memop) +{ + unsigned a = memop & MO_AMASK; + + if (a == MO_UNALN) { + /* No alignment required. */ + a = 0; + } else if (a == MO_ALIGN) { + /* A natural alignment requirement. */ + a = memop & MO_SIZE; + } else { + /* A specific alignment requirement. */ + a = a >> MO_ASHIFT; + } + return a; +} + #endif diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 21d5884741..824fb3560d 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -281,29 +281,6 @@ static inline int tcg_type_size(TCGType t) return 4 << i; } -/** - * get_alignment_bits - * @memop: MemOp value - * - * Extract the alignment size from the memop. - */ -static inline unsigned get_alignment_bits(MemOp memop) -{ - unsigned a = memop & MO_AMASK; - - if (a == MO_UNALN) { - /* No alignment required. */ - a = 0; - } else if (a == MO_ALIGN) { - /* A natural alignment requirement. */ - a = memop & MO_SIZE; - } else { - /* A specific alignment requirement. */ - a = a >> MO_ASHIFT; - } - return a; -} - typedef tcg_target_ulong TCGArg; /* Define type and accessor macros for TCG variables. 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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20c1396948dsm14351765ad.225.2024.10.05.08.25.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 05 Oct 2024 08:25:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@kernel.org, peter.maydell@linaro.org, alex.bennee@linaro.org, linux-parisc@vger.kernel.org, qemu-arm@nongnu.org Subject: [PATCH 04/20] include/exec/memop: Rename get_alignment_bits Date: Sat, 5 Oct 2024 08:25:35 -0700 Message-ID: <20241005152551.307923-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241005152551.307923-1-richard.henderson@linaro.org> References: <20241005152551.307923-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Rename to use "memop_" prefix, like other functions that operate on MemOp. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- include/exec/memop.h | 4 ++-- accel/tcg/cputlb.c | 4 ++-- accel/tcg/user-exec.c | 4 ++-- target/arm/tcg/translate-a64.c | 4 ++-- target/xtensa/translate.c | 2 +- tcg/tcg-op-ldst.c | 6 +++--- tcg/tcg.c | 2 +- tcg/arm/tcg-target.c.inc | 4 ++-- tcg/sparc64/tcg-target.c.inc | 2 +- 9 files changed, 16 insertions(+), 16 deletions(-) diff --git a/include/exec/memop.h b/include/exec/memop.h index 97720a8ee7..f53bf618c6 100644 --- a/include/exec/memop.h +++ b/include/exec/memop.h @@ -171,12 +171,12 @@ static inline bool memop_big_endian(MemOp op) } /** - * get_alignment_bits + * memop_alignment_bits: * @memop: MemOp value * * Extract the alignment size from the memop. */ -static inline unsigned get_alignment_bits(MemOp memop) +static inline unsigned memop_alignment_bits(MemOp memop) { unsigned a = memop & MO_AMASK; diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 58960969f4..b5bff220a3 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1693,7 +1693,7 @@ static bool mmu_lookup(CPUState *cpu, vaddr addr, MemOpIdx oi, tcg_debug_assert(l->mmu_idx < NB_MMU_MODES); /* Handle CPU specific unaligned behaviour */ - a_bits = get_alignment_bits(l->memop); + a_bits = memop_alignment_bits(l->memop); if (addr & ((1 << a_bits) - 1)) { cpu_unaligned_access(cpu, addr, type, l->mmu_idx, ra); } @@ -1781,7 +1781,7 @@ static void *atomic_mmu_lookup(CPUState *cpu, vaddr addr, MemOpIdx oi, { uintptr_t mmu_idx = get_mmuidx(oi); MemOp mop = get_memop(oi); - int a_bits = get_alignment_bits(mop); + int a_bits = memop_alignment_bits(mop); uintptr_t index; CPUTLBEntry *tlbe; vaddr tlb_addr; diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 7ddc47b0ba..08a6df9987 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -959,7 +959,7 @@ void page_reset_target_data(target_ulong start, target_ulong last) { } static void *cpu_mmu_lookup(CPUState *cpu, vaddr addr, MemOp mop, uintptr_t ra, MMUAccessType type) { - int a_bits = get_alignment_bits(mop); + int a_bits = memop_alignment_bits(mop); void *ret; /* Enforce guest required alignment. */ @@ -1241,7 +1241,7 @@ static void *atomic_mmu_lookup(CPUState *cpu, vaddr addr, MemOpIdx oi, int size, uintptr_t retaddr) { MemOp mop = get_memop(oi); - int a_bits = get_alignment_bits(mop); + int a_bits = memop_alignment_bits(mop); void *ret; /* Enforce guest required alignment. */ diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 071b6349fc..ec0b1ee252 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -294,7 +294,7 @@ static TCGv_i64 gen_mte_check1_mmuidx(DisasContext *s, TCGv_i64 addr, desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid); desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma); desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write); - desc = FIELD_DP32(desc, MTEDESC, ALIGN, get_alignment_bits(memop)); + desc = FIELD_DP32(desc, MTEDESC, ALIGN, memop_alignment_bits(memop)); desc = FIELD_DP32(desc, MTEDESC, SIZEM1, memop_size(memop) - 1); ret = tcg_temp_new_i64(); @@ -326,7 +326,7 @@ TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr, bool is_write, desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid); desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma); desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write); - desc = FIELD_DP32(desc, MTEDESC, ALIGN, get_alignment_bits(single_mop)); + desc = FIELD_DP32(desc, MTEDESC, ALIGN, memop_alignment_bits(single_mop)); desc = FIELD_DP32(desc, MTEDESC, SIZEM1, total_size - 1); ret = tcg_temp_new_i64(); diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 75b7bfda4c..f4da4a40f9 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -521,7 +521,7 @@ static MemOp gen_load_store_alignment(DisasContext *dc, MemOp mop, mop |= MO_ALIGN; } if (!option_enabled(dc, XTENSA_OPTION_UNALIGNED_EXCEPTION)) { - tcg_gen_andi_i32(addr, addr, ~0 << get_alignment_bits(mop)); + tcg_gen_andi_i32(addr, addr, ~0 << memop_alignment_bits(mop)); } return mop; } diff --git a/tcg/tcg-op-ldst.c b/tcg/tcg-op-ldst.c index 23dc807f11..a318011229 100644 --- a/tcg/tcg-op-ldst.c +++ b/tcg/tcg-op-ldst.c @@ -45,7 +45,7 @@ static void check_max_alignment(unsigned a_bits) static MemOp tcg_canonicalize_memop(MemOp op, bool is64, bool st) { - unsigned a_bits = get_alignment_bits(op); + unsigned a_bits = memop_alignment_bits(op); check_max_alignment(a_bits); @@ -559,7 +559,7 @@ static void tcg_gen_qemu_ld_i128_int(TCGv_i128 val, TCGTemp *addr, TCGv_i64 ext_addr = NULL; TCGOpcode opc; - check_max_alignment(get_alignment_bits(memop)); + check_max_alignment(memop_alignment_bits(memop)); tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); /* In serial mode, reduce atomicity. */ @@ -676,7 +676,7 @@ static void tcg_gen_qemu_st_i128_int(TCGv_i128 val, TCGTemp *addr, TCGv_i64 ext_addr = NULL; TCGOpcode opc; - check_max_alignment(get_alignment_bits(memop)); + check_max_alignment(memop_alignment_bits(memop)); tcg_gen_req_mo(TCG_MO_ST_LD | TCG_MO_ST_ST); /* In serial mode, reduce atomicity. */ diff --git a/tcg/tcg.c b/tcg/tcg.c index 34e3056380..5decd83cf4 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -5506,7 +5506,7 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op) static TCGAtomAlign atom_and_align_for_opc(TCGContext *s, MemOp opc, MemOp host_atom, bool allow_two_ops) { - MemOp align = get_alignment_bits(opc); + MemOp align = memop_alignment_bits(opc); MemOp size = opc & MO_SIZE; MemOp half = size ? size - 1 : 0; MemOp atom = opc & MO_ATOM_MASK; diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 3de5f50b62..56072d89a2 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -1587,7 +1587,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc, TCGReg datalo, tcg_debug_assert((datalo & 1) == 0); tcg_debug_assert(datahi == datalo + 1); /* LDRD requires alignment; double-check that. */ - if (get_alignment_bits(opc) >= MO_64) { + if (memop_alignment_bits(opc) >= MO_64) { if (h.index < 0) { tcg_out_ldrd_8(s, h.cond, datalo, h.base, 0); break; @@ -1691,7 +1691,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc, TCGReg datalo, tcg_debug_assert((datalo & 1) == 0); tcg_debug_assert(datahi == datalo + 1); /* STRD requires alignment; double-check that. */ - if (get_alignment_bits(opc) >= MO_64) { + if (memop_alignment_bits(opc) >= MO_64) { if (h.index < 0) { tcg_out_strd_8(s, h.cond, datalo, h.base, 0); } else { diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index 176c98740b..32f9ec24b5 100644 --- a/tcg/sparc64/tcg-target.c.inc +++ b/tcg/sparc64/tcg-target.c.inc @@ -1133,7 +1133,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, * Otherwise, test for at least natural alignment and defer * everything else to the helper functions. */ - if (s_bits != get_alignment_bits(opc)) { + if (s_bits != memop_alignment_bits(opc)) { tcg_debug_assert(check_fit_tl(a_mask, 13)); tcg_out_arithi(s, TCG_REG_G0, addr_reg, a_mask, ARITH_ANDCC); From patchwork Sat Oct 5 15:25:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 832976 Delivered-To: patch@linaro.org Received: by 2002:adf:8b52:0:b0:367:895a:4699 with SMTP id v18csp1256162wra; Sat, 5 Oct 2024 08:28:40 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUfqvsYxJoI4lIYBO04h+wKLAeVTe4miPr7TGfQzNlqyAxk0xCwEg35KttHCb/IkrSPngT/nQ==@linaro.org X-Google-Smtp-Source: AGHT+IEb2BBBPMDo4CjMWO1tA+g8aDMkI9FblgLP8ruwzWP4xCsXH7eJBT23fzvAI3LBgJV93Kfy X-Received: by 2002:a05:620a:29d2:b0:7a9:c2d5:a9f0 with SMTP id af79cd13be357-7ae6f42dfadmr912352685a.6.1728142119955; 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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20c1396948dsm14351765ad.225.2024.10.05.08.25.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 05 Oct 2024 08:25:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@kernel.org, peter.maydell@linaro.org, alex.bennee@linaro.org, linux-parisc@vger.kernel.org, qemu-arm@nongnu.org Subject: [PATCH 05/20] include/exec/memop: Introduce memop_atomicity_bits Date: Sat, 5 Oct 2024 08:25:36 -0700 Message-ID: <20241005152551.307923-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241005152551.307923-1-richard.henderson@linaro.org> References: <20241005152551.307923-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Split out of mmu_lookup. Signed-off-by: Richard Henderson --- include/exec/memop.h | 24 ++++++++++++++++++++++++ accel/tcg/cputlb.c | 16 ++-------------- 2 files changed, 26 insertions(+), 14 deletions(-) diff --git a/include/exec/memop.h b/include/exec/memop.h index f53bf618c6..b699bf7688 100644 --- a/include/exec/memop.h +++ b/include/exec/memop.h @@ -193,4 +193,28 @@ static inline unsigned memop_alignment_bits(MemOp memop) return a; } +/* + * memop_atomicity_bits: + * @memop: MemOp value + * + * Extract the atomicity size from the memop. + */ +static inline unsigned memop_atomicity_bits(MemOp memop) +{ + unsigned size = memop & MO_SIZE; + + switch (memop & MO_ATOM_MASK) { + case MO_ATOM_NONE: + size = MO_8; + break; + case MO_ATOM_IFALIGN_PAIR: + case MO_ATOM_WITHIN16_PAIR: + size = size ? size - 1 : 0; + break; + default: + break; + } + return size; +} + #endif diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index b5bff220a3..f5fca5a118 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1751,20 +1751,8 @@ static bool mmu_lookup(CPUState *cpu, vaddr addr, MemOpIdx oi, * Device memory type require alignment. */ if (unlikely(flags & TLB_CHECK_ALIGNED)) { - MemOp size = l->memop & MO_SIZE; - - switch (l->memop & MO_ATOM_MASK) { - case MO_ATOM_NONE: - size = MO_8; - break; - case MO_ATOM_IFALIGN_PAIR: - case MO_ATOM_WITHIN16_PAIR: - size = size ? size - 1 : 0; - break; - default: - break; - } - if (addr & ((1 << size) - 1)) { + a_bits = memop_atomicity_bits(l->memop); + if (addr & ((1 << a_bits) - 1)) { cpu_unaligned_access(cpu, addr, type, l->mmu_idx, ra); } } From patchwork Sat Oct 5 15:25:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 832975 Delivered-To: patch@linaro.org Received: by 2002:adf:8b52:0:b0:367:895a:4699 with SMTP id v18csp1256147wra; Sat, 5 Oct 2024 08:28:37 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWZluEZhqgdaItTWP/kQGWDcZ5nzT5eAtENWZTTHLCwnNCRSMmeCR3yvPhWJUGczejzu/7odA==@linaro.org X-Google-Smtp-Source: AGHT+IGX8/tJs2t99c+02u89O47BQQ5xhUzsR6DYMm8iBLLD1y0y1gg1FXwjkIrJZrr2pkyktK3S X-Received: by 2002:a05:620a:248d:b0:7ab:36c8:6607 with SMTP id af79cd13be357-7ae6f49c99dmr1085155985a.54.1728142116771; Sat, 05 Oct 2024 08:28:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1728142116; cv=none; d=google.com; s=arc-20240605; b=dbpexDrnk9J3RtKan2oCYGn00pXOB30KeRDtn0fNjs29RpNzO9oCqlcB7FWOhY6bCE GMNggJu4WCD+qieehqg7vCEPyD1KFOWEhb/LMFYNe2SYUrpgARuTM7gasW+WZcKLdZNP PIjI/uZYOlplB/hMD6rvVNvRr0UJDGiAsVxZe2H1EzZmEYMPNT3hYVWH9Q/ipqj0QrZ/ gePUOKYKyPIyV+XZbZsJNfpi9QgpcQxrqF0eIdjjEeU6T+dx07SGJSZSRpQnbAzLxCHB KrKA7tSNYMqmsehpeaecasgbwjcyH9kLpt+tQFVazHpPqg5gJ+7Rw2zIcB4iO1mL8z1S 8qIg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=1f/qgYd1hp1mLwoixEUX+NfB0hBePURRnKwRiQEkN3A=; fh=rQg8EQ8KH04w/0VkDYF6/ktgEyHJ2dqn1eatHCfBaLw=; b=JKA4mvIHMJIBQ+suMbg8k77Q1TnxzvMei/lo++ApPSrnpkkDiz5L1vhAQ5A3NHy0G7 6xFszaNp21eZrmHzPTnXnlnJUk0YL/TK51L51JfVcokJ3SvsZMrNWt3ha6f557Ao3hpT doXG5V4VSpRlMBc0EMzmtcpYRhjnA6cX5sXQ05r4TLKG6sXKDEV0KsuTaKbWhVT2Tjl8 M/vQwDNExwiMlTqr/OjHoE/DahwHBeKbbZhhNewvRqgiLTS0RHglv5fNpBVaChSN600G dlOx5uNkLFrhTGvZG/VDqUN/b/Peb0FtDfV9D9XDMqB1BZs6SFjlum1AgJkhgOhMBvnz o56A==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=d2PHUhhP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20c1396948dsm14351765ad.225.2024.10.05.08.25.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 05 Oct 2024 08:25:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@kernel.org, peter.maydell@linaro.org, alex.bennee@linaro.org, linux-parisc@vger.kernel.org, qemu-arm@nongnu.org Subject: [PATCH 06/20] hw/core/tcg-cpu-ops: Introduce tlb_fill_align hook Date: Sat, 5 Oct 2024 08:25:37 -0700 Message-ID: <20241005152551.307923-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241005152551.307923-1-richard.henderson@linaro.org> References: <20241005152551.307923-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Add the hook to struct TCGCPUOps. Add a default implementation that recognizes alignment faults before page faults. Populate all TCGCPUOps structures with the default implementation. Signed-off-by: Richard Henderson --- include/hw/core/tcg-cpu-ops.h | 25 +++++++++++++++++++++++++ accel/tcg/cputlb.c | 19 +++++++++++++++++++ target/alpha/cpu.c | 1 + target/arm/cpu.c | 1 + target/arm/tcg/cpu-v7m.c | 1 + target/avr/cpu.c | 1 + target/hppa/cpu.c | 1 + target/i386/tcg/tcg-cpu.c | 1 + target/loongarch/cpu.c | 1 + target/m68k/cpu.c | 1 + target/microblaze/cpu.c | 1 + target/mips/cpu.c | 1 + target/openrisc/cpu.c | 1 + target/ppc/cpu_init.c | 1 + target/riscv/tcg/tcg-cpu.c | 1 + target/rx/cpu.c | 1 + target/s390x/cpu.c | 1 + target/sh4/cpu.c | 1 + target/sparc/cpu.c | 1 + target/tricore/cpu.c | 1 + target/xtensa/cpu.c | 1 + 21 files changed, 63 insertions(+) diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index 34318cf0e6..49420bc93d 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -13,6 +13,7 @@ #include "exec/breakpoint.h" #include "exec/hwaddr.h" #include "exec/memattrs.h" +#include "exec/memop.h" #include "exec/mmu-access-type.h" #include "exec/vaddr.h" @@ -131,6 +132,21 @@ struct TCGCPUOps { * same function signature. */ bool (*cpu_exec_halt)(CPUState *cpu); + + /** + * @tlb_fill_align: Handle a softmmu tlb miss, and alignment fault + * + * If the access is valid, call tlb_set_page and return true; + * if the access is invalid and probe is true, return false; + * otherwise raise an exception and do not return. + * + * The alignment check is deferred to this hook, so that the + * target can choose to recognize either before or after the + * permission check. + */ + bool (*tlb_fill_align)(CPUState *cpu, vaddr address, MemOp mop, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); /** * @tlb_fill: Handle a softmmu tlb miss * @@ -234,6 +250,15 @@ void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len, */ int cpu_watchpoint_address_matches(CPUState *cpu, vaddr addr, vaddr len); +/* + * tlb_fill_align_first: + * + * Prioritize alignment faults over page faults. + */ +bool tlb_fill_align_first(CPUState *cpu, vaddr address, MemOp mop, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); + #endif #endif /* TCG_CPU_OPS_H */ diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index f5fca5a118..4bc34c8a37 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1565,6 +1565,25 @@ bool tlb_plugin_lookup(CPUState *cpu, vaddr addr, int mmu_idx, } #endif + +/* + * Generic implementation of tlb_fill_align which recognizes + * alignment faults before page faults. + */ +bool tlb_fill_align_first(CPUState *cpu, vaddr addr, MemOp mop, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) +{ + unsigned a_bits = memop_alignment_bits(mop); + + if (unlikely(addr & ((1 << a_bits) - 1))) { + cpu_unaligned_access(cpu, addr, access_type, mmu_idx, retaddr); + } + + return cpu->cc->tcg_ops->tlb_fill(cpu, addr, size, access_type, + mmu_idx, probe, retaddr); +} + /* * Probe for a load/store operation. * Return the host address and into @flags. diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 9db1dffc03..2eb5afd34a 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -217,6 +217,7 @@ static const TCGCPUOps alpha_tcg_ops = { .record_sigsegv = alpha_cpu_record_sigsegv, .record_sigbus = alpha_cpu_record_sigbus, #else + .tlb_fill_align = tlb_fill_align_first, .tlb_fill = alpha_cpu_tlb_fill, .cpu_exec_interrupt = alpha_cpu_exec_interrupt, .cpu_exec_halt = alpha_cpu_has_work, diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 19191c2391..08731ed4e0 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2663,6 +2663,7 @@ static const TCGCPUOps arm_tcg_ops = { .record_sigsegv = arm_cpu_record_sigsegv, .record_sigbus = arm_cpu_record_sigbus, #else + .tlb_fill_align = tlb_fill_align_first, .tlb_fill = arm_cpu_tlb_fill, .cpu_exec_interrupt = arm_cpu_exec_interrupt, .cpu_exec_halt = arm_cpu_exec_halt, diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c index 5496f14dc1..8874fe0e11 100644 --- a/target/arm/tcg/cpu-v7m.c +++ b/target/arm/tcg/cpu-v7m.c @@ -242,6 +242,7 @@ static const TCGCPUOps arm_v7m_tcg_ops = { .record_sigsegv = arm_cpu_record_sigsegv, .record_sigbus = arm_cpu_record_sigbus, #else + .tlb_fill_align = tlb_fill_align_first, .tlb_fill = arm_cpu_tlb_fill, .cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt, .cpu_exec_halt = arm_cpu_exec_halt, diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 3132842d56..6ac4434f1d 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -211,6 +211,7 @@ static const TCGCPUOps avr_tcg_ops = { .restore_state_to_opc = avr_restore_state_to_opc, .cpu_exec_interrupt = avr_cpu_exec_interrupt, .cpu_exec_halt = avr_cpu_has_work, + .tlb_fill_align = tlb_fill_align_first, .tlb_fill = avr_cpu_tlb_fill, .do_interrupt = avr_cpu_do_interrupt, }; diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 7cf2e2f266..3b6c325e09 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -226,6 +226,7 @@ static const TCGCPUOps hppa_tcg_ops = { .restore_state_to_opc = hppa_restore_state_to_opc, #ifndef CONFIG_USER_ONLY + .tlb_fill_align = tlb_fill_align_first, .tlb_fill = hppa_cpu_tlb_fill, .cpu_exec_interrupt = hppa_cpu_exec_interrupt, .cpu_exec_halt = hppa_cpu_has_work, diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index cca19cd40e..83cfb86346 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -117,6 +117,7 @@ static const TCGCPUOps x86_tcg_ops = { .record_sigsegv = x86_cpu_record_sigsegv, .record_sigbus = x86_cpu_record_sigbus, #else + .tlb_fill_align = tlb_fill_align_first, .tlb_fill = x86_cpu_tlb_fill, .do_interrupt = x86_cpu_do_interrupt, .cpu_exec_halt = x86_cpu_exec_halt, diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 7212fb5f8f..ae8856d988 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -755,6 +755,7 @@ static const TCGCPUOps loongarch_tcg_ops = { .restore_state_to_opc = loongarch_restore_state_to_opc, #ifndef CONFIG_USER_ONLY + .tlb_fill_align = tlb_fill_align_first, .tlb_fill = loongarch_cpu_tlb_fill, .cpu_exec_interrupt = loongarch_cpu_exec_interrupt, .cpu_exec_halt = loongarch_cpu_has_work, diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 1d49f4cb23..295ebd941b 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -534,6 +534,7 @@ static const TCGCPUOps m68k_tcg_ops = { .restore_state_to_opc = m68k_restore_state_to_opc, #ifndef CONFIG_USER_ONLY + .tlb_fill_align = tlb_fill_align_first, .tlb_fill = m68k_cpu_tlb_fill, .cpu_exec_interrupt = m68k_cpu_exec_interrupt, .cpu_exec_halt = m68k_cpu_has_work, diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 135947ee80..6e63600631 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -411,6 +411,7 @@ static const TCGCPUOps mb_tcg_ops = { .restore_state_to_opc = mb_restore_state_to_opc, #ifndef CONFIG_USER_ONLY + .tlb_fill_align = tlb_fill_align_first, .tlb_fill = mb_cpu_tlb_fill, .cpu_exec_interrupt = mb_cpu_exec_interrupt, .cpu_exec_halt = mb_cpu_has_work, diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 89655b1900..5a36b22256 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -553,6 +553,7 @@ static const TCGCPUOps mips_tcg_ops = { .restore_state_to_opc = mips_restore_state_to_opc, #if !defined(CONFIG_USER_ONLY) + .tlb_fill_align = tlb_fill_align_first, .tlb_fill = mips_cpu_tlb_fill, .cpu_exec_interrupt = mips_cpu_exec_interrupt, .cpu_exec_halt = mips_cpu_has_work, diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 6ec54ad7a6..9223228758 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -231,6 +231,7 @@ static const TCGCPUOps openrisc_tcg_ops = { .restore_state_to_opc = openrisc_restore_state_to_opc, #ifndef CONFIG_USER_ONLY + .tlb_fill_align = tlb_fill_align_first, .tlb_fill = openrisc_cpu_tlb_fill, .cpu_exec_interrupt = openrisc_cpu_exec_interrupt, .cpu_exec_halt = openrisc_cpu_has_work, diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 23881d09e9..42a38ec155 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7482,6 +7482,7 @@ static const TCGCPUOps ppc_tcg_ops = { #ifdef CONFIG_USER_ONLY .record_sigsegv = ppc_cpu_record_sigsegv, #else + .tlb_fill_align = tlb_fill_align_first, .tlb_fill = ppc_cpu_tlb_fill, .cpu_exec_interrupt = ppc_cpu_exec_interrupt, .cpu_exec_halt = ppc_cpu_has_work, diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index dea8ab7a43..42c4ea13af 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -137,6 +137,7 @@ static const TCGCPUOps riscv_tcg_ops = { .restore_state_to_opc = riscv_restore_state_to_opc, #ifndef CONFIG_USER_ONLY + .tlb_fill_align = tlb_fill_align_first, .tlb_fill = riscv_cpu_tlb_fill, .cpu_exec_interrupt = riscv_cpu_exec_interrupt, .cpu_exec_halt = riscv_cpu_has_work, diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 36d2a6f189..27fc372ca4 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -188,6 +188,7 @@ static const TCGCPUOps rx_tcg_ops = { .initialize = rx_translate_init, .synchronize_from_tb = rx_cpu_synchronize_from_tb, .restore_state_to_opc = rx_restore_state_to_opc, + .tlb_fill_align = tlb_fill_align_first, .tlb_fill = rx_cpu_tlb_fill, #ifndef CONFIG_USER_ONLY diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 4e41a3dff5..8120ddeb5b 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -363,6 +363,7 @@ static const TCGCPUOps s390_tcg_ops = { .record_sigsegv = s390_cpu_record_sigsegv, .record_sigbus = s390_cpu_record_sigbus, #else + .tlb_fill_align = tlb_fill_align_first, .tlb_fill = s390_cpu_tlb_fill, .cpu_exec_interrupt = s390_cpu_exec_interrupt, .cpu_exec_halt = s390_cpu_has_work, diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 8f07261dcf..b03f6dfad8 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -252,6 +252,7 @@ static const TCGCPUOps superh_tcg_ops = { .restore_state_to_opc = superh_restore_state_to_opc, #ifndef CONFIG_USER_ONLY + .tlb_fill_align = tlb_fill_align_first, .tlb_fill = superh_cpu_tlb_fill, .cpu_exec_interrupt = superh_cpu_exec_interrupt, .cpu_exec_halt = superh_cpu_has_work, diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 54cb269e0a..da1bfad5f0 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -924,6 +924,7 @@ static const TCGCPUOps sparc_tcg_ops = { .restore_state_to_opc = sparc_restore_state_to_opc, #ifndef CONFIG_USER_ONLY + .tlb_fill_align = tlb_fill_align_first, .tlb_fill = sparc_cpu_tlb_fill, .cpu_exec_interrupt = sparc_cpu_exec_interrupt, .cpu_exec_halt = sparc_cpu_has_work, diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 1a26171590..9d8f8f13d2 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -173,6 +173,7 @@ static const TCGCPUOps tricore_tcg_ops = { .initialize = tricore_tcg_init, .synchronize_from_tb = tricore_cpu_synchronize_from_tb, .restore_state_to_opc = tricore_restore_state_to_opc, + .tlb_fill_align = tlb_fill_align_first, .tlb_fill = tricore_cpu_tlb_fill, .cpu_exec_interrupt = tricore_cpu_exec_interrupt, .cpu_exec_halt = tricore_cpu_has_work, diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index a08c7a0b1f..b0f84403f0 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -232,6 +232,7 @@ static const TCGCPUOps xtensa_tcg_ops = { .restore_state_to_opc = xtensa_restore_state_to_opc, #ifndef CONFIG_USER_ONLY + .tlb_fill_align = tlb_fill_align_first, .tlb_fill = xtensa_cpu_tlb_fill, .cpu_exec_interrupt = xtensa_cpu_exec_interrupt, .cpu_exec_halt = xtensa_cpu_has_work, From patchwork Sat Oct 5 15:25:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 832984 Delivered-To: patch@linaro.org Received: by 2002:adf:8b52:0:b0:367:895a:4699 with SMTP id v18csp1256625wra; Sat, 5 Oct 2024 08:30:11 -0700 (PDT) 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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20c1396948dsm14351765ad.225.2024.10.05.08.25.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 05 Oct 2024 08:25:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@kernel.org, peter.maydell@linaro.org, alex.bennee@linaro.org, linux-parisc@vger.kernel.org, qemu-arm@nongnu.org Subject: [PATCH 07/20] accel/tcg: Use the tlb_fill_align hook Date: Sat, 5 Oct 2024 08:25:38 -0700 Message-ID: <20241005152551.307923-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241005152551.307923-1-richard.henderson@linaro.org> References: <20241005152551.307923-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org When we have a tlb miss, defer the alignment check to the new tlb_fill_align hook. Move the existing alignment check so that we only perform it with a tlb hit. Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c | 89 +++++++++++++++++++++++++--------------------- 1 file changed, 49 insertions(+), 40 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 4bc34c8a37..0e6ae65a39 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1616,14 +1616,14 @@ typedef struct MMULookupLocals { * tlb_fill will longjmp out. Return true if the softmmu tlb for * @mmu_idx may have resized. */ -static bool mmu_lookup1(CPUState *cpu, MMULookupPageData *data, +static bool mmu_lookup1(CPUState *cpu, MMULookupPageData *data, MemOp memop, int mmu_idx, MMUAccessType access_type, uintptr_t ra) { vaddr addr = data->addr; uintptr_t index = tlb_index(cpu, mmu_idx, addr); CPUTLBEntry *entry = tlb_entry(cpu, mmu_idx, addr); uint64_t tlb_addr = tlb_read_idx(entry, access_type); - bool maybe_resized = false; + bool did_tlb_fill = false; CPUTLBEntryFull *full; int flags; @@ -1631,17 +1631,26 @@ static bool mmu_lookup1(CPUState *cpu, MMULookupPageData *data, if (!tlb_hit(tlb_addr, addr)) { if (!victim_tlb_hit(cpu, mmu_idx, index, access_type, addr & TARGET_PAGE_MASK)) { - bool ok = cpu->cc->tcg_ops->tlb_fill(cpu, addr, data->size, - access_type, mmu_idx, - false, ra); + bool ok = cpu->cc->tcg_ops->tlb_fill_align(cpu, addr, memop, + data->size, access_type, + mmu_idx, false, ra); assert(ok); - maybe_resized = true; + did_tlb_fill = true; index = tlb_index(cpu, mmu_idx, addr); entry = tlb_entry(cpu, mmu_idx, addr); } tlb_addr = tlb_read_idx(entry, access_type) & ~TLB_INVALID_MASK; } + if (!did_tlb_fill) { + /* We didn't use tlb_fill_align, so alignment not yet checked. */ + unsigned a_bits = memop_alignment_bits(memop); + + if (unlikely(addr & ((1 << a_bits) - 1))) { + cpu_unaligned_access(cpu, addr, access_type, mmu_idx, ra); + } + } + full = &cpu->neg.tlb.d[mmu_idx].fulltlb[index]; flags = tlb_addr & (TLB_FLAGS_MASK & ~TLB_FORCE_SLOW); flags |= full->slow_flags[access_type]; @@ -1651,7 +1660,7 @@ static bool mmu_lookup1(CPUState *cpu, MMULookupPageData *data, /* Compute haddr speculatively; depending on flags it might be invalid. */ data->haddr = (void *)((uintptr_t)addr + entry->addend); - return maybe_resized; + return did_tlb_fill; } /** @@ -1702,7 +1711,6 @@ static void mmu_watch_or_dirty(CPUState *cpu, MMULookupPageData *data, static bool mmu_lookup(CPUState *cpu, vaddr addr, MemOpIdx oi, uintptr_t ra, MMUAccessType type, MMULookupLocals *l) { - unsigned a_bits; bool crosspage; int flags; @@ -1711,12 +1719,6 @@ static bool mmu_lookup(CPUState *cpu, vaddr addr, MemOpIdx oi, tcg_debug_assert(l->mmu_idx < NB_MMU_MODES); - /* Handle CPU specific unaligned behaviour */ - a_bits = memop_alignment_bits(l->memop); - if (addr & ((1 << a_bits) - 1)) { - cpu_unaligned_access(cpu, addr, type, l->mmu_idx, ra); - } - l->page[0].addr = addr; l->page[0].size = memop_size(l->memop); l->page[1].addr = (addr + l->page[0].size - 1) & TARGET_PAGE_MASK; @@ -1724,7 +1726,7 @@ static bool mmu_lookup(CPUState *cpu, vaddr addr, MemOpIdx oi, crosspage = (addr ^ l->page[1].addr) & TARGET_PAGE_MASK; if (likely(!crosspage)) { - mmu_lookup1(cpu, &l->page[0], l->mmu_idx, type, ra); + mmu_lookup1(cpu, &l->page[0], l->memop, l->mmu_idx, type, ra); flags = l->page[0].flags; if (unlikely(flags & (TLB_WATCHPOINT | TLB_NOTDIRTY))) { @@ -1743,8 +1745,8 @@ static bool mmu_lookup(CPUState *cpu, vaddr addr, MemOpIdx oi, * Lookup both pages, recognizing exceptions from either. If the * second lookup potentially resized, refresh first CPUTLBEntryFull. */ - mmu_lookup1(cpu, &l->page[0], l->mmu_idx, type, ra); - if (mmu_lookup1(cpu, &l->page[1], l->mmu_idx, type, ra)) { + mmu_lookup1(cpu, &l->page[0], l->memop, l->mmu_idx, type, ra); + if (mmu_lookup1(cpu, &l->page[1], 0, l->mmu_idx, type, ra)) { uintptr_t index = tlb_index(cpu, l->mmu_idx, addr); l->page[0].full = &cpu->neg.tlb.d[l->mmu_idx].fulltlb[index]; } @@ -1770,7 +1772,7 @@ static bool mmu_lookup(CPUState *cpu, vaddr addr, MemOpIdx oi, * Device memory type require alignment. */ if (unlikely(flags & TLB_CHECK_ALIGNED)) { - a_bits = memop_atomicity_bits(l->memop); + unsigned a_bits = memop_atomicity_bits(l->memop); if (addr & ((1 << a_bits) - 1)) { cpu_unaligned_access(cpu, addr, type, l->mmu_idx, ra); } @@ -1788,34 +1790,18 @@ static void *atomic_mmu_lookup(CPUState *cpu, vaddr addr, MemOpIdx oi, { uintptr_t mmu_idx = get_mmuidx(oi); MemOp mop = get_memop(oi); - int a_bits = memop_alignment_bits(mop); uintptr_t index; CPUTLBEntry *tlbe; vaddr tlb_addr; void *hostaddr; CPUTLBEntryFull *full; + bool did_tlb_fill = false; tcg_debug_assert(mmu_idx < NB_MMU_MODES); /* Adjust the given return address. */ retaddr -= GETPC_ADJ; - /* Enforce guest required alignment. */ - if (unlikely(a_bits > 0 && (addr & ((1 << a_bits) - 1)))) { - /* ??? Maybe indicate atomic op to cpu_unaligned_access */ - cpu_unaligned_access(cpu, addr, MMU_DATA_STORE, - mmu_idx, retaddr); - } - - /* Enforce qemu required alignment. */ - if (unlikely(addr & (size - 1))) { - /* We get here if guest alignment was not requested, - or was not enforced by cpu_unaligned_access above. - We might widen the access and emulate, but for now - mark an exception and exit the cpu loop. */ - goto stop_the_world; - } - index = tlb_index(cpu, mmu_idx, addr); tlbe = tlb_entry(cpu, mmu_idx, addr); @@ -1824,10 +1810,11 @@ static void *atomic_mmu_lookup(CPUState *cpu, vaddr addr, MemOpIdx oi, if (!tlb_hit(tlb_addr, addr)) { if (!victim_tlb_hit(cpu, mmu_idx, index, MMU_DATA_STORE, addr & TARGET_PAGE_MASK)) { - bool ok = cpu->cc->tcg_ops->tlb_fill(cpu, addr, size, - MMU_DATA_STORE, mmu_idx, - false, retaddr); + bool ok = cpu->cc->tcg_ops->tlb_fill_align(cpu, addr, mop, size, + MMU_DATA_STORE, mmu_idx, + false, retaddr); assert(ok); + did_tlb_fill = true; index = tlb_index(cpu, mmu_idx, addr); tlbe = tlb_entry(cpu, mmu_idx, addr); } @@ -1841,8 +1828,8 @@ static void *atomic_mmu_lookup(CPUState *cpu, vaddr addr, MemOpIdx oi, * but addr_read will only be -1 if PAGE_READ was unset. */ if (unlikely(tlbe->addr_read == -1)) { - cpu->cc->tcg_ops->tlb_fill(cpu, addr, size, MMU_DATA_LOAD, - mmu_idx, false, retaddr); + cpu->cc->tcg_ops->tlb_fill_align(cpu, addr, mop, size, MMU_DATA_LOAD, + mmu_idx, false, retaddr); /* * Since we don't support reads and writes to different * addresses, and we do have the proper page loaded for @@ -1850,6 +1837,28 @@ static void *atomic_mmu_lookup(CPUState *cpu, vaddr addr, MemOpIdx oi, */ g_assert_not_reached(); } + + /* Enforce guest required alignment, if not handled by tlb_fill_align. */ + if (!did_tlb_fill) { + int a_bits = memop_alignment_bits(mop); + if (unlikely(a_bits > 0 && (addr & ((1 << a_bits) - 1)))) { + /* ??? Maybe indicate atomic op to cpu_unaligned_access */ + cpu_unaligned_access(cpu, addr, MMU_DATA_STORE, + mmu_idx, retaddr); + } + } + + /* Enforce qemu required alignment. */ + if (unlikely(addr & (size - 1))) { + /* + * We get here if guest alignment was not requested, + * or was not enforced by cpu_unaligned_access above. + * We might widen the access and emulate, but for now + * mark an exception and exit the cpu loop. + */ + goto stop_the_world; + } + /* Collect tlb flags for read. */ tlb_addr |= tlbe->addr_read; From patchwork Sat Oct 5 15:25:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 832988 Delivered-To: patch@linaro.org Received: by 2002:adf:8b52:0:b0:367:895a:4699 with SMTP id v18csp1257045wra; Sat, 5 Oct 2024 08:31:16 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUxrcsNS3VKBwFgqNz0tPK5tbSb7fPzSvVTVTn4RrKjqsvZSlmtxJ+iESEHijXRMoodOeCRtA==@linaro.org X-Google-Smtp-Source: AGHT+IEqQ006RW387zJbFXEjKepNvUge/tN4S/Z+23LPEjRm2HoezjAdgzVJZj7rOfwyuLPl74Ej X-Received: by 2002:a05:6122:1822:b0:509:197b:3e2 with SMTP id 71dfb90a1353d-50c85594bbemr5030736e0c.11.1728142275990; Sat, 05 Oct 2024 08:31:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1728142275; cv=none; d=google.com; s=arc-20240605; b=hiUt9jF606N/XOp7gX1hqzN5D6OfHlNtJyp3iCedupIz2EVHhta+Y4Zv37cE9+5+gk zWN9wE6Iz0CmoJR99b1dZ6qs9XBpslC7A5TfReU8US044fwbu5YS9oY2XQDNLySAvKlg mIMzYyHwYKgrIs7iocAcywxvmSmaJbXCcuEJGViYVveLJt53UppIa1LoIDWhXFnl68+w 1JBMAsWvI0Yp1FloFp7PDKSr17ZN/7dZTRcZvuBj0/B4mqot220lyifgvPUXhZCJmYUo 71ZlZFdCUHs/GzGjH2DuaIYoDKRnrfFSPfps1H1tkQ77hTzaTspg/50+Fv+MDx3BsMSP oslg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=MP+WvwE/XecW9wPOVCpjk+gA5jxWiH/v3HQ4ejXK7hQ=; fh=rQg8EQ8KH04w/0VkDYF6/ktgEyHJ2dqn1eatHCfBaLw=; b=Y+ju+9KFX0th2aQkzFzSsDJNHZdkMiD9uGVmKC3yZHViFhydApqkQjZgCBswkBOWW6 PS+L7h2xZMQO3Z/VMene8TqX860Zh18q2/yxB1PcR3tcG5Xk03umLSAr9b5g5XIj5vZm 7zJT5216SBWYXMzk5IoSmHCYhZtsRxc3JUg0j2oFR5oTdIIZ+lQ6NlrsiHiHWV75PBfs 7kjvT1lKzbc4rOwTYzepoh55e6rsjGWFjLJXBH5IEt+CPYbiqporQ+8s+z6Fni15oDcs urMNlEQ2aW4CwtcrVgQtgwBH/I/SYf0mwcBoGTJRT7yqZf6ZbtOK90/3ulptVlwof8OC lYYA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PD9Inbel; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20c1396948dsm14351765ad.225.2024.10.05.08.25.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 05 Oct 2024 08:26:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@kernel.org, peter.maydell@linaro.org, alex.bennee@linaro.org, linux-parisc@vger.kernel.org, qemu-arm@nongnu.org Subject: [PATCH 08/20] target/hppa: Add MemOp argument to hppa_get_physical_address Date: Sat, 5 Oct 2024 08:25:39 -0700 Message-ID: <20241005152551.307923-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241005152551.307923-1-richard.henderson@linaro.org> References: <20241005152551.307923-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Just add the argument, unused at this point. Zero is the safe do-nothing value for all callers. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- target/hppa/cpu.h | 2 +- target/hppa/int_helper.c | 2 +- target/hppa/mem_helper.c | 9 +++++---- target/hppa/op_helper.c | 2 +- 4 files changed, 8 insertions(+), 7 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index f4e051f176..526855f982 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -369,7 +369,7 @@ bool hppa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, void hppa_cpu_do_interrupt(CPUState *cpu); bool hppa_cpu_exec_interrupt(CPUState *cpu, int int_req); int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, - int type, hwaddr *pphys, int *pprot); + int type, MemOp mop, hwaddr *pphys, int *pprot); void hppa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, unsigned size, MMUAccessType access_type, diff --git a/target/hppa/int_helper.c b/target/hppa/int_helper.c index 391f32f27d..58695def82 100644 --- a/target/hppa/int_helper.c +++ b/target/hppa/int_helper.c @@ -167,7 +167,7 @@ void hppa_cpu_do_interrupt(CPUState *cs) vaddr = hppa_form_gva_psw(old_psw, env->iasq_f, vaddr); t = hppa_get_physical_address(env, vaddr, MMU_KERNEL_IDX, - 0, &paddr, &prot); + 0, 0, &paddr, &prot); if (t >= 0) { /* We can't re-load the instruction. */ env->cr[CR_IIR] = 0; diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index b984f730aa..a386c80fa4 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -197,7 +197,7 @@ static int match_prot_id64(CPUHPPAState *env, uint32_t access_id) } int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, - int type, hwaddr *pphys, int *pprot) + int type, MemOp mop, hwaddr *pphys, int *pprot) { hwaddr phys; int prot, r_prot, w_prot, x_prot, priv; @@ -340,7 +340,7 @@ hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) mmu_idx = (cpu->env.psw & PSW_D ? MMU_KERNEL_IDX : cpu->env.psw & PSW_W ? MMU_ABS_W_IDX : MMU_ABS_IDX); - excp = hppa_get_physical_address(&cpu->env, addr, mmu_idx, 0, + excp = hppa_get_physical_address(&cpu->env, addr, mmu_idx, 0, 0, &phys, &prot); /* Since we're translating for debugging, the only error that is a @@ -438,7 +438,8 @@ bool hppa_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, break; } - excp = hppa_get_physical_address(env, addr, mmu_idx, a_prot, &phys, &prot); + excp = hppa_get_physical_address(env, addr, mmu_idx, a_prot, 0, + &phys, &prot); if (unlikely(excp >= 0)) { if (probe) { return false; @@ -678,7 +679,7 @@ target_ulong HELPER(lpa)(CPUHPPAState *env, target_ulong addr) hwaddr phys; int prot, excp; - excp = hppa_get_physical_address(env, addr, MMU_KERNEL_IDX, 0, + excp = hppa_get_physical_address(env, addr, MMU_KERNEL_IDX, 0, 0, &phys, &prot); if (excp >= 0) { if (excp == EXCP_DTLB_MISS) { diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index 7f79196fff..744325969f 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -334,7 +334,7 @@ target_ulong HELPER(probe)(CPUHPPAState *env, target_ulong addr, } mmu_idx = PRIV_P_TO_MMU_IDX(level, env->psw & PSW_P); - excp = hppa_get_physical_address(env, addr, mmu_idx, 0, &phys, &prot); + excp = hppa_get_physical_address(env, addr, mmu_idx, 0, 0, &phys, &prot); if (excp >= 0) { cpu_restore_state(env_cpu(env), GETPC()); hppa_set_ior_and_isr(env, addr, MMU_IDX_MMU_DISABLED(mmu_idx)); From patchwork Sat Oct 5 15:25:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 832985 Delivered-To: patch@linaro.org Received: by 2002:adf:8b52:0:b0:367:895a:4699 with SMTP id v18csp1256766wra; Sat, 5 Oct 2024 08:30:33 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXr1McqzfJp7e1K7Z6IzNwNmm6OwFM4fXyJFNmWQvqh7KfYI27glvRIUvCAxNLiMo9+Rx+lgQ==@linaro.org X-Google-Smtp-Source: AGHT+IF4nZLscfWjKCNfIMSb5gETu6ABJ7fCSGWINs5nNdprfr/13To3KPLfS7+ThwfcB8oSC6AB X-Received: by 2002:a05:6102:d89:b0:49b:d1d1:8f7d with SMTP id ada2fe7eead31-4a4059264d5mr6007247137.26.1728142233312; Sat, 05 Oct 2024 08:30:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1728142233; cv=none; d=google.com; s=arc-20240605; b=Zz1sHnLK1YNiQz9VIeOhOGfwambSRUMF5pUzAf9jcNTut3+CN80EFYfRMIa56hEvB4 /kwb6cKVSdOMwDKUec/luVLNoaZ7+mytKw2F4iFIJXWQzRN7VDwCBCseP904B3aQVcP6 UxKJN2fxepFD4f4btIZlpIhgDaY3v9gAVC7g6imDtBpwlTYmI5m/J5HyZ5RLlCIH3+GP BSVjYfeRGLmCCh6pwcFYNT4EiKYDZc4MEhZztEaxDIkcQPHCl87MzyD5YIAsXzmZUOcT batbqHfty3UrXbUQheXSFiyDa9DCdBPqQDt124HEN/GuHh7Ap1C2YgaNFaJuHZYkKcSk taaA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=/wa2JC5GTiuZOa9FUt+c/E5R/4D7wBSs90VoPwelenc=; fh=rQg8EQ8KH04w/0VkDYF6/ktgEyHJ2dqn1eatHCfBaLw=; b=fheuN08EvvYZ/7329kBqMFGbpn2uSgi259pmAPLM36Tn10ROjko2kC84USw62rPpmG dcvbw/JTqYfZgU5nmu84786X4UISzveO//lnkgj9ZhOrmeWl23pXb6Zbc+CJ4fOowst9 xOBE89DlyaNMBvuR40zxLiE/KRNk+ZzTiI4DfBggKFPQWkLGe7qUMJGvxanfA7slWFSj D+f77eUGZnU00fAXbLaKOI+VTEUbiea9DNixx/bkA+DTQL8cz8jgOABcHwRMJDPHRFub CcHPLvGHi5HojGQHwR4AISCiuDp2APg5g7KdDUAxxHaYUnF4goML5QTDsTRVFdutp+6e w8/Q==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XKTTdeWx; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20c1396948dsm14351765ad.225.2024.10.05.08.26.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 05 Oct 2024 08:26:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@kernel.org, peter.maydell@linaro.org, alex.bennee@linaro.org, linux-parisc@vger.kernel.org, qemu-arm@nongnu.org Subject: [PATCH 09/20] target/hppa: Perform access rights before protection id check Date: Sat, 5 Oct 2024 08:25:40 -0700 Message-ID: <20241005152551.307923-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241005152551.307923-1-richard.henderson@linaro.org> References: <20241005152551.307923-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In Chapter 5, Interruptions, the group 3 exceptions lists "Data memory access rights trap" in priority order ahead of "Data memory protection ID trap". Swap these checks in hppa_get_physical_address. Signed-off-by: Richard Henderson --- target/hppa/mem_helper.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index a386c80fa4..f027c494e2 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -267,6 +267,12 @@ int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, goto egress; } + if (unlikely(!(prot & type))) { + /* Not allowed -- Inst/Data Memory Access Rights Fault. */ + ret = (type & PAGE_EXEC) ? EXCP_IMP : EXCP_DMAR; + goto egress; + } + /* access_id == 0 means public page and no check is performed */ if (ent->access_id && MMU_IDX_TO_P(mmu_idx)) { int access_prot = (hppa_is_pa20(env) @@ -281,12 +287,6 @@ int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, prot &= access_prot; } - if (unlikely(!(prot & type))) { - /* Not allowed -- Inst/Data Memory Access Rights Fault. */ - ret = (type & PAGE_EXEC) ? EXCP_IMP : EXCP_DMAR; - goto egress; - } - /* * In priority order, check for conditions which raise faults. * Remove PROT bits that cover the condition we want to check, From patchwork Sat Oct 5 15:25:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 832983 Delivered-To: patch@linaro.org Received: by 2002:adf:8b52:0:b0:367:895a:4699 with SMTP id v18csp1256580wra; Sat, 5 Oct 2024 08:30:04 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUPQgb+3NOwCUpI42oPVRXmy+NfH9q0nzAn9hB7iTwwlb57Ax6bbVj2bjmRx8AejesFpxSVTA==@linaro.org X-Google-Smtp-Source: AGHT+IGCwTyRRKCK7kukyNd0IufdxP97+zOB+4dsCoeAtHk05SyyQ5a0sBnEULBIE+JDffmZZGsQ X-Received: by 2002:a05:620a:1aa8:b0:7a9:b20d:cfe7 with SMTP id af79cd13be357-7ae6f444983mr1131661185a.15.1728142204435; Sat, 05 Oct 2024 08:30:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1728142204; cv=none; d=google.com; s=arc-20240605; b=lXFa8/mbsjWk+BVOKR/6FH7ruasU9lKxBD+8/33czceSm1g7TjcqQGfPLN5zO3LdvM 11cbWjRtj97z12sZpuKtz/JAMw0169sa7b72C5znU+B83a0KTM7Q3yCm4TvibxiBcWtx wpfzj3NEUFYkW5zDLNy7UKxERaT9T70fHubh63q4zq1laVXQb/DtUTZqNpyjUd0TPV2k sFOdjFhhO5uILV30kQLdCpeQfG3etpyoh7lptUIXwS3Iw0a5+rI/SUJKjWMmrAo1+laN VZlcf4bx+KSX5m2a5ixh1bykHTHrA07dDDQAySHOfFr3XPhUTqmmLesnYG6BuJ815yU2 xKhQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=posPbKSzdb+ffX+WhfgYFaW0pAyKjx4IZlbzVQLaTuc=; fh=rQg8EQ8KH04w/0VkDYF6/ktgEyHJ2dqn1eatHCfBaLw=; b=KMQPG6ViPfySSnDNgBuuD2gV8t81jQfXVxT5P0BgBqsV018LDy0lfy8vqsHJd1if6p Jp0LbLQmoROkT5vYRGTwnS7dvbH5lrGsyr0sEbZzvmRSDwWdm9vlBTjgr3EIbePj6Qna kIJDaKjR/7Evxu03sVR36nL4gqYUGcOu5oJGVTPylDgqr/V5MBt3AYRHkGXmMvut2O3q uxSG0ZQewjWyJhxUs2Ohcj7WLso8lrUM4qLAnqRnvShMUfj7xFVjgeFpJPe3KIfMXzeY aqvX/4DArZnLt133UFO8VMu8bexmmEh/aguU9ezyn1K6sQh95mzjc+lTYfGmI0KDCgFb QyNA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Ma6Alayf; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20c1396948dsm14351765ad.225.2024.10.05.08.26.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 05 Oct 2024 08:26:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@kernel.org, peter.maydell@linaro.org, alex.bennee@linaro.org, linux-parisc@vger.kernel.org, qemu-arm@nongnu.org Subject: [PATCH 10/20] target/hppa: Fix priority of T, D, and B page faults Date: Sat, 5 Oct 2024 08:25:41 -0700 Message-ID: <20241005152551.307923-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241005152551.307923-1-richard.henderson@linaro.org> References: <20241005152551.307923-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Drop the 'else' so that ret is overridden with the highest priority fault. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- target/hppa/mem_helper.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index f027c494e2..f71cedd7a9 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -288,7 +288,7 @@ int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, } /* - * In priority order, check for conditions which raise faults. + * In reverse priority order, check for conditions which raise faults. * Remove PROT bits that cover the condition we want to check, * so that the resulting PROT will force a re-check of the * architectural TLB entry for the next access. @@ -299,13 +299,15 @@ int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, /* The T bit is set -- Page Reference Fault. */ ret = EXCP_PAGE_REF; } - } else if (!ent->d) { + } + if (unlikely(!ent->d)) { prot &= PAGE_READ | PAGE_EXEC; if (type & PAGE_WRITE) { /* The D bit is not set -- TLB Dirty Bit Fault. */ ret = EXCP_TLB_DIRTY; } - } else if (unlikely(ent->b)) { + } + if (unlikely(ent->b)) { prot &= PAGE_READ | PAGE_EXEC; if (type & PAGE_WRITE) { /* From patchwork Sat Oct 5 15:25:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 832981 Delivered-To: patch@linaro.org Received: by 2002:adf:8b52:0:b0:367:895a:4699 with SMTP id v18csp1256460wra; Sat, 5 Oct 2024 08:29:41 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUK1t26gYkAL10efEJb0UJZ+ylKAto4U3jVbEQnJTPZIJsVeIWFoZUv2Un4m/OZciOo/6HB4Q==@linaro.org X-Google-Smtp-Source: AGHT+IGsx9SZ76yjWaL7GfUfqbu8VndILYg3rOwAx88/IwgD9H/eLA8HIPyv452XZ7y+9+3Ft8hT X-Received: by 2002:a05:6214:318c:b0:6cb:1006:e9cb with SMTP id 6a1803df08f44-6cb9a45e98dmr92242536d6.28.1728142181743; Sat, 05 Oct 2024 08:29:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1728142181; cv=none; d=google.com; s=arc-20240605; b=dgLwlW20cJr8kkIqJ1JiG8q090+hDcP8XjHdflRb3lw6oKbqYlLPF9aq86U2jO1/78 eIZ0YO6A1v1M+C+7f01eP4XJkwd2rbXnh1A8oip4kMXNV7mPyyd9ohQkffOgaGwmTMxn 35e0CX/DBkVqaQJm+3utEhgAmJ5f/UqengdKgljD6sRR2Fpr9o0fmcNSmc5Nf81gaD+D dNJZE3AL0xp5UGdWyOIyYnFAe3VAhVjH313znVwLuz+nVN3Bnh9AmkzhGaqGKEUiT6ub JnM15lp35invDbyXYi5pixrQPq+dsVIfSJ9+iQeXYloq4kKtXKSMGNqk0sJ4pT8M3YZt e78g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=TZFSB9ZUy/VXACo96L3HUXARpyVU9ywq9XNxX+p9inM=; fh=rQg8EQ8KH04w/0VkDYF6/ktgEyHJ2dqn1eatHCfBaLw=; b=UmmC7UD4eqGl9/xQvy4FU4jDehvvrdmRu8dQl9O7zhakypreEyPF3m9a97CYP1UGwH 4zCkIELt2RhO7uidz0MO6p5zKlUHYict5VmPt8ZhZ0DslOsn6JUk1icamoGOVu1q3Uit 9DMZxcLvcuLXzdJKIPqAn5DkhIh8DxxYFLvrXXvSAf1wEl243LR2CNBHaHyW8gHpAZLH 2GdScApyfhpkySFh2pgTpWYmVTpNOpXizp2zNrozZ/qzFl05HhyFy6lbaUgEKA50er8/ KhWRCQudknMNGbwMxOMwQ0SPpVi92y2vmCFNPEDHO8kxpStMKKI10QY3xBCoJwkK6Yyw Zqrg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=k8e89w4C; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20c1396948dsm14351765ad.225.2024.10.05.08.26.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 05 Oct 2024 08:26:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@kernel.org, peter.maydell@linaro.org, alex.bennee@linaro.org, linux-parisc@vger.kernel.org, qemu-arm@nongnu.org Subject: [PATCH 11/20] target/hppa: Handle alignment faults in hppa_get_physical_address Date: Sat, 5 Oct 2024 08:25:42 -0700 Message-ID: <20241005152551.307923-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241005152551.307923-1-richard.henderson@linaro.org> References: <20241005152551.307923-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In Chapter 5, Interruptions, the group 3 exceptions lists "Unaligned data reference trap" has higher priority than "Data memory break trap". Signed-off-by: Richard Henderson --- target/hppa/mem_helper.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index f71cedd7a9..d38054da8a 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -221,7 +221,7 @@ int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, g_assert_not_reached(); } prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; - goto egress; + goto egress_align; } /* Find a valid tlb entry that matches the virtual address. */ @@ -323,6 +323,11 @@ int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, } } + egress_align: + if (addr & ((1u << memop_alignment_bits(mop)) - 1)) { + ret = EXCP_UNALIGN; + } + egress: *pphys = phys; *pprot = prot; From patchwork Sat Oct 5 15:25:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 832982 Delivered-To: patch@linaro.org Received: by 2002:adf:8b52:0:b0:367:895a:4699 with SMTP id v18csp1256560wra; Sat, 5 Oct 2024 08:30:02 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCX8+1z1A/PlF4N174nHKhk32eAlpgSR2AMN2F4QT6ODf7B3OXW6S6PGkqU3zsmRnVdgGPiNRw==@linaro.org X-Google-Smtp-Source: AGHT+IH0hEMJkJoEa3W+EzEyB8ctanl7CwXljFBTVXjeuQTC8eX7rs6lsQCOR9vZEZLIQCARnPXh X-Received: by 2002:a05:6214:4803:b0:6cb:50d0:56ae with SMTP id 6a1803df08f44-6cb9a30e901mr85216896d6.29.1728142201980; Sat, 05 Oct 2024 08:30:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1728142201; cv=none; d=google.com; s=arc-20240605; b=h5fSPVS7UyS9tEWQH9Mn0+g+e9r8dU4Rz63Ry56ftlWaH8a1IBUQKVpfxoi2yGBUMu A9DtkTXtOXV8rzvLGE9nbRd7AxNCJ+XIcfz2n5KQYNcqCz0P4BvX2HvCLphNqv61R/4D Rbcfvn2N25EA40vK0VulkHdsvmZOZIZG8SXMcZUsGwOzOsjS8YGK06bZ0dVoPt2A8v5D 6C1dh8Pl8Qz6FTPaWD0ix/jBZ++dP6QUelOdGDhsjdM8L4rqI8R/0DC5vtvqsQRMYDf0 pmTQTJ5ojpcIW9HE/vVytqu0SjftCf0OZS/YKg0KIubIfn9bFgarmzsXxTy8hflt/J5d RWCw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Rc7m2CC+o/vfg9459Vx/ro/giFzSXc14VGjLvy+03yM=; fh=rQg8EQ8KH04w/0VkDYF6/ktgEyHJ2dqn1eatHCfBaLw=; b=PeIaIAtVgWwf8fi0C+D97jF3remm0Vhz57ck6aMCIYAUqP9Skdn+LY2h3a+o/d/fuR cHi6rHLbV4SIRNAVDTAR9D/x893yGXZ2SaZrEpr0PIQgzwBkzCvbNk35yzvh2SPXuLdP nGsorCaPVcIIPR3Hvrg8NjaJnIp1AWClH8nMJ7bDZLKZ7gSNtLBfF1uqfy6qs7vMAXRT 5TD884xnarF93hpnB782W4hH0+qDrJl9X0sfINaqfok8JuNbnhK7QKo7glpIg3a/jpl/ LkkIpYP/ZLyy7uPgacjY5eUxQpIlwO2eWvYxxglIlPzeRIDz8gh1LSsRl6mH8RIdk1u1 D/BA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="RGG8ZX+/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20c1396948dsm14351765ad.225.2024.10.05.08.26.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 05 Oct 2024 08:26:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@kernel.org, peter.maydell@linaro.org, alex.bennee@linaro.org, linux-parisc@vger.kernel.org, qemu-arm@nongnu.org Subject: [PATCH 12/20] target/hppa: Add hppa_cpu_tlb_fill_align Date: Sat, 5 Oct 2024 08:25:43 -0700 Message-ID: <20241005152551.307923-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241005152551.307923-1-richard.henderson@linaro.org> References: <20241005152551.307923-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Fill in the tlb_fill_align hook, so that we can recognize alignment exceptions in the correct priority order. Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 3 +++ target/hppa/cpu.c | 2 +- target/hppa/mem_helper.c | 16 ++++++++++++---- 3 files changed, 16 insertions(+), 5 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 526855f982..c0567ce0ab 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -366,6 +366,9 @@ void hppa_set_ior_and_isr(CPUHPPAState *env, vaddr addr, bool mmu_disabled); bool hppa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); +bool hppa_cpu_tlb_fill_align(CPUState *cs, vaddr address, MemOp mop, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); void hppa_cpu_do_interrupt(CPUState *cpu); bool hppa_cpu_exec_interrupt(CPUState *cpu, int int_req); int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 3b6c325e09..768abc6e5d 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -226,7 +226,7 @@ static const TCGCPUOps hppa_tcg_ops = { .restore_state_to_opc = hppa_restore_state_to_opc, #ifndef CONFIG_USER_ONLY - .tlb_fill_align = tlb_fill_align_first, + .tlb_fill_align = hppa_cpu_tlb_fill_align, .tlb_fill = hppa_cpu_tlb_fill, .cpu_exec_interrupt = hppa_cpu_exec_interrupt, .cpu_exec_halt = hppa_cpu_has_work, diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index d38054da8a..35e9170bf3 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -424,9 +424,9 @@ void hppa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, } } -bool hppa_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, - MMUAccessType type, int mmu_idx, - bool probe, uintptr_t retaddr) +bool hppa_cpu_tlb_fill_align(CPUState *cs, vaddr addr, MemOp mop, int size, + MMUAccessType type, int mmu_idx, + bool probe, uintptr_t retaddr) { HPPACPU *cpu = HPPA_CPU(cs); CPUHPPAState *env = &cpu->env; @@ -445,7 +445,7 @@ bool hppa_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, break; } - excp = hppa_get_physical_address(env, addr, mmu_idx, a_prot, 0, + excp = hppa_get_physical_address(env, addr, mmu_idx, a_prot, mop, &phys, &prot); if (unlikely(excp >= 0)) { if (probe) { @@ -473,6 +473,14 @@ bool hppa_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, return true; } +bool hppa_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, + MMUAccessType type, int mmu_idx, + bool probe, uintptr_t retaddr) +{ + return hppa_cpu_tlb_fill_align(cs, addr, 0, size, type, + mmu_idx, probe, retaddr); +} + /* Insert (Insn/Data) TLB Address. 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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20c1396948dsm14351765ad.225.2024.10.05.08.26.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 05 Oct 2024 08:26:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@kernel.org, peter.maydell@linaro.org, alex.bennee@linaro.org, linux-parisc@vger.kernel.org, qemu-arm@nongnu.org Subject: [PATCH 13/20] target/arm: Pass MemOp to get_phys_addr Date: Sat, 5 Oct 2024 08:25:44 -0700 Message-ID: <20241005152551.307923-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241005152551.307923-1-richard.henderson@linaro.org> References: <20241005152551.307923-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Zero is the safe do-nothing value for callers to use. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- target/arm/internals.h | 3 ++- target/arm/ptw.c | 2 +- target/arm/tcg/m_helper.c | 8 ++++---- target/arm/tcg/tlb_helper.c | 2 +- 4 files changed, 8 insertions(+), 7 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 1e5da81ce9..2b16579fa5 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1432,6 +1432,7 @@ typedef struct GetPhysAddrResult { * @env: CPUARMState * @address: virtual address to get physical address for * @access_type: 0 for read, 1 for write, 2 for execute + * @memop: memory operation feeding this access, or 0 for none * @mmu_idx: MMU index indicating required translation regime * @result: set on translation success. * @fi: set to fault info if the translation fails @@ -1450,7 +1451,7 @@ typedef struct GetPhysAddrResult { * value. */ bool get_phys_addr(CPUARMState *env, vaddr address, - MMUAccessType access_type, ARMMMUIdx mmu_idx, + MMUAccessType access_type, MemOp memop, ARMMMUIdx mmu_idx, GetPhysAddrResult *result, ARMMMUFaultInfo *fi) __attribute__((nonnull)); diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 659855133c..373095a339 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -3572,7 +3572,7 @@ bool get_phys_addr_with_space_nogpc(CPUARMState *env, vaddr address, } bool get_phys_addr(CPUARMState *env, vaddr address, - MMUAccessType access_type, ARMMMUIdx mmu_idx, + MMUAccessType access_type, MemOp memop, ARMMMUIdx mmu_idx, GetPhysAddrResult *result, ARMMMUFaultInfo *fi) { S1Translate ptw = { diff --git a/target/arm/tcg/m_helper.c b/target/arm/tcg/m_helper.c index 23d7f73035..f7354f3c6e 100644 --- a/target/arm/tcg/m_helper.c +++ b/target/arm/tcg/m_helper.c @@ -222,7 +222,7 @@ static bool v7m_stack_write(ARMCPU *cpu, uint32_t addr, uint32_t value, int exc; bool exc_secure; - if (get_phys_addr(env, addr, MMU_DATA_STORE, mmu_idx, &res, &fi)) { + if (get_phys_addr(env, addr, MMU_DATA_STORE, 0, mmu_idx, &res, &fi)) { /* MPU/SAU lookup failed */ if (fi.type == ARMFault_QEMU_SFault) { if (mode == STACK_LAZYFP) { @@ -311,7 +311,7 @@ static bool v7m_stack_read(ARMCPU *cpu, uint32_t *dest, uint32_t addr, bool exc_secure; uint32_t value; - if (get_phys_addr(env, addr, MMU_DATA_LOAD, mmu_idx, &res, &fi)) { + if (get_phys_addr(env, addr, MMU_DATA_LOAD, 0, mmu_idx, &res, &fi)) { /* MPU/SAU lookup failed */ if (fi.type == ARMFault_QEMU_SFault) { qemu_log_mask(CPU_LOG_INT, @@ -2009,7 +2009,7 @@ static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx, bool secure, "...really SecureFault with SFSR.INVEP\n"); return false; } - if (get_phys_addr(env, addr, MMU_INST_FETCH, mmu_idx, &res, &fi)) { + if (get_phys_addr(env, addr, MMU_INST_FETCH, 0, mmu_idx, &res, &fi)) { /* the MPU lookup failed */ env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_IACCVIOL_MASK; armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM, env->v7m.secure); @@ -2045,7 +2045,7 @@ static bool v7m_read_sg_stack_word(ARMCPU *cpu, ARMMMUIdx mmu_idx, ARMMMUFaultInfo fi = {}; uint32_t value; - if (get_phys_addr(env, addr, MMU_DATA_LOAD, mmu_idx, &res, &fi)) { + if (get_phys_addr(env, addr, MMU_DATA_LOAD, 0, mmu_idx, &res, &fi)) { /* MPU/SAU lookup failed */ if (fi.type == ARMFault_QEMU_SFault) { qemu_log_mask(CPU_LOG_INT, diff --git a/target/arm/tcg/tlb_helper.c b/target/arm/tcg/tlb_helper.c index 885bf4ec14..1d8b7bcaa2 100644 --- a/target/arm/tcg/tlb_helper.c +++ b/target/arm/tcg/tlb_helper.c @@ -344,7 +344,7 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size, * return false. 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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20c1396948dsm14351765ad.225.2024.10.05.08.26.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 05 Oct 2024 08:26:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@kernel.org, peter.maydell@linaro.org, alex.bennee@linaro.org, linux-parisc@vger.kernel.org, qemu-arm@nongnu.org Subject: [PATCH 14/20] target/arm: Pass MemOp to get_phys_addr_with_space_nogpc Date: Sat, 5 Oct 2024 08:25:45 -0700 Message-ID: <20241005152551.307923-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241005152551.307923-1-richard.henderson@linaro.org> References: <20241005152551.307923-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Zero is the safe do-nothing value for callers to use. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- target/arm/internals.h | 3 ++- target/arm/helper.c | 4 ++-- target/arm/ptw.c | 2 +- 3 files changed, 5 insertions(+), 4 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 2b16579fa5..a6088d551c 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1461,6 +1461,7 @@ bool get_phys_addr(CPUARMState *env, vaddr address, * @env: CPUARMState * @address: virtual address to get physical address for * @access_type: 0 for read, 1 for write, 2 for execute + * @memop: memory operation feeding this access, or 0 for none * @mmu_idx: MMU index indicating required translation regime * @space: security space for the access * @result: set on translation success. @@ -1470,7 +1471,7 @@ bool get_phys_addr(CPUARMState *env, vaddr address, * a Granule Protection Check on the resulting address. */ bool get_phys_addr_with_space_nogpc(CPUARMState *env, vaddr address, - MMUAccessType access_type, + MMUAccessType access_type, MemOp memop, ARMMMUIdx mmu_idx, ARMSecuritySpace space, GetPhysAddrResult *result, ARMMMUFaultInfo *fi) diff --git a/target/arm/helper.c b/target/arm/helper.c index 3f77b40734..f2f329e00a 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3602,8 +3602,8 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value, * I_MXTJT: Granule protection checks are not performed on the final address * of a successful translation. */ - ret = get_phys_addr_with_space_nogpc(env, value, access_type, mmu_idx, ss, - &res, &fi); + ret = get_phys_addr_with_space_nogpc(env, value, access_type, 0, + mmu_idx, ss, &res, &fi); /* * ATS operations only do S1 or S1+S2 translations, so we never diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 373095a339..9af86da597 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -3559,7 +3559,7 @@ static bool get_phys_addr_gpc(CPUARMState *env, S1Translate *ptw, } bool get_phys_addr_with_space_nogpc(CPUARMState *env, vaddr address, - MMUAccessType access_type, + MMUAccessType access_type, MemOp memop, ARMMMUIdx mmu_idx, ARMSecuritySpace space, GetPhysAddrResult *result, ARMMMUFaultInfo *fi) From patchwork Sat Oct 5 15:25:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 832980 Delivered-To: patch@linaro.org Received: by 2002:adf:8b52:0:b0:367:895a:4699 with SMTP id v18csp1256371wra; Sat, 5 Oct 2024 08:29:21 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUanykKoaZGqPIM75g48Tsnx3+nfcLoR21gKqtF/yJU5iFni9aVooE1sAikbe4W7b/bSX4L5A==@linaro.org X-Google-Smtp-Source: AGHT+IE1f4bsgVupErIDnAJc9MdxEUr+bJezYk70KkDsT8oBf5rB50ambMUkMBzaWeV1wXCh5X7t X-Received: by 2002:a05:620a:294d:b0:7a1:c40d:7573 with SMTP id af79cd13be357-7ae6f48e01bmr1110853085a.49.1728142161428; Sat, 05 Oct 2024 08:29:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1728142161; cv=none; d=google.com; s=arc-20240605; b=KRKyFkR8IBmuctQ8F/fakqFdc8/yNVqaPwDyh98EuqLI+PqBYHf90VOm4rsurTe45t lm5xBEQqq+AXXC2hv1prLeYmRHQqgwO6mLFkFzAlfaYGoCUe5y7+7lBOz6MEAMQGcmmn YxuMp/Db9uFwmdH6ZunPN+/C0w2Mp71HHQTAGu5I2z7lsQ9i5DQ0LGz4D93fDvlHz9Dt roGBUwVWXg+6OAaX0GN/REuIx3mvbwFC1kY/kukqjcvMjGCZBtDFHwLh/MSpuAXHPaO2 2Bke0qTg1zNIfortUOWZpmZNnZOWcY9sLz9cXPu8X+QcLuRicGvxAd3p3wDqMYMpuJ9p /bvQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=4X5zP7zXx4H0vSkmfgBSYylbUDArgVMPw2dfqzvhfaA=; fh=rQg8EQ8KH04w/0VkDYF6/ktgEyHJ2dqn1eatHCfBaLw=; b=d0Gs+FpJguvkhzWD708800U7R5LgcJTuVdE4qv8sIPkDpuYJCm+0Bwm2dBrBpcp4Hx mLxr2Df7ICTukN0dNsdWTgkHaktphfUVCVl2aqDuHmiZ8e0gE46UpN96pueFn2rqM4nb HTLxSYNa54KmLjiUFZyPd9m+BQ6ozonzMpCnTbyE0TKKigfvBabOy/rhpjNYBQ0AxuY2 j00hps7Uc919ZylRVfy4xU7ZFgF/mncFZa4L8XB2beirL1AzymTi7t9ZvoQHD7Y1EzNo qd+cvnJ+dzdKwUYqOppsijdUE3Sc3y/JhKAkF0udVQN4Beg+s5X/f+/gTgAtwZgWzeKi 3R9A==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=x5YzRLk4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20c1396948dsm14351765ad.225.2024.10.05.08.26.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 05 Oct 2024 08:26:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@kernel.org, peter.maydell@linaro.org, alex.bennee@linaro.org, linux-parisc@vger.kernel.org, qemu-arm@nongnu.org Subject: [PATCH 15/20] target/arm: Pass MemOp to get_phys_addr_gpc Date: Sat, 5 Oct 2024 08:25:46 -0700 Message-ID: <20241005152551.307923-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241005152551.307923-1-richard.henderson@linaro.org> References: <20241005152551.307923-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Zero is the safe do-nothing value for callers to use. Pass the value through from get_phys_addr. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- target/arm/ptw.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 9af86da597..e92537d8f2 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -81,7 +81,7 @@ static bool get_phys_addr_nogpc(CPUARMState *env, S1Translate *ptw, static bool get_phys_addr_gpc(CPUARMState *env, S1Translate *ptw, vaddr address, - MMUAccessType access_type, + MMUAccessType access_type, MemOp memop, GetPhysAddrResult *result, ARMMMUFaultInfo *fi); @@ -579,7 +579,7 @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, }; GetPhysAddrResult s2 = { }; - if (get_phys_addr_gpc(env, &s2ptw, addr, MMU_DATA_LOAD, &s2, fi)) { + if (get_phys_addr_gpc(env, &s2ptw, addr, MMU_DATA_LOAD, 0, &s2, fi)) { goto fail; } @@ -3543,7 +3543,7 @@ static bool get_phys_addr_nogpc(CPUARMState *env, S1Translate *ptw, static bool get_phys_addr_gpc(CPUARMState *env, S1Translate *ptw, vaddr address, - MMUAccessType access_type, + MMUAccessType access_type, MemOp memop, GetPhysAddrResult *result, ARMMMUFaultInfo *fi) { @@ -3641,7 +3641,8 @@ bool get_phys_addr(CPUARMState *env, vaddr address, } ptw.in_space = ss; - return get_phys_addr_gpc(env, &ptw, address, access_type, result, fi); + return get_phys_addr_gpc(env, &ptw, address, access_type, + memop, result, fi); } hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, @@ -3660,7 +3661,7 @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, ARMMMUFaultInfo fi = {}; bool ret; - ret = get_phys_addr_gpc(env, &ptw, addr, MMU_DATA_LOAD, &res, &fi); + ret = get_phys_addr_gpc(env, &ptw, addr, MMU_DATA_LOAD, 0, &res, &fi); *attrs = res.f.attrs; if (ret) { From patchwork Sat Oct 5 15:25:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 832989 Delivered-To: patch@linaro.org Received: by 2002:adf:8b52:0:b0:367:895a:4699 with SMTP id v18csp1257051wra; Sat, 5 Oct 2024 08:31:17 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXap5AIkgCwRTlF+HReN5ea+UbC0PFthZh682xJMHEHCNt1KAToJCl9vFm+CkXIV6Pild58Rg==@linaro.org X-Google-Smtp-Source: AGHT+IFDs4/Yffd4VVuUDLQH2Q2VL6Q2eoTyUaHOaCTtaCckFF4X1bgTMahVCr3SVS9QOOzPSeag X-Received: by 2002:a05:620a:1925:b0:7a9:aeb3:4b22 with SMTP id af79cd13be357-7ae6f421d78mr1158690585a.6.1728142276818; Sat, 05 Oct 2024 08:31:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1728142276; cv=none; d=google.com; s=arc-20240605; b=TZva6pZwnluWnTxJ/sZuO8/6xEKhnOkaNvSlwptfWeQmk4FLyaJODAVSZURDrZPjLO jE/xvzYxwsTtDvmlhb4MnojpM5nGusBh16l9SBq1wY8jPFZwULLyyvt6Y0XhMvZys7gk WAhtB80tfTDR8K/4ylDzxWLRyf77DggOSwMyBuLbKNNVIHraOAiJGrkR9GO9QvSsAa46 Ctngzmvsnk6s+AjX/cBaA+pbZvoOB16zq0bLEcwebgE+5ADe3CawH91b+QVfaWDkelLj gKbc5AE0sMxg/vVgwQiHnt6CULkIDgSsxc/JtLJB8t8RLgmcHPVQ40J9OhB+luPPyju4 yExw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=3KXMhwqlNY3FEn9X64ijA0SceY+BOiTFnpHj8/s1p5o=; fh=rQg8EQ8KH04w/0VkDYF6/ktgEyHJ2dqn1eatHCfBaLw=; b=abCNZktf78541AOVy5TtKfbJat6SggJCEY86JqnwkF8GNvGeQBskDJr/n0vxka2fGz ZMED3ZhqDN1eREZvFs5XCzq6d8Wv3EYgxnf/mr9mEbut9wYCTg5CSAuQzMcNe5xTqWEr lqADESSx4CBoxmMtwIrpLj5pcM8xRSvrLGVKQva/nATbr6pS/sbTuwTP+o84NzTMowzb 2EbqWhHPnA7WZu2tNfpS43VjPeb+Xi/9UHspjb5yrEBvcRwyoVKBvSvIZAhroVkL7vyg YGu9mNNpsOYyjwupHq7uSvH3brPoWJLZnB996d1E+Fc9Frmc4n4tf4rnEIMQHPqB9hDY oXgw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zdimwVRY; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20c1396948dsm14351765ad.225.2024.10.05.08.26.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 05 Oct 2024 08:26:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@kernel.org, peter.maydell@linaro.org, alex.bennee@linaro.org, linux-parisc@vger.kernel.org, qemu-arm@nongnu.org Subject: [PATCH 16/20] target/arm: Pass MemOp to get_phys_addr_nogpc Date: Sat, 5 Oct 2024 08:25:47 -0700 Message-ID: <20241005152551.307923-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241005152551.307923-1-richard.henderson@linaro.org> References: <20241005152551.307923-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Zero is the safe do-nothing value for callers to use. Pass the value through from get_phys_addr_gpc and get_phys_addr_with_space_nogpc. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- target/arm/ptw.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index e92537d8f2..0445c3ccf3 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -75,7 +75,7 @@ typedef struct S1Translate { static bool get_phys_addr_nogpc(CPUARMState *env, S1Translate *ptw, vaddr address, - MMUAccessType access_type, + MMUAccessType access_type, MemOp memop, GetPhysAddrResult *result, ARMMMUFaultInfo *fi); @@ -3313,7 +3313,7 @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw, ARMSecuritySpace ipa_space; uint64_t hcr; - ret = get_phys_addr_nogpc(env, ptw, address, access_type, result, fi); + ret = get_phys_addr_nogpc(env, ptw, address, access_type, 0, result, fi); /* If S1 fails, return early. */ if (ret) { @@ -3339,7 +3339,7 @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw, cacheattrs1 = result->cacheattrs; memset(result, 0, sizeof(*result)); - ret = get_phys_addr_nogpc(env, ptw, ipa, access_type, result, fi); + ret = get_phys_addr_nogpc(env, ptw, ipa, access_type, 0, result, fi); fi->s2addr = ipa; /* Combine the S1 and S2 perms. */ @@ -3406,7 +3406,7 @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw, static bool get_phys_addr_nogpc(CPUARMState *env, S1Translate *ptw, vaddr address, - MMUAccessType access_type, + MMUAccessType access_type, MemOp memop, GetPhysAddrResult *result, ARMMMUFaultInfo *fi) { @@ -3547,7 +3547,8 @@ static bool get_phys_addr_gpc(CPUARMState *env, S1Translate *ptw, GetPhysAddrResult *result, ARMMMUFaultInfo *fi) { - if (get_phys_addr_nogpc(env, ptw, address, access_type, result, fi)) { + if (get_phys_addr_nogpc(env, ptw, address, access_type, + memop, result, fi)) { return true; } if (!granule_protection_check(env, result->f.phys_addr, @@ -3568,7 +3569,8 @@ bool get_phys_addr_with_space_nogpc(CPUARMState *env, vaddr address, .in_mmu_idx = mmu_idx, .in_space = space, }; - return get_phys_addr_nogpc(env, &ptw, address, access_type, result, fi); + return get_phys_addr_nogpc(env, &ptw, address, access_type, + memop, result, fi); } bool get_phys_addr(CPUARMState *env, vaddr address, From patchwork Sat Oct 5 15:25:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 832973 Delivered-To: patch@linaro.org Received: by 2002:adf:8b52:0:b0:367:895a:4699 with SMTP id v18csp1255846wra; Sat, 5 Oct 2024 08:27:32 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXDY68uFZQFJPBhIod8AxepLhQIYb3L0SSDRXtid0RvfvhswhFqwLZyRLsJi5I6jRgWb+pT0w==@linaro.org X-Google-Smtp-Source: AGHT+IFMY0wWjW7ci4kdCw1RrTUsZQyzA1vby8lU8S+r6yRazgy2O//KMbW9+GVYx91Og0hcD7po X-Received: by 2002:a05:622a:2b0c:b0:45d:a127:8257 with SMTP id d75a77b69052e-45da1278757mr68759421cf.57.1728142052194; Sat, 05 Oct 2024 08:27:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1728142052; cv=none; d=google.com; s=arc-20240605; b=NeMhGXgY6EPfryYNsYJkfuKB5XnXwPDuY3Xi0kDswFHhu+9VUkY48intlq/HFCizuk 8mnZ2peOL1K/6HrXQ2yUNygRAunbOyDvuEOC0mEMxhHyq9sePQXf8UhbMCw1w/hrxaA9 z74kqfYnPEkG9Uh+JtyYBlqHwq/QE3XJoM/LtPk+8KWkFnjq/+KNsV3kv3gdTTn6297z qMtkuDV/UYu1pID7xNFxDhwRkZcd7jPyOdOzZi/mHOyCgN8+U0n0ekIW9z48Ux2N9GE9 JOiXtZDvLQ1FKiVDq4kEv2EFcYC/ZG0LdAVqOcBz7W3ZGFahcN8Hp0oWMPCGItLuaTUH 0SNw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=oB3S/z+Tf/YurYPbjZAkQ2iOmy2pkllXkguo9aONGm0=; fh=rQg8EQ8KH04w/0VkDYF6/ktgEyHJ2dqn1eatHCfBaLw=; b=HXYa3J7schBYghLGy8zYltYxpDE6I3UU8CU+gjXzMrIxeljsJMb99NneLXueLdLntU nwVBxonlH9wUNAcgO5bJ2XZ4ML8Gr5XCGNM6rRWDiQbI+k6YRaZw4OQQ5oAGhaitovLk S4VfO112jJsh2h46Fz2I9e3aCTiOWxz3vB9OoJlMzuoDMk9YrCqIEHAoLMD3TOzF9zy9 uwheuof46kq+HPoAWqp5rx0wbbNxP4eDQGS9j+yUFhsWCR9EhqVS3zqzXhOMxWLivG4O BzwZ0edINOka/MRK+7IAQ3wtrUV30/pIh08Spb3Snh3FO/BLxDv3J3rjFVD65IKM5Ehq EZbw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OtTQd1cd; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20c1396948dsm14351765ad.225.2024.10.05.08.26.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 05 Oct 2024 08:26:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@kernel.org, peter.maydell@linaro.org, alex.bennee@linaro.org, linux-parisc@vger.kernel.org, qemu-arm@nongnu.org Subject: [PATCH 17/20] target/arm: Pass MemOp through get_phys_addr_twostage Date: Sat, 5 Oct 2024 08:25:48 -0700 Message-ID: <20241005152551.307923-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241005152551.307923-1-richard.henderson@linaro.org> References: <20241005152551.307923-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Pass memop through get_phys_addr_twostage with its recursion with get_phys_addr_nogpc. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- target/arm/ptw.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 0445c3ccf3..f1fca086a4 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -3301,7 +3301,7 @@ static bool get_phys_addr_disabled(CPUARMState *env, static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw, vaddr address, - MMUAccessType access_type, + MMUAccessType access_type, MemOp memop, GetPhysAddrResult *result, ARMMMUFaultInfo *fi) { @@ -3313,7 +3313,8 @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw, ARMSecuritySpace ipa_space; uint64_t hcr; - ret = get_phys_addr_nogpc(env, ptw, address, access_type, 0, result, fi); + ret = get_phys_addr_nogpc(env, ptw, address, access_type, + memop, result, fi); /* If S1 fails, return early. */ if (ret) { @@ -3339,7 +3340,8 @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw, cacheattrs1 = result->cacheattrs; memset(result, 0, sizeof(*result)); - ret = get_phys_addr_nogpc(env, ptw, ipa, access_type, 0, result, fi); + ret = get_phys_addr_nogpc(env, ptw, ipa, access_type, + memop, result, fi); fi->s2addr = ipa; /* Combine the S1 and S2 perms. */ @@ -3469,7 +3471,7 @@ static bool get_phys_addr_nogpc(CPUARMState *env, S1Translate *ptw, if (arm_feature(env, ARM_FEATURE_EL2) && !regime_translation_disabled(env, ARMMMUIdx_Stage2, ptw->in_space)) { return get_phys_addr_twostage(env, ptw, address, access_type, - result, fi); + memop, result, fi); } /* fall through */ From patchwork Sat Oct 5 15:25:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 832986 Delivered-To: patch@linaro.org Received: by 2002:adf:8b52:0:b0:367:895a:4699 with SMTP id v18csp1256936wra; Sat, 5 Oct 2024 08:30:59 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUovEJWrsfYy5Zj6E/O3xlL5dMRKSRoz+6P22vDfmseipmE9KJXZy7hF/9f3Zc8KZrKEvdnAw==@linaro.org X-Google-Smtp-Source: AGHT+IFDgT2EiHeMDQRWmpXdBBp2HmiFnsfud+xGuN7SyYphwGrVoZJOKxgMS0zX/GpzYtNGcbu4 X-Received: by 2002:a05:620a:1a86:b0:7a9:d0d2:a5fc with SMTP id af79cd13be357-7ae6f43c967mr1159325285a.15.1728142259151; Sat, 05 Oct 2024 08:30:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1728142259; cv=none; d=google.com; s=arc-20240605; b=UcT6TJ9MB+EzygOJPPx53Bt1dQZTI3JSM5Tv6SIb/mnmgMNr+dhNMyQl61SVIkNvI9 kYIrPWr7ZHSt7QLgC3buSFnT8y8s+6rAGfvkzcSzg9Qm0NMCku7WYFMV4CoFNubKOi52 SikbAXtFl65xuDrDMnaAkTPH9xDpLatpYgOCcjM3gGP/GY4FohwMLTIPXoYpMONfq3j+ Od51Dhci+f6DGRZ6YDrcCbohGXayCVltQ1ZOIUYKO1cdkNnnUmLgUkjO22sdPP/LIbDu n4cdxOeurHiaGmUHT5duBaAKZ7lR64UW+kIr2pAFqrpqf1y4hEn2OGWCq1cNfQWxBaDr WOYQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=9tqb0TUsQOZF/sRJ8YxWqhKeQa3g/EH2JXyCvd2UdW4=; fh=rQg8EQ8KH04w/0VkDYF6/ktgEyHJ2dqn1eatHCfBaLw=; b=KvQrWZQWWIEkHHz1d43HbFdzXZntqjoOyIpBDEbgs/8d7finkXATZUpnquOt/iSSsg wCkz1Ju0Oj8ere82uatYYTXx8Xmu2Y23wsAQOI5XvEsOUtmYUxnpShpHKc6X1SIyMBu5 K6Ww26nEteZkvQFtQEjLvctsRmbITCVX0Rs01yjh60mxQV/NbKGebPrWJZZq1QZ0IrPT rEQFHAyy5JK0PeDtMRsQP2easaF8MIii8Hz5iYBZrI/yfhMyzJy19KAFG+YksaJxlazu VSMlCwacbAhmfjEOUrOcmkxyWosiCwCcrSqz8b7Sr8OTSiPhVH8m7mWyF9rOz6mN4bYw urbg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=y2YAOQ2M; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20c1396948dsm14351765ad.225.2024.10.05.08.26.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 05 Oct 2024 08:26:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@kernel.org, peter.maydell@linaro.org, alex.bennee@linaro.org, linux-parisc@vger.kernel.org, qemu-arm@nongnu.org Subject: [PATCH 18/20] target/arm: Pass MemOp to get_phys_addr_lpae Date: Sat, 5 Oct 2024 08:25:49 -0700 Message-ID: <20241005152551.307923-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241005152551.307923-1-richard.henderson@linaro.org> References: <20241005152551.307923-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Pass the value through from get_phys_addr_nogpc. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- target/arm/ptw.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index f1fca086a4..238b2c92a9 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1684,12 +1684,13 @@ static bool nv_nv1_enabled(CPUARMState *env, S1Translate *ptw) * @ptw: Current and next stage parameters for the walk. * @address: virtual address to get physical address for * @access_type: MMU_DATA_LOAD, MMU_DATA_STORE or MMU_INST_FETCH + * @memop: memory operation feeding this access, or 0 for none * @result: set on translation success, * @fi: set to fault info if the translation fails */ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, uint64_t address, - MMUAccessType access_type, + MMUAccessType access_type, MemOp memop, GetPhysAddrResult *result, ARMMMUFaultInfo *fi) { ARMCPU *cpu = env_archcpu(env); @@ -3534,7 +3535,8 @@ static bool get_phys_addr_nogpc(CPUARMState *env, S1Translate *ptw, } if (regime_using_lpae_format(env, mmu_idx)) { - return get_phys_addr_lpae(env, ptw, address, access_type, result, fi); + return get_phys_addr_lpae(env, ptw, address, access_type, + memop, result, fi); } else if (arm_feature(env, ARM_FEATURE_V7) || regime_sctlr(env, mmu_idx) & SCTLR_XP) { return get_phys_addr_v6(env, ptw, address, access_type, result, fi); From patchwork Sat Oct 5 15:25:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 832972 Delivered-To: patch@linaro.org Received: by 2002:adf:8b52:0:b0:367:895a:4699 with SMTP id v18csp1255831wra; Sat, 5 Oct 2024 08:27:28 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVtxArnvgy1zuYlGmPDIqsxfj+7U3Dbb9lj+h4NmAd/ipqLcOtaqVIfWAAfEt7lw8lXSNzsmw==@linaro.org X-Google-Smtp-Source: AGHT+IHtsGS4Im5ho43XCp2oFDgCrCBhDXIiG0J04HJjZ596mqaYiq8CXJTl/dhVODERaTgcW2ZZ X-Received: by 2002:a05:620a:1929:b0:7ad:832a:4063 with SMTP id af79cd13be357-7ae6f432b64mr1067967285a.7.1728142048532; Sat, 05 Oct 2024 08:27:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1728142048; cv=none; d=google.com; s=arc-20240605; b=iTgCauaPK0bSFj4fXS0Bo/IRX/D4n6N6lmfhNNjHwyCe2KesCfXVQ0dlzYjVUpBevg PVixDoj1TVYl8Ft+xqyXXnezS8D7e1h4OUBZrpkAp/iFGNr6gQD/DS7sqFoskg5F+kMQ 4KlL+IMcenoyKRvxhqmkDmSi7+RhMVPtTjQHbzrL4FaP2NPIFUcbiEdvT+V3zZ3qwJvV Y90ETz+1NycP3LlvHti31fj6J981PPX+uvWC1nhONbObZkJocPER7sUkOrAAruCKF3ks bZua+4O8J/K8QR1iIZzDHL7KEMJ1SawqdESbmLFgg/6H0cv3LtJTMH5PjzVDIoVNvjwk couQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=/ZHU/9Bj/Yhl/fLIAf9ED9KKjqQvRkGT+c+Pl2SvUJY=; fh=rQg8EQ8KH04w/0VkDYF6/ktgEyHJ2dqn1eatHCfBaLw=; b=fnBwXM9AwZuHXLbCT9TrFccogHv/yf6zPz1jDPuWAVpmpnwE6YQzYFf07sWvrxRfjb 8/vQ7WbUwh8lA22rarziZSe8+kG1V8G/3HChuoLI1Ezsno4aTOOJuDYpnP70A6U+4hdx zvYfhLtgMwq2iV2JSjr9SbTd87kzBd/a7xdQo/N5QIE910o/moh9yGia/lEvnbStZ49+ kGKKxQxlEfNxIvkb/E6b+jbk8LFP74lWt2zRCpgfM+Vz8E8hdbWrrU2FFGtJgNS238kg p0AlPA3Oip4IAso6JfB5T/U0JukeMbmaIVjuT1NSdB0LzpXGOVtzB9Wxog4X/M5G5vJx RU1w==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NbCZxWDX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20c1396948dsm14351765ad.225.2024.10.05.08.26.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 05 Oct 2024 08:26:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@kernel.org, peter.maydell@linaro.org, alex.bennee@linaro.org, linux-parisc@vger.kernel.org, qemu-arm@nongnu.org Subject: [PATCH 19/20] target/arm: Move device detection earlier in get_phys_addr_lpae Date: Sat, 5 Oct 2024 08:25:50 -0700 Message-ID: <20241005152551.307923-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241005152551.307923-1-richard.henderson@linaro.org> References: <20241005152551.307923-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Determine cache attributes, and thence Device vs Normal memory, earlier in the function. We have an existing regime_is_stage2 if block into which this can be slotted. Signed-off-by: Richard Henderson --- target/arm/ptw.c | 49 ++++++++++++++++++++++++------------------------ 1 file changed, 25 insertions(+), 24 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 238b2c92a9..0a1a820362 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2029,8 +2029,20 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, xn = extract64(attrs, 53, 2); result->f.prot = get_S2prot(env, ap, xn, ptw->in_s1_is_el0); } + + result->cacheattrs.is_s2_format = true; + result->cacheattrs.attrs = extract32(attrs, 2, 4); + /* + * Security state does not really affect HCR_EL2.FWB; + * we only need to filter FWB for aa32 or other FEAT. + */ + device = S2_attrs_are_device(arm_hcr_el2_eff(env), + result->cacheattrs.attrs); } else { int nse, ns = extract32(attrs, 5, 1); + uint8_t attrindx; + uint64_t mair; + switch (out_space) { case ARMSS_Root: /* @@ -2102,6 +2114,19 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, */ result->f.prot = get_S1prot(env, mmu_idx, aarch64, ap, xn, pxn, result->f.attrs.space, out_space); + + /* Index into MAIR registers for cache attributes */ + attrindx = extract32(attrs, 2, 3); + mair = env->cp15.mair_el[regime_el(env, mmu_idx)]; + assert(attrindx <= 7); + result->cacheattrs.is_s2_format = false; + result->cacheattrs.attrs = extract64(mair, attrindx * 8, 8); + + /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */ + if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) { + result->f.extra.arm.guarded = extract64(attrs, 50, 1); /* GP */ + } + device = S1_attrs_are_device(result->cacheattrs.attrs); } if (!(result->f.prot & (1 << access_type))) { @@ -2131,30 +2156,6 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, result->f.attrs.space = out_space; result->f.attrs.secure = arm_space_is_secure(out_space); - if (regime_is_stage2(mmu_idx)) { - result->cacheattrs.is_s2_format = true; - result->cacheattrs.attrs = extract32(attrs, 2, 4); - /* - * Security state does not really affect HCR_EL2.FWB; - * we only need to filter FWB for aa32 or other FEAT. - */ - device = S2_attrs_are_device(arm_hcr_el2_eff(env), - result->cacheattrs.attrs); - } else { - /* Index into MAIR registers for cache attributes */ - uint8_t attrindx = extract32(attrs, 2, 3); - uint64_t mair = env->cp15.mair_el[regime_el(env, mmu_idx)]; - assert(attrindx <= 7); - result->cacheattrs.is_s2_format = false; - result->cacheattrs.attrs = extract64(mair, attrindx * 8, 8); - - /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */ - if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) { - result->f.extra.arm.guarded = extract64(attrs, 50, 1); /* GP */ - } - device = S1_attrs_are_device(result->cacheattrs.attrs); - } - /* * Enable alignment checks on Device memory. * From patchwork Sat Oct 5 15:25:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 832970 Delivered-To: patch@linaro.org Received: by 2002:adf:8b52:0:b0:367:895a:4699 with SMTP id v18csp1255586wra; Sat, 5 Oct 2024 08:26:35 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVj1ke+x70O31fzCAI66z6wSRKjluJSmx8DiEVLStLpcRyldh2DRyU+j21l/VPZisot3eNN9Q==@linaro.org X-Google-Smtp-Source: AGHT+IHAsxw1Ia4cBJlzuoA4hORx5apueNt2708cERrx3+7n10CrqTj1vizotb3lhvk8qtaxUnCG X-Received: by 2002:a05:622a:1ba5:b0:458:2c22:e696 with SMTP id d75a77b69052e-45d9bb2a884mr83834051cf.56.1728141995098; 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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20c1396948dsm14351765ad.225.2024.10.05.08.26.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 05 Oct 2024 08:26:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@kernel.org, peter.maydell@linaro.org, alex.bennee@linaro.org, linux-parisc@vger.kernel.org, qemu-arm@nongnu.org Subject: [PATCH 20/20] target/arm: Fix alignment fault priority in get_phys_addr_lpae Date: Sat, 5 Oct 2024 08:25:51 -0700 Message-ID: <20241005152551.307923-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241005152551.307923-1-richard.henderson@linaro.org> References: <20241005152551.307923-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Now that we have the MemOp for the access, we can order the alignment fault caused by memory type before the permission fault for the page. For subsequent page hits, permission and stage 2 checks are known to pass, and so the TLB_CHECK_ALIGNED fault raised in generic code is not mis-ordered. Signed-off-by: Richard Henderson --- target/arm/ptw.c | 49 +++++++++++++++++++++++++++--------------------- 1 file changed, 28 insertions(+), 21 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 0a1a820362..50aa5e338c 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2129,6 +2129,34 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, device = S1_attrs_are_device(result->cacheattrs.attrs); } + /* + * Enable alignment checks on Device memory. + * + * Per R_XCHFJ, the correct ordering for alignment, permission, + * and stage 2 faults is: + * - Alignment fault caused by the memory type + * - Permission fault + * - A stage 2 fault on the memory access + * Perform the alignment check now, so that we recognize it in + * the correct order. Set TLB_CHECK_ALIGNED so that any subsequent + * softmmu tlb hit will also check the alignment. + * + * In v7, for a CPU without the Virtualization Extensions this + * access is UNPREDICTABLE; we choose to make it take the alignment + * fault as is required for a v7VE CPU. (QEMU doesn't emulate any + * CPUs with ARM_FEATURE_LPAE but not ARM_FEATURE_V7VE anyway.) + */ + if (device) { + unsigned a_bits = memop_atomicity_bits(memop); + if (address & ((1 << a_bits) - 1)) { + fi->type = ARMFault_Alignment; + goto do_fault; + } + result->f.tlb_fill_flags = TLB_CHECK_ALIGNED; + } else { + result->f.tlb_fill_flags = 0; + } + if (!(result->f.prot & (1 << access_type))) { fi->type = ARMFault_Permission; goto do_fault; @@ -2156,27 +2184,6 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, result->f.attrs.space = out_space; result->f.attrs.secure = arm_space_is_secure(out_space); - /* - * Enable alignment checks on Device memory. - * - * Per R_XCHFJ, this check is mis-ordered. The correct ordering - * for alignment, permission, and stage 2 faults should be: - * - Alignment fault caused by the memory type - * - Permission fault - * - A stage 2 fault on the memory access - * but due to the way the TCG softmmu TLB operates, we will have - * implicitly done the permission check and the stage2 lookup in - * finding the TLB entry, so the alignment check cannot be done sooner. - * - * In v7, for a CPU without the Virtualization Extensions this - * access is UNPREDICTABLE; we choose to make it take the alignment - * fault as is required for a v7VE CPU. (QEMU doesn't emulate any - * CPUs with ARM_FEATURE_LPAE but not ARM_FEATURE_V7VE anyway.) - */ - if (device) { - result->f.tlb_fill_flags |= TLB_CHECK_ALIGNED; - } - /* * For FEAT_LPA2 and effective DS, the SH field in the attributes * was re-purposed for output address bits. The SH attribute in