From patchwork Fri Oct 4 21:48:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guillaume Stols X-Patchwork-Id: 832829 Received: from mail-lf1-f41.google.com (mail-lf1-f41.google.com [209.85.167.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ED2391B4F0C for ; Fri, 4 Oct 2024 21:48:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728078533; cv=none; b=iBecghfy/ha+NgCeyBdUOW7CsA30iu/Pe/hnJTZ2uBur1vJEIb3ktnzWCTPnjtSEPi60n4b2Uuu70tHnH3o5zfWCWz6lQTtDL91czKG+1VTY2UoV0IqwlfO4zWao/GtlOUX0N0COQsQHmmlLoGjTVbz+XEezmVvJPFBjfi//SDQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728078533; c=relaxed/simple; bh=dW6NuJWAL0tnqJGgsGPu8j1VoVP4zCeNUzqvDunBNqs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=FC2N22bH0FIXrO877NVjT1gEkQ6r8Ng1J9WLay+O4TZa7IhScqvsRPYPulybI7/SimDeeNn8IXPbxFyNjurHtVi0SEKy1rzyFmeci9v7dVw59XHhy9mCG9crwRoZUTK8f4jVny94j0Eub+gHKXkS7t8RA0ZDGjtNdVFXmIUDxww= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=KHbKMBzO; arc=none smtp.client-ip=209.85.167.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="KHbKMBzO" Received: by mail-lf1-f41.google.com with SMTP id 2adb3069b0e04-5398d171fa2so3190284e87.0 for ; Fri, 04 Oct 2024 14:48:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1728078529; x=1728683329; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=Zi1jIhrpiRkiS4x4FePba+v93fkZAzTXFTnvV0Q7SJI=; b=KHbKMBzOUkxinDQspNRqlLP9ZOOyfi6oFUC0tlAEzXGYDRRq9n2lJ3pAfBu6DymGB1 2fJmYNG21/XX3Whkxuf1dPcmVe925V4lEjK5oOht8EIc5v5HFqhhbSITVVR8co/cdPZB nfeeSQhgaC4OZDQSgNVaZclcAwfZj/9U8Jh2TXw6zJKjOGI0yezjV2s1bdp9ZhqP3NXo aGlc7KsarJFeJQBlFoB7LlsBjTcrekddx5p2Hh88YZrKlaKjIn1xg/rKCO1hI+8waQ5C cpZWAY71bFDxtjCwCG42HEJ46s9wJW9l0xokQkG/q4shKIpFb2bMQosgnwtk+dYS20Sn p49Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1728078529; x=1728683329; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Zi1jIhrpiRkiS4x4FePba+v93fkZAzTXFTnvV0Q7SJI=; b=lHegFF+IWLZBdOZGWHYlggs8zpt0DQJfnyLGdeksKKZ+EJDwIa8V3LZXJNdxeQCuP4 QLW/R/Q2GHuPTPXHfBvHj+zun/EfYuPhFCYsseV1YjU+u9R73sqSBAcGSuZ3xEkeTbwk gBCXuq8CTakUam65vYHmuc+SlJGfCLLhC026CJjzoojDf1v3gMbtpyBKDO/f7A7dvogU ELu6yIZ77ZRlKHvF5ZTlV44WocVwUFpHxwFCqjQCqZJFqzKacmoLP1yEYUQUyXYhNrDr K9LxZaAdC+EOIKX3uhGpr40epKaT+vuY0nKT/14p+antSHGhttKhpoB4Zn4gKgKfQzBi oc+A== X-Forwarded-Encrypted: i=1; AJvYcCWoaRYKvFqRd5VuILaSMTupuQWgaKyW4yc0phk17OCLwBuGdpeq13g8IMN6DJ+8tS0tON8zaOM7FYxmjg==@vger.kernel.org X-Gm-Message-State: AOJu0YxWUW1CCNVTfjdV78fKHehpFfQAxY8DKnaK5NM60dwK24nb7Nhg UDkVAp09auAGKkZULP5e2YYyozxlIg3SN0syylPPGOMsWSV95sUaXDUAkocWUGs= X-Google-Smtp-Source: AGHT+IG9vKnlCyYpJNJyXVcqaNvjMhM227pXj314Ws0xBmbWWcURKzDXKJu6hWgq+z1B4KbbgtI7zg== X-Received: by 2002:a05:6512:3090:b0:52c:e1cd:39b7 with SMTP id 2adb3069b0e04-539ab85be3fmr2837875e87.5.1728078528670; Fri, 04 Oct 2024 14:48:48 -0700 (PDT) Received: from [127.0.1.1] (frhb82016ds.ikexpress.com. [185.246.87.17]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42f86b4ab63sm24680375e9.40.2024.10.04.14.48.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Oct 2024 14:48:47 -0700 (PDT) From: Guillaume Stols Date: Fri, 04 Oct 2024 21:48:36 +0000 Subject: [PATCH v3 02/10] dt-bindings: iio: adc: ad7606: Remove spi-cpha from required Precedence: bulk X-Mailing-List: linux-fbdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241004-ad7606_add_iio_backend_support-v3-2-38757012ce82@baylibre.com> References: <20241004-ad7606_add_iio_backend_support-v3-0-38757012ce82@baylibre.com> In-Reply-To: <20241004-ad7606_add_iio_backend_support-v3-0-38757012ce82@baylibre.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Greg Kroah-Hartman , "Rafael J. Wysocki" , Jonathan Corbet Cc: linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org, Michael Hennerich , linux-fbdev@vger.kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, aardelean@baylibre.com, dlechner@baylibre.com, Jonathan Cameron , Guillaume Stols X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1728078523; l=2037; i=gstols@baylibre.com; s=20240417; h=from:subject:message-id; bh=dW6NuJWAL0tnqJGgsGPu8j1VoVP4zCeNUzqvDunBNqs=; b=1JBVnXogi8Y6VmRN4ENJTNsSU2nRs5+Y+Xu9FQStSslUOMfRP19G/XBoT+HQFyDiYJCMz/qD8 NFHk3dWGBGUD1Y8O56KBx8G/wlK2ECH14DN83u6ihheoy5zIGdM+Ejb X-Developer-Key: i=gstols@baylibre.com; a=ed25519; pk=XvMm5WHuV67sGYOJZqIYzXndbaJOlNd8Q6li6vnb4Cs= The documentation is erroneously stating that spi-cpha is required, and the example is erroneously setting both spi-cpol and spi-cpha. According to the datasheet, only cpol should be set. On zedboard for instance, setting the devicetree as in the example will simply not work. Fixes: 416f882c3b40 ("dt-bindings: iio: adc: Migrate AD7606 documentation to yaml") Fixes: 6e33a125df66 ("dt-bindings: iio: adc: Add docs for AD7606 ADC") Signed-off-by: Guillaume Stols --- Documentation/devicetree/bindings/iio/adc/adi,ad7606.yaml | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7606.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad7606.yaml index bec7cfba52a7..47081c79a1cf 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7606.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7606.yaml @@ -39,6 +39,11 @@ properties: "#size-cells": const: 0 + # According to the datasheet, "Data is clocked in from SDI on the falling + # edge of SCLK, while data is clocked out on DOUTA on the rising edge of + # SCLK". Also, even if not stated textually in the datasheet, it is made + # clear on the diagrams that sclk idles at high. Subsequently, in case SPI + # interface is used, the correct way is to only set spi-cpol. spi-cpha: true spi-cpol: true @@ -168,7 +173,6 @@ patternProperties: required: - compatible - reg - - spi-cpha - avcc-supply - vdrive-supply - interrupts @@ -255,7 +259,6 @@ examples: reg = <0>; spi-max-frequency = <1000000>; spi-cpol; - spi-cpha; avcc-supply = <&adc_vref>; vdrive-supply = <&vdd_supply>; @@ -288,7 +291,6 @@ examples: spi-max-frequency = <1000000>; spi-cpol; - spi-cpha; avcc-supply = <&adc_vref>; vdrive-supply = <&vdd_supply>; From patchwork Fri Oct 4 21:48:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guillaume Stols X-Patchwork-Id: 832828 Received: from mail-wm1-f48.google.com (mail-wm1-f48.google.com [209.85.128.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 27FAF1CACC0 for ; Fri, 4 Oct 2024 21:48:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728078535; cv=none; b=EjHePBlOPgjmM6vgrFeIdHJJX9damCVkQF93GfAzbSkW7tpDO7RGe3g3J9MlEzTcsnzLaY9mXw97F03l8r6km1Z4zITsfbTCwG1C82xWhLA6XnMmBhGA8TSnoVQzkz8qCdCijhrSWj7RgNFoUsQL8enunrjhipDIqVzBIrYkKxw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728078535; c=relaxed/simple; bh=jVSeA1GybXKEqinyGc0o/mVBc+cGPLYZuh+OWslR0Lg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=PMrVtE1LtEK8aPMcOO6qVssgj18Aml5qt8Fqwxd5QSQHyzskanxmQCPY68/9Lt475cqHA0FLkXVVpT9LJQHtwcrjHl9cAFGm2GUcHRdyOpdwgSGyoMoIDTyZfx3NtTGnhn4oYOSzbXvi9reAovNRUy8ZyDkuGge5eq/E3OrkKwo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=nXCKFoPh; arc=none smtp.client-ip=209.85.128.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="nXCKFoPh" Received: by mail-wm1-f48.google.com with SMTP id 5b1f17b1804b1-42cde6b5094so25949665e9.3 for ; Fri, 04 Oct 2024 14:48:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1728078531; x=1728683331; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=Ws6OvwIpBgzbrhXwN/bI0GwmZw37Oa3ub3+JwbGz+M4=; b=nXCKFoPh+Zk0Y08lyb2vuk4nDlt1ReSas6f2gHvyz9JN3lDiQ7JJRXx+l+za0FPjFb jrJdcWxrHl7SIf553HuN5NSQs/QzmVSGA7diN+RKuU6u0dAuPZqWLI1ITOBhyNoqIQjQ HYXXt0QjffTXelSfUNKtalD0d2rGLSdR+Y3maVxHoQLw+oanE05xpR/2ZZYo2r6dLoB7 Z8NCFX9dhiXpZWy1YkGc+384e7PucbPsrjljYyU7VmC2m6cAmmCv+5q3NpYG2atC+C94 i+yWHXsYlYdjwRTehnwzPgwXld3pBZ8G4MIoLE7EFTThXN8qbBJLYRFTAnuJfmk4Px5M fWYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1728078531; x=1728683331; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Ws6OvwIpBgzbrhXwN/bI0GwmZw37Oa3ub3+JwbGz+M4=; b=U0yoJNYC2hEEJIFLPv0GX2yNI9VgCAclabeBzdv8T9S4GQ4fHUgLRd9H/62/hLyqmL MoMfb33YmcAf3lywx0eTAcaH0ke1cJ+Q1J3GTCWaLxm+6Q04I6QuPBHakPDA6lal+JG5 VN1YHHWhSyxE/qb/W5Chj21fzQDV9ZGi2/G1fxc+h3pfrFGRt/nYvAt7WX7MTq7pROcd j2qHmIKsg4XIihtR/jOFkkotKvFA2H3B/bB/jxUspADAdej5qXaVq894BDN41FnmLP2S GEB94N+VMAAe+Dy5VtQmq/F1QVTBOuotwvG/f+AL0GyLaE3z2moVWu/m3lbhc0b0w51+ Lctg== X-Forwarded-Encrypted: i=1; AJvYcCWGa82reUB0+cy5AHH4CXQ7IFXQJ1aCJ4MmaTvyjcUMUhtedF6MwopBGteK+RySyX8K3LgY9c5k1/kfGg==@vger.kernel.org X-Gm-Message-State: AOJu0YxM8eB5GcEiApl1qSXEO5Fo+LVYahoPjQwX6qS8ynHebRe/tvRE iTwdWw855fFI7okSE6PhW8LEZyBeldi+L8SRpHeFW4X8JT4Yc1bKbKJ0dI0BzWg= X-Google-Smtp-Source: AGHT+IEp8lVDApG6/0v+gqntIFP0H2r8NnVYzaeUF9YEnuWGMOZ09DXkJeh3ASsOFaRjuQwShIJQWQ== X-Received: by 2002:a05:600c:4e89:b0:42c:b750:19d8 with SMTP id 5b1f17b1804b1-42f85a700ecmr30381585e9.4.1728078531059; Fri, 04 Oct 2024 14:48:51 -0700 (PDT) Received: from [127.0.1.1] (frhb82016ds.ikexpress.com. [185.246.87.17]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42f86b4ab63sm24680375e9.40.2024.10.04.14.48.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Oct 2024 14:48:50 -0700 (PDT) From: Guillaume Stols Date: Fri, 04 Oct 2024 21:48:38 +0000 Subject: [PATCH v3 04/10] Documentation: iio: Document ad7606 driver Precedence: bulk X-Mailing-List: linux-fbdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241004-ad7606_add_iio_backend_support-v3-4-38757012ce82@baylibre.com> References: <20241004-ad7606_add_iio_backend_support-v3-0-38757012ce82@baylibre.com> In-Reply-To: <20241004-ad7606_add_iio_backend_support-v3-0-38757012ce82@baylibre.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Greg Kroah-Hartman , "Rafael J. Wysocki" , Jonathan Corbet Cc: linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org, Michael Hennerich , linux-fbdev@vger.kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, aardelean@baylibre.com, dlechner@baylibre.com, Jonathan Cameron , Guillaume Stols X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1728078523; l=6859; i=gstols@baylibre.com; s=20240417; h=from:subject:message-id; bh=jVSeA1GybXKEqinyGc0o/mVBc+cGPLYZuh+OWslR0Lg=; b=GaY3nxCWEFM2NgxV+4xbSLb9wBvMIgJLyCLCMlhKHcOFI1tfKQUpHa2pswAJP8b6Kwp3hWoSV OSyZmLuSxlvCFOk2/W62joq0HB/6y8CTGWodgDZ+b5XgM4NR8ZrngxU X-Developer-Key: i=gstols@baylibre.com; a=ed25519; pk=XvMm5WHuV67sGYOJZqIYzXndbaJOlNd8Q6li6vnb4Cs= The Analog Devices Inc. AD7606 (and similar chips) are complex ADCs that will benefit from a detailed driver documentation. This documents the current features supported by the driver. Signed-off-by: Guillaume Stols --- Documentation/iio/ad7606.rst | 145 +++++++++++++++++++++++++++++++++++++++++++ Documentation/iio/index.rst | 1 + MAINTAINERS | 1 + 3 files changed, 147 insertions(+) diff --git a/Documentation/iio/ad7606.rst b/Documentation/iio/ad7606.rst new file mode 100644 index 000000000000..a1173708b489 --- /dev/null +++ b/Documentation/iio/ad7606.rst @@ -0,0 +1,145 @@ +.. SPDX-License-Identifier: GPL-2.0-only + +============= +AD7606 driver +============= + +ADC driver for Analog Devices Inc. AD7606 and similar devices. The module name +is ``ad7606``. + +Supported devices +================= + +The following chips are supported by this driver: + +* `AD7605 `_ +* `AD7606 `_ +* `AD7606B `_ +* `AD7616 `_ + +Supported features +================== + +SPI wiring modes +---------------- + +These ADCs can output data on several SDO lines (1/2/4/8). The driver +currently supports only 1 SDO line. + +Parallel wiring mode +-------------------- + +There is also a parallel interface, with 16 lines (that can be reduced to 8 in +byte mode). The parallel interface is selected by declaring the device as +platform in the device tree (with no io-backends node defined, see below). + +IIO-backend mode +---------------- + +This mode allows to reach the best sample rates, but it requires an external +hardware (eg HDL or APU) to handle the low level communication. +The backend mode is enabled when through the definition of the "io-backends" +property in the device tree. + +The reference configuration for the current implementation of IIO-backend mode +is the HDL reference provided by ADI: +https://wiki.analog.com/resources/eval/user-guides/ad7606x-fmc/hdl + +This implementation embeds an IIO-backend compatible IP (adi-axi-adc) and a PWM +connected to the conversion trigger pin. + +.. code-block:: + + +---+ +---------------------------- + | | +-------+ |AD76xx + | A | controls | | | + | D |-------------->| PWM |-------------->| cnvst + | 7 | | | | + | 6 | +-------+ | + | 0 | controls +-----------+-----------+ | + | 6 |---------->| | |<--| frstdata + | | | Backend | Backend |<--| busy + | D | | Driver | | | + | R | | | |-->| clk + | I | requests |+---------+| DMA | | + | V |----------->| Buffer ||<---- |<=>| DATA + | E | |+---------+| | | + | R | +-----------+-----------+ | + | |-------------------------------------->| reset/configuration gpios + +---+ +----------------------------- + + +Software and hardware modes +--------------------------- + +While all the AD7606/AD7616 series parts can be configured using GPIOs, some of +them can be configured using register. + +The chips that support software mode have more values available for configuring +the device, as well as more settings, and allow to control the range and +calibration per channel. + +The following settings are available per channel in software mode: + - Scale + +Also, there is a broader choice of oversampling ratios in software mode. + +Conversion triggering +--------------------- + +The conversion can be triggered by two distinct ways: + + - A GPIO is connected to the conversion trigger pin, and this GPIO is controlled + by the driver directly. In this configuration, the driver sets back the + conversion trigger pin to high as soon as it has read all the conversions. + + - An external source is connected to the conversion trigger pin. In the + current implementation, it must be a PWM. In this configuration, the driver + does not control directly the conversion trigger pin. Instead, it can + control the PWM's frequency. This trigger is enabled only for iio-backend. + +Reference voltage +----------------- + +2 possible reference voltage sources are supported: + + - Internal reference (2.5V) + - External reference (2.5V) + +The source is determined by the device tree. If ``refin-supply`` is present, +then the external reference is used, otherwise the internal reference is used. + +Oversampling +------------ + +This family supports oversampling to improve SNR. +In software mode, the following ratios are available: +1 (oversampling disabled)/2/4/8/16/32/64/128/256. + +Unimplemented features +---------------------- + +- 2/4/8 SDO lines +- CRC indication +- Calibration + +Device buffers +============== + +IIO triggered buffer +-------------------- + +This driver supports IIO triggered buffers, with a "built in" trigger, i.e the +trigger is allocated and linked by the driver, and a new conversion is triggered +as soon as the samples are transferred, and a timestamp channel is added to make +up for the potential jitter induced by the delays in the interrupt handling. + +IIO backend buffer +------------------ + +When IIO backend is used, the trigger is not needed, and the sample rate is +considered as stable. There is no timestamp channel. The communication is +delegated to an external logic, called a backend, and the backend's driver +handles the buffer. When this mode is enabled, the driver cannot control the +conversion pin, because the busy pin is bound to the backend. + diff --git a/Documentation/iio/index.rst b/Documentation/iio/index.rst index dfcf9618568a..88bc36326b74 100644 --- a/Documentation/iio/index.rst +++ b/Documentation/iio/index.rst @@ -21,6 +21,7 @@ Industrial I/O Kernel Drivers ad4000 ad4695 ad7380 + ad7606 ad7944 adis16475 adis16480 diff --git a/MAINTAINERS b/MAINTAINERS index bcdf43f37660..45c33d1a4403 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1561,6 +1561,7 @@ F: Documentation/ABI/testing/sysfs-bus-iio-frequency-adf4350 F: Documentation/devicetree/bindings/iio/*/adi,* F: Documentation/devicetree/bindings/iio/adc/lltc,ltc2496.yaml F: Documentation/devicetree/bindings/iio/adc/lltc,ltc2497.yaml +F: Documentation/iio/ad7606.rst F: drivers/iio/*/ad* F: drivers/iio/adc/ltc249* F: drivers/iio/amplifiers/hmc425a.c From patchwork Fri Oct 4 21:48:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Guillaume Stols X-Patchwork-Id: 832827 Received: from mail-wm1-f53.google.com (mail-wm1-f53.google.com [209.85.128.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2DD3C1D8DFB for ; Fri, 4 Oct 2024 21:48:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728078539; cv=none; b=pKNSwWPDTdyKXaFH16bIjQWcoXkJxwiERDdqQDTJabMoxSiXux5zvpuXleTNNrOhjlIEAvyub7EV9ld2CL7cl2rxQf/pSuvF4WOChPPna4mTuOEt4VQo3wO6XrFDCqFJuyAbSvhBF9stllSbw6cOCSptcjnCnwBteIdOrth97h0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728078539; c=relaxed/simple; bh=MPX+gxSXSRVkD6yBFhZnDYs0/lqv0mAf/wM0wEpSIqo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=f29lK3aSn9HBViuytebeem2YKTUQXq2I/AvjtJ4VLBxDl08ytBtTxhEfSTOmV2JobU4CCUqtnGamqy5iUs+E7yHNC5bVnkZvQMWTQGdEwkgzngGgCd1BGNsLD+xKR1fmbWU25Bzr2Erl2jeZ68vCwqSX2AkfQDQKBtAQ7H/bCf8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=TgKMp65B; arc=none smtp.client-ip=209.85.128.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="TgKMp65B" Received: by mail-wm1-f53.google.com with SMTP id 5b1f17b1804b1-42ca4e0299eso23240775e9.2 for ; Fri, 04 Oct 2024 14:48:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1728078534; x=1728683334; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=96IaB7ZOrC1D6CinpPMwTazn0uYiER61veLcA10WMPk=; b=TgKMp65BWBgaiZe4MOI9jjIHWh19LGaq7O7dK2viVnZrlW1phP6qeXdVQBXowvooyU +uPOPsWmUU+LwYLUkS4ovV/6nQL8XwWxpkcS/tI158KdrTLz5q0xh7xo2gDix7nGTXVl VjbWXb/kBb3VNtrz126ki2QVKhghamfl5n0XwTM2ph9zo0PZr/RW2TnH8yxLr5wI6uof vVCVVBhtKlYXxH3aXzkTqCoRj9/7jJ65PM/inZnZlkG8uH7SJUVgM1kuGZx1cTKhGpf7 mUlGQKW9NF/QxQLG/qz0sQWvqpqX/vipqjlw8Yj3DqbXyv/5I5sdHQyhX7YQpcPAJunI bgvg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1728078534; x=1728683334; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=96IaB7ZOrC1D6CinpPMwTazn0uYiER61veLcA10WMPk=; b=eqzI6fm2MapPWFGYiA2uOILJhtMBDsb6yRKpcG+2chY+z2X8Wanw+qEuy7z/Kr977L JbWcnB/pmh8e+rYfW79cSNALDO+CtOCGG/80+rl/eMi91gGx5Ta7Hi/bshXpdEWYENrF elt3/RaZ0R/iHaoFnZxBvM1BbOSYR/wkRqhe/Y/3GS+IaMgOvHYRy2ivCn6eOWMDpZ6K M1pMVlg/oBycETEi6MsD1TKEVAihMXicfDJZ+LT6Iwt50//uk1vsebdj2kYrHKZbWcss 08QMWtrpxrCAIv3g2YVXH/fhYLe85shmq8hhBmb5DATLAvcqqC6BzCofBwZYCYmIsciF 1z6Q== X-Forwarded-Encrypted: i=1; AJvYcCUhouWeENZurSw0akSYEME0S13PrVkV6EnAzMw76PBvIM5kSNanm+ke/jgsoARlV1Vy44+qFNG0MVwkJA==@vger.kernel.org X-Gm-Message-State: AOJu0YwUfwXZIAYuEzAsFfr0tkPhF+kThTCOqD4ZXcrTZfn8K6c6D0XW jOLK5ypv8SebpGhSfTQiM2tF7lxfwCUbye4X0klbBZOJ+WqEi7jkC2Bq/H8nfPk= X-Google-Smtp-Source: AGHT+IHFFnL/fyuYp/t9j06RFOtG2IGJ5n8dGdwUIEZ3jSTxTbhe/WFN270jW/R88z4lbqNHbwhd3w== X-Received: by 2002:a05:600c:4514:b0:42f:7e87:3438 with SMTP id 5b1f17b1804b1-42f859b1931mr31524045e9.0.1728078534077; Fri, 04 Oct 2024 14:48:54 -0700 (PDT) Received: from [127.0.1.1] (frhb82016ds.ikexpress.com. [185.246.87.17]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42f86b4ab63sm24680375e9.40.2024.10.04.14.48.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Oct 2024 14:48:52 -0700 (PDT) From: Guillaume Stols Date: Fri, 04 Oct 2024 21:48:40 +0000 Subject: [PATCH v3 06/10] iio: adc: ad7606: Add PWM support for conversion trigger Precedence: bulk X-Mailing-List: linux-fbdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241004-ad7606_add_iio_backend_support-v3-6-38757012ce82@baylibre.com> References: <20241004-ad7606_add_iio_backend_support-v3-0-38757012ce82@baylibre.com> In-Reply-To: <20241004-ad7606_add_iio_backend_support-v3-0-38757012ce82@baylibre.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Greg Kroah-Hartman , "Rafael J. Wysocki" , Jonathan Corbet Cc: linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org, Michael Hennerich , linux-fbdev@vger.kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, aardelean@baylibre.com, dlechner@baylibre.com, Jonathan Cameron , Guillaume Stols X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1728078523; l=9431; i=gstols@baylibre.com; s=20240417; h=from:subject:message-id; bh=MPX+gxSXSRVkD6yBFhZnDYs0/lqv0mAf/wM0wEpSIqo=; b=4lyU/0RkOrYql/6qWrpQY+utIuSAhkyIj/LBny7Fc0wc5mR+tU/W2e0ZmJmp+wg5rwM4YAdJL p/E9i2QG639Dn0R+45EH3vyCDdrYXUcS7wt5hVV19v9/JF0e7rKqumL X-Developer-Key: i=gstols@baylibre.com; a=ed25519; pk=XvMm5WHuV67sGYOJZqIYzXndbaJOlNd8Q6li6vnb4Cs= Until now, the conversion were triggered by setting high the GPIO connected to the convst pin. This commit gives the possibility to connect the convst pin to a PWM. Connecting a PWM allows to have a better control on the samplerate, but it must be handled with care, as it is completely decorrelated of the driver's busy pin handling. Hence it is not recommended to be used "as is" but must be exploited in conjunction with IIO backend, and for now only a mock functionality is enabled, i.e PWM never swings, but is used as a GPIO, i.e duty_cycle == period equals high state, duty_cycle == 0 equals low state. This mock functionality will be disabled after the IIO backend usecase is introduced. Signed-off-by: Guillaume Stols --- drivers/iio/adc/ad7606.c | 164 ++++++++++++++++++++++++++++++++++++++++------- drivers/iio/adc/ad7606.h | 2 + 2 files changed, 144 insertions(+), 22 deletions(-) diff --git a/drivers/iio/adc/ad7606.c b/drivers/iio/adc/ad7606.c index d1aec53e0bcf..224ffaf3dbff 100644 --- a/drivers/iio/adc/ad7606.c +++ b/drivers/iio/adc/ad7606.c @@ -13,10 +13,12 @@ #include #include #include +#include #include #include #include #include +#include #include #include @@ -299,6 +301,82 @@ static int ad7606_reg_access(struct iio_dev *indio_dev, } } +static int ad7606_pwm_set_high(struct ad7606_state *st) +{ + struct pwm_state cnvst_pwm_state; + int ret; + + if (!st->cnvst_pwm) + return -EINVAL; + + pwm_get_state(st->cnvst_pwm, &cnvst_pwm_state); + cnvst_pwm_state.enabled = true; + cnvst_pwm_state.duty_cycle = cnvst_pwm_state.period; + + ret = pwm_apply_might_sleep(st->cnvst_pwm, &cnvst_pwm_state); + /* sleep 2 µS to let finish the current pulse */ + fleep(2) + + return ret; +} + +static int ad7606_pwm_set_low(struct ad7606_state *st) +{ + struct pwm_state cnvst_pwm_state; + int ret; + + if (!st->cnvst_pwm) + return -EINVAL; + + pwm_get_state(st->cnvst_pwm, &cnvst_pwm_state); + cnvst_pwm_state.enabled = true; + cnvst_pwm_state.duty_cycle = 0; + + ret = pwm_apply_might_sleep(st->cnvst_pwm, &cnvst_pwm_state); + /* sleep 2 µS to let finish the current pulse */ + fleep(2) + + return ret; +} + +static bool ad7606_pwm_is_swinging(struct ad7606_state *st) +{ + struct pwm_state cnvst_pwm_state; + + if (!st->cnvst_pwm) + return false; + + pwm_get_state(st->cnvst_pwm, &cnvst_pwm_state); + + return cnvst_pwm_state.duty_cycle != cnvst_pwm_state.period && + cnvst_pwm_state.duty_cycle != 0; +} + +static int ad7606_set_sampling_freq(struct ad7606_state *st, unsigned long freq) +{ + struct pwm_state cnvst_pwm_state; + bool is_swinging = ad7606_pwm_is_swinging(st); + bool is_high; + + if (freq == 0) + return -EINVAL; + + /* Retrieve the previous state. */ + pwm_get_state(st->cnvst_pwm, &cnvst_pwm_state); + is_high = cnvst_pwm_state.duty_cycle == cnvst_pwm_state.period; + + cnvst_pwm_state.period = DIV_ROUND_UP_ULL(NSEC_PER_SEC, freq); + cnvst_pwm_state.polarity = PWM_POLARITY_NORMAL; + if (is_high) + cnvst_pwm_state.duty_cycle = cnvst_pwm_state.period; + else if (is_swinging) + cnvst_pwm_state.duty_cycle = cnvst_pwm_state.period / 2; + else + cnvst_pwm_state.duty_cycle = 0; + + return pwm_apply_might_sleep(st->cnvst_pwm, &cnvst_pwm_state); +} + static int ad7606_read_samples(struct ad7606_state *st) { unsigned int num = st->chip_info->num_channels - 1; @@ -325,6 +403,7 @@ static irqreturn_t ad7606_trigger_handler(int irq, void *p) iio_trigger_notify_done(indio_dev->trig); /* The rising edge of the CONVST signal starts a new conversion. */ gpiod_set_value(st->gpio_convst, 1); + ad7606_pwm_set_high(st); return IRQ_HANDLED; } @@ -337,7 +416,13 @@ static int ad7606_scan_direct(struct iio_dev *indio_dev, unsigned int ch, const struct iio_chan_spec *chan; int ret; - gpiod_set_value(st->gpio_convst, 1); + if (st->gpio_convst) { + gpiod_set_value(st->gpio_convst, 1); + } else { + ret = ad7606_pwm_set_high(st); + if (ret < 0) + return ret; + } ret = wait_for_completion_timeout(&st->completion, msecs_to_jiffies(1000)); if (!ret) { @@ -364,6 +449,11 @@ static int ad7606_scan_direct(struct iio_dev *indio_dev, unsigned int ch, } error_ret: + if (!st->gpio_convst) { + ret = ad7606_pwm_set_low(st); + if (ret < 0) + return ret; + } gpiod_set_value(st->gpio_convst, 0); return ret; @@ -663,8 +753,9 @@ static int ad7606_request_gpios(struct ad7606_state *st) { struct device *dev = st->dev; - st->gpio_convst = devm_gpiod_get(dev, "adi,conversion-start", - GPIOD_OUT_LOW); + st->gpio_convst = devm_gpiod_get_optional(dev, "adi,conversion-start", + GPIOD_OUT_LOW); + if (IS_ERR(st->gpio_convst)) return PTR_ERR(st->gpio_convst); @@ -709,6 +800,7 @@ static irqreturn_t ad7606_interrupt(int irq, void *dev_id) if (iio_buffer_enabled(indio_dev)) { gpiod_set_value(st->gpio_convst, 0); + ad7606_pwm_set_low(st); iio_trigger_poll_nested(st->trig); } else { complete(&st->completion); @@ -733,6 +825,7 @@ static int ad7606_buffer_postenable(struct iio_dev *indio_dev) struct ad7606_state *st = iio_priv(indio_dev); gpiod_set_value(st->gpio_convst, 1); + ad7606_pwm_set_high(st); return 0; } @@ -742,6 +835,7 @@ static int ad7606_buffer_predisable(struct iio_dev *indio_dev) struct ad7606_state *st = iio_priv(indio_dev); gpiod_set_value(st->gpio_convst, 0); + ad7606_pwm_set_low(st); return 0; } @@ -875,6 +969,11 @@ static int ad7606_chan_scales_setup(struct iio_dev *indio_dev) return 0; } +static void ad7606_pwm_disable(void *data) +{ + pwm_disable(data); +} + int ad7606_probe(struct device *dev, int irq, void __iomem *base_address, const char *name, unsigned int id, const struct ad7606_bus_ops *bops) @@ -951,20 +1050,48 @@ int ad7606_probe(struct device *dev, int irq, void __iomem *base_address, if (ret) return ret; - st->trig = devm_iio_trigger_alloc(dev, "%s-dev%d", - indio_dev->name, - iio_device_id(indio_dev)); - if (!st->trig) - return -ENOMEM; - - st->trig->ops = &ad7606_trigger_ops; - iio_trigger_set_drvdata(st->trig, indio_dev); - ret = devm_iio_trigger_register(dev, st->trig); - if (ret) - return ret; + /* If convst pin is not defined, setup PWM. */ + if (!st->gpio_convst) { + st->cnvst_pwm = devm_pwm_get(dev, NULL); + if (IS_ERR(st->cnvst_pwm)) + return PTR_ERR(st->cnvst_pwm); + /* The PWM is initialized at 1MHz to have a fast enough GPIO emulation. */ + ret = ad7606_set_sampling_freq(st, 1 * MEGA); + if (ret) + return ret; - indio_dev->trig = iio_trigger_get(st->trig); + ret = ad7606_pwm_set_low(st); + if (ret) + return ret; + /* + * PWM is not disabled when sampling stops, but instead its duty cycle is set + * to 0% to be sure we have a "low" state. After we unload the driver, let's + * disable the PWM. + */ + ret = devm_add_action_or_reset(dev, ad7606_pwm_disable, + st->cnvst_pwm); + if (ret) + return ret; + } else { + st->trig = devm_iio_trigger_alloc(dev, "%s-dev%d", + indio_dev->name, + iio_device_id(indio_dev)); + if (!st->trig) + return -ENOMEM; + st->trig->ops = &ad7606_trigger_ops; + iio_trigger_set_drvdata(st->trig, indio_dev); + ret = devm_iio_trigger_register(dev, st->trig); + if (ret) + return ret; + indio_dev->trig = iio_trigger_get(st->trig); + ret = devm_iio_triggered_buffer_setup(dev, indio_dev, + &iio_pollfunc_store_time, + &ad7606_trigger_handler, + &ad7606_buffer_ops); + if (ret) + return ret; + } ret = devm_request_threaded_irq(dev, irq, NULL, &ad7606_interrupt, @@ -973,13 +1100,6 @@ int ad7606_probe(struct device *dev, int irq, void __iomem *base_address, if (ret) return ret; - ret = devm_iio_triggered_buffer_setup(dev, indio_dev, - &iio_pollfunc_store_time, - &ad7606_trigger_handler, - &ad7606_buffer_ops); - if (ret) - return ret; - return devm_iio_device_register(dev, indio_dev); } EXPORT_SYMBOL_NS_GPL(ad7606_probe, IIO_AD7606); diff --git a/drivers/iio/adc/ad7606.h b/drivers/iio/adc/ad7606.h index fc05a4afa3b8..760cf5e2ecb6 100644 --- a/drivers/iio/adc/ad7606.h +++ b/drivers/iio/adc/ad7606.h @@ -115,6 +115,7 @@ struct ad7606_chan_scale { * @bops bus operations (SPI or parallel) * @chan_scales scale configuration for channels * @oversampling oversampling selection + * @cnvst_pwm pointer to the PWM device connected to the cnvst pin * @base_address address from where to read data in parallel operation * @sw_mode_en software mode enabled * @oversampling_avail pointer to the array which stores the available @@ -142,6 +143,7 @@ struct ad7606_state { const struct ad7606_bus_ops *bops; struct ad7606_chan_scale chan_scales[AD760X_MAX_CHANNELS]; unsigned int oversampling; + struct pwm_device *cnvst_pwm; void __iomem *base_address; bool sw_mode_en; const unsigned int *oversampling_avail; From patchwork Fri Oct 4 21:48:42 2024 Content-Type: text/plain; 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[185.246.87.17]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42f86b4ab63sm24680375e9.40.2024.10.04.14.48.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Oct 2024 14:48:56 -0700 (PDT) From: Guillaume Stols Date: Fri, 04 Oct 2024 21:48:42 +0000 Subject: [PATCH v3 08/10] iio: adc: ad7606: Introduce num_adc_channels Precedence: bulk X-Mailing-List: linux-fbdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241004-ad7606_add_iio_backend_support-v3-8-38757012ce82@baylibre.com> References: <20241004-ad7606_add_iio_backend_support-v3-0-38757012ce82@baylibre.com> In-Reply-To: <20241004-ad7606_add_iio_backend_support-v3-0-38757012ce82@baylibre.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Greg Kroah-Hartman , "Rafael J. Wysocki" , Jonathan Corbet Cc: linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org, Michael Hennerich , linux-fbdev@vger.kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, aardelean@baylibre.com, dlechner@baylibre.com, Jonathan Cameron , Guillaume Stols X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1728078523; l=4625; i=gstols@baylibre.com; s=20240417; h=from:subject:message-id; bh=xHVL9hFRnsVwqhbglw04wIIXIdpeMmNkgRFma7ACntE=; b=HWtQ4Rbfr4rMrWvXXCRwlOWpd809HtkywgIKDMU2hLnEDQGQSDGgUrgUf1Zu0m2TfBFXeCaEz 4F6rv8pYXYbD9lqyUccTndw0VHq2O+D1qX89k19LL4gZd6MDsejjYeg X-Developer-Key: i=gstols@baylibre.com; a=ed25519; pk=XvMm5WHuV67sGYOJZqIYzXndbaJOlNd8Q6li6vnb4Cs= This variable determines how many hardware channels has the chip, oppositely to the num_channels that can contain more channels, e.g a timestamp channel in our case. Introducing this variable avoids decreasing the former num_channels variable when reading the ADC's channels, and clarifies a bit the code. Signed-off-by: Guillaume Stols --- drivers/iio/adc/ad7606.c | 10 +++++++++- drivers/iio/adc/ad7606.h | 2 ++ 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/iio/adc/ad7606.c b/drivers/iio/adc/ad7606.c index 612e6d9f57ed..3666a58f8a6f 100644 --- a/drivers/iio/adc/ad7606.c +++ b/drivers/iio/adc/ad7606.c @@ -150,6 +150,7 @@ static int ad7606_16bit_chan_scale_setup(struct ad7606_state *st, const struct ad7606_chip_info ad7605_4_info = { .channels = ad7605_channels, .name = "ad7605-4", + .num_adc_channels = 4, .num_channels = 5, .scale_setup_cb = ad7606_16bit_chan_scale_setup, }; @@ -158,6 +159,7 @@ EXPORT_SYMBOL_NS_GPL(ad7605_4_info, IIO_AD7606); const struct ad7606_chip_info ad7606_8_info = { .channels = ad7606_channels_16bit, .name = "ad7606-8", + .num_adc_channels = 8, .num_channels = 9, .oversampling_avail = ad7606_oversampling_avail, .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail), @@ -168,6 +170,7 @@ EXPORT_SYMBOL_NS_GPL(ad7606_8_info, IIO_AD7606); const struct ad7606_chip_info ad7606_6_info = { .channels = ad7606_channels_16bit, .name = "ad7606-6", + .num_adc_channels = 6, .num_channels = 7, .oversampling_avail = ad7606_oversampling_avail, .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail), @@ -178,6 +181,7 @@ EXPORT_SYMBOL_NS_GPL(ad7606_6_info, IIO_AD7606); const struct ad7606_chip_info ad7606_4_info = { .channels = ad7606_channels_16bit, .name = "ad7606-4", + .num_adc_channels = 4, .num_channels = 5, .oversampling_avail = ad7606_oversampling_avail, .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail), @@ -188,6 +192,7 @@ EXPORT_SYMBOL_NS_GPL(ad7606_4_info, IIO_AD7606); const struct ad7606_chip_info ad7606b_info = { .channels = ad7606_channels_16bit, .name = "ad7606b", + .num_adc_channels = 8, .num_channels = 9, .oversampling_avail = ad7606_oversampling_avail, .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail), @@ -198,6 +203,7 @@ EXPORT_SYMBOL_NS_GPL(ad7606b_info, IIO_AD7606); const struct ad7606_chip_info ad7606c_16_info = { .channels = ad7606_channels_16bit, .name = "ad7606c16", + .num_adc_channels = 8, .num_channels = 9, .oversampling_avail = ad7606_oversampling_avail, .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail), @@ -208,6 +214,7 @@ EXPORT_SYMBOL_NS_GPL(ad7606c_16_info, IIO_AD7606); const struct ad7606_chip_info ad7606c_18_info = { .channels = ad7606_channels_18bit, .name = "ad7606c18", + .num_adc_channels = 8, .num_channels = 9, .oversampling_avail = ad7606_oversampling_avail, .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail), @@ -219,6 +226,7 @@ const struct ad7606_chip_info ad7616_info = { .channels = ad7616_channels, .init_delay_ms = 15, .name = "ad7616", + .num_adc_channels = 16, .num_channels = 17, .oversampling_avail = ad7616_oversampling_avail, .oversampling_num = ARRAY_SIZE(ad7616_oversampling_avail), @@ -528,7 +536,7 @@ static int ad7606_set_sampling_freq(struct ad7606_state *st, unsigned long freq) static int ad7606_read_samples(struct ad7606_state *st) { - unsigned int num = st->chip_info->num_channels - 1; + unsigned int num = st->chip_info->num_adc_channels; return st->bops->read_block(st->dev, num, &st->data); } diff --git a/drivers/iio/adc/ad7606.h b/drivers/iio/adc/ad7606.h index d401d3ab37e0..b26a11b2eba1 100644 --- a/drivers/iio/adc/ad7606.h +++ b/drivers/iio/adc/ad7606.h @@ -71,6 +71,7 @@ typedef int (*ad7606_scale_setup_cb_t)(struct ad7606_state *st, * @channels: channel specification * @name device name * @num_channels: number of channels + * @num_adc_channels the number of channels the ADC actually inputs. * @scale_setup_cb: callback to setup the scales for each channel * @oversampling_avail pointer to the array which stores the available * oversampling ratios. @@ -82,6 +83,7 @@ typedef int (*ad7606_scale_setup_cb_t)(struct ad7606_state *st, struct ad7606_chip_info { const struct iio_chan_spec *channels; const char *name; + unsigned int num_adc_channels; unsigned int num_channels; ad7606_scale_setup_cb_t scale_setup_cb; const unsigned int *oversampling_avail; From patchwork Fri Oct 4 21:48:44 2024 Content-Type: text/plain; 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[185.246.87.17]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42f86b4ab63sm24680375e9.40.2024.10.04.14.48.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Oct 2024 14:48:58 -0700 (PDT) From: Guillaume Stols Date: Fri, 04 Oct 2024 21:48:44 +0000 Subject: [PATCH v3 10/10] iio: adc: ad7606: Disable PWM usage for non backend version Precedence: bulk X-Mailing-List: linux-fbdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241004-ad7606_add_iio_backend_support-v3-10-38757012ce82@baylibre.com> References: <20241004-ad7606_add_iio_backend_support-v3-0-38757012ce82@baylibre.com> In-Reply-To: <20241004-ad7606_add_iio_backend_support-v3-0-38757012ce82@baylibre.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Greg Kroah-Hartman , "Rafael J. Wysocki" , Jonathan Corbet Cc: linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org, Michael Hennerich , linux-fbdev@vger.kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, aardelean@baylibre.com, dlechner@baylibre.com, Jonathan Cameron , Guillaume Stols X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1728078523; l=2322; i=gstols@baylibre.com; s=20240417; h=from:subject:message-id; bh=KILZmuz9ow44vIq//sP6mcCwlyWKYRWENjjTm5mPzG0=; b=V1//BkjB3KmevEEh7iNe+Ik1D5yorX+BR9PwVTNLgBma08CQC6efmz2xTQWL70TtsmmAjdxN8 zoDQV9i4/KCCNsoS49wGya0TBkhVp3ptAH3YD9OUUo86YOXEL5TeLem X-Developer-Key: i=gstols@baylibre.com; a=ed25519; pk=XvMm5WHuV67sGYOJZqIYzXndbaJOlNd8Q6li6vnb4Cs= Since the pwm was introduced before backend, there was a mock use, with a GPIO emulation. Now that iio backend is introduced, the mock use can be removed. Signed-off-by: Guillaume Stols --- drivers/iio/adc/ad7606.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/drivers/iio/adc/ad7606.c b/drivers/iio/adc/ad7606.c index d86eb7c3e4f7..7d02aad45242 100644 --- a/drivers/iio/adc/ad7606.c +++ b/drivers/iio/adc/ad7606.c @@ -473,8 +473,6 @@ static int ad7606_pwm_set_high(struct ad7606_state *st) cnvst_pwm_state.duty_cycle = cnvst_pwm_state.period; ret = pwm_apply_might_sleep(st->cnvst_pwm, &cnvst_pwm_state); - /* sleep 2 µS to let finish the current pulse */ - fleep(2) return ret; } @@ -492,8 +490,6 @@ static int ad7606_pwm_set_low(struct ad7606_state *st) cnvst_pwm_state.duty_cycle = 0; ret = pwm_apply_might_sleep(st->cnvst_pwm, &cnvst_pwm_state); - /* sleep 2 µS to let finish the current pulse */ - fleep(2) return ret; } @@ -576,7 +572,6 @@ static irqreturn_t ad7606_trigger_handler(int irq, void *p) iio_trigger_notify_done(indio_dev->trig); /* The rising edge of the CONVST signal starts a new conversion. */ gpiod_set_value(st->gpio_convst, 1); - ad7606_pwm_set_high(st); return IRQ_HANDLED; } @@ -900,7 +895,6 @@ static int ad7606_buffer_postenable(struct iio_dev *indio_dev) struct ad7606_state *st = iio_priv(indio_dev); gpiod_set_value(st->gpio_convst, 1); - ad7606_pwm_set_high(st); return 0; } @@ -910,7 +904,6 @@ static int ad7606_buffer_predisable(struct iio_dev *indio_dev) struct ad7606_state *st = iio_priv(indio_dev); gpiod_set_value(st->gpio_convst, 0); - ad7606_pwm_set_low(st); return 0; } @@ -1204,6 +1197,12 @@ int ad7606_probe(struct device *dev, int irq, void __iomem *base_address, indio_dev->setup_ops = &ad7606_pwm_buffer_ops; } else { init_completion(&st->completion); + + /* Reserve the PWM use only for backend (force gpio_convst definition) */ + if (!st->gpio_convst) + return dev_err_probe(dev, -EINVAL, + "No backend, connect convst to a GPIO"); + st->trig = devm_iio_trigger_alloc(dev, "%s-dev%d", indio_dev->name, iio_device_id(indio_dev));