From patchwork Fri Oct 4 21:23:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Mukesh Ojha X-Patchwork-Id: 832785 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B2E9C1B4F14; Fri, 4 Oct 2024 21:24:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728077067; cv=none; b=DooT6qsKW7sT76hy/yDFAVPCV/Lwb0aYXb7CpjA7TQwICO+LmF40YV2mlO7g/ErtGEgFYz6oIBugBX07lu1+ChpSOT90D3/FAzN6XbakAZjihMMv/Ojv1FqlpkKJHdLcNIN4/xm9D5QH5dROn66NqcQrAej1rlJXxBy3AK3Wny8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728077067; c=relaxed/simple; bh=K8QQuCcgEoB0Q/fSJMyIy/O8BgM0uWG0H4wK+BbDIfM=; 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Fri, 4 Oct 2024 21:24:21 GMT Received: from hu-mojha-hyd.qualcomm.com (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 4 Oct 2024 14:24:16 -0700 From: Mukesh Ojha To: Bjorn Andersson , Mathieu Poirier , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , "Konrad Dybcio" , Bartosz Golaszewski , Manivannan Sadhasivam CC: , , , , Shiraz Hashim , Mukesh Ojha Subject: [PATCH 1/6] dt-bindings: remoteproc: qcom,pas-common: Introduce iommus and qcom,devmem property Date: Sat, 5 Oct 2024 02:53:54 +0530 Message-ID: <20241004212359.2263502-2-quic_mojha@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241004212359.2263502-1-quic_mojha@quicinc.com> References: <20241004212359.2263502-1-quic_mojha@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: tp2FVau3JffewU54Y8bYH2Tadybq9hSw X-Proofpoint-GUID: tp2FVau3JffewU54Y8bYH2Tadybq9hSw X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 clxscore=1015 adultscore=0 lowpriorityscore=0 mlxscore=0 priorityscore=1501 phishscore=0 bulkscore=0 impostorscore=0 malwarescore=0 suspectscore=0 mlxlogscore=627 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410040148 From: Shiraz Hashim Qualcomm’s PAS implementation for remote processors only supports a single stage of IOMMU translation and is presently managed by the Qualcomm EL2 hypervisor (QHEE) if it is present. In the absence of QHEE, such as with a KVM hypervisor, IOMMU translations need to be set up by the KVM host. Remoteproc needs carveout memory region and its resource (device memory) permissions to be set before it comes up, and this information is presently available statically with QHEE. In the absence of QHEE, the boot firmware needs to overlay this information based on SoCs running with either QHEE or a KVM hypervisor (CPUs booted in EL2). The qcom,devmem property provides IOMMU devmem translation information intended for non-QHEE based systems. Signed-off-by: Shiraz Hashim Co-Developed-by: Mukesh Ojha Signed-off-by: Mukesh Ojha --- .../bindings/remoteproc/qcom,pas-common.yaml | 42 +++++++++++++++++++ .../bindings/remoteproc/qcom,sa8775p-pas.yaml | 20 +++++++++ 2 files changed, 62 insertions(+) diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,pas-common.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,pas-common.yaml index 63a82e7a8bf8..068e177ad934 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,pas-common.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,pas-common.yaml @@ -52,6 +52,48 @@ properties: minItems: 1 maxItems: 3 + iommus: + maxItems: 1 + + qcom,devmem: + $ref: /schemas/types.yaml#/definitions/uint32-matrix + description: + Qualcomm’s PAS implementation for remote processors only supports a + single stage of IOMMU translation and is presently managed by the + Qualcomm EL2 hypervisor (QHEE) if it is present. In the absence of QHEE, + such as with a KVM hypervisor, IOMMU translations need to be set up by + the KVM host. Remoteproc might need some device resources and related + access permissions to be set before it comes up, and this information is + presently available statically with QHEE. + + In the absence of QHEE, the boot firmware needs to overlay this + information based on SoCs running with either QHEE or a KVM hypervisor + (CPUs booted in EL2). + + The qcom,devmem property provides IOMMU devmem translation information + intended for non-QHEE based systems. It is an array of u32 values + describing the device memory regions for which IOMMU translations need to + be set up before bringing up Remoteproc. This array consists of 4-tuples + defining the device address, physical address, size, and attribute flags + with which it has to be mapped. + + remoteproc@3000000 { + ... + + qcom,devmem = <0x82000 0x82000 0x2000 0x3>, + <0x92000 0x92000 0x1000 0x1>; + } + + items: + items: + - description: device address + - description: physical address + - description: size of mapping + - description: | + iommu attributes - IOMMU_READ, IOMMU_WRITE, IOMMU_CACHE, IOMMU_NOEXEC, IOMMU_MMIO + enum: [ 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, + 25, 26, 27, 28, 29, 30, 31 ] + qcom,smem-states: $ref: /schemas/types.yaml#/definitions/phandle-array description: States used by the AP to signal the Hexagon core diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sa8775p-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sa8775p-pas.yaml index 7fe401a06805..503c5c9d8ea7 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,sa8775p-pas.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sa8775p-pas.yaml @@ -139,6 +139,26 @@ examples: power-domains = <&rpmhpd RPMHPD_LCX>, <&rpmhpd RPMHPD_LMX>; power-domain-names = "lcx", "lmx"; + iommus = <&apps_smmu 0x3000 0x0>; + qcom,devmem = <0x00110000 0x00110000 0x4000 0x1>, + <0x00123000 0x00123000 0x1000 0x3>, + <0x00124000 0x00124000 0x3000 0x3>, + <0x00127000 0x00127000 0x2000 0x3>, + <0x0012a000 0x0012a000 0x3000 0x3>, + <0x0012e000 0x0012e000 0x1000 0x3>, + <0x0012f000 0x0012f000 0x1000 0x1>, + <0x00144000 0x00144000 0x1000 0x1>, + <0x00148000 0x00148000 0x1000 0x1>, + <0x00149000 0x00149000 0xe000 0x3>, + <0x00157000 0x00157000 0x1000 0x3>, + <0x00158000 0x00158000 0xd000 0x3>, + <0x00165000 0x00165000 0x1000 0x3>, + <0x00172000 0x00172000 0x1000 0x3>, + <0x00173000 0x00173000 0x8000 0x3>, + <0x0017b000 0x0017b000 0x2000 0x3>, + <0x0017f000 0x0017f000 0x1000 0x3>, + <0x00184000 0x00184000 0x1000 0x1>; + interconnects = <&lpass_ag_noc MASTER_LPASS_PROC 0 &mc_virt SLAVE_EBI1 0>; memory-region = <&pil_adsp_mem>; From patchwork Fri Oct 4 21:23:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mukesh Ojha X-Patchwork-Id: 833045 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5F4C01B4F27; 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Fri, 04 Oct 2024 21:24:25 +0000 (GMT) Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 494LOP1F028680 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 4 Oct 2024 21:24:25 GMT Received: from hu-mojha-hyd.qualcomm.com (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 4 Oct 2024 14:24:21 -0700 From: Mukesh Ojha To: Bjorn Andersson , Mathieu Poirier , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , "Konrad Dybcio" , Bartosz Golaszewski , Manivannan Sadhasivam CC: , , , , Komal Bajaj , Mukesh Ojha Subject: [PATCH 2/6] remoteproc: qcom: Add iommu map_unmap helper function Date: Sat, 5 Oct 2024 02:53:55 +0530 Message-ID: <20241004212359.2263502-3-quic_mojha@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241004212359.2263502-1-quic_mojha@quicinc.com> References: <20241004212359.2263502-1-quic_mojha@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: fq1HxFWB7AG4tAYwhcz0oTNOsr-ivfCX X-Proofpoint-GUID: fq1HxFWB7AG4tAYwhcz0oTNOsr-ivfCX X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 clxscore=1015 adultscore=0 lowpriorityscore=0 mlxscore=0 priorityscore=1501 phishscore=0 bulkscore=0 impostorscore=0 malwarescore=0 suspectscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410040148 From: Komal Bajaj Qualcomm remote processor's IOMMU translation running on Linux KVM host should be managed by PAS driver and to do this PAS driver need to do map and unmap remoteproc carveout memory region. Similar map and unmap private functions for the similar purpose are already available in qcom_q6v5_adsp.c. So, in motivation to reuse code, introduce common exported functions like qcom_map_unmap_carveout() such that it can be used by both qcom_q6v5_adsp and qcom_q6v5_pas. Signed-off-by: Komal Bajaj Co-Developed-by: Mukesh Ojha Signed-off-by: Mukesh Ojha --- drivers/remoteproc/qcom_common.c | 52 ++++++++++++++++++++++++++++++++ drivers/remoteproc/qcom_common.h | 3 ++ 2 files changed, 55 insertions(+) diff --git a/drivers/remoteproc/qcom_common.c b/drivers/remoteproc/qcom_common.c index 8c8688f99f0a..1c7887dc65b4 100644 --- a/drivers/remoteproc/qcom_common.c +++ b/drivers/remoteproc/qcom_common.c @@ -8,6 +8,7 @@ */ #include +#include #include #include #include @@ -35,6 +36,8 @@ #define MINIDUMP_SS_ENCR_DONE ('D' << 24 | 'O' << 16 | 'N' << 8 | 'E' << 0) #define MINIDUMP_SS_ENABLED ('E' << 24 | 'N' << 16 | 'B' << 8 | 'L' << 0) +#define SID_MASK_DEFAULT 0xfUL + /** * struct minidump_region - Minidump region * @name : Name of the region to be dumped @@ -606,5 +609,54 @@ void qcom_remove_pdm_subdev(struct rproc *rproc, struct qcom_rproc_pdm *pdm) } EXPORT_SYMBOL_GPL(qcom_remove_pdm_subdev); +/** + * qcom_map_unmap_carveout() - iommu map and unmap carveout region + * + * @rproc: rproc handle + * @mem_phys: starting physical address of carveout region + * @mem_size: size of carveout region + * @map: if true, map otherwise, unmap + * @use_sid: decision to append sid to iova + * @sid: SID value + */ +int qcom_map_unmap_carveout(struct rproc *rproc, phys_addr_t mem_phys, size_t mem_size, + bool map, bool use_sid, unsigned long sid) +{ + unsigned long iova = mem_phys; + unsigned long sid_def_val; + int ret; + + if (!rproc->has_iommu) + return 0; + + if (!rproc->domain) + return -EINVAL; + + /* + * Remote processor like ADSP supports upto 36 bit device + * address space and some of its clients like fastrpc uses + * upper 32-35 bits to keep lower 4 bits of its SID to use + * larger address space. To keep this consistent across other + * use cases add remoteproc SID configuration for firmware + * to IOMMU for carveouts. + */ + if (use_sid && sid) { + sid_def_val = sid & SID_MASK_DEFAULT; + iova |= (sid_def_val << 32); + } + + if (map) + ret = iommu_map(rproc->domain, iova, mem_phys, mem_size, IOMMU_READ | IOMMU_WRITE, GFP_KERNEL); + else + ret = iommu_unmap(rproc->domain, iova, mem_size); + + if (ret) + dev_err(&rproc->dev, "Unable to %s IOVA Memory, ret: %d\n", + map ? "map" : "unmap", ret); + + return ret; +} +EXPORT_SYMBOL_GPL(qcom_map_unmap_carveout); + MODULE_DESCRIPTION("Qualcomm Remoteproc helper driver"); MODULE_LICENSE("GPL v2"); diff --git a/drivers/remoteproc/qcom_common.h b/drivers/remoteproc/qcom_common.h index b07fbaa091a0..bbc41054e1ea 100644 --- a/drivers/remoteproc/qcom_common.h +++ b/drivers/remoteproc/qcom_common.h @@ -59,6 +59,9 @@ void qcom_add_ssr_subdev(struct rproc *rproc, struct qcom_rproc_ssr *ssr, const char *ssr_name); void qcom_remove_ssr_subdev(struct rproc *rproc, struct qcom_rproc_ssr *ssr); +int qcom_map_unmap_carveout(struct rproc *rproc, phys_addr_t mem_phys, size_t mem_size, + bool map, bool use_sid, unsigned long sid); + void qcom_add_pdm_subdev(struct rproc *rproc, struct qcom_rproc_pdm *pdm); void qcom_remove_pdm_subdev(struct rproc *rproc, struct qcom_rproc_pdm *pdm); From patchwork Fri Oct 4 21:23:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mukesh Ojha X-Patchwork-Id: 832784 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9B8561C876D; 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Fri, 04 Oct 2024 21:24:30 +0000 (GMT) Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 494LOTTh028848 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 4 Oct 2024 21:24:29 GMT Received: from hu-mojha-hyd.qualcomm.com (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 4 Oct 2024 14:24:25 -0700 From: Mukesh Ojha To: Bjorn Andersson , Mathieu Poirier , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , "Konrad Dybcio" , Bartosz Golaszewski , Manivannan Sadhasivam CC: , , , , Shiraz Hashim , Mukesh Ojha Subject: [PATCH 3/6] remoteproc: qcom: Add helper function to support IOMMU devmem translation Date: Sat, 5 Oct 2024 02:53:56 +0530 Message-ID: <20241004212359.2263502-4-quic_mojha@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241004212359.2263502-1-quic_mojha@quicinc.com> References: <20241004212359.2263502-1-quic_mojha@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: rEJPNYJazC8d2KQD9hj8ViYb6dLxOmA- X-Proofpoint-ORIG-GUID: rEJPNYJazC8d2KQD9hj8ViYb6dLxOmA- X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 mlxlogscore=999 priorityscore=1501 phishscore=0 bulkscore=0 impostorscore=0 clxscore=1015 lowpriorityscore=0 spamscore=0 mlxscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410040148 From: Shiraz Hashim Qualcomm SoCs runnning with Qualcomm EL2 hypervisor(QHEE), IOMMU translation set up for remote processors is managed by QHEE itself however, for a case when these remote processors has to run under KVM hypervisor, IOMMU translation need to setup from Linux remoteproc driver before it is brought up. Add qcom_devmem_info and qcom_devmem_table data structure and make a common helper functions which caller can call if these translation need to be taken care by the driver to enable iommu devmem access for remoteproc processors. Signed-off-by: Shiraz Hashim Co-developed-by: Mukesh Ojha Signed-off-by: Mukesh Ojha --- drivers/remoteproc/qcom_common.c | 96 ++++++++++++++++++++++++++++++++ drivers/remoteproc/qcom_common.h | 35 ++++++++++++ 2 files changed, 131 insertions(+) diff --git a/drivers/remoteproc/qcom_common.c b/drivers/remoteproc/qcom_common.c index 1c7887dc65b4..644920972b58 100644 --- a/drivers/remoteproc/qcom_common.c +++ b/drivers/remoteproc/qcom_common.c @@ -658,5 +658,101 @@ int qcom_map_unmap_carveout(struct rproc *rproc, phys_addr_t mem_phys, size_t me } EXPORT_SYMBOL_GPL(qcom_map_unmap_carveout); +/** + * qcom_map_devmem() - Map the device memories needed by Remoteproc using IOMMU + * + * When Qualcomm EL2 hypervisor(QHEE) present, device memories needed for remoteproc + * processors is managed by it and Linux remoteproc drivers should not call + * this and its respective unmap function in such scenario. This function + * should only be called if remoteproc IOMMU translation need to be managed + * from Linux side. + * + * @rproc: rproc handle + * @devmem_table: list of devmem regions to map + * @use_sid: decision to append sid to iova + * @sid: SID value + */ +int qcom_map_devmem(struct rproc *rproc, struct qcom_devmem_table *devmem_table, + bool use_sid, unsigned long sid) +{ + struct qcom_devmem_info *info; + unsigned long sid_def_val; + int ret; + int i; + + if (!rproc->has_iommu) + return 0; + + if (!rproc->domain) + return -EINVAL; + + /* remoteproc may not have devmem data */ + if (!devmem_table) + return 0; + + if (use_sid && sid) + sid_def_val = sid & SID_MASK_DEFAULT; + + info = &devmem_table->entries[0]; + for (i = 0; i < devmem_table->num_entries; i++, info++) { + /* + * Remote processor like ADSP supports upto 36 bit device + * address space and some of its clients like fastrpc uses + * upper 32-35 bits to keep lower 4 bits of its SID to use + * larger address space. To keep this consistent across other + * use cases add remoteproc SID configuration for firmware + * to IOMMU for carveouts. + */ + if (use_sid) + info->da |= (sid_def_val << 32); + + ret = iommu_map(rproc->domain, info->da, info->pa, info->len, info->flags, GFP_KERNEL); + if (ret) { + dev_err(&rproc->dev, "Unable to map devmem, ret: %d\n", ret); + if (use_sid) + info->da &= ~(SID_MASK_DEFAULT << 32); + goto undo_mapping; + } + } + + return 0; + +undo_mapping: + for (i = i - 1; i >= 0; i--, info--) { + iommu_unmap(rproc->domain, info->da, info->len); + if (use_sid) + info->da &= ~(SID_MASK_DEFAULT << 32); + } + + return ret; +} +EXPORT_SYMBOL_GPL(qcom_map_devmem); + +/** + * qcom_unmap_devmem() - unmap the device memories needed by Remoteproc using IOMMU + * + * @rproc: rproc handle + * @devmem_table: list of devmem regions to unmap + * @use_sid: decision to append sid to iova + */ +void qcom_unmap_devmem(struct rproc *rproc, struct qcom_devmem_table *devmem_table, bool use_sid) +{ + struct qcom_devmem_info *info; + int i; + + if (!rproc->has_iommu || !rproc->domain || !devmem_table) + return; + + info = &devmem_table->entries[0]; + for (i = 0; i < devmem_table->num_entries; i++, info++) { + iommu_unmap(rproc->domain, info->da, info->len); + if (use_sid) + info->da &= ~(SID_MASK_DEFAULT << 32); + } + + return; +} +EXPORT_SYMBOL_GPL(qcom_unmap_devmem); + MODULE_DESCRIPTION("Qualcomm Remoteproc helper driver"); MODULE_LICENSE("GPL v2"); diff --git a/drivers/remoteproc/qcom_common.h b/drivers/remoteproc/qcom_common.h index bbc41054e1ea..bbc684e1df01 100644 --- a/drivers/remoteproc/qcom_common.h +++ b/drivers/remoteproc/qcom_common.h @@ -41,6 +41,36 @@ struct qcom_rproc_pdm { struct auxiliary_device *adev; }; +/** + * struct qcom_devmem_info - iommu devmem region + * @da: device address + * @pa: physical address + * @len: length (in bytes) + * @flags: iommu protection flags + * + * The resource entry carries the device address to which a physical address is + * to be mapped with required permissions in flag. The pa, len is expected to + * be a physically contiguous memory region. + */ +struct qcom_devmem_info { + u64 da; + u64 pa; + u32 len; + u32 flags; +}; + +/** + * struct qcom_devmem_table - iommu devmem entries + * @num_entries: number of devmem entries + * @entries: devmem entries + * + * The table that carries each devmem resource entry. + */ +struct qcom_devmem_table { + int num_entries; + struct qcom_devmem_info entries[0]; +}; + void qcom_minidump(struct rproc *rproc, unsigned int minidump_id, void (*rproc_dumpfn_t)(struct rproc *rproc, struct rproc_dump_segment *segment, void *dest, size_t offset, @@ -65,6 +95,11 @@ int qcom_map_unmap_carveout(struct rproc *rproc, phys_addr_t mem_phys, size_t me void qcom_add_pdm_subdev(struct rproc *rproc, struct qcom_rproc_pdm *pdm); void qcom_remove_pdm_subdev(struct rproc *rproc, struct qcom_rproc_pdm *pdm); +int qcom_map_devmem(struct rproc *rproc, struct qcom_devmem_table *table, + bool use_sid, unsigned long sid); +void qcom_unmap_devmem(struct rproc *rproc, struct qcom_devmem_table *table, + bool use_sid); + #if IS_ENABLED(CONFIG_QCOM_SYSMON) struct qcom_sysmon *qcom_add_sysmon_subdev(struct rproc *rproc, const char *name, From patchwork Fri Oct 4 21:23:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mukesh Ojha X-Patchwork-Id: 833044 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 27FCD1D89EE; Fri, 4 Oct 2024 21:24:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728077078; cv=none; b=hpw1qG9Jo13/A+xPFN+dT7jP8WhjsmYMP0xyZc2sBKpyD1X4BEdmcXhXGawCWxQ6mpgHUUK2R2EPY6wlOyzO9EKbS8hRW0lsJg4ey5K9c5YaueBE2pdYpNU8zKfs3lhXbwZZucFvntOhH6sa1UNwT6VmvHv6OgoBeNrb+iO5KmQ= ARC-Message-Signature: i=1; a=rsa-sha256; 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Fri, 4 Oct 2024 21:24:33 GMT Received: from hu-mojha-hyd.qualcomm.com (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 4 Oct 2024 14:24:29 -0700 From: Mukesh Ojha To: Bjorn Andersson , Mathieu Poirier , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , "Konrad Dybcio" , Bartosz Golaszewski , Manivannan Sadhasivam CC: , , , , Shiraz Hashim , Mukesh Ojha Subject: [PATCH 4/6] remoteproc: qcom: Add support to parse qcom,devmem property Date: Sat, 5 Oct 2024 02:53:57 +0530 Message-ID: <20241004212359.2263502-5-quic_mojha@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241004212359.2263502-1-quic_mojha@quicinc.com> References: <20241004212359.2263502-1-quic_mojha@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: X-U1aWEMgeaLRZT-cdi_3nhg9i6jfHUs X-Proofpoint-ORIG-GUID: X-U1aWEMgeaLRZT-cdi_3nhg9i6jfHUs X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 mlxlogscore=999 priorityscore=1501 phishscore=0 bulkscore=0 impostorscore=0 clxscore=1015 lowpriorityscore=0 spamscore=0 mlxscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410040148 From: Shiraz Hashim Qualcomm remote processors firmware does not contain resource table data where devmem setting information should actually be present and for its SoC running with Qualcomm EL2 hypervisor(QHEE), IOMMU translation for remoteproc is managed by QHEE and it has all the IOMMU resource information available to it to apply the settings however, when the same SoCs run with KVM hypervisor these translation needs to setup by remoteproc PAS driver and required setting information is being overlaid from boot firmware to remoteproc device tree node. Add helper function which parses qcom,devmem information. Signed-off-by: Shiraz Hashim Co-developed-by: Mukesh Ojha Signed-off-by: Mukesh Ojha --- drivers/remoteproc/qcom_q6v5_pas.c | 55 ++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/drivers/remoteproc/qcom_q6v5_pas.c b/drivers/remoteproc/qcom_q6v5_pas.c index ef82835e98a4..bdb071ab5938 100644 --- a/drivers/remoteproc/qcom_q6v5_pas.c +++ b/drivers/remoteproc/qcom_q6v5_pas.c @@ -34,6 +34,7 @@ #define ADSP_DECRYPT_SHUTDOWN_DELAY_MS 100 #define MAX_ASSIGN_COUNT 3 +#define DEVMEM_ENTRY_SIZE 4 struct adsp_data { int crash_reason_smem; @@ -117,6 +118,8 @@ struct qcom_adsp { struct qcom_scm_pas_metadata pas_metadata; struct qcom_scm_pas_metadata dtb_pas_metadata; + + struct qcom_devmem_table *devmem; }; static void adsp_segment_dump(struct rproc *rproc, struct rproc_dump_segment *segment, @@ -683,6 +686,58 @@ static void adsp_unassign_memory_region(struct qcom_adsp *adsp) } } +static int adsp_devmem_init(struct qcom_adsp *adsp) +{ + unsigned int entry_size = DEVMEM_ENTRY_SIZE; + struct qcom_devmem_table *devmem_table; + struct rproc *rproc = adsp->rproc; + struct device *dev = adsp->dev; + struct qcom_devmem_info *info; + char *pname = "qcom,devmem"; + size_t table_size; + int num_entries; + u32 i; + + if (!rproc->has_iommu) + return 0; + + /* devmem property is a set of n-tuple */ + num_entries = of_property_count_u32_elems(dev->of_node, pname); + if (num_entries < 0) { + dev_err(adsp->dev, "No '%s' property present\n", pname); + return num_entries; + } + + if (!num_entries || (num_entries % entry_size)) { + dev_err(adsp->dev, "All '%s' list entries need %d vals\n", pname, + entry_size); + return -EINVAL; + } + + num_entries /= entry_size; + table_size = sizeof(*devmem_table) + sizeof(*info) * num_entries; + devmem_table = devm_kzalloc(dev, table_size, GFP_KERNEL); + if (!devmem_table) + return -ENOMEM; + + devmem_table->num_entries = num_entries; + info = &devmem_table->entries[0]; + for (i = 0; i < num_entries; i++, info++) { + of_property_read_u32_index(dev->of_node, pname, + i * entry_size, (u32 *)&info->da); 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Fri, 04 Oct 2024 21:24:38 +0000 (GMT) Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 494LOb7a007294 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 4 Oct 2024 21:24:37 GMT Received: from hu-mojha-hyd.qualcomm.com (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 4 Oct 2024 14:24:33 -0700 From: Mukesh Ojha To: Bjorn Andersson , Mathieu Poirier , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , "Konrad Dybcio" , Bartosz Golaszewski , Manivannan Sadhasivam CC: , , , , Mukesh Ojha Subject: [PATCH 5/6] remoteproc: qcom: Add support of SHM bridge to enable memory protection Date: Sat, 5 Oct 2024 02:53:58 +0530 Message-ID: <20241004212359.2263502-6-quic_mojha@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241004212359.2263502-1-quic_mojha@quicinc.com> References: <20241004212359.2263502-1-quic_mojha@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: ZWoBSKDGp8hdkpCoVnrK_PgM9lMswc_F X-Proofpoint-ORIG-GUID: ZWoBSKDGp8hdkpCoVnrK_PgM9lMswc_F X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 adultscore=0 malwarescore=0 clxscore=1015 mlxlogscore=999 phishscore=0 priorityscore=1501 impostorscore=0 lowpriorityscore=0 spamscore=0 bulkscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410040148 Qualcomm SoCs running with the Qualcomm EL2 hypervisor(QHEE) have been utilizing the Peripheral Authentication Service (PAS) from its TrustZone (TZ) firmware to securely authenticate and reset via sequence of SMC calls like qcom_scm_pas_init_image(), qcom_scm_pas_mem_setup(), and qcom_scm_pas_auth_and_reset(). Memory protection need to be enabled for both meta data memory region and remoteproc carveout memory region. For memory passed to Qualcomm TrustZone, the memory should be part of SHM bridge memory. However, when QHEE is present, PAS SMC calls are getting trapped in QHEE, which create or gets memory from SHM bridge for both meta data memory and for remoteproc carve out regions before it get passed to TZ. However, in absence of QHEE hypervisor, Linux need to create SHM bridge for both meta data in qcom_scm_pas_init_image() and for remoteproc memory before the call being made to qcom_scm_pas_auth_and_reset(). For qcom_scm_pas_init_image() call, metadata content need to be copied to the buffer allocated from SHM bridge before making the SMC call. For qcom_scm_pas_auth_and_reset(), remoteproc memory region need to be protected and for that SHM bridge need to be created. Make qcom_tzmem_init_area() and qcom_tzmem_cleanup_area() exported symbol so that it could be used to create SHM bridge for remoteproc region. Signed-off-by: Mukesh Ojha --- drivers/firmware/qcom/qcom_scm.c | 29 +++++++++++----- drivers/firmware/qcom/qcom_tzmem.c | 14 +++----- drivers/remoteproc/qcom_q6v5_pas.c | 44 ++++++++++++++++++++++++ include/linux/firmware/qcom/qcom_scm.h | 1 + include/linux/firmware/qcom/qcom_tzmem.h | 10 ++++++ 5 files changed, 80 insertions(+), 18 deletions(-) diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_scm.c index 10986cb11ec0..dafc07dc181f 100644 --- a/drivers/firmware/qcom/qcom_scm.c +++ b/drivers/firmware/qcom/qcom_scm.c @@ -591,15 +591,19 @@ int qcom_scm_pas_init_image(u32 peripheral, const void *metadata, size_t size, * data blob, so make sure it's physically contiguous, 4K aligned and * non-cachable to avoid XPU violations. * - * For PIL calls the hypervisor creates SHM Bridges for the blob - * buffers on behalf of Linux so we must not do it ourselves hence - * not using the TZMem allocator here. + * For PIL calls the hypervisor like Gunyah or older QHEE creates SHM + * Bridges for the blob buffers on behalf of Linux so we must not do it + * ourselves hence use TZMem allocator only when these hypervisors are + * not present. * * If we pass a buffer that is already part of an SHM Bridge to this * call, it will fail. */ - mdata_buf = dma_alloc_coherent(__scm->dev, size, &mdata_phys, - GFP_KERNEL); + if (ctx && ctx->shm_bridge_needed) + mdata_buf = qcom_tzmem_alloc(__scm->mempool, size, GFP_KERNEL); + else + mdata_buf = dma_alloc_coherent(__scm->dev, size, &mdata_phys, GFP_KERNEL); + if (!mdata_buf) return -ENOMEM; @@ -613,7 +617,10 @@ int qcom_scm_pas_init_image(u32 peripheral, const void *metadata, size_t size, if (ret) goto disable_clk; - desc.args[1] = mdata_phys; + if (ctx && ctx->shm_bridge_needed) + desc.args[1] = qcom_tzmem_to_phys(mdata_buf); + else + desc.args[1] = mdata_phys; ret = qcom_scm_call(__scm->dev, &desc, &res); qcom_scm_bw_disable(); @@ -625,8 +632,11 @@ int qcom_scm_pas_init_image(u32 peripheral, const void *metadata, size_t size, if (ret < 0 || !ctx) { dma_free_coherent(__scm->dev, size, mdata_buf, mdata_phys); } else if (ctx) { + if (ctx->shm_bridge_needed) + ctx->phys = qcom_tzmem_to_phys(mdata_buf); + else + ctx->phys = mdata_phys; ctx->ptr = mdata_buf; - ctx->phys = mdata_phys; ctx->size = size; } @@ -643,7 +653,10 @@ void qcom_scm_pas_metadata_release(struct qcom_scm_pas_metadata *ctx) if (!ctx->ptr) return; - dma_free_coherent(__scm->dev, ctx->size, ctx->ptr, ctx->phys); + if (ctx->shm_bridge_needed) + qcom_tzmem_free(ctx->ptr); + else + dma_free_coherent(__scm->dev, ctx->size, ctx->ptr, ctx->phys); ctx->ptr = NULL; ctx->phys = 0; diff --git a/drivers/firmware/qcom/qcom_tzmem.c b/drivers/firmware/qcom/qcom_tzmem.c index 92b365178235..66aba2fc979d 100644 --- a/drivers/firmware/qcom/qcom_tzmem.c +++ b/drivers/firmware/qcom/qcom_tzmem.c @@ -22,14 +22,6 @@ #include "qcom_tzmem.h" -struct qcom_tzmem_area { - struct list_head list; - void *vaddr; - dma_addr_t paddr; - size_t size; - void *priv; -}; - struct qcom_tzmem_pool { struct gen_pool *genpool; struct list_head areas; @@ -107,7 +99,7 @@ static int qcom_tzmem_init(void) return 0; } -static int qcom_tzmem_init_area(struct qcom_tzmem_area *area) +int qcom_tzmem_init_area(struct qcom_tzmem_area *area) { u64 pfn_and_ns_perm, ipfn_and_s_perm, size_and_flags; int ret; @@ -133,8 +125,9 @@ static int qcom_tzmem_init_area(struct qcom_tzmem_area *area) return 0; } +EXPORT_SYMBOL_GPL(qcom_tzmem_init_area); -static void qcom_tzmem_cleanup_area(struct qcom_tzmem_area *area) +void qcom_tzmem_cleanup_area(struct qcom_tzmem_area *area) { u64 *handle = area->priv; @@ -144,6 +137,7 @@ static void qcom_tzmem_cleanup_area(struct qcom_tzmem_area *area) qcom_scm_shm_bridge_delete(qcom_tzmem_dev, *handle); kfree(handle); } +EXPORT_SYMBOL_GPL(qcom_tzmem_cleanup_area); #endif /* CONFIG_QCOM_TZMEM_MODE_SHMBRIDGE */ diff --git a/drivers/remoteproc/qcom_q6v5_pas.c b/drivers/remoteproc/qcom_q6v5_pas.c index bdb071ab5938..ac339145e072 100644 --- a/drivers/remoteproc/qcom_q6v5_pas.c +++ b/drivers/remoteproc/qcom_q6v5_pas.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include #include @@ -120,6 +121,7 @@ struct qcom_adsp { struct qcom_scm_pas_metadata dtb_pas_metadata; struct qcom_devmem_table *devmem; + struct qcom_tzmem_area *tzmem; }; static void adsp_segment_dump(struct rproc *rproc, struct rproc_dump_segment *segment, @@ -262,6 +264,43 @@ static int adsp_load(struct rproc *rproc, const struct firmware *fw) return ret; } +static int adsp_create_shmbridge(struct qcom_adsp *adsp) +{ + struct qcom_tzmem_area *rproc_tzmem; + struct rproc *rproc = adsp->rproc; + int ret; + + if (!rproc->has_iommu) + return 0; + + rproc_tzmem = devm_kzalloc(adsp->dev, sizeof(*rproc_tzmem), GFP_KERNEL); + if (!rproc_tzmem) + return -ENOMEM; + + rproc_tzmem->size = PAGE_ALIGN(adsp->mem_size); + rproc_tzmem->paddr = adsp->mem_phys; + ret = qcom_tzmem_init_area(rproc_tzmem); + if (ret) { + dev_err(adsp->dev, + "failed to create shmbridge for carveout: %d\n", ret); + return ret; + } + + adsp->tzmem = rproc_tzmem; + + return ret; +} + +static void adsp_delete_shmbridge(struct qcom_adsp *adsp) +{ + struct rproc *rproc = adsp->rproc; + + if (!rproc->has_iommu) + return; + + qcom_tzmem_cleanup_area(adsp->tzmem); +} + static int adsp_start(struct rproc *rproc) { struct qcom_adsp *adsp = rproc->priv; @@ -317,6 +356,10 @@ static int adsp_start(struct rproc *rproc) qcom_pil_info_store(adsp->info_name, adsp->mem_phys, adsp->mem_size); + ret = adsp_create_shmbridge(adsp); + if (ret) + goto release_pas_metadata; + ret = qcom_scm_pas_auth_and_reset(adsp->pas_id); if (ret) { dev_err(adsp->dev, @@ -324,6 +367,7 @@ static int adsp_start(struct rproc *rproc) goto release_pas_metadata; } + adsp_delete_shmbridge(adsp); ret = qcom_q6v5_wait_for_start(&adsp->q6v5, msecs_to_jiffies(5000)); if (ret == -ETIMEDOUT) { dev_err(adsp->dev, "start timed out\n"); diff --git a/include/linux/firmware/qcom/qcom_scm.h b/include/linux/firmware/qcom/qcom_scm.h index 9f14976399ab..25243cd889bb 100644 --- a/include/linux/firmware/qcom/qcom_scm.h +++ b/include/linux/firmware/qcom/qcom_scm.h @@ -70,6 +70,7 @@ struct qcom_scm_pas_metadata { void *ptr; dma_addr_t phys; ssize_t size; + bool shm_bridge_needed; }; int qcom_scm_pas_init_image(u32 peripheral, const void *metadata, size_t size, diff --git a/include/linux/firmware/qcom/qcom_tzmem.h b/include/linux/firmware/qcom/qcom_tzmem.h index b83b63a0c049..e0a57cc8f74b 100644 --- a/include/linux/firmware/qcom/qcom_tzmem.h +++ b/include/linux/firmware/qcom/qcom_tzmem.h @@ -39,6 +39,14 @@ struct qcom_tzmem_pool_config { size_t max_size; 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Fri, 04 Oct 2024 21:24:42 +0000 (GMT) Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 494LOf7t007310 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 4 Oct 2024 21:24:41 GMT Received: from hu-mojha-hyd.qualcomm.com (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 4 Oct 2024 14:24:37 -0700 From: Mukesh Ojha To: Bjorn Andersson , Mathieu Poirier , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , "Konrad Dybcio" , Bartosz Golaszewski , Manivannan Sadhasivam CC: , , , , Mukesh Ojha Subject: [PATCH 6/6] remoteproc: qcom: Enable map/unmap and SHM bridge support Date: Sat, 5 Oct 2024 02:53:59 +0530 Message-ID: <20241004212359.2263502-7-quic_mojha@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241004212359.2263502-1-quic_mojha@quicinc.com> References: <20241004212359.2263502-1-quic_mojha@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: O33KIk_m2Wxv9CUVPkpsby8As9vkmR_E X-Proofpoint-ORIG-GUID: O33KIk_m2Wxv9CUVPkpsby8As9vkmR_E X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 mlxlogscore=999 priorityscore=1501 malwarescore=0 clxscore=1015 phishscore=0 bulkscore=0 impostorscore=0 mlxscore=0 lowpriorityscore=0 suspectscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410040148 For Qualcomm SoCs runnning with Qualcomm EL2 hypervisor(QHEE), IOMMU translation for remote processors is managed by QHEE and if the same SoC run under KVM, remoteproc carveout and devmem region should be IOMMU mapped from Linux PAS driver before remoteproc is brought up and unmapped once it is tear down and apart from this, SHM bridge also need to set up to enable memory protection on both remoteproc meta data memory as well as for the carveout region. Enable the support required to run Qualcomm remoteprocs on non-QHEE hypervisors. Signed-off-by: Mukesh Ojha --- drivers/remoteproc/qcom_q6v5_pas.c | 41 +++++++++++++++++++++++++++++- 1 file changed, 40 insertions(+), 1 deletion(-) diff --git a/drivers/remoteproc/qcom_q6v5_pas.c b/drivers/remoteproc/qcom_q6v5_pas.c index ac339145e072..13bd13f1b989 100644 --- a/drivers/remoteproc/qcom_q6v5_pas.c +++ b/drivers/remoteproc/qcom_q6v5_pas.c @@ -122,6 +122,7 @@ struct qcom_adsp { struct qcom_devmem_table *devmem; struct qcom_tzmem_area *tzmem; + unsigned long sid; }; static void adsp_segment_dump(struct rproc *rproc, struct rproc_dump_segment *segment, @@ -310,9 +311,21 @@ static int adsp_start(struct rproc *rproc) if (ret) return ret; + ret = qcom_map_unmap_carveout(rproc, adsp->mem_phys, adsp->mem_size, true, true, adsp->sid); + if (ret) { + dev_err(adsp->dev, "iommu mapping failed, ret: %d\n", ret); + goto disable_irqs; + } + + ret = qcom_map_devmem(rproc, adsp->devmem, true, adsp->sid); + if (ret) { + dev_err(adsp->dev, "devmem iommu mapping failed, ret: %d\n", ret); + goto unmap_carveout; + } + ret = adsp_pds_enable(adsp, adsp->proxy_pds, adsp->proxy_pd_count); if (ret < 0) - goto disable_irqs; + goto unmap_devmem; ret = clk_prepare_enable(adsp->xo); if (ret) @@ -400,6 +413,10 @@ static int adsp_start(struct rproc *rproc) clk_disable_unprepare(adsp->xo); disable_proxy_pds: adsp_pds_disable(adsp, adsp->proxy_pds, adsp->proxy_pd_count); +unmap_devmem: + qcom_unmap_devmem(rproc, adsp->devmem, adsp->sid); +unmap_carveout: + qcom_map_unmap_carveout(rproc, adsp->mem_phys, adsp->mem_size, false, true, adsp->sid); disable_irqs: qcom_q6v5_unprepare(&adsp->q6v5); @@ -445,6 +462,9 @@ static int adsp_stop(struct rproc *rproc) dev_err(adsp->dev, "failed to shutdown dtb: %d\n", ret); } + qcom_unmap_devmem(rproc, adsp->devmem, adsp->sid); + qcom_map_unmap_carveout(rproc, adsp->mem_phys, adsp->mem_size, false, true, adsp->sid); + handover = qcom_q6v5_unprepare(&adsp->q6v5); if (handover) qcom_pas_handover(&adsp->q6v5); @@ -844,6 +864,25 @@ static int adsp_probe(struct platform_device *pdev) } platform_set_drvdata(pdev, adsp); + if (of_property_present(pdev->dev.of_node, "iommus")) { + struct of_phandle_args args; + + ret = of_parse_phandle_with_args(pdev->dev.of_node, "iommus", "#iommu-cells", 0, &args); + if (ret < 0) + return ret; + + rproc->has_iommu = true; + adsp->sid = args.args[0]; + of_node_put(args.np); + ret = adsp_devmem_init(adsp); + if (ret) + return ret; + + adsp->pas_metadata.shm_bridge_needed = true; + } else { + rproc->has_iommu = false; + } + ret = device_init_wakeup(adsp->dev, true); if (ret) goto free_rproc;