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[84.217.220.205]) by smtp.gmail.com with ESMTPSA id 15sm4016640ljq.62.2019.11.25.06.25.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Nov 2019 06:25:31 -0800 (PST) From: Niklas Cassel To: Andy Gross , Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org, amit.kucheria@linaro.org, Jorge Ramirez-Ortiz , Niklas Cassel , Rob Herring , Mark Rutland , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 3/5] arm64: dts: qcom: qcs404: Add the clocks for APCS mux/divider Date: Mon, 25 Nov 2019 15:25:08 +0100 Message-Id: <20191125142511.681149-4-niklas.cassel@linaro.org> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191125142511.681149-1-niklas.cassel@linaro.org> References: <20191125142511.681149-1-niklas.cassel@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Jorge Ramirez-Ortiz Specify the clocks that feed the APCS mux/divider instead of using default hardcoded values in the source code. Co-developed-by: Niklas Cassel Signed-off-by: Niklas Cassel Signed-off-by: Jorge Ramirez-Ortiz Reviewed-by: Bjorn Andersson --- Changes since v1: -Swapped order of "pll" and "aux" clocks, in order to not break DT backwards compatibility. (In case no clock-names are given, "pll" still has to be the first clock). arch/arm64/boot/dts/qcom/qcs404.dtsi | 3 +++ 1 file changed, 3 insertions(+) -- 2.23.0 diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index 78065fbb3626..ee5ecf413664 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -902,6 +902,9 @@ compatible = "qcom,qcs404-apcs-apps-global", "syscon"; reg = <0x0b011000 0x1000>; #mbox-cells = <1>; + clocks = <&apcs_hfpll>, <&gcc GCC_GPLL0_AO_OUT_MAIN>; + clock-names = "pll", "aux"; + #clock-cells = <0>; }; apcs_hfpll: clock-controller@b016000 {