From patchwork Thu Oct 3 14:00:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 832395 Delivered-To: patch@linaro.org Received: by 2002:adf:8b52:0:b0:367:895a:4699 with SMTP id v18csp279010wra; Thu, 3 Oct 2024 07:03:30 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWr6kfpDl3rqGtKaHSJSswWbU0rRUEmA/ihroxWqzdcAsPfztO7fRxwCdxhAkA+mxevkFhmvQ==@linaro.org X-Google-Smtp-Source: AGHT+IE6rX+POZUC3ksEEl+40EwwYD3H5ZpBw+jyJ1yhqyK48Khrhb52DsIf1nvcfHKlB/F0uYfK X-Received: by 2002:a05:6214:5683:b0:6c5:bc40:9bdb with SMTP id 6a1803df08f44-6cb819f5fbamr102067426d6.22.1727964210301; Thu, 03 Oct 2024 07:03:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1727964210; cv=none; d=google.com; s=arc-20240605; b=JjlIBz29GEX5Tvn8yfzwfp33EviN04kyzwvgTEBxBQ4IkmuClZYbrT6m+SWAiyoKNa fJAbVTWfv9+tUa/13MClQnM8irqz0VXBYhEuJ9p6uFcMn3+cFIwIJr1a095vi54Ccdlf 3iiiwAmiFUwQT5ybWJqYszw45l5ifFQNw0RA6ARaKRAYDsa2VOi/AQ8UP871oKsS2eEO HkK7lHaXt+e2kq8aBmIteHmNiLuLGnVkSaoz0qUZaIhsnu+CvubmhsturZvKESTiQHwh 1fnKkFB3GTVxCDPewoEjfMAx4dWGsrNJN36uL0XJZ/HimRHFCUd/S3AoSn/BnLtTPAlx yR9A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=3Ok18kr1nMkw/0rVgIWp/xbgbnOWA7nawrP/P6cDv6w=; fh=Ioe1xazNVDuGg+tdavhyuIVvUTROGIifTlC4LzOQVOI=; b=MaFWwL3NE08GBSbOmgIr2s+XygRaG7OFNYk7PWQ+aWuqIpEbWU1BlZYmW6OG7hq0eK 2PT64ksddM4lpZaALx8Av/Dz3rM2vX6su4cev94ACwd35d/9434MyYUTYmocExbud+Dt VQQPkAeAXEEQYr+9qjkWdDN64NwighxHzSnrCJ4++sN4hwWlhJ5x48/EDb3Ukhtc7WXe 9KiPOzCyN+O4gV3VgK6K6ay15pFbkeGYarhwH6k2T15wg6f20OD+NeQYwnX5kGpo7BmB 7qqA7iFP9YUohiTwbP1F+mp+SvzbL+pla70A0ihV+cjbjm/S35S2lkl2Ga7L9YJWM7GA VFaQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vH6qJZMe; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 6a1803df08f44-6cb9384364esi13726146d6.479.2024.10.03.07.03.30 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 03 Oct 2024 07:03:30 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vH6qJZMe; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1swMNx-00049x-30; Thu, 03 Oct 2024 10:00:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1swMNQ-00046y-Jy for qemu-devel@nongnu.org; Thu, 03 Oct 2024 10:00:25 -0400 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1swMNL-0002qk-1i for qemu-devel@nongnu.org; Thu, 03 Oct 2024 10:00:18 -0400 Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-42f6bec84b5so9845375e9.1 for ; Thu, 03 Oct 2024 07:00:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1727964013; x=1728568813; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3Ok18kr1nMkw/0rVgIWp/xbgbnOWA7nawrP/P6cDv6w=; b=vH6qJZMeRpJFQuMCeeRbLN8k6DyA/WzBHZ4ffLRirgJrD8cnEfT9wLUklfaQFOXohA n5rvrJ6+oKX+VEF/x7J17Q+Qe58X9lFmo3j6V9bFfYa+czvJFm+qTDC/QxfnL8cwpoRF wmBR57pc47okkcCGXImzQNBHxhZSZROeLYx3c5FJ1F/XcBMUm6Yvk+W79WgbohwkMEMk vsfAnZg3fCHTKmMcpEAe7MP4FBDS5ads/fQDOoTRHwWfM7N/VN6QtnKzHkZ9vS5WRd8E zbOREtCZMPVBHF1X237dFgJlSx/077xRcGhw1wsLmFvRUKq1W3EAiirLjyLfQzXTIl/R z9jA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1727964013; x=1728568813; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3Ok18kr1nMkw/0rVgIWp/xbgbnOWA7nawrP/P6cDv6w=; b=iSzz6pLOXMLqYd663NRjYLPLy/VpA/VlY6SVkC78V0E0PhkMT58lNN2H3yVqXIqyfA brp9J9xANgIC45xi7YqOfEMLfbRHzA/BrRtzr28vLOgMoPg9QW4kWIZguVrLgzjaIP0F DmIPyaVAw42Qm3BUoI7LNIVgWAS33Zt3AhpR57rZRcU523fADkC6LAFxmnBUAmmHlQ9T EjT4ygw47xRMC6wN8M0cjjulXpIWRUKB46v362howEJy/gCL/Cj/VM5f3F7wl5szuFFN sfRqlD/Pz/hYzzxA4Jart3zNcGwfSuqIsPd7fvOXri65erMEyf9Pc+1wh1uSwzXi9Mys bQlg== X-Forwarded-Encrypted: i=1; AJvYcCUVn+Z8S6JJvhd7jjuHCOT404xWgOK/BIA8amDKCAVwxLvgqpGlI8Lmb+kLYgDF1drC4qz0vBh4kJxM@nongnu.org X-Gm-Message-State: AOJu0YzWQJIOOAQc8VzmPJ/6KP+JEVRGFaox7RS3/7cwGKUZpqo5n5Sp nHz4MN/9sFJgCD270yLojv/ym+QRnp/UkCx9VFo0UXN9j0VOS1DIyTlXPyQ3Z/Q0duRsYv/spLD M X-Received: by 2002:adf:e643:0:b0:374:c847:852 with SMTP id ffacd0b85a97d-37cfb9d024cmr4686638f8f.29.1727964012887; Thu, 03 Oct 2024 07:00:12 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37d0822bc38sm1340255f8f.45.2024.10.03.07.00.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Oct 2024 07:00:12 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Guenter Roeck , Paolo Bonzini Subject: [PATCH v2 1/6] hw/adc: Remove MAX111X device Date: Thu, 3 Oct 2024 15:00:05 +0100 Message-Id: <20241003140010.1653808-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241003140010.1653808-1-peter.maydell@linaro.org> References: <20241003140010.1653808-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The MAX111X ADC device was used only by the XScale-based Zaurus machine types. Now they have all been removed, we can drop this device model too. Because this device is an SSI device, in theory it could be created by users on the command line for boards with a different SSI controller, but we don't believe users are doing this -- it would be impossible on the command line to connect up the GPIO inputs which correspond to ADC inputs, or the GPIO output which is an interrupt line. The only example a web search produces for "device max1111" or "device max1110" is our own bug report https://gitlab.com/qemu-project/qemu/-/issues/2228 where it's used as an example of a bogus command that causes an assertion in an aspeed machine type that wasn't expecting anything other than flash devices on its SMC bus. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé --- include/hw/adc/max111x.h | 56 ---------- hw/adc/max111x.c | 236 --------------------------------------- hw/adc/Kconfig | 3 - hw/adc/meson.build | 1 - 4 files changed, 296 deletions(-) delete mode 100644 include/hw/adc/max111x.h delete mode 100644 hw/adc/max111x.c diff --git a/include/hw/adc/max111x.h b/include/hw/adc/max111x.h deleted file mode 100644 index beff59c815d..00000000000 --- a/include/hw/adc/max111x.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * Maxim MAX1110/1111 ADC chip emulation. - * - * Copyright (c) 2006 Openedhand Ltd. - * Written by Andrzej Zaborowski - * - * This code is licensed under the GNU GPLv2. - * - * Contributions after 2012-01-13 are licensed under the terms of the - * GNU GPL, version 2 or (at your option) any later version. - */ - -#ifndef HW_MISC_MAX111X_H -#define HW_MISC_MAX111X_H - -#include "hw/ssi/ssi.h" -#include "qom/object.h" - -/* - * This is a model of the Maxim MAX1110/1111 ADC chip, which for QEMU - * is an SSI slave device. It has either 4 (max1110) or 8 (max1111) - * 8-bit ADC channels. - * - * QEMU interface: - * + GPIO inputs 0..3 (for max1110) or 0..7 (for max1111): set the value - * of each ADC input, as an unsigned 8-bit value - * + GPIO output 0: interrupt line - * + Properties "input0" to "input3" (max1110) or "input0" to "input7" - * (max1111): initial reset values for ADC inputs. - * - * Known bugs: - * + the interrupt line is not correctly implemented, and will never - * be lowered once it has been asserted. - */ -struct MAX111xState { - SSIPeripheral parent_obj; - - qemu_irq interrupt; - /* Values of inputs at system reset (settable by QOM property) */ - uint8_t reset_input[8]; - - uint8_t tb1, rb2, rb3; - int cycle; - - uint8_t input[8]; - int inputs, com; -}; - -#define TYPE_MAX_111X "max111x" - -OBJECT_DECLARE_SIMPLE_TYPE(MAX111xState, MAX_111X) - -#define TYPE_MAX_1110 "max1110" -#define TYPE_MAX_1111 "max1111" - -#endif diff --git a/hw/adc/max111x.c b/hw/adc/max111x.c deleted file mode 100644 index aa51e47245d..00000000000 --- a/hw/adc/max111x.c +++ /dev/null @@ -1,236 +0,0 @@ -/* - * Maxim MAX1110/1111 ADC chip emulation. - * - * Copyright (c) 2006 Openedhand Ltd. - * Written by Andrzej Zaborowski - * - * This code is licensed under the GNU GPLv2. - * - * Contributions after 2012-01-13 are licensed under the terms of the - * GNU GPL, version 2 or (at your option) any later version. - */ - -#include "qemu/osdep.h" -#include "hw/adc/max111x.h" -#include "hw/irq.h" -#include "migration/vmstate.h" -#include "qemu/module.h" -#include "hw/qdev-properties.h" - -/* Control-byte bitfields */ -#define CB_PD0 (1 << 0) -#define CB_PD1 (1 << 1) -#define CB_SGL (1 << 2) -#define CB_UNI (1 << 3) -#define CB_SEL0 (1 << 4) -#define CB_SEL1 (1 << 5) -#define CB_SEL2 (1 << 6) -#define CB_START (1 << 7) - -#define CHANNEL_NUM(v, b0, b1, b2) \ - ((((v) >> (2 + (b0))) & 4) | \ - (((v) >> (3 + (b1))) & 2) | \ - (((v) >> (4 + (b2))) & 1)) - -static uint32_t max111x_read(MAX111xState *s) -{ - if (!s->tb1) - return 0; - - switch (s->cycle ++) { - case 1: - return s->rb2; - case 2: - return s->rb3; - } - - return 0; -} - -/* Interpret a control-byte */ -static void max111x_write(MAX111xState *s, uint32_t value) -{ - int measure, chan; - - /* Ignore the value if START bit is zero */ - if (!(value & CB_START)) - return; - - s->cycle = 0; - - if (!(value & CB_PD1)) { - s->tb1 = 0; - return; - } - - s->tb1 = value; - - if (s->inputs == 8) - chan = CHANNEL_NUM(value, 1, 0, 2); - else - chan = CHANNEL_NUM(value & ~CB_SEL0, 0, 1, 2); - - if (value & CB_SGL) - measure = s->input[chan] - s->com; - else - measure = s->input[chan] - s->input[chan ^ 1]; - - if (!(value & CB_UNI)) - measure ^= 0x80; - - s->rb2 = (measure >> 2) & 0x3f; - s->rb3 = (measure << 6) & 0xc0; - - /* FIXME: When should the IRQ be lowered? */ - qemu_irq_raise(s->interrupt); -} - -static uint32_t max111x_transfer(SSIPeripheral *dev, uint32_t value) -{ - MAX111xState *s = MAX_111X(dev); - max111x_write(s, value); - return max111x_read(s); -} - -static const VMStateDescription vmstate_max111x = { - .name = "max111x", - .version_id = 1, - .minimum_version_id = 1, - .fields = (const VMStateField[]) { - VMSTATE_SSI_PERIPHERAL(parent_obj, MAX111xState), - VMSTATE_UINT8(tb1, MAX111xState), - VMSTATE_UINT8(rb2, MAX111xState), - VMSTATE_UINT8(rb3, MAX111xState), - VMSTATE_INT32_EQUAL(inputs, MAX111xState, NULL), - VMSTATE_INT32(com, MAX111xState), - VMSTATE_ARRAY_INT32_UNSAFE(input, MAX111xState, inputs, - vmstate_info_uint8, uint8_t), - VMSTATE_END_OF_LIST() - } -}; - -static void max111x_input_set(void *opaque, int line, int value) -{ - MAX111xState *s = MAX_111X(opaque); - - assert(line >= 0 && line < s->inputs); - s->input[line] = value; -} - -static int max111x_init(SSIPeripheral *d, int inputs) -{ - DeviceState *dev = DEVICE(d); - MAX111xState *s = MAX_111X(dev); - - qdev_init_gpio_out(dev, &s->interrupt, 1); - qdev_init_gpio_in(dev, max111x_input_set, inputs); - - s->inputs = inputs; - - return 0; -} - -static void max1110_realize(SSIPeripheral *dev, Error **errp) -{ - max111x_init(dev, 8); -} - -static void max1111_realize(SSIPeripheral *dev, Error **errp) -{ - max111x_init(dev, 4); -} - -static void max111x_reset(DeviceState *dev) -{ - MAX111xState *s = MAX_111X(dev); - int i; - - for (i = 0; i < s->inputs; i++) { - s->input[i] = s->reset_input[i]; - } - s->com = 0; - s->tb1 = 0; - s->rb2 = 0; - s->rb3 = 0; - s->cycle = 0; -} - -static Property max1110_properties[] = { - /* Reset values for ADC inputs */ - DEFINE_PROP_UINT8("input0", MAX111xState, reset_input[0], 0xf0), - DEFINE_PROP_UINT8("input1", MAX111xState, reset_input[1], 0xe0), - DEFINE_PROP_UINT8("input2", MAX111xState, reset_input[2], 0xd0), - DEFINE_PROP_UINT8("input3", MAX111xState, reset_input[3], 0xc0), - DEFINE_PROP_END_OF_LIST(), -}; - -static Property max1111_properties[] = { - /* Reset values for ADC inputs */ - DEFINE_PROP_UINT8("input0", MAX111xState, reset_input[0], 0xf0), - DEFINE_PROP_UINT8("input1", MAX111xState, reset_input[1], 0xe0), - DEFINE_PROP_UINT8("input2", MAX111xState, reset_input[2], 0xd0), - DEFINE_PROP_UINT8("input3", MAX111xState, reset_input[3], 0xc0), - DEFINE_PROP_UINT8("input4", MAX111xState, reset_input[4], 0xb0), - DEFINE_PROP_UINT8("input5", MAX111xState, reset_input[5], 0xa0), - DEFINE_PROP_UINT8("input6", MAX111xState, reset_input[6], 0x90), - DEFINE_PROP_UINT8("input7", MAX111xState, reset_input[7], 0x80), - DEFINE_PROP_END_OF_LIST(), -}; - -static void max111x_class_init(ObjectClass *klass, void *data) -{ - SSIPeripheralClass *k = SSI_PERIPHERAL_CLASS(klass); - DeviceClass *dc = DEVICE_CLASS(klass); - - k->transfer = max111x_transfer; - device_class_set_legacy_reset(dc, max111x_reset); - dc->vmsd = &vmstate_max111x; - set_bit(DEVICE_CATEGORY_MISC, dc->categories); -} - -static const TypeInfo max111x_info = { - .name = TYPE_MAX_111X, - .parent = TYPE_SSI_PERIPHERAL, - .instance_size = sizeof(MAX111xState), - .class_init = max111x_class_init, - .abstract = true, -}; - -static void max1110_class_init(ObjectClass *klass, void *data) -{ - SSIPeripheralClass *k = SSI_PERIPHERAL_CLASS(klass); - DeviceClass *dc = DEVICE_CLASS(klass); - - k->realize = max1110_realize; - device_class_set_props(dc, max1110_properties); -} - -static const TypeInfo max1110_info = { - .name = TYPE_MAX_1110, - .parent = TYPE_MAX_111X, - .class_init = max1110_class_init, -}; - -static void max1111_class_init(ObjectClass *klass, void *data) -{ - SSIPeripheralClass *k = SSI_PERIPHERAL_CLASS(klass); - DeviceClass *dc = DEVICE_CLASS(klass); - - k->realize = max1111_realize; - device_class_set_props(dc, max1111_properties); -} - -static const TypeInfo max1111_info = { - .name = TYPE_MAX_1111, - .parent = TYPE_MAX_111X, - .class_init = max1111_class_init, -}; - -static void max111x_register_types(void) -{ - type_register_static(&max111x_info); - type_register_static(&max1110_info); - type_register_static(&max1111_info); -} - -type_init(max111x_register_types) diff --git a/hw/adc/Kconfig b/hw/adc/Kconfig index a825bd3d343..25d2229fb83 100644 --- a/hw/adc/Kconfig +++ b/hw/adc/Kconfig @@ -1,5 +1,2 @@ config STM32F2XX_ADC bool - -config MAX111X - bool diff --git a/hw/adc/meson.build b/hw/adc/meson.build index a4f85b7d468..7f7acc16196 100644 --- a/hw/adc/meson.build +++ b/hw/adc/meson.build @@ -2,4 +2,3 @@ system_ss.add(when: 'CONFIG_STM32F2XX_ADC', if_true: files('stm32f2xx_adc.c')) system_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_adc.c')) system_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_adc.c')) system_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq-xadc.c')) -system_ss.add(when: 'CONFIG_MAX111X', if_true: files('max111x.c')) From patchwork Thu Oct 3 14:00:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 832391 Delivered-To: patch@linaro.org Received: by 2002:adf:8b52:0:b0:367:895a:4699 with SMTP id v18csp277932wra; Thu, 3 Oct 2024 07:02:00 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVOh/3NxpTDFZaTEhZgebFdQ5QtnTWflY/TuoNv5f4TrsEORSOlfwd3ufIkygsyU6DyCBGuYg==@linaro.org X-Google-Smtp-Source: AGHT+IF1Y8+bz3TBTGlLdGQd77zXa9dnePnhIdwxoHz35IG4eRityAVCpJhGlLwpFWw7Cd8nihIa X-Received: by 2002:a05:6830:628d:b0:710:ebc6:a1aa with SMTP id 46e09a7af769-7153ce01bc8mr4958272a34.31.1727964120527; Thu, 03 Oct 2024 07:02:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1727964120; cv=none; d=google.com; s=arc-20240605; b=cQcQO/sEwYwQViY8DY7vQ9qkWlVK6damOaRJMZl+vq8XR5hBWVxZojalJfjRHt61QG rQrtymehMbzelecMuYBSGpzZCaHKjdz7l7nohBKxZXawgy+XlCbgXgJxldJDf3LnlKzx eLngJ74SGrhShMyvewusyDeqA7UDBQy7G+bqR26xXuF74YIHrpNrJ6AINy40qsRUGKSG zyfRKgFs3Fyqqft4DN+wAU0bpiReGxs8HlU0IuZb/l0QNjg/CvV3rxse3LoXmzMV1tfL X7aOgdjCgNW0Hyqkwxu15XJnhOGqaw9l3zD5CMPiVazIIfbaiLH6vSDkw9LFhIr/tviO YePQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=GbrP9MmrJ0+K+HvI7PXjyGE5YoOWjRR/6vqiaVbTMdM=; fh=aUbenXEfhWwRzuRh6hV73naeN6apPEaQI6KfBcxlr/U=; b=Mg4bAC6UmqfgvzVj7iYV74SWnGEigGJl+z50dK9H3j6b82WPchdQuilA73843iVn6n FiOPQ4V6E/ELldoo8tXDCdTZK84kSRTBAUes5nKzbc3k2NNyxy7LfbcCTAdlvAVq32mn c1j4qHS4eaDaH5bwhAll35I8d4D2dytXCPchri+QkQU48e9R2VrsZWayjAzD2Wrn4/+M MmEIwkY2A6wgvnGVgHrYouTYKqnF9ZYfCoMk84kDLBlfwSw+Sw0k0Q5IndjQJMxC6Dzk gHAcxpjwipNKiHC4PH0ZLa+6oPpJ243AZdTDJrWJ4p/vVbbAwVNrs4IFuCGsf9vTyQPl zUVQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Bda4ATXe; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id ada2fe7eead31-4a3f9ba5d52si210400137.207.2024.10.03.07.02.00 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 03 Oct 2024 07:02:00 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Bda4ATXe; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1swMO7-0004Eu-Jn; Thu, 03 Oct 2024 10:01:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1swMNQ-00046x-Jb for qemu-devel@nongnu.org; Thu, 03 Oct 2024 10:00:25 -0400 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1swMNM-0002qr-P5 for qemu-devel@nongnu.org; Thu, 03 Oct 2024 10:00:18 -0400 Received: by mail-wr1-x431.google.com with SMTP id ffacd0b85a97d-37ccfbbd467so857406f8f.0 for ; Thu, 03 Oct 2024 07:00:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1727964014; x=1728568814; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=GbrP9MmrJ0+K+HvI7PXjyGE5YoOWjRR/6vqiaVbTMdM=; b=Bda4ATXeYCa0rgPOiGPzxlfkgvxo5RWqayLxF+4dN1MYBeEMnPTaXyrIi+iBTEIrM5 4mp4ndwagFO+uA+/Atlw1TDqychVrYNxOfjwpMhaC9aLiShBcIFkv/kY5TCRPEWeHIWn f9wofnxAje5SF2IoSeQvOVKs1TpcfkO0LjOabMYwrLi8duzUweknLtDDBj/pZPEmpFog yGcwPp6wX84niAoyIxDaDlExID44BBckgSM3FIpJrTZq1D3J02J32/UX/1lZU/avakSi IPT/6E3ZUHkzAcabdhrt1E+CWNo2gqO9YEaAC8+GqYHApi92V0WsB8sDY2VFV4M8kjXv G1mA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1727964014; x=1728568814; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GbrP9MmrJ0+K+HvI7PXjyGE5YoOWjRR/6vqiaVbTMdM=; b=pwdfg6LMl2ERciYwKIq6kzc1XlHpz+4Ec2s3/1OdKB/orOo404432VskxBBpYWDGk/ 65l3fPHzBRhSRZgvae7L7oaTvRsmlmfHBcSXf5rtbcAZDBNZpGI594wtCCITLK8nw0xr McmAyH72GlbLUlnGVU9wrjOYA6Mpj7FqolhcMd+I4eLR0VX56gO+eMuC/wwCz3npCdM4 oqVeLLlkkqPCwOxTy1fMDcSwHjyAnK5qOL+vgk56arYVMLBJN2isu3EM6SOGzDScfqo4 Q8m2cI2tPnI6iKte7MSZJrtGkJgrgPTqcXEJuSylebr6yzhLrCJIqRduT4vLMTOrFLuf QWLA== X-Forwarded-Encrypted: i=1; AJvYcCVv5mpnTwJ16jf0pfkRP7F0ty8lszyVCsvQ+WWWpzGvQMQCFTX4WiHEnnuxKFfarRhrd/54I/BA/zeR@nongnu.org X-Gm-Message-State: AOJu0Yzzs6cB8EkSvdPC2k4JhYaQFQd8oYgwv3dTwWmXEv/ikZeW2nOB wbTgRgPCieDGWX8D21ykFgTTKu3DvF//JamIZi7n0xx3nM6px9ZVAT8t7JLAk9o= X-Received: by 2002:adf:a2de:0:b0:37c:c5fc:89f4 with SMTP id ffacd0b85a97d-37cfba139a9mr4222227f8f.51.1727964013556; Thu, 03 Oct 2024 07:00:13 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37d0822bc38sm1340255f8f.45.2024.10.03.07.00.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Oct 2024 07:00:13 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Guenter Roeck , Paolo Bonzini Subject: [PATCH v2 2/6] hw/gpio: Remove MAX7310 device Date: Thu, 3 Oct 2024 15:00:06 +0100 Message-Id: <20241003140010.1653808-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241003140010.1653808-1-peter.maydell@linaro.org> References: <20241003140010.1653808-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The MAX7310 GPIO controller was used only by the XScale-based Zaurus machine types. Now they have been removed we can remove this device model as well. Because this device is an I2C device, in theory it could be created by users on the command line for boards with a different I2c controller, but we don't believe users are doing this -- it would be impossible on the command line to connect up the GPIO inputs/outputs. The only example a web search produces for "device max7310" is a user trying to create this because they didn't realize that there was no way to manipulate the GPIO lines. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé --- hw/gpio/max7310.c | 217 -------------------------------------------- hw/gpio/Kconfig | 4 - hw/gpio/meson.build | 1 - 3 files changed, 222 deletions(-) delete mode 100644 hw/gpio/max7310.c diff --git a/hw/gpio/max7310.c b/hw/gpio/max7310.c deleted file mode 100644 index 43a92b8db97..00000000000 --- a/hw/gpio/max7310.c +++ /dev/null @@ -1,217 +0,0 @@ -/* - * MAX7310 8-port GPIO expansion chip. - * - * Copyright (c) 2006 Openedhand Ltd. - * Written by Andrzej Zaborowski - * - * This file is licensed under GNU GPL. - */ - -#include "qemu/osdep.h" -#include "hw/i2c/i2c.h" -#include "hw/irq.h" -#include "migration/vmstate.h" -#include "qemu/log.h" -#include "qemu/module.h" -#include "qom/object.h" - -#define TYPE_MAX7310 "max7310" -OBJECT_DECLARE_SIMPLE_TYPE(MAX7310State, MAX7310) - -struct MAX7310State { - I2CSlave parent_obj; - - int i2c_command_byte; - int len; - - uint8_t level; - uint8_t direction; - uint8_t polarity; - uint8_t status; - uint8_t command; - qemu_irq handler[8]; - qemu_irq *gpio_in; -}; - -static void max7310_reset(DeviceState *dev) -{ - MAX7310State *s = MAX7310(dev); - - s->level &= s->direction; - s->direction = 0xff; - s->polarity = 0xf0; - s->status = 0x01; - s->command = 0x00; -} - -static uint8_t max7310_rx(I2CSlave *i2c) -{ - MAX7310State *s = MAX7310(i2c); - - switch (s->command) { - case 0x00: /* Input port */ - return s->level ^ s->polarity; - - case 0x01: /* Output port */ - return s->level & ~s->direction; - - case 0x02: /* Polarity inversion */ - return s->polarity; - - case 0x03: /* Configuration */ - return s->direction; - - case 0x04: /* Timeout */ - return s->status; - - case 0xff: /* Reserved */ - return 0xff; - - default: - qemu_log_mask(LOG_UNIMP, "%s: Unsupported register 0x02%" PRIx8 "\n", - __func__, s->command); - break; - } - return 0xff; -} - -static int max7310_tx(I2CSlave *i2c, uint8_t data) -{ - MAX7310State *s = MAX7310(i2c); - uint8_t diff; - int line; - - if (s->len ++ > 1) { -#ifdef VERBOSE - printf("%s: message too long (%i bytes)\n", __func__, s->len); -#endif - return 1; - } - - if (s->i2c_command_byte) { - s->command = data; - s->i2c_command_byte = 0; - return 0; - } - - switch (s->command) { - case 0x01: /* Output port */ - for (diff = (data ^ s->level) & ~s->direction; diff; - diff &= ~(1 << line)) { - line = ctz32(diff); - if (s->handler[line]) - qemu_set_irq(s->handler[line], (data >> line) & 1); - } - s->level = (s->level & s->direction) | (data & ~s->direction); - break; - - case 0x02: /* Polarity inversion */ - s->polarity = data; - break; - - case 0x03: /* Configuration */ - s->level &= ~(s->direction ^ data); - s->direction = data; - break; - - case 0x04: /* Timeout */ - s->status = data; - break; - - case 0x00: /* Input port - ignore writes */ - break; - default: - qemu_log_mask(LOG_UNIMP, "%s: Unsupported register 0x02%" PRIx8 "\n", - __func__, s->command); - return 1; - } - - return 0; -} - -static int max7310_event(I2CSlave *i2c, enum i2c_event event) -{ - MAX7310State *s = MAX7310(i2c); - s->len = 0; - - switch (event) { - case I2C_START_SEND: - s->i2c_command_byte = 1; - break; - case I2C_FINISH: -#ifdef VERBOSE - if (s->len == 1) - printf("%s: message too short (%i bytes)\n", __func__, s->len); -#endif - break; - default: - break; - } - - return 0; -} - -static const VMStateDescription vmstate_max7310 = { - .name = "max7310", - .version_id = 0, - .minimum_version_id = 0, - .fields = (const VMStateField[]) { - VMSTATE_INT32(i2c_command_byte, MAX7310State), - VMSTATE_INT32(len, MAX7310State), - VMSTATE_UINT8(level, MAX7310State), - VMSTATE_UINT8(direction, MAX7310State), - VMSTATE_UINT8(polarity, MAX7310State), - VMSTATE_UINT8(status, MAX7310State), - VMSTATE_UINT8(command, MAX7310State), - VMSTATE_I2C_SLAVE(parent_obj, MAX7310State), - VMSTATE_END_OF_LIST() - } -}; - -static void max7310_gpio_set(void *opaque, int line, int level) -{ - MAX7310State *s = (MAX7310State *) opaque; - assert(line >= 0 && line < ARRAY_SIZE(s->handler)); - - if (level) - s->level |= s->direction & (1 << line); - else - s->level &= ~(s->direction & (1 << line)); -} - -/* MAX7310 is SMBus-compatible (can be used with only SMBus protocols), - * but also accepts sequences that are not SMBus so return an I2C device. */ -static void max7310_realize(DeviceState *dev, Error **errp) -{ - MAX7310State *s = MAX7310(dev); - - qdev_init_gpio_in(dev, max7310_gpio_set, ARRAY_SIZE(s->handler)); - qdev_init_gpio_out(dev, s->handler, ARRAY_SIZE(s->handler)); -} - -static void max7310_class_init(ObjectClass *klass, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(klass); - I2CSlaveClass *k = I2C_SLAVE_CLASS(klass); - - dc->realize = max7310_realize; - k->event = max7310_event; - k->recv = max7310_rx; - k->send = max7310_tx; - device_class_set_legacy_reset(dc, max7310_reset); - dc->vmsd = &vmstate_max7310; -} - -static const TypeInfo max7310_info = { - .name = TYPE_MAX7310, - .parent = TYPE_I2C_SLAVE, - .instance_size = sizeof(MAX7310State), - .class_init = max7310_class_init, -}; - -static void max7310_register_types(void) -{ - type_register_static(&max7310_info); -} - -type_init(max7310_register_types) diff --git a/hw/gpio/Kconfig b/hw/gpio/Kconfig index 843630d4f5f..c423e10f59f 100644 --- a/hw/gpio/Kconfig +++ b/hw/gpio/Kconfig @@ -1,7 +1,3 @@ -config MAX7310 - bool - depends on I2C - config PL061 bool diff --git a/hw/gpio/meson.build b/hw/gpio/meson.build index 089b24802ef..74840619c01 100644 --- a/hw/gpio/meson.build +++ b/hw/gpio/meson.build @@ -1,7 +1,6 @@ system_ss.add(when: 'CONFIG_GPIO_KEY', if_true: files('gpio_key.c')) system_ss.add(when: 'CONFIG_GPIO_MPC8XXX', if_true: files('mpc8xxx.c')) system_ss.add(when: 'CONFIG_GPIO_PWR', if_true: files('gpio_pwr.c')) -system_ss.add(when: 'CONFIG_MAX7310', if_true: files('max7310.c')) system_ss.add(when: 'CONFIG_PCA9552', if_true: files('pca9552.c')) system_ss.add(when: 'CONFIG_PCA9554', if_true: files('pca9554.c')) system_ss.add(when: 'CONFIG_PL061', if_true: files('pl061.c')) From patchwork Thu Oct 3 14:00:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 832392 Delivered-To: patch@linaro.org Received: by 2002:adf:8b52:0:b0:367:895a:4699 with SMTP id v18csp278158wra; Thu, 3 Oct 2024 07:02:18 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWXd+sgEK4Xd6Qy8ttIGQ5SRoIWES8UwONwzJxzEh7+CivZMQ48JmuoSFmQqeiYCzebJYkK8Q==@linaro.org X-Google-Smtp-Source: AGHT+IFa2y+DQnIR8HhCOulW9M8vet4mkQd9v5ghdPZxFzS5k1EMD55ccH7a0DcY4xGxeuBWnTvq X-Received: by 2002:a05:620a:4310:b0:7a9:9ed7:b49b with SMTP id af79cd13be357-7ae626d4017mr1146749385a.30.1727964138669; Thu, 03 Oct 2024 07:02:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1727964138; cv=none; d=google.com; s=arc-20240605; b=Me40hd+FtsTAdXQSvMO5F+UErMqdpOpWnrbmp4CxTOS2FCquEwHDx/LpRFXCSU0em8 I5RfKZBcfXp69CWnKxnBluJYCW/vZASiwsNdFIXIu86rIFve1WBcf8WaX7TovRnLb1yE 4n0lrMyP2KpGy/wur+PvcZ/LdLFjOTP6a9G7m/P7xarJaCua9xFPOYOXxd6kgKS0eBKU bWqLPWNqHMWuVnGo50xAtRTtZJrTD5cib//DZp8jIsp/L5CTCx0kt6rashxTXJ+GS15/ uu98+mvYByreJQJJ81veIMCudWdhYNksnHGECIIDgzTjsCZ0Wr8ZCdugn3l/HNOwnevd zxLQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=5YfeG5jC30ICdEmD4L7YfElHyWYG3PKB3Jupds5FC1o=; fh=yxxSOZW08qA3pQZYu65Ky82cQ1eZndjEVlUiP62ttSo=; b=UapjhTMHj0U2CBVIo4990b62QBwT7I4q16w0dBL8fBKg+68IltByYuAEUmcskXPljs 5US5uIsETDIg8lFgX6FyT0hrK1VK4VnaEEe+psOcpw5zdd0MgCf1sTS0Xs4G2moskR0l 7IVcOzQYNHYo6GjXbEke4B/qQiAV837I7q/o4sTRsywgemqa5f5sOFhXc2nkjZ1oAV7V KMI21fGdRRXhG4vOb2GXnSaER7turxA0mPyp7G5sC2y6erueCe7GeLid9X1uGsOblFZP KTZ2lC0aXFW+kN6BJq8pp0aYAYj8cpTvNtL9AuaIaCf/4jzgvrtgbGm3P4gD1dWD77w3 Zojw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=iotOYRgl; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id af79cd13be357-7ae6b9966f1si106342985a.279.2024.10.03.07.02.18 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 03 Oct 2024 07:02:18 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=iotOYRgl; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1swMOC-0004L6-Bn; Thu, 03 Oct 2024 10:01:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1swMNS-00047I-Mt for qemu-devel@nongnu.org; Thu, 03 Oct 2024 10:00:26 -0400 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1swMNN-0002r5-40 for qemu-devel@nongnu.org; Thu, 03 Oct 2024 10:00:21 -0400 Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-42cb57f8b41so13165935e9.0 for ; Thu, 03 Oct 2024 07:00:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1727964014; x=1728568814; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5YfeG5jC30ICdEmD4L7YfElHyWYG3PKB3Jupds5FC1o=; b=iotOYRgltHSsyVND6gb9eZYE9Xch+RK0uvEoNj3CgQQ/4U2E0LoGlzg20nMXpyM2hB R1wm2UD8TJCXLdEj9RG7q3fgNE+tKqa3BR/ZFWRuebBXxcqCn4eZFYdAVyGu+deMmM30 XJGtoodCakD83sm71kn3gbalCmeq0gzqvkP0C09KvVAW7p6d6J9Bkg1XnwWRUwsyN7V2 QZ2IqKGWQ5gDLWlo9flQR7okzdfU7Jf41ySA1ggeBUMxwZEPMN+Tv5WKtDdPtF2ZYuIu 0VncuO0jQZhkKchvWODnZcS3d/xuc9TRIsgiJm6Z95MBwBcZvLLZWADHNeISAFV6QToz ZMjQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1727964014; x=1728568814; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5YfeG5jC30ICdEmD4L7YfElHyWYG3PKB3Jupds5FC1o=; b=nokzcuKpOY966ayQjpxyRDbbD2vEevGuT/ZmXyA5AjC3Qlr4WcNCneFwPHqf5gR5i3 9asqm+6XfFPBxht/2vJthI7lTU2L+IND0kRTfQ/Q8FX+WR/07uK+PDtnocfSk3P890WP Ty1CFBSocky6VQew5bdB6Ib6N233L0TY16XSDtITvveJoieZ1mxvhOIat43Lr1D0F3at lXjagibBDS4L5IEbil6i5dHuop+VCvXzRbSS6k+rDtcliX/3wHdKFIRxQYYCzWW934Cx jrdv42TsCZW4x/raBkLQ491O/o8qOnMykGqELn5Wren0ljpur5rgs7aaXSudUBmJmnKm 6SnQ== X-Forwarded-Encrypted: i=1; AJvYcCUhX+uZiR0FqLkTCLSnYEVvG/DnPmU9RYmd/0vQ7c5hv+KPzRM1zONh5J9okBX4iDkSCaKqtnIVXeCn@nongnu.org X-Gm-Message-State: AOJu0Yz3Zt43cto7d8KE97mvqBVVIOxR0LsfgW5NDrJLModXLXBWRUob P5fXdiXw6+co6isDmb5RDphJhMp8U/DR+VbGmIm73xn1ojDBBwgZjg8JaHfC0Cj5yb8Cb5LaBtM L X-Received: by 2002:a5d:58d2:0:b0:37c:cea2:826f with SMTP id ffacd0b85a97d-37cfb8b562bmr5642691f8f.2.1727964014263; Thu, 03 Oct 2024 07:00:14 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37d0822bc38sm1340255f8f.45.2024.10.03.07.00.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Oct 2024 07:00:13 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Guenter Roeck , Paolo Bonzini Subject: [PATCH v2 3/6] hw/ide: Remove DSCM-1XXXX microdrive device model Date: Thu, 3 Oct 2024 15:00:07 +0100 Message-Id: <20241003140010.1653808-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241003140010.1653808-1-peter.maydell@linaro.org> References: <20241003140010.1653808-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The DSCM-1XXXX microdrive device model was used only by the XScale-based Zaurus machine types. Now they have been removed, we can delete this device too. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé --- include/hw/pcmcia.h | 3 - hw/ide/microdrive.c | 644 -------------------------------------------- hw/ide/Kconfig | 6 - hw/ide/meson.build | 1 - 4 files changed, 654 deletions(-) delete mode 100644 hw/ide/microdrive.c diff --git a/include/hw/pcmcia.h b/include/hw/pcmcia.h index ab268027511..6c08ad616a5 100644 --- a/include/hw/pcmcia.h +++ b/include/hw/pcmcia.h @@ -60,7 +60,4 @@ struct PCMCIACardClass { #define CISTPL_END 0xff /* Tuple End */ #define CISTPL_ENDMARK 0xff -/* dscm1xxxx.c */ -PCMCIACardState *dscm1xxxx_init(DriveInfo *bdrv); - #endif diff --git a/hw/ide/microdrive.c b/hw/ide/microdrive.c deleted file mode 100644 index 5475d599788..00000000000 --- a/hw/ide/microdrive.c +++ /dev/null @@ -1,644 +0,0 @@ -/* - * QEMU IDE Emulation: microdrive (CF / PCMCIA) - * - * Copyright (c) 2003 Fabrice Bellard - * Copyright (c) 2006 Openedhand Ltd. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include "qemu/osdep.h" -#include "hw/pcmcia.h" -#include "migration/vmstate.h" -#include "qapi/error.h" -#include "qemu/module.h" -#include "sysemu/dma.h" -#include "hw/irq.h" - -#include "qom/object.h" -#include "ide-internal.h" - -#define TYPE_MICRODRIVE "microdrive" -OBJECT_DECLARE_SIMPLE_TYPE(MicroDriveState, MICRODRIVE) - -/***********************************************************/ -/* CF-ATA Microdrive */ - -#define METADATA_SIZE 0x20 - -/* DSCM-1XXXX Microdrive hard disk with CF+ II / PCMCIA interface. */ - -struct MicroDriveState { - /*< private >*/ - PCMCIACardState parent_obj; - /*< public >*/ - - IDEBus bus; - uint32_t attr_base; - uint32_t io_base; - - /* Card state */ - uint8_t opt; - uint8_t stat; - uint8_t pins; - - uint8_t ctrl; - uint16_t io; - uint8_t cycle; -}; - -/* Register bitfields */ -enum md_opt { - OPT_MODE_MMAP = 0, - OPT_MODE_IOMAP16 = 1, - OPT_MODE_IOMAP1 = 2, - OPT_MODE_IOMAP2 = 3, - OPT_MODE = 0x3f, - OPT_LEVIREQ = 0x40, - OPT_SRESET = 0x80, -}; -enum md_cstat { - STAT_INT = 0x02, - STAT_PWRDWN = 0x04, - STAT_XE = 0x10, - STAT_IOIS8 = 0x20, - STAT_SIGCHG = 0x40, - STAT_CHANGED = 0x80, -}; -enum md_pins { - PINS_MRDY = 0x02, - PINS_CRDY = 0x20, -}; -enum md_ctrl { - CTRL_IEN = 0x02, - CTRL_SRST = 0x04, -}; - -static inline void md_interrupt_update(MicroDriveState *s) -{ - PCMCIACardState *card = PCMCIA_CARD(s); - - if (card->slot == NULL) { - return; - } - - qemu_set_irq(card->slot->irq, - !(s->stat & STAT_INT) && /* Inverted */ - !(s->ctrl & (CTRL_IEN | CTRL_SRST)) && - !(s->opt & OPT_SRESET)); -} - -static void md_set_irq(void *opaque, int irq, int level) -{ - MicroDriveState *s = opaque; - - if (level) { - s->stat |= STAT_INT; - } else { - s->stat &= ~STAT_INT; - } - - md_interrupt_update(s); -} - -static void md_reset(DeviceState *dev) -{ - MicroDriveState *s = MICRODRIVE(dev); - - s->opt = OPT_MODE_MMAP; - s->stat = 0; - s->pins = 0; - s->cycle = 0; - s->ctrl = 0; - ide_bus_reset(&s->bus); -} - -static uint8_t md_attr_read(PCMCIACardState *card, uint32_t at) -{ - MicroDriveState *s = MICRODRIVE(card); - PCMCIACardClass *pcc = PCMCIA_CARD_GET_CLASS(card); - - if (at < s->attr_base) { - if (at < pcc->cis_len) { - return pcc->cis[at]; - } else { - return 0x00; - } - } - - at -= s->attr_base; - - switch (at) { - case 0x00: /* Configuration Option Register */ - return s->opt; - case 0x02: /* Card Configuration Status Register */ - if (s->ctrl & CTRL_IEN) { - return s->stat & ~STAT_INT; - } else { - return s->stat; - } - case 0x04: /* Pin Replacement Register */ - return (s->pins & PINS_CRDY) | 0x0c; - case 0x06: /* Socket and Copy Register */ - return 0x00; -#ifdef VERBOSE - default: - printf("%s: Bad attribute space register %02x\n", __func__, at); -#endif - } - - return 0; -} - -static void md_attr_write(PCMCIACardState *card, uint32_t at, uint8_t value) -{ - MicroDriveState *s = MICRODRIVE(card); - - at -= s->attr_base; - - switch (at) { - case 0x00: /* Configuration Option Register */ - s->opt = value & 0xcf; - if (value & OPT_SRESET) { - device_cold_reset(DEVICE(s)); - } - md_interrupt_update(s); - break; - case 0x02: /* Card Configuration Status Register */ - if ((s->stat ^ value) & STAT_PWRDWN) { - s->pins |= PINS_CRDY; - } - s->stat &= 0x82; - s->stat |= value & 0x74; - md_interrupt_update(s); - /* Word 170 in Identify Device must be equal to STAT_XE */ - break; - case 0x04: /* Pin Replacement Register */ - s->pins &= PINS_CRDY; - s->pins |= value & PINS_MRDY; - break; - case 0x06: /* Socket and Copy Register */ - break; - default: - printf("%s: Bad attribute space register %02x\n", __func__, at); - } -} - -static uint16_t md_common_read(PCMCIACardState *card, uint32_t at) -{ - MicroDriveState *s = MICRODRIVE(card); - IDEState *ifs; - uint16_t ret; - at -= s->io_base; - - switch (s->opt & OPT_MODE) { - case OPT_MODE_MMAP: - if ((at & ~0x3ff) == 0x400) { - at = 0; - } - break; - case OPT_MODE_IOMAP16: - at &= 0xf; - break; - case OPT_MODE_IOMAP1: - if ((at & ~0xf) == 0x3f0) { - at -= 0x3e8; - } else if ((at & ~0xf) == 0x1f0) { - at -= 0x1f0; - } - break; - case OPT_MODE_IOMAP2: - if ((at & ~0xf) == 0x370) { - at -= 0x368; - } else if ((at & ~0xf) == 0x170) { - at -= 0x170; - } - } - - switch (at) { - case 0x0: /* Even RD Data */ - case 0x8: - return ide_data_readw(&s->bus, 0); - - /* TODO: 8-bit accesses */ - if (s->cycle) { - ret = s->io >> 8; - } else { - s->io = ide_data_readw(&s->bus, 0); - ret = s->io & 0xff; - } - s->cycle = !s->cycle; - return ret; - case 0x9: /* Odd RD Data */ - return s->io >> 8; - case 0xd: /* Error */ - return ide_ioport_read(&s->bus, 0x1); - case 0xe: /* Alternate Status */ - ifs = ide_bus_active_if(&s->bus); - if (ifs->blk) { - return ifs->status; - } else { - return 0; - } - case 0xf: /* Device Address */ - ifs = ide_bus_active_if(&s->bus); - return 0xc2 | ((~ifs->select << 2) & 0x3c); - default: - return ide_ioport_read(&s->bus, at); - } - - return 0; -} - -static void md_common_write(PCMCIACardState *card, uint32_t at, uint16_t value) -{ - MicroDriveState *s = MICRODRIVE(card); - at -= s->io_base; - - switch (s->opt & OPT_MODE) { - case OPT_MODE_MMAP: - if ((at & ~0x3ff) == 0x400) { - at = 0; - } - break; - case OPT_MODE_IOMAP16: - at &= 0xf; - break; - case OPT_MODE_IOMAP1: - if ((at & ~0xf) == 0x3f0) { - at -= 0x3e8; - } else if ((at & ~0xf) == 0x1f0) { - at -= 0x1f0; - } - break; - case OPT_MODE_IOMAP2: - if ((at & ~0xf) == 0x370) { - at -= 0x368; - } else if ((at & ~0xf) == 0x170) { - at -= 0x170; - } - } - - switch (at) { - case 0x0: /* Even WR Data */ - case 0x8: - ide_data_writew(&s->bus, 0, value); - break; - - /* TODO: 8-bit accesses */ - if (s->cycle) { - ide_data_writew(&s->bus, 0, s->io | (value << 8)); - } else { - s->io = value & 0xff; - } - s->cycle = !s->cycle; - break; - case 0x9: - s->io = value & 0xff; - s->cycle = !s->cycle; - break; - case 0xd: /* Features */ - ide_ioport_write(&s->bus, 0x1, value); - break; - case 0xe: /* Device Control */ - s->ctrl = value; - if (value & CTRL_SRST) { - device_cold_reset(DEVICE(s)); - } - md_interrupt_update(s); - break; - default: - if (s->stat & STAT_PWRDWN) { - s->pins |= PINS_CRDY; - s->stat &= ~STAT_PWRDWN; - } - ide_ioport_write(&s->bus, at, value); - } -} - -static const VMStateDescription vmstate_microdrive = { - .name = "microdrive", - .version_id = 3, - .minimum_version_id = 0, - .fields = (const VMStateField[]) { - VMSTATE_UINT8(opt, MicroDriveState), - VMSTATE_UINT8(stat, MicroDriveState), - VMSTATE_UINT8(pins, MicroDriveState), - VMSTATE_UINT8(ctrl, MicroDriveState), - VMSTATE_UINT16(io, MicroDriveState), - VMSTATE_UINT8(cycle, MicroDriveState), - VMSTATE_IDE_BUS(bus, MicroDriveState), - VMSTATE_IDE_DRIVES(bus.ifs, MicroDriveState), - VMSTATE_END_OF_LIST() - } -}; - -static const uint8_t dscm1xxxx_cis[0x14a] = { - [0x000] = CISTPL_DEVICE, /* 5V Device Information */ - [0x002] = 0x03, /* Tuple length = 4 bytes */ - [0x004] = 0xdb, /* ID: DTYPE_FUNCSPEC, non WP, DSPEED_150NS */ - [0x006] = 0x01, /* Size = 2K bytes */ - [0x008] = CISTPL_ENDMARK, - - [0x00a] = CISTPL_DEVICE_OC, /* Additional Device Information */ - [0x00c] = 0x04, /* Tuple length = 4 byest */ - [0x00e] = 0x03, /* Conditions: Ext = 0, Vcc 3.3V, MWAIT = 1 */ - [0x010] = 0xdb, /* ID: DTYPE_FUNCSPEC, non WP, DSPEED_150NS */ - [0x012] = 0x01, /* Size = 2K bytes */ - [0x014] = CISTPL_ENDMARK, - - [0x016] = CISTPL_JEDEC_C, /* JEDEC ID */ - [0x018] = 0x02, /* Tuple length = 2 bytes */ - [0x01a] = 0xdf, /* PC Card ATA with no Vpp required */ - [0x01c] = 0x01, - - [0x01e] = CISTPL_MANFID, /* Manufacture ID */ - [0x020] = 0x04, /* Tuple length = 4 bytes */ - [0x022] = 0xa4, /* TPLMID_MANF = 00a4 (IBM) */ - [0x024] = 0x00, - [0x026] = 0x00, /* PLMID_CARD = 0000 */ - [0x028] = 0x00, - - [0x02a] = CISTPL_VERS_1, /* Level 1 Version */ - [0x02c] = 0x12, /* Tuple length = 23 bytes */ - [0x02e] = 0x04, /* Major Version = JEIDA 4.2 / PCMCIA 2.1 */ - [0x030] = 0x01, /* Minor Version = 1 */ - [0x032] = 'I', - [0x034] = 'B', - [0x036] = 'M', - [0x038] = 0x00, - [0x03a] = 'm', - [0x03c] = 'i', - [0x03e] = 'c', - [0x040] = 'r', - [0x042] = 'o', - [0x044] = 'd', - [0x046] = 'r', - [0x048] = 'i', - [0x04a] = 'v', - [0x04c] = 'e', - [0x04e] = 0x00, - [0x050] = CISTPL_ENDMARK, - - [0x052] = CISTPL_FUNCID, /* Function ID */ - [0x054] = 0x02, /* Tuple length = 2 bytes */ - [0x056] = 0x04, /* TPLFID_FUNCTION = Fixed Disk */ - [0x058] = 0x01, /* TPLFID_SYSINIT: POST = 1, ROM = 0 */ - - [0x05a] = CISTPL_FUNCE, /* Function Extension */ - [0x05c] = 0x02, /* Tuple length = 2 bytes */ - [0x05e] = 0x01, /* TPLFE_TYPE = Disk Device Interface */ - [0x060] = 0x01, /* TPLFE_DATA = PC Card ATA Interface */ - - [0x062] = CISTPL_FUNCE, /* Function Extension */ - [0x064] = 0x03, /* Tuple length = 3 bytes */ - [0x066] = 0x02, /* TPLFE_TYPE = Basic PC Card ATA Interface */ - [0x068] = 0x08, /* TPLFE_DATA: Rotating, Unique, Single */ - [0x06a] = 0x0f, /* TPLFE_DATA: Sleep, Standby, Idle, Auto */ - - [0x06c] = CISTPL_CONFIG, /* Configuration */ - [0x06e] = 0x05, /* Tuple length = 5 bytes */ - [0x070] = 0x01, /* TPCC_RASZ = 2 bytes, TPCC_RMSZ = 1 byte */ - [0x072] = 0x07, /* TPCC_LAST = 7 */ - [0x074] = 0x00, /* TPCC_RADR = 0200 */ - [0x076] = 0x02, - [0x078] = 0x0f, /* TPCC_RMSK = 200, 202, 204, 206 */ - - [0x07a] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */ - [0x07c] = 0x0b, /* Tuple length = 11 bytes */ - [0x07e] = 0xc0, /* TPCE_INDX = Memory Mode, Default, Iface */ - [0x080] = 0xc0, /* TPCE_IF = Memory, no BVDs, no WP, READY */ - [0x082] = 0xa1, /* TPCE_FS = Vcc only, no I/O, Memory, Misc */ - [0x084] = 0x27, /* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */ - [0x086] = 0x55, /* NomV: 5.0 V */ - [0x088] = 0x4d, /* MinV: 4.5 V */ - [0x08a] = 0x5d, /* MaxV: 5.5 V */ - [0x08c] = 0x4e, /* Peakl: 450 mA */ - [0x08e] = 0x08, /* TPCE_MS = 1 window, 1 byte, Host address */ - [0x090] = 0x00, /* Window descriptor: Window length = 0 */ - [0x092] = 0x20, /* TPCE_MI: support power down mode, RW */ - - [0x094] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */ - [0x096] = 0x06, /* Tuple length = 6 bytes */ - [0x098] = 0x00, /* TPCE_INDX = Memory Mode, no Default */ - [0x09a] = 0x01, /* TPCE_FS = Vcc only, no I/O, no Memory */ - [0x09c] = 0x21, /* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */ - [0x09e] = 0xb5, /* NomV: 3.3 V */ - [0x0a0] = 0x1e, - [0x0a2] = 0x3e, /* Peakl: 350 mA */ - - [0x0a4] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */ - [0x0a6] = 0x0d, /* Tuple length = 13 bytes */ - [0x0a8] = 0xc1, /* TPCE_INDX = I/O and Memory Mode, Default */ - [0x0aa] = 0x41, /* TPCE_IF = I/O and Memory, no BVD, no WP */ - [0x0ac] = 0x99, /* TPCE_FS = Vcc only, I/O, Interrupt, Misc */ - [0x0ae] = 0x27, /* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */ - [0x0b0] = 0x55, /* NomV: 5.0 V */ - [0x0b2] = 0x4d, /* MinV: 4.5 V */ - [0x0b4] = 0x5d, /* MaxV: 5.5 V */ - [0x0b6] = 0x4e, /* Peakl: 450 mA */ - [0x0b8] = 0x64, /* TPCE_IO = 16-byte boundary, 16/8 accesses */ - [0x0ba] = 0xf0, /* TPCE_IR = MASK, Level, Pulse, Share */ - [0x0bc] = 0xff, /* IRQ0..IRQ7 supported */ - [0x0be] = 0xff, /* IRQ8..IRQ15 supported */ - [0x0c0] = 0x20, /* TPCE_MI = support power down mode */ - - [0x0c2] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */ - [0x0c4] = 0x06, /* Tuple length = 6 bytes */ - [0x0c6] = 0x01, /* TPCE_INDX = I/O and Memory Mode */ - [0x0c8] = 0x01, /* TPCE_FS = Vcc only, no I/O, no Memory */ - [0x0ca] = 0x21, /* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */ - [0x0cc] = 0xb5, /* NomV: 3.3 V */ - [0x0ce] = 0x1e, - [0x0d0] = 0x3e, /* Peakl: 350 mA */ - - [0x0d2] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */ - [0x0d4] = 0x12, /* Tuple length = 18 bytes */ - [0x0d6] = 0xc2, /* TPCE_INDX = I/O Primary Mode */ - [0x0d8] = 0x41, /* TPCE_IF = I/O and Memory, no BVD, no WP */ - [0x0da] = 0x99, /* TPCE_FS = Vcc only, I/O, Interrupt, Misc */ - [0x0dc] = 0x27, /* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */ - [0x0de] = 0x55, /* NomV: 5.0 V */ - [0x0e0] = 0x4d, /* MinV: 4.5 V */ - [0x0e2] = 0x5d, /* MaxV: 5.5 V */ - [0x0e4] = 0x4e, /* Peakl: 450 mA */ - [0x0e6] = 0xea, /* TPCE_IO = 1K boundary, 16/8 access, Range */ - [0x0e8] = 0x61, /* Range: 2 fields, 2 bytes addr, 1 byte len */ - [0x0ea] = 0xf0, /* Field 1 address = 0x01f0 */ - [0x0ec] = 0x01, - [0x0ee] = 0x07, /* Address block length = 8 */ - [0x0f0] = 0xf6, /* Field 2 address = 0x03f6 */ - [0x0f2] = 0x03, - [0x0f4] = 0x01, /* Address block length = 2 */ - [0x0f6] = 0xee, /* TPCE_IR = IRQ E, Level, Pulse, Share */ - [0x0f8] = 0x20, /* TPCE_MI = support power down mode */ - - [0x0fa] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */ - [0x0fc] = 0x06, /* Tuple length = 6 bytes */ - [0x0fe] = 0x02, /* TPCE_INDX = I/O Primary Mode, no Default */ - [0x100] = 0x01, /* TPCE_FS = Vcc only, no I/O, no Memory */ - [0x102] = 0x21, /* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */ - [0x104] = 0xb5, /* NomV: 3.3 V */ - [0x106] = 0x1e, - [0x108] = 0x3e, /* Peakl: 350 mA */ - - [0x10a] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */ - [0x10c] = 0x12, /* Tuple length = 18 bytes */ - [0x10e] = 0xc3, /* TPCE_INDX = I/O Secondary Mode, Default */ - [0x110] = 0x41, /* TPCE_IF = I/O and Memory, no BVD, no WP */ - [0x112] = 0x99, /* TPCE_FS = Vcc only, I/O, Interrupt, Misc */ - [0x114] = 0x27, /* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */ - [0x116] = 0x55, /* NomV: 5.0 V */ - [0x118] = 0x4d, /* MinV: 4.5 V */ - [0x11a] = 0x5d, /* MaxV: 5.5 V */ - [0x11c] = 0x4e, /* Peakl: 450 mA */ - [0x11e] = 0xea, /* TPCE_IO = 1K boundary, 16/8 access, Range */ - [0x120] = 0x61, /* Range: 2 fields, 2 byte addr, 1 byte len */ - [0x122] = 0x70, /* Field 1 address = 0x0170 */ - [0x124] = 0x01, - [0x126] = 0x07, /* Address block length = 8 */ - [0x128] = 0x76, /* Field 2 address = 0x0376 */ - [0x12a] = 0x03, - [0x12c] = 0x01, /* Address block length = 2 */ - [0x12e] = 0xee, /* TPCE_IR = IRQ E, Level, Pulse, Share */ - [0x130] = 0x20, /* TPCE_MI = support power down mode */ - - [0x132] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */ - [0x134] = 0x06, /* Tuple length = 6 bytes */ - [0x136] = 0x03, /* TPCE_INDX = I/O Secondary Mode */ - [0x138] = 0x01, /* TPCE_FS = Vcc only, no I/O, no Memory */ - [0x13a] = 0x21, /* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */ - [0x13c] = 0xb5, /* NomV: 3.3 V */ - [0x13e] = 0x1e, - [0x140] = 0x3e, /* Peakl: 350 mA */ - - [0x142] = CISTPL_NO_LINK, /* No Link */ - [0x144] = 0x00, /* Tuple length = 0 bytes */ - - [0x146] = CISTPL_END, /* Tuple End */ -}; - -#define TYPE_DSCM1XXXX "dscm1xxxx" - -static int dscm1xxxx_attach(PCMCIACardState *card) -{ - MicroDriveState *md = MICRODRIVE(card); - PCMCIACardClass *pcc = PCMCIA_CARD_GET_CLASS(card); - - md->attr_base = pcc->cis[0x74] | (pcc->cis[0x76] << 8); - md->io_base = 0x0; - - device_cold_reset(DEVICE(md)); - md_interrupt_update(md); - - return 0; -} - -static int dscm1xxxx_detach(PCMCIACardState *card) -{ - MicroDriveState *md = MICRODRIVE(card); - - device_cold_reset(DEVICE(md)); - return 0; -} - -PCMCIACardState *dscm1xxxx_init(DriveInfo *dinfo) -{ - MicroDriveState *md; - - md = MICRODRIVE(object_new(TYPE_DSCM1XXXX)); - qdev_realize(DEVICE(md), NULL, &error_fatal); - - if (dinfo != NULL) { - ide_bus_create_drive(&md->bus, 0, dinfo); - } - md->bus.ifs[0].drive_kind = IDE_CFATA; - md->bus.ifs[0].mdata_size = METADATA_SIZE; - md->bus.ifs[0].mdata_storage = g_malloc0(METADATA_SIZE); - - return PCMCIA_CARD(md); -} - -static void dscm1xxxx_class_init(ObjectClass *oc, void *data) -{ - PCMCIACardClass *pcc = PCMCIA_CARD_CLASS(oc); - DeviceClass *dc = DEVICE_CLASS(oc); - - pcc->cis = dscm1xxxx_cis; - pcc->cis_len = sizeof(dscm1xxxx_cis); - - pcc->attach = dscm1xxxx_attach; - pcc->detach = dscm1xxxx_detach; - /* Reason: Needs to be wired-up in code, see dscm1xxxx_init() */ - dc->user_creatable = false; -} - -static const TypeInfo dscm1xxxx_type_info = { - .name = TYPE_DSCM1XXXX, - .parent = TYPE_MICRODRIVE, - .class_init = dscm1xxxx_class_init, -}; - -static void microdrive_realize(DeviceState *dev, Error **errp) -{ - MicroDriveState *md = MICRODRIVE(dev); - - ide_bus_init_output_irq(&md->bus, qemu_allocate_irq(md_set_irq, md, 0)); -} - -static void microdrive_init(Object *obj) -{ - MicroDriveState *md = MICRODRIVE(obj); - - ide_bus_init(&md->bus, sizeof(md->bus), DEVICE(obj), 0, 1); -} - -static void microdrive_class_init(ObjectClass *oc, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(oc); - PCMCIACardClass *pcc = PCMCIA_CARD_CLASS(oc); - - pcc->attr_read = md_attr_read; - pcc->attr_write = md_attr_write; - pcc->common_read = md_common_read; - pcc->common_write = md_common_write; - pcc->io_read = md_common_read; - pcc->io_write = md_common_write; - - dc->realize = microdrive_realize; - device_class_set_legacy_reset(dc, md_reset); - dc->vmsd = &vmstate_microdrive; -} - -static const TypeInfo microdrive_type_info = { - .name = TYPE_MICRODRIVE, - .parent = TYPE_PCMCIA_CARD, - .instance_size = sizeof(MicroDriveState), - .instance_init = microdrive_init, - .abstract = true, - .class_init = microdrive_class_init, -}; - -static void microdrive_register_types(void) -{ - type_register_static(µdrive_type_info); - type_register_static(&dscm1xxxx_type_info); -} - -type_init(microdrive_register_types) diff --git a/hw/ide/Kconfig b/hw/ide/Kconfig index 6dfc5a21292..2e22b677da3 100644 --- a/hw/ide/Kconfig +++ b/hw/ide/Kconfig @@ -43,12 +43,6 @@ config IDE_VIA bool select IDE_PCI -config MICRODRIVE - bool - select IDE_BUS - select IDE_DEV - depends on PCMCIA - config AHCI bool select IDE_BUS diff --git a/hw/ide/meson.build b/hw/ide/meson.build index d09705cac03..90ea8614233 100644 --- a/hw/ide/meson.build +++ b/hw/ide/meson.build @@ -13,4 +13,3 @@ system_ss.add(when: 'CONFIG_IDE_PCI', if_true: files('pci.c')) system_ss.add(when: 'CONFIG_IDE_PIIX', if_true: files('piix.c', 'ioport.c')) system_ss.add(when: 'CONFIG_IDE_SII3112', if_true: files('sii3112.c')) system_ss.add(when: 'CONFIG_IDE_VIA', if_true: files('via.c')) -system_ss.add(when: 'CONFIG_MICRODRIVE', if_true: files('microdrive.c')) From patchwork Thu Oct 3 14:00:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 832394 Delivered-To: patch@linaro.org Received: by 2002:adf:8b52:0:b0:367:895a:4699 with SMTP id v18csp278498wra; Thu, 3 Oct 2024 07:02:47 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCU8NPcVKu17oI9i2V9UrOMDwRhbHlVQZHtovz/0VbmsR4jnTzG3gXNJ6kicDZA6vBl2AlQSkw==@linaro.org X-Google-Smtp-Source: AGHT+IFojerKO+z7CiDGMwJmFtD37f7lGD9R6L83LlHx8xlSisoObFMLIot062YbNYgR7AfgIITL X-Received: by 2002:a05:6808:212a:b0:3e0:4c44:ebaa with SMTP id 5614622812f47-3e3b41254b5mr5396314b6e.24.1727964166829; Thu, 03 Oct 2024 07:02:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1727964166; cv=none; d=google.com; s=arc-20240605; b=Q/6JoLxv9Y/dYKrOo0H2XCU8Z2k9gDahlOGz/DQXklw0/Fuy3CHzzqP/v9lmwPdRcR y6T+o+jh96M6TU/YWGWdHVoJUKGL1cqCtx7vju/Q6UpPwB/CHM1Kx+cZvBc+s+ZqoiVE VgN0kps6uv0TYvdL4sDlUD5QxdBC2bOp/3GHdtg2X93T6dgB3QjyBrsygEea5OM+IrNs D2T0mAaWMaIrKyx2H4SQ3KlQmiZ/T15fCgrUq1WmQnqhdWUGVEH4rzVBe75HwkAcli8X KeMgNkb7yJsalleFT/N91/glcBqTuSnbUuZ4aPdO4gwuSnljRcvl+GBCsCh66jkvyu9R M1NQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Em52MAkD+Yby6Vik40PbgLdJ9+Dl1OUfHlmPxxRRT14=; fh=44fV78kkMcYWSfjKL55JbOhLP8ak4CfeeaHPT1YieOQ=; b=acvlAAIFkazm4bbc3L9nryaPF2fB45cE5b9Fko8qzwRD5+H5t/KVMjsqXb/rFQmn0T sSfhYvnDQOQ/T4az6rYssx4Iq+MqcCz0WBQ1FnzZuN4xdTCv/CkeNwC+CetCoXdSJs4S w3pWr2n15YDAQYVUmpHi3/SlZeyhOoaU6gP3gvF4CjX9GXEQEarxFarMk/wyqiLGlD0g QLbbDBO2yEbeJBMUi5PwzpSM3bPuvdolBhA6YtQBnCd2ChX6KGAz0RfzmE60iBOBqFty 3SWWU/L5hyQVJHWSchlXKof+kOaZdao/f8GjZS6P5AbjIunwwuz6Ee1XGOAIM8jZ2nSH w/AA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=pFfbfhQY; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id a1e0cc1a2514c-84f3af3cc05si179242241.160.2024.10.03.07.02.46 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 03 Oct 2024 07:02:46 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=pFfbfhQY; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1swMNy-0004CA-02; Thu, 03 Oct 2024 10:00:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1swMNQ-00046v-Ha for qemu-devel@nongnu.org; Thu, 03 Oct 2024 10:00:25 -0400 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1swMNN-0002rN-5C for qemu-devel@nongnu.org; Thu, 03 Oct 2024 10:00:18 -0400 Received: by mail-wm1-x331.google.com with SMTP id 5b1f17b1804b1-42e82f7f36aso8917605e9.0 for ; Thu, 03 Oct 2024 07:00:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1727964015; x=1728568815; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Em52MAkD+Yby6Vik40PbgLdJ9+Dl1OUfHlmPxxRRT14=; b=pFfbfhQYzGmlgqxBbT7lJXGxLH+daErznLZNrunVGKQmKS7InU/4ETCyywrvRcsn2t 35HajqC9ghVLfZEAsJjyyHEGYqI7OFQimE0RnqnXdrUXFHAOAv90lnmRq0hHLu57r5ck ooy8qiK1YM4NfdHy5HyeIaC0MOkAxBzruOL+yb8aKPxAJsqfsRZI+LL56N9L0TNVwjqk LzFA1GKV0dU9wOhUE91k6rTy+Y71R5LY3beJxGzr4jgsgBofQQluRvaoAXoQeRSm51i1 asLygn37JB3ODmKGZXyT5qNMRNzXEJddJVOPQ09QYu5x83Bo8RiFlhTN9jHaj99D+x9n MIMw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1727964015; x=1728568815; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Em52MAkD+Yby6Vik40PbgLdJ9+Dl1OUfHlmPxxRRT14=; b=bvcMzk9Vg58u0WJY3B97mXwzIisTT83+/qR8Tb9S/kCgR90sSflTMwi7XAMPto6eM5 hbjN1pUGJ6zmr5RtiuGcyLHt3ythlmD/G26dn54Kg3XuLWvfz3wDI2hZ7C4LQpbRRv17 EkrGN06RioGc+DrynBv9bUqbOJc2Brpb+qKsDCGirVQTjDCYVTIWTpwZSvmH+QGM0iDt n2gbLvo4Qji8USm83Cjo+a3zqMYrAi0YAn5Xy0j3BsTK4i54SVRmbSur29Ea2vJyhcrg Oj7kEq+TKlJfsKVubiZN1bvqR04ZQdzGnoVqxK77AjYYBioBq7sd9mvRYffxE0kaIXFT IfGw== X-Forwarded-Encrypted: i=1; AJvYcCX7X9iF5rlNjW+hlQdr3C/9B3HCrTCdL2+tKI4/Dcg34ZCLI3xduDvqjfRTDHbJvt9BlEe0NVuaKCfI@nongnu.org X-Gm-Message-State: AOJu0YyWa1KHXQPUzJ4Y8Qv/UHI22ilHXQrOR7kRvOyXzucYxGNhJBet RlmpTWGBbCUgrYgGahK6eRKEAjEo8ioYzybA87nxX6Uhq7DWcndCzlgFpcu3uwU= X-Received: by 2002:adf:978a:0:b0:37c:ce45:96f2 with SMTP id ffacd0b85a97d-37cfba07a8emr3648176f8f.50.1727964015485; Thu, 03 Oct 2024 07:00:15 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37d0822bc38sm1340255f8f.45.2024.10.03.07.00.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Oct 2024 07:00:15 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Guenter Roeck , Paolo Bonzini Subject: [PATCH v2 4/6] hw: Remove PCMCIA subsystem Date: Thu, 3 Oct 2024 15:00:08 +0100 Message-Id: <20241003140010.1653808-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241003140010.1653808-1-peter.maydell@linaro.org> References: <20241003140010.1653808-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The only PCMCIA subsystem was the PXA2xx SoC and the machines using it, which have now been removed. Although in theory we have a few machine types which have PCMCIA (e.g. kzm, the strongarm machines, sh4's sh7750), none of those machines implement their PCMCIA controller, and they're all old and no longer very interesting machine types. Rather than keeping all the PCMCIA code in-tree without any active users of it, delete it. If we need PCMCIA in future we can always resurrect it. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé --- include/hw/pcmcia.h | 63 ------------------------------------------- hw/pcmcia/pcmcia.c | 24 ----------------- hw/Kconfig | 1 - hw/meson.build | 1 - hw/pcmcia/Kconfig | 2 -- hw/pcmcia/meson.build | 1 - 6 files changed, 92 deletions(-) delete mode 100644 include/hw/pcmcia.h delete mode 100644 hw/pcmcia/pcmcia.c delete mode 100644 hw/pcmcia/Kconfig delete mode 100644 hw/pcmcia/meson.build diff --git a/include/hw/pcmcia.h b/include/hw/pcmcia.h deleted file mode 100644 index 6c08ad616a5..00000000000 --- a/include/hw/pcmcia.h +++ /dev/null @@ -1,63 +0,0 @@ -#ifndef HW_PCMCIA_H -#define HW_PCMCIA_H - -/* PCMCIA/Cardbus */ - -#include "hw/qdev-core.h" -#include "qom/object.h" - -typedef struct PCMCIASocket { - qemu_irq irq; - bool attached; -} PCMCIASocket; - -#define TYPE_PCMCIA_CARD "pcmcia-card" -OBJECT_DECLARE_TYPE(PCMCIACardState, PCMCIACardClass, PCMCIA_CARD) - -struct PCMCIACardState { - /*< private >*/ - DeviceState parent_obj; - /*< public >*/ - - PCMCIASocket *slot; -}; - -struct PCMCIACardClass { - /*< private >*/ - DeviceClass parent_class; - /*< public >*/ - - int (*attach)(PCMCIACardState *state); - int (*detach)(PCMCIACardState *state); - - const uint8_t *cis; - int cis_len; - - /* Only valid if attached */ - uint8_t (*attr_read)(PCMCIACardState *card, uint32_t address); - void (*attr_write)(PCMCIACardState *card, uint32_t address, uint8_t value); - uint16_t (*common_read)(PCMCIACardState *card, uint32_t address); - void (*common_write)(PCMCIACardState *card, - uint32_t address, uint16_t value); - uint16_t (*io_read)(PCMCIACardState *card, uint32_t address); - void (*io_write)(PCMCIACardState *card, uint32_t address, uint16_t value); -}; - -#define CISTPL_DEVICE 0x01 /* 5V Device Information Tuple */ -#define CISTPL_NO_LINK 0x14 /* No Link Tuple */ -#define CISTPL_VERS_1 0x15 /* Level 1 Version Tuple */ -#define CISTPL_JEDEC_C 0x18 /* JEDEC ID Tuple */ -#define CISTPL_JEDEC_A 0x19 /* JEDEC ID Tuple */ -#define CISTPL_CONFIG 0x1a /* Configuration Tuple */ -#define CISTPL_CFTABLE_ENTRY 0x1b /* 16-bit PCCard Configuration */ -#define CISTPL_DEVICE_OC 0x1c /* Additional Device Information */ -#define CISTPL_DEVICE_OA 0x1d /* Additional Device Information */ -#define CISTPL_DEVICE_GEO 0x1e /* Additional Device Information */ -#define CISTPL_DEVICE_GEO_A 0x1f /* Additional Device Information */ -#define CISTPL_MANFID 0x20 /* Manufacture ID Tuple */ -#define CISTPL_FUNCID 0x21 /* Function ID Tuple */ -#define CISTPL_FUNCE 0x22 /* Function Extension Tuple */ -#define CISTPL_END 0xff /* Tuple End */ -#define CISTPL_ENDMARK 0xff - -#endif diff --git a/hw/pcmcia/pcmcia.c b/hw/pcmcia/pcmcia.c deleted file mode 100644 index 03d13e7d670..00000000000 --- a/hw/pcmcia/pcmcia.c +++ /dev/null @@ -1,24 +0,0 @@ -/* - * PCMCIA emulation - * - * Copyright 2013 SUSE LINUX Products GmbH - */ - -#include "qemu/osdep.h" -#include "qemu/module.h" -#include "hw/pcmcia.h" - -static const TypeInfo pcmcia_card_type_info = { - .name = TYPE_PCMCIA_CARD, - .parent = TYPE_DEVICE, - .instance_size = sizeof(PCMCIACardState), - .abstract = true, - .class_size = sizeof(PCMCIACardClass), -}; - -static void pcmcia_register_types(void) -{ - type_register_static(&pcmcia_card_type_info); -} - -type_init(pcmcia_register_types) diff --git a/hw/Kconfig b/hw/Kconfig index 6fdaff1b1be..1b4e9bb07f7 100644 --- a/hw/Kconfig +++ b/hw/Kconfig @@ -27,7 +27,6 @@ source nvme/Kconfig source nvram/Kconfig source pci-bridge/Kconfig source pci-host/Kconfig -source pcmcia/Kconfig source pci/Kconfig source remote/Kconfig source rtc/Kconfig diff --git a/hw/meson.build b/hw/meson.build index e86badc5417..b827c82c5d7 100644 --- a/hw/meson.build +++ b/hw/meson.build @@ -27,7 +27,6 @@ subdir('nvram') subdir('pci') subdir('pci-bridge') subdir('pci-host') -subdir('pcmcia') subdir('rtc') subdir('scsi') subdir('sd') diff --git a/hw/pcmcia/Kconfig b/hw/pcmcia/Kconfig deleted file mode 100644 index 41f2df91366..00000000000 --- a/hw/pcmcia/Kconfig +++ /dev/null @@ -1,2 +0,0 @@ -config PCMCIA - bool diff --git a/hw/pcmcia/meson.build b/hw/pcmcia/meson.build deleted file mode 100644 index edcb7f5d263..00000000000 --- a/hw/pcmcia/meson.build +++ /dev/null @@ -1 +0,0 @@ -system_ss.add(when: 'CONFIG_PCMCIA', if_true: files('pcmcia.c')) From patchwork Thu Oct 3 14:00:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 832390 Delivered-To: patch@linaro.org Received: by 2002:adf:8b52:0:b0:367:895a:4699 with SMTP id v18csp277931wra; Thu, 3 Oct 2024 07:02:00 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVu55Rgx7POJeao0F7OQ2Rcy0C44Cc3Tjb/vJuZvHDHqYJKQI5p3l2zjzAmb3sVx4cU9xOKIA==@linaro.org X-Google-Smtp-Source: AGHT+IFJSHQF3ZywGzje9C71KZfSrOFezXdiaRzeff39CRNRl31aWjfyjoyeqkerygcQjDgN9IVA X-Received: by 2002:a05:6830:d01:b0:70f:e8bd:2b61 with SMTP id 46e09a7af769-7153cd769a2mr6019933a34.11.1727964120543; Thu, 03 Oct 2024 07:02:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1727964120; cv=none; d=google.com; s=arc-20240605; b=c5MagGCDSY6SzkbbCwfqMRAHs0tzIDtsDqQHxiTro7Sk92mXMTnTLsarg0CqzLxMAW 5cgPKvPzcLAjlpwNNBlpDvYRG2ceCVmb4KoBI+nWX+wqf9+hSRhIA44WwgCTqFareyBl B83gUki2EfbZPOAoQ7BE3fl80RbK8pK1AabUMOTEj4QQbGAXtOA/tW7gOOPnSOK1ze3J 24WUhrad1+hsvCvvZsqNbTX/o6nuzRSFSg/z/IvzwuJ44LpwnOXEr+Z9pgK8pQQMClhO HEh81w6Dn/BB20RX/WK0zwx2Cpnr6R8ARU5Y0GnSbtJqglFt4o953uQPyb2PgC2c1JH9 X32w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=LPD0ziR8yfL/HjZu6b/yEmmqErN3Sv3BQp33o6QEumo=; fh=tDUnKAOzH3m+e+SVCPqqHBIbaZ4/EHUx1hmJy36Agss=; b=O2jFeprJprZgBfrahBnpeFUXcFRr+AmQmh7UQt67WnHvZ/cCOaHxCrWnNWuKQ8fGQi T8kXNu94jCd+AE/PZnlABmqkyn6jwLeQkNPONxS8Wfait9DTkhrpH1Zc+sCJAB3tmVsS 4PN6ndJLbMRtUCYpwSeFApsJtdBkdrh/RaF7TvFh6zxoKJcLMGaN3MHnSoIjWCX87I/O Hrx2uwQc02cavAf1uLBuAZ23p0EZuJRVeD97P3UoIlYFZT1Ecpqp/cl7HSWdeiSNfZWl FLRWaN25dahiV+ZY2drsOTFjRvtX44SmyCSM8rfh49y+CHnBT/g3Ay9Q/SEtwXFkTbyT CpJg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=paSZkejc; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id a1e0cc1a2514c-84f3af0aea2si171269241.143.2024.10.03.07.02.00 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 03 Oct 2024 07:02:00 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=paSZkejc; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1swMOC-0004Lf-EN; Thu, 03 Oct 2024 10:01:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1swMNQ-000471-NU for qemu-devel@nongnu.org; Thu, 03 Oct 2024 10:00:25 -0400 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1swMNO-0002rV-Af for qemu-devel@nongnu.org; Thu, 03 Oct 2024 10:00:20 -0400 Received: by mail-wr1-x42e.google.com with SMTP id ffacd0b85a97d-37ccd81de57so617229f8f.0 for ; Thu, 03 Oct 2024 07:00:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1727964016; x=1728568816; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=LPD0ziR8yfL/HjZu6b/yEmmqErN3Sv3BQp33o6QEumo=; b=paSZkejcLJehhIKtxeAm7c6dbsEA+0qHftsZSbuKCTOOt2h23ReqjdvnTr459qqFas TJ6RFkql2+9bZs3+AwImySZZr4kuZsGUwxzVR/ikY5yQTCpHeWhbyT4dpu4+FFt06Gfx 8GYfOy4/eeL1b48CCoJbucAl/E1aDZOQPB+7eQsF8qUbnjOCbkv/oUPGcljLXUwQ0mmo 0Lh+S1A2ZKwGgVJMDVz8BQuki+EYEdUa3kaLzsdySnBhoIckdR7do1RKoh8MYcb2lszJ ZKUrXRfb/JhFB/Fy8XJ64qxVrQhVaUb76T20iiTqGOAdi9Bs46yFJTmmQW3NptT1RIkX qcyg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1727964016; x=1728568816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LPD0ziR8yfL/HjZu6b/yEmmqErN3Sv3BQp33o6QEumo=; b=cjkHQ7Jx6flfQLZON+hbs52XsIM3sKXaunGjnhVt+0GvAftLeLUcC3eYxdNe6vOwD+ IpJUImSrabxkJYoFtUiaTLLzvyttyR8MbdsU7CVoPRSqDRLsBLTbdfWqd6OeQOWxi8+r w4ethW1ClEL0yG624enIPJDujiax8xI8PmXG5Ds9Kdlu85D/OZcdMbZ4mkE3dqJ75p8H kcLC1YgWGLwFRIi1ka/kkuWqCdfYrkDYNXFistfmDmTG9nD/hdUjdFgSR3dOsLOLo7U7 ZBNQHrc+bYa0lUHxXU33okhuN543NfEl1BOh9nEGFeoxTeMqzWQdquf0DP1aeJUaDEVW P/VQ== X-Forwarded-Encrypted: i=1; AJvYcCVKO71mNCBpQ6qo8AM3s3odT4B0M/YtXVSoa/v/NgY8+W4kP7mwnE52v2mY+YDW1v7Zdsh4pa9JwZzZ@nongnu.org X-Gm-Message-State: AOJu0Yx9n0Mb9/lcBk80LGRdKIhFuZ7BA908flw2eFBAsiTM+/H63CN/ B2GJ4QxkbqVxbJIw93Vhc3KKQyJB/r5FHs86xi1mXtkHeY7Vboila6g7ydRjRck= X-Received: by 2002:adf:a30d:0:b0:37c:f561:1130 with SMTP id ffacd0b85a97d-37d04a04aa2mr2286429f8f.18.1727964016185; Thu, 03 Oct 2024 07:00:16 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37d0822bc38sm1340255f8f.45.2024.10.03.07.00.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Oct 2024 07:00:15 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Guenter Roeck , Paolo Bonzini Subject: [PATCH v2 5/6] hw/block: Remove ecc Date: Thu, 3 Oct 2024 15:00:09 +0100 Message-Id: <20241003140010.1653808-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241003140010.1653808-1-peter.maydell@linaro.org> References: <20241003140010.1653808-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The ecc.c code was used only by the PXA2xx and OMAP2 SoC devices, which we have removed, so it is now completely unused. Note that hw/misc/eccmemctl.c does not in fact use any of the code frome ecc.c, so that KConfig dependency was incorrect. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé --- include/hw/block/flash.h | 11 ----- hw/block/ecc.c | 91 ---------------------------------------- hw/arm/Kconfig | 1 - hw/block/Kconfig | 3 -- hw/block/meson.build | 1 - hw/misc/Kconfig | 1 - 6 files changed, 108 deletions(-) delete mode 100644 hw/block/ecc.c diff --git a/include/hw/block/flash.h b/include/hw/block/flash.h index b985c825a01..5fd67f5bb79 100644 --- a/include/hw/block/flash.h +++ b/include/hw/block/flash.h @@ -62,17 +62,6 @@ uint32_t nand_getbuswidth(DeviceState *dev); #define NAND_MFR_HYNIX 0xad #define NAND_MFR_MICRON 0x2c -/* ecc.c */ -typedef struct { - uint8_t cp; /* Column parity */ - uint16_t lp[2]; /* Line parity */ - uint16_t count; -} ECCState; - -uint8_t ecc_digest(ECCState *s, uint8_t sample); -void ecc_reset(ECCState *s); -extern const VMStateDescription vmstate_ecc_state; - /* m25p80.c */ #define TYPE_M25P80 "m25p80-generic" diff --git a/hw/block/ecc.c b/hw/block/ecc.c deleted file mode 100644 index ed889a4184f..00000000000 --- a/hw/block/ecc.c +++ /dev/null @@ -1,91 +0,0 @@ -/* - * Calculate Error-correcting Codes. Used by NAND Flash controllers - * (not by NAND chips). - * - * Copyright (c) 2006 Openedhand Ltd. - * Written by Andrzej Zaborowski - * - * This code is licensed under the GNU GPL v2. - * - * Contributions after 2012-01-13 are licensed under the terms of the - * GNU GPL, version 2 or (at your option) any later version. - */ - -#include "qemu/osdep.h" -#include "migration/vmstate.h" -#include "hw/block/flash.h" - -/* - * Pre-calculated 256-way 1 byte column parity. Table borrowed from Linux. - */ -static const uint8_t nand_ecc_precalc_table[] = { - 0x00, 0x55, 0x56, 0x03, 0x59, 0x0c, 0x0f, 0x5a, - 0x5a, 0x0f, 0x0c, 0x59, 0x03, 0x56, 0x55, 0x00, - 0x65, 0x30, 0x33, 0x66, 0x3c, 0x69, 0x6a, 0x3f, - 0x3f, 0x6a, 0x69, 0x3c, 0x66, 0x33, 0x30, 0x65, - 0x66, 0x33, 0x30, 0x65, 0x3f, 0x6a, 0x69, 0x3c, - 0x3c, 0x69, 0x6a, 0x3f, 0x65, 0x30, 0x33, 0x66, - 0x03, 0x56, 0x55, 0x00, 0x5a, 0x0f, 0x0c, 0x59, - 0x59, 0x0c, 0x0f, 0x5a, 0x00, 0x55, 0x56, 0x03, - 0x69, 0x3c, 0x3f, 0x6a, 0x30, 0x65, 0x66, 0x33, - 0x33, 0x66, 0x65, 0x30, 0x6a, 0x3f, 0x3c, 0x69, - 0x0c, 0x59, 0x5a, 0x0f, 0x55, 0x00, 0x03, 0x56, - 0x56, 0x03, 0x00, 0x55, 0x0f, 0x5a, 0x59, 0x0c, - 0x0f, 0x5a, 0x59, 0x0c, 0x56, 0x03, 0x00, 0x55, - 0x55, 0x00, 0x03, 0x56, 0x0c, 0x59, 0x5a, 0x0f, - 0x6a, 0x3f, 0x3c, 0x69, 0x33, 0x66, 0x65, 0x30, - 0x30, 0x65, 0x66, 0x33, 0x69, 0x3c, 0x3f, 0x6a, - 0x6a, 0x3f, 0x3c, 0x69, 0x33, 0x66, 0x65, 0x30, - 0x30, 0x65, 0x66, 0x33, 0x69, 0x3c, 0x3f, 0x6a, - 0x0f, 0x5a, 0x59, 0x0c, 0x56, 0x03, 0x00, 0x55, - 0x55, 0x00, 0x03, 0x56, 0x0c, 0x59, 0x5a, 0x0f, - 0x0c, 0x59, 0x5a, 0x0f, 0x55, 0x00, 0x03, 0x56, - 0x56, 0x03, 0x00, 0x55, 0x0f, 0x5a, 0x59, 0x0c, - 0x69, 0x3c, 0x3f, 0x6a, 0x30, 0x65, 0x66, 0x33, - 0x33, 0x66, 0x65, 0x30, 0x6a, 0x3f, 0x3c, 0x69, - 0x03, 0x56, 0x55, 0x00, 0x5a, 0x0f, 0x0c, 0x59, - 0x59, 0x0c, 0x0f, 0x5a, 0x00, 0x55, 0x56, 0x03, - 0x66, 0x33, 0x30, 0x65, 0x3f, 0x6a, 0x69, 0x3c, - 0x3c, 0x69, 0x6a, 0x3f, 0x65, 0x30, 0x33, 0x66, - 0x65, 0x30, 0x33, 0x66, 0x3c, 0x69, 0x6a, 0x3f, - 0x3f, 0x6a, 0x69, 0x3c, 0x66, 0x33, 0x30, 0x65, - 0x00, 0x55, 0x56, 0x03, 0x59, 0x0c, 0x0f, 0x5a, - 0x5a, 0x0f, 0x0c, 0x59, 0x03, 0x56, 0x55, 0x00, -}; - -/* Update ECC parity count. */ -uint8_t ecc_digest(ECCState *s, uint8_t sample) -{ - uint8_t idx = nand_ecc_precalc_table[sample]; - - s->cp ^= idx & 0x3f; - if (idx & 0x40) { - s->lp[0] ^= ~s->count; - s->lp[1] ^= s->count; - } - s->count ++; - - return sample; -} - -/* Reinitialise the counters. */ -void ecc_reset(ECCState *s) -{ - s->lp[0] = 0x0000; - s->lp[1] = 0x0000; - s->cp = 0x00; - s->count = 0; -} - -/* Save/restore */ -const VMStateDescription vmstate_ecc_state = { - .name = "ecc-state", - .version_id = 0, - .minimum_version_id = 0, - .fields = (const VMStateField[]) { - VMSTATE_UINT8(cp, ECCState), - VMSTATE_UINT16_ARRAY(lp, ECCState, 2), - VMSTATE_UINT16(count, ECCState), - VMSTATE_END_OF_LIST(), - }, -}; diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index a70ceff504b..7b19a9559f6 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -146,7 +146,6 @@ config OMAP bool select FRAMEBUFFER select I2C - select ECC select NAND select PFLASH_CFI01 select SD diff --git a/hw/block/Kconfig b/hw/block/Kconfig index e67a6fd8af7..a898e04f03b 100644 --- a/hw/block/Kconfig +++ b/hw/block/Kconfig @@ -22,9 +22,6 @@ config PFLASH_CFI01 config PFLASH_CFI02 bool -config ECC - bool - config VIRTIO_BLK bool default y diff --git a/hw/block/meson.build b/hw/block/meson.build index 999a93d900f..16a51bf8e21 100644 --- a/hw/block/meson.build +++ b/hw/block/meson.build @@ -3,7 +3,6 @@ system_ss.add(files( 'cdrom.c', 'hd-geometry.c' )) -system_ss.add(when: 'CONFIG_ECC', if_true: files('ecc.c')) system_ss.add(when: 'CONFIG_FDC', if_true: files('fdc.c')) system_ss.add(when: 'CONFIG_FDC_ISA', if_true: files('fdc-isa.c')) system_ss.add(when: 'CONFIG_FDC_SYSBUS', if_true: files('fdc-sysbus.c')) diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig index 1e08785b832..8568aaa2293 100644 --- a/hw/misc/Kconfig +++ b/hw/misc/Kconfig @@ -74,7 +74,6 @@ config IVSHMEM_DEVICE config ECCMEMCTL bool - select ECC config IMX bool From patchwork Thu Oct 3 14:00:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 832393 Delivered-To: patch@linaro.org Received: by 2002:adf:8b52:0:b0:367:895a:4699 with SMTP id v18csp278398wra; Thu, 3 Oct 2024 07:02:38 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWWhE9ipp311TlEDRTcLBZnmRqrN9KgQp/iVX+/toaYsPQ8QkhZpaJwxu4xTqfzbqeFqOTfSg==@linaro.org X-Google-Smtp-Source: AGHT+IGLalAb7d6/H0Z/NFVURM5VpFtNS04pQXDYxmbE5HSS5i02rNd1Ia3T+GM9MVD7JLz4EZTr X-Received: by 2002:a05:6512:1254:b0:534:5453:ecc8 with SMTP id 2adb3069b0e04-539a07a82f5mr4433456e87.52.1727964158674; Thu, 03 Oct 2024 07:02:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1727964158; cv=none; d=google.com; s=arc-20240605; b=SY0Z7IrOBSHLKMebe/ZZ9shCjO5wjP6EzWu5G89xQ7U6fKdEIFb319Uob0mr71ZqFc Gd73SpD05sdz0GXN/G6qLekljxY+Ju7niHFEJVL97aoFxIaa+76Jb0PyR4Hadg+tyfWj 34WE5kh55hRNKMMmo7Im4LXFhE1/RjxTbpfWbhUjyuquncs52pDyUCW1sxfW4emRTWiQ M0lVKEXDIIoINKfoLnaso4R2X0+c2A6E8rf17IuEysXI++34o2xLir+BbWgYMR9o6YP8 R6cbwdQAGy+zIFt3Rijhz9/a6r8NrhQJap7LhzAQUvf15Y/S2EbW83Ay1KOs48npdKqM 62LA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=/NdtSVHO79et12wC7mRevKMLx4j9u2HZmS8+HJMur2g=; fh=HsE6s3/qhpbH+b4nm3inF74w+gJz7towDOZVR7GQIeM=; b=TzWfdeNXQUjUI0kpKASmLf1NVTXTMJfXEYDRFHLTd6zPEk0crx2Yl+OzeDBb+5fWvq w17O0q70c9cvYttN4AM6it+Dnisae4zv7pYPPU+7ssb9mPOaei1KiTyUIQnyCmxgrvfb aaK3O42Z4vqFr6mZY+9ULwJZ9SjVEoWD5xFkMBWbqlb1f3HiCDMMrP/kqqDihjwcn+XM J27PNGgtUszXQVpI/PZCtQBQAYvi7eV8Dn05NcalzhKLWectf69QcHauxDKSPDBMWy/X d9tnDT/NCoa1xWakkEphUJCHBWMWcd9fco/bxDIDN8j/DP7slrgMKAhTCuiRGzS8Xm5m TDRQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Fik2p2y4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 2adb3069b0e04-539a829e100si516781e87.367.2024.10.03.07.02.38 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 03 Oct 2024 07:02:38 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Fik2p2y4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1swMO8-0004HR-0Y; Thu, 03 Oct 2024 10:01:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1swMNS-00047E-M7 for qemu-devel@nongnu.org; Thu, 03 Oct 2024 10:00:25 -0400 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1swMNQ-0002rn-5l for qemu-devel@nongnu.org; Thu, 03 Oct 2024 10:00:21 -0400 Received: by mail-wm1-x329.google.com with SMTP id 5b1f17b1804b1-42cba6cdf32so10200095e9.1 for ; Thu, 03 Oct 2024 07:00:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1727964017; x=1728568817; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/NdtSVHO79et12wC7mRevKMLx4j9u2HZmS8+HJMur2g=; b=Fik2p2y4e8bfjLBLZoePIJA+OcBr5qffo7kBeyD2APPYg19agQI22883QKHqHZg42T F8TK1u7Pq8t6tZbpdTqpuuYzrErmW3O1+BX4jCWrUA1uswWZhuG0MNsjzON+aF/NAXV+ joXjViGMmuNvEd1aauhcnGRK7lQ+xnN0reLBOWx6GOJ91LPSZD3nFnD98dD8MrSSjB6B 85e84d69BVCQmsfSjoCxGveig83QhybmC99UkQYBH4RebJedGfwfaVC/IUC/tYqy7Is0 YxZuiGJmr/We5MMMA4ka07mqScE5o1rNWspAnZJw31nuarBFjjQPu3FLhyP3ZV3R9+C2 eDMA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1727964017; x=1728568817; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/NdtSVHO79et12wC7mRevKMLx4j9u2HZmS8+HJMur2g=; b=OyVfgnLEWCJ9DOHKf2qyu/NkglAzyUPMGD6iqeJmCfNQBvGgxFZTLsw5otTUCM+As3 vu+U2kfjTh96jKLcXy4DBscSj2dfQR2hzGbThpAZaRzzuJFQ0CC0WLydcu8/gXARNNGp yGCq79j+C5mhzy22PMT3stJUk2XzCpBWLdZbJdC3k4zBXBH4F+XzbpaMFQQEQcOiO+k6 4aBJBoOnDX6C0MNn7WcAvV+qpqmyi2pxQAWW3KwOIBMbO5pd2Q6y+80Gsz8rdxFlhR+Z iXZUv2wlsENfKL6wgLbu3h7a8cSu+jg6iGm/I/6dcVp5s6clAtz3tGsrNziUTMppAA3W xmSA== X-Forwarded-Encrypted: i=1; AJvYcCWlHp+H45oWWl3x+/vCjCM+yI0OzOYQzGSpMn6J836XMAfsskiUf+cmIUK2Nt59FXGyZcAqD63GsAK9@nongnu.org X-Gm-Message-State: AOJu0YxvzIzL7COQhxAJdqmvTHBybO/b4xVCpJY42gg5CMiAEYSodt4p ywu34h+Jv3L/zmZ0O7mD8RGrzBX5z0adcLuxkOPRuePbEyIC3H9d9QvEc45gcRY= X-Received: by 2002:a05:600c:4f10:b0:42c:b5f1:4508 with SMTP id 5b1f17b1804b1-42f778f360emr45374425e9.23.1727964016820; Thu, 03 Oct 2024 07:00:16 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37d0822bc38sm1340255f8f.45.2024.10.03.07.00.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Oct 2024 07:00:16 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Guenter Roeck , Paolo Bonzini Subject: [PATCH v2 6/6] vl.c: Remove pxa2xx-specific -portrait and -rotate options Date: Thu, 3 Oct 2024 15:00:10 +0100 Message-Id: <20241003140010.1653808-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241003140010.1653808-1-peter.maydell@linaro.org> References: <20241003140010.1653808-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The ``-portrait`` and ``-rotate`` options were documented as only working with the PXA LCD device, and all the machine types using that display device were removed in 9.2. These options were intended to simulate a mobile device being rotated by the user, and had three effects: * the display output was rotated by 90, 180 or 270 degrees (implemented in the PXA display device models) * the mouse/trackpad input was rotated the opposite way (implemented in generic code) * the machine model would signal to the guest about its orientation (implemented by e.g. the spitz machine model) Of these three things, the input-rotation was coded without being restricted to boards which supported the full set of device-rotation handling, so in theory the options were usable on other machine models with odd effects (rotating input but not display output). But this was never intended or documented behaviour, so we can reasonably drop these command line arguments without a formal deprecate-and-drop cycle for them. Remove the options, and their implementation and documentation. Describe the removal in removed-features.rst. Signed-off-by: Peter Maydell --- docs/about/removed-features.rst | 22 ++++++++++++++++++++ include/sysemu/sysemu.h | 1 - system/globals.c | 1 - system/vl.c | 11 ---------- ui/input.c | 36 --------------------------------- qemu-options.hx | 16 --------------- 6 files changed, 22 insertions(+), 65 deletions(-) diff --git a/docs/about/removed-features.rst b/docs/about/removed-features.rst index 6e96cd067fa..567e653e1d3 100644 --- a/docs/about/removed-features.rst +++ b/docs/about/removed-features.rst @@ -517,6 +517,28 @@ The virtio-blk SCSI passthrough feature is a legacy VIRTIO feature. VIRTIO 1.0 and later do not support it because the virtio-scsi device was introduced for full SCSI support. Use virtio-scsi instead when SCSI passthrough is required. +``-portrait`` and ``-rotate`` (since 9.2) +''''''''''''''''''''''''''''''''''''''''' + +The ``-portrait`` and ``-rotate`` options were documented as only +working with the PXA LCD device, and all the machine types using +that display device were removed in 9.2, so these options also +have been dropped. + +These options were intended to simulate a mobile device being +rotated by the user, and had three effects: + +* the display output was rotated by 90, 180 or 270 degrees +* the mouse/trackpad input was rotated the opposite way +* the machine model would signal to the guest about its + orientation + +Of these three things, the input-rotation was coded without being +restricted to boards which supported the full set of device-rotation +handling, so in theory the options were usable on other machine models +to produce an odd effect (rotating input but not display output). But +this was never intended or documented behaviour, so we have dropped +the options along with the machine models they were intended for. User-mode emulator command line arguments ----------------------------------------- diff --git a/include/sysemu/sysemu.h b/include/sysemu/sysemu.h index 5b4397eeb80..7ec419ce132 100644 --- a/include/sysemu/sysemu.h +++ b/include/sysemu/sysemu.h @@ -41,7 +41,6 @@ extern int graphic_height; extern int graphic_depth; extern int display_opengl; extern const char *keyboard_layout; -extern int graphic_rotate; extern int old_param; extern uint8_t *boot_splash_filedata; extern bool enable_mlock; diff --git a/system/globals.c b/system/globals.c index d602a04fa28..84ce943ac96 100644 --- a/system/globals.c +++ b/system/globals.c @@ -40,7 +40,6 @@ int autostart = 1; int vga_interface_type = VGA_NONE; bool vga_interface_created; Chardev *parallel_hds[MAX_PARALLEL_PORTS]; -int graphic_rotate; QEMUOptionRom option_rom[MAX_OPTION_ROMS]; int nb_option_roms; int old_param; diff --git a/system/vl.c b/system/vl.c index fe547ca47c2..e83b3b2608b 100644 --- a/system/vl.c +++ b/system/vl.c @@ -2910,17 +2910,6 @@ void qemu_init(int argc, char **argv) nographic = true; dpy.type = DISPLAY_TYPE_NONE; break; - case QEMU_OPTION_portrait: - graphic_rotate = 90; - break; - case QEMU_OPTION_rotate: - graphic_rotate = strtol(optarg, (char **) &optarg, 10); - if (graphic_rotate != 0 && graphic_rotate != 90 && - graphic_rotate != 180 && graphic_rotate != 270) { - error_report("only 90, 180, 270 deg rotation is available"); - exit(1); - } - break; case QEMU_OPTION_kernel: qdict_put_str(machine_opts_dict, "kernel", optarg); break; diff --git a/ui/input.c b/ui/input.c index dc745860f48..7ddefebc439 100644 --- a/ui/input.c +++ b/ui/input.c @@ -174,37 +174,6 @@ void qmp_input_send_event(const char *device, qemu_input_event_sync(); } -static int qemu_input_transform_invert_abs_value(int value) -{ - return (int64_t)INPUT_EVENT_ABS_MAX - value + INPUT_EVENT_ABS_MIN; -} - -static void qemu_input_transform_abs_rotate(InputEvent *evt) -{ - InputMoveEvent *move = evt->u.abs.data; - switch (graphic_rotate) { - case 90: - if (move->axis == INPUT_AXIS_X) { - move->axis = INPUT_AXIS_Y; - } else if (move->axis == INPUT_AXIS_Y) { - move->axis = INPUT_AXIS_X; - move->value = qemu_input_transform_invert_abs_value(move->value); - } - break; - case 180: - move->value = qemu_input_transform_invert_abs_value(move->value); - break; - case 270: - if (move->axis == INPUT_AXIS_X) { - move->axis = INPUT_AXIS_Y; - move->value = qemu_input_transform_invert_abs_value(move->value); - } else if (move->axis == INPUT_AXIS_Y) { - move->axis = INPUT_AXIS_X; - } - break; - } -} - static void qemu_input_event_trace(QemuConsole *src, InputEvent *evt) { const char *name; @@ -340,11 +309,6 @@ void qemu_input_event_send_impl(QemuConsole *src, InputEvent *evt) qemu_input_event_trace(src, evt); - /* pre processing */ - if (graphic_rotate && (evt->type == INPUT_EVENT_KIND_ABS)) { - qemu_input_transform_abs_rotate(evt); - } - /* send event */ s = qemu_input_find_handler(1 << evt->type, src); if (!s) { diff --git a/qemu-options.hx b/qemu-options.hx index d94e2cbbaeb..d013742e4a3 100644 --- a/qemu-options.hx +++ b/qemu-options.hx @@ -2377,22 +2377,6 @@ SRST pick the first available. (Since 2.9) ERST -DEF("portrait", 0, QEMU_OPTION_portrait, - "-portrait rotate graphical output 90 deg left (only PXA LCD)\n", - QEMU_ARCH_ALL) -SRST -``-portrait`` - Rotate graphical output 90 deg left (only PXA LCD). -ERST - -DEF("rotate", HAS_ARG, QEMU_OPTION_rotate, - "-rotate rotate graphical output some deg left (only PXA LCD)\n", - QEMU_ARCH_ALL) -SRST -``-rotate deg`` - Rotate graphical output some deg left (only PXA LCD). -ERST - DEF("vga", HAS_ARG, QEMU_OPTION_vga, "-vga [std|cirrus|vmware|qxl|xenfb|tcx|cg3|virtio|none]\n" " select video card type\n", QEMU_ARCH_ALL)