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Add two new UFS phy modes to the phy framework so that this is possible. One such platform that requires this is Pixel 6 which uses the gs101 SoC. Signed-off-by: Peter Griffin --- include/linux/phy/phy.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h index 03cd5bae92d3..1874e55e2bb9 100644 --- a/include/linux/phy/phy.h +++ b/include/linux/phy/phy.h @@ -42,7 +42,9 @@ enum phy_mode { PHY_MODE_MIPI_DPHY, PHY_MODE_SATA, PHY_MODE_LVDS, - PHY_MODE_DP + PHY_MODE_DP, + PHY_MODE_UFS_HIBERN8_ENTER, + PHY_MODE_UFS_HIBERN8_EXIT, }; enum phy_media { From patchwork Wed Oct 2 20:15:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Griffin X-Patchwork-Id: 832334 Received: from mail-wm1-f54.google.com (mail-wm1-f54.google.com [209.85.128.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 71B6021730E for ; Wed, 2 Oct 2024 20:16:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Wed, 02 Oct 2024 13:16:16 -0700 (PDT) Received: from gpeter-l.lan ([145.224.66.77]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37cd564d2e8sm14850600f8f.18.2024.10.02.13.16.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Oct 2024 13:16:16 -0700 (PDT) From: Peter Griffin To: vkoul@kernel.org, kishon@kernel.org, krzysztof.kozlowski@linaro.org, alim.akhtar@samsung.com Cc: tudor.ambarus@linaro.org, andre.draszik@linaro.org, kernel-team@android.com, willmcvicker@google.com, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, Peter Griffin Subject: [PATCH 3/3] phy: samsung: gs101-ufs: Add hibern8 enter and exit specific tuning values Date: Wed, 2 Oct 2024 21:15:55 +0100 Message-ID: <20241002201555.3332138-4-peter.griffin@linaro.org> X-Mailer: git-send-email 2.46.1.824.gd892dcdcdd-goog In-Reply-To: <20241002201555.3332138-1-peter.griffin@linaro.org> References: <20241002201555.3332138-1-peter.griffin@linaro.org> Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add the gs101 specific phy calibration values that need to be programmed when entering and exiting hibern8 state. Signed-off-by: Peter Griffin --- drivers/phy/samsung/phy-gs101-ufs.c | 31 ++++++++++++++++++++++++++--- 1 file changed, 28 insertions(+), 3 deletions(-) diff --git a/drivers/phy/samsung/phy-gs101-ufs.c b/drivers/phy/samsung/phy-gs101-ufs.c index 17b798da5b57..5363d8be6c76 100644 --- a/drivers/phy/samsung/phy-gs101-ufs.c +++ b/drivers/phy/samsung/phy-gs101-ufs.c @@ -108,10 +108,35 @@ static const struct samsung_ufs_phy_cfg tensor_gs101_post_pwr_hs_config[] = { END_UFS_PHY_CFG, }; +static const struct samsung_ufs_phy_cfg tensor_gs101_post_h8_enter[] = { + PHY_TRSV_REG_CFG_GS101(0x262, 0x08, PWR_MODE_ANY), + PHY_TRSV_REG_CFG_GS101(0x265, 0x0A, PWR_MODE_ANY), + PHY_COMN_REG_CFG(0x1, 0x8, PWR_MODE_ANY), + PHY_COMN_REG_CFG(0x0, 0x86, PWR_MODE_ANY), + PHY_COMN_REG_CFG(0x8, 0x60, PWR_MODE_HS_ANY), + PHY_TRSV_REG_CFG_GS101(0x222, 0x08, PWR_MODE_HS_ANY), + PHY_TRSV_REG_CFG_GS101(0x246, 0x01, PWR_MODE_HS_ANY), + END_UFS_PHY_CFG, +}; + +static const struct samsung_ufs_phy_cfg tensor_gs101_pre_h8_exit[] = { + PHY_COMN_REG_CFG(0x0, 0xC6, PWR_MODE_ANY), + PHY_COMN_REG_CFG(0x1, 0x0C, PWR_MODE_ANY), + PHY_TRSV_REG_CFG_GS101(0x262, 0x00, PWR_MODE_ANY), + PHY_TRSV_REG_CFG_GS101(0x265, 0x00, PWR_MODE_ANY), + PHY_COMN_REG_CFG(0x8, 0xE0, PWR_MODE_HS_ANY), + PHY_TRSV_REG_CFG_GS101(0x246, 0x03, PWR_MODE_HS_ANY), + PHY_TRSV_REG_CFG_GS101(0x222, 0x18, PWR_MODE_HS_ANY), + END_UFS_PHY_CFG, +}; + + static const struct samsung_ufs_phy_cfg *tensor_gs101_ufs_phy_cfgs[CFG_TAG_MAX] = { - [CFG_PRE_INIT] = tensor_gs101_pre_init_cfg, - [CFG_PRE_PWR_HS] = tensor_gs101_pre_pwr_hs_config, - [CFG_POST_PWR_HS] = tensor_gs101_post_pwr_hs_config, + [CFG_PRE_INIT] = tensor_gs101_pre_init_cfg, + [CFG_PRE_PWR_HS] = tensor_gs101_pre_pwr_hs_config, + [CFG_POST_PWR_HS] = tensor_gs101_post_pwr_hs_config, + [CFG_POST_HIBERN8_ENTER] = tensor_gs101_post_h8_enter, + [CFG_PRE_HIBERN8_EXIT] = tensor_gs101_pre_h8_exit, }; static const char * const tensor_gs101_ufs_phy_clks[] = {