From patchwork Fri Sep 27 06:52:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sricharan Ramabadhran X-Patchwork-Id: 831361 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DA233171089; Fri, 27 Sep 2024 06:53:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727420019; cv=none; b=gPnb68/+bt5JDKhU8RMCoVAd2QoYALORV+ilpR6KrZX92C1GJYHEe0cUJ2VEB5uC/gR/PggbyDbn0A2ztPg8JOAUJHB4fDhxdtFHxsd1TDU0/Rr3OYFIDISHm+f5HLVI6NVJNDuKtJIL2z69OUYWUou5LxzRK4E2Nk4jXuX2ZLY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727420019; c=relaxed/simple; bh=maHaRC7G4ApxMvy0j9pfBw3Wy0L29px+aMyHk75BtA8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=oc0TxqfGwLl5f9Ac1fUolk4xuQKsLrwW54wkqZHMLxwAGlgdzsuLMM2xUfNb83E39Eq34k46Weuj0QeYTfRRliWpkiGKjfUDp/gLv2MKkC1jS1JSLwVLoneWznYd+HzJX9c7wmbSRzruQmsmFjMccRp4DjLsnwr5bwe+4+HIhWc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=iNvngJtH; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="iNvngJtH" Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 48R6PIx1003387; Fri, 27 Sep 2024 06:53:18 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= jNH7SqgEIYHSRpmTRXNvTGNuQC+ckV8noxzw3gnEVm8=; b=iNvngJtHKPdjKdTd Qb7XyrC6iEIWNx2XYEV3B4rZLNMiDQUl2NnBpcw0B+JnD48R/l++EGD8Og9K6Cgh FStSgdB8xRNNdleTNXxNyNKGnt1RBQj6WRmt+t05v+k1v1rQQLDS5UsVaVjEzJXq Kk/DDOGUxLqSKlMnrSW6TRB9fys3UcMZWirxl9VLu/YNNfaL+EENGAX8IJfHnTav FLHmnFDXi9BCh9V2Wr0Ey1w1zg00fJ6UaBDp9V8Rhn90z5Bhiq2bIciy1cI6cnoM yQt7J9pD9fOPLWcOgkJXIHhcGj1rNJo8pduRmprFScF5gzBWsY8fdxX54yaD/nOq 17lEfg== Received: from nalasppmta01.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 41snqyt2ng-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 27 Sep 2024 06:53:17 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 48R6rGOW016235 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 27 Sep 2024 06:53:16 GMT Received: from hu-srichara-blr.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 26 Sep 2024 23:53:09 -0700 From: Sricharan R To: , , , , , , , , , , , , , , , , , , , , CC: , Subject: [PATCH V2 1/9] clk: qcom: clk-alpha-pll: Add NSS HUAYRA ALPHA PLL support for ipq9574 Date: Fri, 27 Sep 2024 12:22:36 +0530 Message-ID: <20240927065244.3024604-2-quic_srichara@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240927065244.3024604-1-quic_srichara@quicinc.com> References: <20240927065244.3024604-1-quic_srichara@quicinc.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: viXawydf8PfFJK9fSPVEQs72CKwFF2oJ X-Proofpoint-ORIG-GUID: viXawydf8PfFJK9fSPVEQs72CKwFF2oJ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 adultscore=0 bulkscore=0 phishscore=0 mlxlogscore=863 spamscore=0 lowpriorityscore=0 clxscore=1015 mlxscore=0 malwarescore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2408220000 definitions=main-2409270046 From: Devi Priya Add support for NSS Huayra alpha pll found on ipq9574 SoCs. Programming sequence is the same as that of Huayra type Alpha PLL, so we can re-use the same. Reviewed-by: Dmitry Baryshkov Signed-off-by: Devi Priya --- [v2] Picked from previous post [1] [1] https://patchwork.kernel.org/project/linux-clk/patch/20240626143302.810632-2-quic_devipriy@quicinc.com/ drivers/clk/qcom/clk-alpha-pll.c | 11 +++++++++++ drivers/clk/qcom/clk-alpha-pll.h | 1 + 2 files changed, 12 insertions(+) diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index 019713c38f25..bbf57444118a 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -267,6 +267,17 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = { [PLL_OFF_OPMODE] = 0x30, [PLL_OFF_STATUS] = 0x3c, }, + [CLK_ALPHA_PLL_TYPE_NSS_HUAYRA] = { + [PLL_OFF_L_VAL] = 0x04, + [PLL_OFF_ALPHA_VAL] = 0x08, + [PLL_OFF_TEST_CTL] = 0x0c, + [PLL_OFF_TEST_CTL_U] = 0x10, + [PLL_OFF_USER_CTL] = 0x14, + [PLL_OFF_CONFIG_CTL] = 0x18, + [PLL_OFF_CONFIG_CTL_U] = 0x1c, + [PLL_OFF_STATUS] = 0x20, + }, + }; EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h index 55eca04b23a1..c6d1b8429f95 100644 --- a/drivers/clk/qcom/clk-alpha-pll.h +++ b/drivers/clk/qcom/clk-alpha-pll.h @@ -32,6 +32,7 @@ enum { CLK_ALPHA_PLL_TYPE_BRAMMO_EVO, CLK_ALPHA_PLL_TYPE_STROMER, CLK_ALPHA_PLL_TYPE_STROMER_PLUS, + CLK_ALPHA_PLL_TYPE_NSS_HUAYRA, CLK_ALPHA_PLL_TYPE_MAX, }; From patchwork Fri Sep 27 06:52:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sricharan Ramabadhran X-Patchwork-Id: 831360 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ED2F6183CAB; Fri, 27 Sep 2024 06:53:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727420026; cv=none; b=P3kwq1eejGU9iE2fgWSz3nQ1cpkIfuhWHjNA8V0MJiAmMzMCpAy8X2/hXE9uFcyn1BYkPU7Vx0MMjCL/434e5dTllW7I/fn4ykkkoyLDyinYwYOdTpMU7C3ZMc/T3LV6kyWPkxKNDpjOjbBZbi6hYbRECiXCkZU5g+DwN4yQss8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727420026; c=relaxed/simple; bh=0mzCFLKo5PuESdsFphgBHrHCPKhZKAKBtGHLTY4PwdQ=; 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Fri, 27 Sep 2024 06:53:30 GMT Received: from hu-srichara-blr.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 26 Sep 2024 23:53:23 -0700 From: Sricharan R To: , , , , , , , , , , , , , , , , , , , , CC: , Subject: [PATCH V2 3/9] dt-bindings: pinctrl: qcom: add IPQ5424 pinctrl Date: Fri, 27 Sep 2024 12:22:38 +0530 Message-ID: <20240927065244.3024604-4-quic_srichara@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240927065244.3024604-1-quic_srichara@quicinc.com> References: <20240927065244.3024604-1-quic_srichara@quicinc.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: DrJC1qsvgKF_zc88bblf0PpAEaBbkag3 X-Proofpoint-GUID: DrJC1qsvgKF_zc88bblf0PpAEaBbkag3 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 mlxlogscore=999 spamscore=0 lowpriorityscore=0 adultscore=0 mlxscore=0 suspectscore=0 malwarescore=0 phishscore=0 impostorscore=0 clxscore=1015 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2408220000 definitions=main-2409270046 From: Sricharan Ramabadhran Add device tree bindings for IPQ5424 TLMM block. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Sricharan Ramabadhran --- [v2] Removed Krzysztof from maintainer list, fixed maxitems, added Krzysztof reviewed-by tag. .../bindings/pinctrl/qcom,ipq5424-tlmm.yaml | 114 ++++++++++++++++++ 1 file changed, 114 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,ipq5424-tlmm.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq5424-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,ipq5424-tlmm.yaml new file mode 100644 index 000000000000..5e64a232fc7a --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq5424-tlmm.yaml @@ -0,0 +1,114 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,ipq5424-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm IPQ5424 TLMM pin controller + +maintainers: + - Bjorn Andersson + +description: + Top Level Mode Multiplexer pin controller in Qualcomm IPQ5424 SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,ipq5424-tlmm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 25 + + gpio-line-names: + maxItems: 50 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-ipq5424-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-ipq5424-tlmm-state" + additionalProperties: false + +$defs: + qcom-ipq5424-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + pattern: "^gpio([0-9]|[1-4][0-9])$" + minItems: 1 + maxItems: 50 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + + enum: [ atest_char, atest_char0, atest_char1, atest_char2, atest_char3, + atest_tic, audio_pri, audio_pri0, audio_pri1, audio_sec, + audio_sec0, audio_sec1, core_voltage, cri_trng0, cri_trng1, + cri_trng2, cri_trng3, cxc_clk, cxc_data, dbg_out, gcc_plltest, + gcc_tlmm, gpio, i2c0_scl, i2c0_sda, i2c1_scl, i2c1_sda, i2c11, + mac0, mac1, mdc_mst, mdc_slv, mdio_mst, mdio_slv, pcie0_clk, + pcie0_wake, pcie1_clk, pcie1_wake, pcie2_clk, pcie2_wake, + pcie3_clk, pcie3_wake, pll_test, prng_rosc0, prng_rosc1, + prng_rosc2, prng_rosc3, PTA0_0, PTA0_1, PTA0_2, PTA10, PTA11, + pwm0, pwm1, pwm2, qdss_cti_trig_in_a0, qdss_cti_trig_out_a0, + qdss_cti_trig_in_a1, qdss_cti_trig_out_a1, qdss_cti_trig_in_b0, + qdss_cti_trig_out_b0, qdss_cti_trig_in_b1, qdss_cti_trig_out_b1, + qdss_traceclk_a, qdss_tracectl_a, qdss_tracedata_a, qspi_clk, + qspi_cs, qspi_data, resout, rx0, rx1, rx2, sdc_clk, sdc_cmd, + sdc_data, spi0, spi1, spi10, spi11, tsens_max, uart0, uart1, + wci_txd, wci_rxd, wsi_clk, wsi_data ] + + required: + - pins + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include + + tlmm: pinctrl@1000000 { + compatible = "qcom,ipq5424-tlmm"; + reg = <0x01000000 0x300000>; + gpio-controller; + #gpio-cells = <0x2>; + gpio-ranges = <&tlmm 0 0 50>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <0x2>; + + uart1_pins: uart1-state { + pins = "gpio43", "gpio44"; + function = "uart1"; + drive-strength = <8>; + bias-pull-up; + }; + }; From patchwork Fri Sep 27 06:52:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sricharan Ramabadhran X-Patchwork-Id: 831359 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 39DC015D5C1; Fri, 27 Sep 2024 06:54:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727420046; cv=none; b=EAEKE+R9mi21Ua3khFEzcfvfrygURN8ZX2OccReHvcFttl8q5V2k4/nRhsKpd/czkNf8/c12qWWNM5yMX+2y9fU0ndethFPb2/8B3jfolAY4Q8sr0O0uZvnnTsa+eEWeg9u1bnnJ9B/nJ1i2IJjNmZOWbOtYhDx4cU4tRrlsszE= ARC-Message-Signature: i=1; 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Fri, 27 Sep 2024 06:53:44 GMT Received: from hu-srichara-blr.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 26 Sep 2024 23:53:37 -0700 From: Sricharan R To: , , , , , , , , , , , , , , , , , , , , CC: , Subject: [PATCH V2 5/9] pinctrl: qcom: Introduce IPQ5424 TLMM driver Date: Fri, 27 Sep 2024 12:22:40 +0530 Message-ID: <20240927065244.3024604-6-quic_srichara@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240927065244.3024604-1-quic_srichara@quicinc.com> References: <20240927065244.3024604-1-quic_srichara@quicinc.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: XjMBd0blnvqBChVr4px-cnQYPQKBjyp0 X-Proofpoint-ORIG-GUID: XjMBd0blnvqBChVr4px-cnQYPQKBjyp0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 phishscore=0 mlxscore=0 impostorscore=0 spamscore=0 malwarescore=0 suspectscore=0 priorityscore=1501 lowpriorityscore=0 mlxlogscore=999 clxscore=1015 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2408220000 definitions=main-2409270046 From: Sricharan Ramabadhran The IPQ5424 SoC comes with a TLMM block, like all other Qualcomm platforms, so add a driver for it. Co-developed-by: Varadarajan Narayanan Signed-off-by: Varadarajan Narayanan Signed-off-by: Sricharan Ramabadhran --- [v2] Added Co-developed by, added ARM64 || COMPILE test in Kconfig drivers/pinctrl/qcom/Kconfig.msm | 9 + drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-ipq5424.c | 792 +++++++++++++++++++++++++ 3 files changed, 802 insertions(+) create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq5424.c diff --git a/drivers/pinctrl/qcom/Kconfig.msm b/drivers/pinctrl/qcom/Kconfig.msm index 8fe459d082ed..9738448f2a8a 100644 --- a/drivers/pinctrl/qcom/Kconfig.msm +++ b/drivers/pinctrl/qcom/Kconfig.msm @@ -46,6 +46,15 @@ config PINCTRL_IPQ5332 Qualcomm Technologies Inc TLMM block found on the Qualcomm Technologies Inc IPQ5332 platform. +config PINCTRL_IPQ5424 + tristate "Qualcomm Technologies, Inc. IPQ5424 pin controller driver" + depends on ARM64 || COMPILE_TEST + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for + the Qualcomm Technologies Inc. TLMM block found on the + Qualcomm Technologies Inc. IPQ5424 platform. Select this for + IPQ5424. + config PINCTRL_IPQ8074 tristate "Qualcomm Technologies, Inc. IPQ8074 pin controller driver" depends on ARM64 || COMPILE_TEST diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index eb04297b6388..5b4712146db5 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -7,6 +7,7 @@ obj-$(CONFIG_PINCTRL_IPQ4019) += pinctrl-ipq4019.o obj-$(CONFIG_PINCTRL_IPQ5018) += pinctrl-ipq5018.o obj-$(CONFIG_PINCTRL_IPQ8064) += pinctrl-ipq8064.o obj-$(CONFIG_PINCTRL_IPQ5332) += pinctrl-ipq5332.o +obj-$(CONFIG_PINCTRL_IPQ5424) += pinctrl-ipq5424.o obj-$(CONFIG_PINCTRL_IPQ8074) += pinctrl-ipq8074.o obj-$(CONFIG_PINCTRL_IPQ6018) += pinctrl-ipq6018.o obj-$(CONFIG_PINCTRL_IPQ9574) += pinctrl-ipq9574.o diff --git a/drivers/pinctrl/qcom/pinctrl-ipq5424.c b/drivers/pinctrl/qcom/pinctrl-ipq5424.c new file mode 100644 index 000000000000..796299cd2e4e --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-ipq5424.c @@ -0,0 +1,792 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2016-2018,2020 The Linux Foundation. All rights reserved. + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include + +#include "pinctrl-msm.h" + +#define REG_SIZE 0x1000 +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ + { \ + .grp = PINCTRL_PINGROUP("gpio" #id, \ + gpio##id##_pins, \ + ARRAY_SIZE(gpio##id##_pins)), \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9 \ + }, \ + .nfuncs = 10, \ + .ctl_reg = REG_SIZE * id, \ + .io_reg = 0x4 + REG_SIZE * id, \ + .intr_cfg_reg = 0x8 + REG_SIZE * id, \ + .intr_status_reg = 0xc + REG_SIZE * id, \ + .intr_target_reg = 0x8 + REG_SIZE * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 3, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +static const struct pinctrl_pin_desc ipq5424_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); + +enum ipq5424_functions { + msm_mux_atest_char, + msm_mux_atest_char0, + msm_mux_atest_char1, + msm_mux_atest_char2, + msm_mux_atest_char3, + msm_mux_atest_tic, + msm_mux_audio_pri, + msm_mux_audio_pri0, + msm_mux_audio_pri1, + msm_mux_audio_sec, + msm_mux_audio_sec0, + msm_mux_audio_sec1, + msm_mux_core_voltage, + msm_mux_cri_trng0, + msm_mux_cri_trng1, + msm_mux_cri_trng2, + msm_mux_cri_trng3, + msm_mux_cxc_clk, + msm_mux_cxc_data, + msm_mux_dbg_out, + msm_mux_gcc_plltest, + msm_mux_gcc_tlmm, + msm_mux_gpio, + msm_mux_i2c0_scl, + msm_mux_i2c0_sda, + msm_mux_i2c1_scl, + msm_mux_i2c1_sda, + msm_mux_i2c11, + msm_mux_mac0, + msm_mux_mac1, + msm_mux_mdc_mst, + msm_mux_mdc_slv, + msm_mux_mdio_mst, + msm_mux_mdio_slv, + msm_mux_pcie0_clk, + msm_mux_pcie0_wake, + msm_mux_pcie1_clk, + msm_mux_pcie1_wake, + msm_mux_pcie2_clk, + msm_mux_pcie2_wake, + msm_mux_pcie3_clk, + msm_mux_pcie3_wake, + msm_mux_pll_test, + msm_mux_prng_rosc0, + msm_mux_prng_rosc1, + msm_mux_prng_rosc2, + msm_mux_prng_rosc3, + msm_mux_PTA0_0, + msm_mux_PTA0_1, + msm_mux_PTA0_2, + msm_mux_PTA10, + msm_mux_PTA11, + msm_mux_pwm0, + msm_mux_pwm1, + msm_mux_pwm2, + msm_mux_qdss_cti_trig_in_a0, + msm_mux_qdss_cti_trig_out_a0, + msm_mux_qdss_cti_trig_in_a1, + msm_mux_qdss_cti_trig_out_a1, + msm_mux_qdss_cti_trig_in_b0, + msm_mux_qdss_cti_trig_out_b0, + msm_mux_qdss_cti_trig_in_b1, + msm_mux_qdss_cti_trig_out_b1, + msm_mux_qdss_traceclk_a, + msm_mux_qdss_tracectl_a, + msm_mux_qdss_tracedata_a, + msm_mux_qspi_clk, + msm_mux_qspi_cs, + msm_mux_qspi_data, + msm_mux_resout, + msm_mux_rx0, + msm_mux_rx1, + msm_mux_rx2, + msm_mux_sdc_clk, + msm_mux_sdc_cmd, + msm_mux_sdc_data, + msm_mux_spi0, + msm_mux_spi1, + msm_mux_spi10, + msm_mux_spi11, + msm_mux_tsens_max, + msm_mux_uart0, + msm_mux_uart1, + msm_mux_wci_txd, + msm_mux_wci_rxd, + msm_mux_wsi_clk, + msm_mux_wsi_data, + msm_mux__, +}; + +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", +}; + +static const char * const sdc_data_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", +}; + +static const char * const qspi_data_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", +}; + +static const char * const pwm2_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", +}; + +static const char * const wci_txd_groups[] = { + "gpio0", "gpio1", "gpio8", "gpio10", "gpio11", "gpio40", "gpio41", +}; + +static const char * const wci_rxd_groups[] = { + "gpio0", "gpio1", "gpio8", "gpio10", "gpio11", "gpio40", "gpio41", +}; + +static const char * const sdc_cmd_groups[] = { + "gpio4", +}; + +static const char * const qspi_cs_groups[] = { + "gpio4", +}; + +static const char * const qdss_cti_trig_out_a1_groups[] = { + "gpio27", +}; + +static const char * const sdc_clk_groups[] = { + "gpio5", +}; + +static const char * const qspi_clk_groups[] = { + "gpio5", +}; + +static const char * const spi0_groups[] = { + "gpio6", "gpio7", "gpio8", "gpio9", +}; + +static const char * const pwm1_groups[] = { + "gpio6", "gpio7", "gpio8", "gpio9", +}; + +static const char * const cri_trng0_groups[] = { + "gpio6", +}; + +static const char * const qdss_tracedata_a_groups[] = { + "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", + "gpio13", "gpio14", "gpio15", "gpio20", "gpio21", "gpio36", "gpio37", + "gpio38", "gpio39", +}; + +static const char * const cri_trng1_groups[] = { + "gpio7", +}; + +static const char * const cri_trng2_groups[] = { + "gpio8", +}; + +static const char * const cri_trng3_groups[] = { + "gpio9", +}; + +static const char * const uart0_groups[] = { + "gpio10", "gpio11", "gpio12", "gpio13", +}; + +static const char * const pwm0_groups[] = { + "gpio10", "gpio11", "gpio12", "gpio13", +}; + +static const char * const prng_rosc0_groups[] = { + "gpio12", +}; + +static const char * const prng_rosc1_groups[] = { + "gpio13", +}; + +static const char * const i2c0_scl_groups[] = { + "gpio14", +}; + +static const char * const tsens_max_groups[] = { + "gpio14", +}; + +static const char * const prng_rosc2_groups[] = { + "gpio14", +}; + +static const char * const i2c0_sda_groups[] = { + "gpio15", +}; + +static const char * const prng_rosc3_groups[] = { + "gpio15", +}; + +static const char * const core_voltage_groups[] = { + "gpio16", "gpio17", +}; + +static const char * const i2c1_scl_groups[] = { + "gpio16", +}; + +static const char * const i2c1_sda_groups[] = { + "gpio17", +}; + +static const char * const mdc_slv_groups[] = { + "gpio20", +}; + +static const char * const atest_char0_groups[] = { + "gpio20", +}; + +static const char * const mdio_slv_groups[] = { + "gpio21", +}; + +static const char * const atest_char1_groups[] = { + "gpio21", +}; + +static const char * const mdc_mst_groups[] = { + "gpio22", +}; + +static const char * const atest_char2_groups[] = { + "gpio22", +}; + +static const char * const mdio_mst_groups[] = { + "gpio23", +}; + +static const char * const atest_char3_groups[] = { + "gpio23", +}; + +static const char * const pcie0_clk_groups[] = { + "gpio24", +}; + +static const char * const PTA10_groups[] = { + "gpio24", "gpio26", "gpio27", +}; + +static const char * const mac0_groups[] = { + "gpio24", "gpio26", +}; + +static const char * const atest_char_groups[] = { + "gpio24", +}; + +static const char * const pcie0_wake_groups[] = { + "gpio26", +}; + +static const char * const pcie1_clk_groups[] = { + "gpio27", +}; + +static const char * const i2c11_groups[] = { + "gpio27", "gpio29", +}; + +static const char * const pcie1_wake_groups[] = { + "gpio29", +}; + +static const char * const pcie2_clk_groups[] = { + "gpio30", +}; + +static const char * const mac1_groups[] = { + "gpio30", "gpio32", +}; + +static const char * const pcie2_wake_groups[] = { + "gpio32", +}; + +static const char * const PTA11_groups[] = { + "gpio30", "gpio32", "gpio33", +}; + +static const char * const audio_pri0_groups[] = { + "gpio32", "gpio32", +}; + +static const char * const pcie3_clk_groups[] = { + "gpio33", +}; + +static const char * const audio_pri1_groups[] = { + "gpio33", "gpio33", +}; + +static const char * const pcie3_wake_groups[] = { + "gpio35", +}; + +static const char * const audio_sec1_groups[] = { + "gpio35", "gpio35", +}; + +static const char * const audio_pri_groups[] = { + "gpio36", "gpio37", "gpio38", "gpio39", +}; + +static const char * const spi1_groups[] = { + "gpio11", "gpio36", "gpio37", "gpio38", "gpio46", +}; + +static const char * const audio_sec0_groups[] = { + "gpio36", "gpio36", +}; + +static const char * const rx1_groups[] = { + "gpio38", "gpio46", +}; + +static const char * const pll_test_groups[] = { + "gpio38", +}; + +static const char * const dbg_out_groups[] = { + "gpio46", +}; + +static const char * const PTA0_0_groups[] = { + "gpio40", +}; + +static const char * const atest_tic_groups[] = { + "gpio40", +}; + +static const char * const PTA0_1_groups[] = { + "gpio41", +}; + +static const char * const cxc_data_groups[] = { + "gpio41", +}; + +static const char * const PTA0_2_groups[] = { + "gpio42", +}; + +static const char * const cxc_clk_groups[] = { + "gpio42", +}; + +static const char * const uart1_groups[] = { + "gpio43", "gpio44", +}; + +static const char * const audio_sec_groups[] = { + "gpio45", "gpio46", "gpio47", "gpio48", +}; + +static const char * const gcc_plltest_groups[] = { + "gpio43", "gpio45", +}; + +static const char * const gcc_tlmm_groups[] = { + "gpio44", +}; + +static const char * const qdss_cti_trig_out_b1_groups[] = { + "gpio33", +}; + +static const char * const rx0_groups[] = { + "gpio39", "gpio47", +}; + +static const char * const qdss_traceclk_a_groups[] = { + "gpio45", +}; + +static const char * const qdss_tracectl_a_groups[] = { + "gpio46", +}; + +static const char * const qdss_cti_trig_out_a0_groups[] = { + "gpio24", +}; + +static const char * const qdss_cti_trig_in_a0_groups[] = { + "gpio26", +}; + +static const char * const resout_groups[] = { + "gpio49", +}; + +static const char * const qdss_cti_trig_in_a1_groups[] = { + "gpio29", +}; + +static const char * const qdss_cti_trig_out_b0_groups[] = { + "gpio30", +}; + +static const char * const qdss_cti_trig_in_b0_groups[] = { + "gpio32", +}; + +static const char * const qdss_cti_trig_in_b1_groups[] = { + "gpio35", +}; + +static const char * const spi10_groups[] = { + "gpio45", "gpio47", "gpio48", +}; + +static const char * const spi11_groups[] = { + "gpio10", "gpio12", "gpio13", +}; + +static const char * const wsi_clk_groups[] = { + "gpio24", "gpio27", +}; + +static const char * const wsi_data_groups[] = { + "gpio26", "gpio29", +}; + +static const char * const rx2_groups[] = { + "gpio37", "gpio45", +}; + +static const struct pinfunction ipq5424_functions[] = { + MSM_PIN_FUNCTION(atest_char), + MSM_PIN_FUNCTION(atest_char0), + MSM_PIN_FUNCTION(atest_char1), + MSM_PIN_FUNCTION(atest_char2), + MSM_PIN_FUNCTION(atest_char3), + MSM_PIN_FUNCTION(atest_tic), + MSM_PIN_FUNCTION(audio_pri), + MSM_PIN_FUNCTION(audio_pri0), + MSM_PIN_FUNCTION(audio_pri1), + MSM_PIN_FUNCTION(audio_sec), + MSM_PIN_FUNCTION(audio_sec0), + MSM_PIN_FUNCTION(audio_sec1), + MSM_PIN_FUNCTION(core_voltage), + MSM_PIN_FUNCTION(cri_trng0), + MSM_PIN_FUNCTION(cri_trng1), + MSM_PIN_FUNCTION(cri_trng2), + MSM_PIN_FUNCTION(cri_trng3), + MSM_PIN_FUNCTION(cxc_clk), + MSM_PIN_FUNCTION(cxc_data), + MSM_PIN_FUNCTION(dbg_out), + MSM_PIN_FUNCTION(gcc_plltest), + MSM_PIN_FUNCTION(gcc_tlmm), + MSM_PIN_FUNCTION(gpio), + MSM_PIN_FUNCTION(i2c0_scl), + MSM_PIN_FUNCTION(i2c0_sda), + MSM_PIN_FUNCTION(i2c1_scl), + MSM_PIN_FUNCTION(i2c1_sda), + MSM_PIN_FUNCTION(i2c11), + MSM_PIN_FUNCTION(mac0), + MSM_PIN_FUNCTION(mac1), + MSM_PIN_FUNCTION(mdc_mst), + MSM_PIN_FUNCTION(mdc_slv), + MSM_PIN_FUNCTION(mdio_mst), + MSM_PIN_FUNCTION(mdio_slv), + MSM_PIN_FUNCTION(pcie0_clk), + MSM_PIN_FUNCTION(pcie0_wake), + MSM_PIN_FUNCTION(pcie1_clk), + MSM_PIN_FUNCTION(pcie1_wake), + MSM_PIN_FUNCTION(pcie2_clk), + MSM_PIN_FUNCTION(pcie2_wake), + MSM_PIN_FUNCTION(pcie3_clk), + MSM_PIN_FUNCTION(pcie3_wake), + MSM_PIN_FUNCTION(pll_test), + MSM_PIN_FUNCTION(prng_rosc0), + MSM_PIN_FUNCTION(prng_rosc1), + MSM_PIN_FUNCTION(prng_rosc2), + MSM_PIN_FUNCTION(prng_rosc3), + MSM_PIN_FUNCTION(PTA0_0), + MSM_PIN_FUNCTION(PTA0_1), + MSM_PIN_FUNCTION(PTA0_2), + MSM_PIN_FUNCTION(PTA10), + MSM_PIN_FUNCTION(PTA11), + MSM_PIN_FUNCTION(pwm0), + MSM_PIN_FUNCTION(pwm1), + MSM_PIN_FUNCTION(pwm2), + MSM_PIN_FUNCTION(qdss_cti_trig_in_a0), + MSM_PIN_FUNCTION(qdss_cti_trig_out_a0), + MSM_PIN_FUNCTION(qdss_cti_trig_in_a1), + MSM_PIN_FUNCTION(qdss_cti_trig_out_a1), + MSM_PIN_FUNCTION(qdss_cti_trig_in_b0), + MSM_PIN_FUNCTION(qdss_cti_trig_out_b0), + MSM_PIN_FUNCTION(qdss_cti_trig_in_b1), + MSM_PIN_FUNCTION(qdss_cti_trig_out_b1), + MSM_PIN_FUNCTION(qdss_traceclk_a), + MSM_PIN_FUNCTION(qdss_tracectl_a), + MSM_PIN_FUNCTION(qdss_tracedata_a), + MSM_PIN_FUNCTION(qspi_clk), + MSM_PIN_FUNCTION(qspi_cs), + MSM_PIN_FUNCTION(qspi_data), + MSM_PIN_FUNCTION(resout), + MSM_PIN_FUNCTION(rx0), + MSM_PIN_FUNCTION(rx1), + MSM_PIN_FUNCTION(rx2), + MSM_PIN_FUNCTION(sdc_clk), + MSM_PIN_FUNCTION(sdc_cmd), + MSM_PIN_FUNCTION(sdc_data), + MSM_PIN_FUNCTION(spi0), + MSM_PIN_FUNCTION(spi1), + MSM_PIN_FUNCTION(spi10), + MSM_PIN_FUNCTION(spi11), + MSM_PIN_FUNCTION(tsens_max), + MSM_PIN_FUNCTION(uart0), + MSM_PIN_FUNCTION(uart1), + MSM_PIN_FUNCTION(wci_txd), + MSM_PIN_FUNCTION(wci_rxd), + MSM_PIN_FUNCTION(wsi_clk), + MSM_PIN_FUNCTION(wsi_data), +}; + +static const struct msm_pingroup ipq5424_groups[] = { + PINGROUP(0, sdc_data, qspi_data, pwm2, wci_txd, wci_rxd, _, _, _, _), + PINGROUP(1, sdc_data, qspi_data, pwm2, wci_txd, wci_rxd, _, _, _, _), + PINGROUP(2, sdc_data, qspi_data, pwm2, _, _, _, _, _, _), + PINGROUP(3, sdc_data, qspi_data, pwm2, _, _, _, _, _, _), + PINGROUP(4, sdc_cmd, qspi_cs, _, _, _, _, _, _, _), + PINGROUP(5, sdc_clk, qspi_clk, _, _, _, _, _, _, _), + PINGROUP(6, spi0, pwm1, _, cri_trng0, qdss_tracedata_a, _, _, _, _), + PINGROUP(7, spi0, pwm1, _, cri_trng1, qdss_tracedata_a, _, _, _, _), + PINGROUP(8, spi0, pwm1, wci_txd, wci_rxd, _, cri_trng2, qdss_tracedata_a, _, _), + PINGROUP(9, spi0, pwm1, _, cri_trng3, qdss_tracedata_a, _, _, _, _), + PINGROUP(10, uart0, pwm0, spi11, _, wci_txd, wci_rxd, _, qdss_tracedata_a, _), + PINGROUP(11, uart0, pwm0, spi1, _, wci_txd, wci_rxd, _, qdss_tracedata_a, _), + PINGROUP(12, uart0, pwm0, spi11, _, prng_rosc0, qdss_tracedata_a, _, _, _), + PINGROUP(13, uart0, pwm0, spi11, _, prng_rosc1, qdss_tracedata_a, _, _, _), + PINGROUP(14, i2c0_scl, tsens_max, _, prng_rosc2, qdss_tracedata_a, _, _, _, _), + PINGROUP(15, i2c0_sda, _, prng_rosc3, qdss_tracedata_a, _, _, _, _, _), + PINGROUP(16, core_voltage, i2c1_scl, _, _, _, _, _, _, _), + PINGROUP(17, core_voltage, i2c1_sda, _, _, _, _, _, _, _), + PINGROUP(18, _, _, _, _, _, _, _, _, _), + PINGROUP(19, _, _, _, _, _, _, _, _, _), + PINGROUP(20, mdc_slv, atest_char0, _, qdss_tracedata_a, _, _, _, _, _), + PINGROUP(21, mdio_slv, atest_char1, _, qdss_tracedata_a, _, _, _, _, _), + PINGROUP(22, mdc_mst, atest_char2, _, _, _, _, _, _, _), + PINGROUP(23, mdio_mst, atest_char3, _, _, _, _, _, _, _), + PINGROUP(24, pcie0_clk, PTA10, mac0, _, wsi_clk, _, atest_char, qdss_cti_trig_out_a0, _), + PINGROUP(25, _, _, _, _, _, _, _, _, _), + PINGROUP(26, pcie0_wake, PTA10, mac0, _, wsi_data, _, qdss_cti_trig_in_a0, _, _), + PINGROUP(27, pcie1_clk, i2c11, PTA10, wsi_clk, qdss_cti_trig_out_a1, _, _, _, _), + PINGROUP(28, _, _, _, _, _, _, _, _, _), + PINGROUP(29, pcie1_wake, i2c11, wsi_data, qdss_cti_trig_in_a1, _, _, _, _, _), + PINGROUP(30, pcie2_clk, PTA11, mac1, qdss_cti_trig_out_b0, _, _, _, _, _), + PINGROUP(31, _, _, _, _, _, _, _, _, _), + PINGROUP(32, pcie2_wake, PTA11, mac1, audio_pri0, audio_pri0, qdss_cti_trig_in_b0, _, _, _), + PINGROUP(33, pcie3_clk, PTA11, audio_pri1, audio_pri1, qdss_cti_trig_out_b1, _, _, _, _), + PINGROUP(34, _, _, _, _, _, _, _, _, _), + PINGROUP(35, pcie3_wake, audio_sec1, audio_sec1, qdss_cti_trig_in_b1, _, _, _, _, _), + PINGROUP(36, audio_pri, spi1, audio_sec0, audio_sec0, qdss_tracedata_a, _, _, _, _), + PINGROUP(37, audio_pri, spi1, rx2, qdss_tracedata_a, _, _, _, _, _), + PINGROUP(38, audio_pri, spi1, pll_test, rx1, qdss_tracedata_a, _, _, _, _), + PINGROUP(39, audio_pri, rx0, _, qdss_tracedata_a, _, _, _, _, _), + PINGROUP(40, PTA0_0, wci_txd, wci_rxd, _, atest_tic, _, _, _, _), + PINGROUP(41, PTA0_1, wci_txd, wci_rxd, cxc_data, _, _, _, _, _), + PINGROUP(42, PTA0_2, cxc_clk, _, _, _, _, _, _, _), + PINGROUP(43, uart1, gcc_plltest, _, _, _, _, _, _, _), + PINGROUP(44, uart1, gcc_tlmm, _, _, _, _, _, _, _), + PINGROUP(45, spi10, rx2, audio_sec, gcc_plltest, _, qdss_traceclk_a, _, _, _), + PINGROUP(46, spi1, rx1, audio_sec, dbg_out, qdss_tracectl_a, _, _, _, _), + PINGROUP(47, spi10, rx0, audio_sec, _, _, _, _, _, _), + PINGROUP(48, spi10, audio_sec, _, _, _, _, _, _, _), + PINGROUP(49, resout, _, _, _, _, _, _, _, _), +}; + +static const struct msm_pinctrl_soc_data ipq5424_pinctrl = { + .pins = ipq5424_pins, + .npins = ARRAY_SIZE(ipq5424_pins), + .functions = ipq5424_functions, + .nfunctions = ARRAY_SIZE(ipq5424_functions), + .groups = ipq5424_groups, + .ngroups = ARRAY_SIZE(ipq5424_groups), + .ngpios = 50, +}; + +static int ipq5424_pinctrl_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &ipq5424_pinctrl); +} + +static const struct of_device_id ipq5424_pinctrl_of_match[] = { + { .compatible = "qcom,ipq5424-tlmm", }, + { }, +}; +MODULE_DEVICE_TABLE(of, ipq5424_pinctrl_of_match); + +static struct platform_driver ipq5424_pinctrl_driver = { + .driver = { + .name = "ipq5424-tlmm", + .of_match_table = ipq5424_pinctrl_of_match, + }, + .probe = ipq5424_pinctrl_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init ipq5424_pinctrl_init(void) +{ + return platform_driver_register(&ipq5424_pinctrl_driver); +} +arch_initcall(ipq5424_pinctrl_init); + +static void __exit ipq5424_pinctrl_exit(void) +{ + platform_driver_unregister(&ipq5424_pinctrl_driver); +} +module_exit(ipq5424_pinctrl_exit); + +MODULE_DESCRIPTION("QTI IPQ5424 TLMM driver"); +MODULE_LICENSE("GPL"); From patchwork Fri Sep 27 06:52:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sricharan Ramabadhran X-Patchwork-Id: 831358 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0BF5F17C9FA; Fri, 27 Sep 2024 06:54:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727420061; cv=none; b=ZW1b1X3NXs40bqtiRp2hF48QS1REoAzu2LJ+weYdJFsUshwuhAJM2omxysX5NxFySzkMprJXe6fqCvZbh5HAFB37hXUstvYovZYXWysHQd43YX3wEfLrM0GHFp2D7zbDeh6jmLooWPWl5HAdp5hK+FqLv0f+DfiX+bO27UeRSpo= ARC-Message-Signature: i=1; a=rsa-sha256; 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Fri, 27 Sep 2024 06:54:05 GMT Received: from hu-srichara-blr.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 26 Sep 2024 23:53:58 -0700 From: Sricharan R To: , , , , , , , , , , , , , , , , , , , , CC: , Subject: [PATCH V2 8/9] arm64: dts: qcom: add IPQ5424 SoC and rdp466 board support Date: Fri, 27 Sep 2024 12:22:43 +0530 Message-ID: <20240927065244.3024604-9-quic_srichara@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240927065244.3024604-1-quic_srichara@quicinc.com> References: <20240927065244.3024604-1-quic_srichara@quicinc.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: gfO-sVqtNeCIRLG5PLgKsPPyKqBzOx24 X-Proofpoint-GUID: gfO-sVqtNeCIRLG5PLgKsPPyKqBzOx24 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 bulkscore=0 mlxlogscore=999 adultscore=0 suspectscore=0 phishscore=0 impostorscore=0 spamscore=0 mlxscore=0 priorityscore=1501 lowpriorityscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2408220000 definitions=main-2409270046 From: Sricharan Ramabadhran Add initial device tree support for the Qualcomm IPQ5424 SoC and rdp466 board. Signed-off-by: Sricharan Ramabadhran --- [v2] Sorted nodes based on address, fixed labels case. Removed CPU_MASK for all nodes Dropped the chosen node Removed the redundant 'status=okay', ordered clocks child nodes alphabetically. arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts | 59 ++++ arch/arm64/boot/dts/qcom/ipq5424.dtsi | 291 ++++++++++++++++++++ 3 files changed, 351 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts create mode 100644 arch/arm64/boot/dts/qcom/ipq5424.dtsi diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 197ab325c0b9..46c4eb758799 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -16,6 +16,7 @@ dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp441.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp442.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp468.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp474.dtb +dtb-$(CONFIG_ARCH_QCOM) += ipq5424-rdp466.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq6018-cp01-c1.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c1.dtb diff --git a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts new file mode 100644 index 000000000000..d4d31026a026 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * IPQ5424 RDP466 board device tree source + * + * Copyright (c) 2024 The Linux Foundation. All rights reserved. + */ + +/dts-v1/; + +#include "ipq5424.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. IPQ5424 RDP466"; + compatible = "qcom,ipq5424-rdp466", "qcom,ipq5424"; + + aliases { + serial0 = &uart1; + }; +}; + +&sleep_clk { + clock-frequency = <32000>; +}; + +&tlmm { + sdc_default_state: sdc-default-state { + clk-pins { + pins = "gpio5"; + function = "sdc_clk"; + drive-strength = <8>; + bias-disable; + }; + + cmd-pins { + pins = "gpio4"; + function = "sdc_cmd"; + drive-strength = <8>; + bias-pull-up; + }; + + data-pins { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "sdc_data"; + drive-strength = <8>; + bias-pull-up; + }; + }; +}; + +&uart1 { + pinctrl-0 = <&uart1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&xo_board { + clock-frequency = <24000000>; +}; + diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi new file mode 100644 index 000000000000..76af0d87e9a8 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi @@ -0,0 +1,291 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * IPQ5424 device tree source + * + * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. + * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include + +/ { + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&intc>; + + clocks { + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + xo_board: xo-board-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + }; + + cpus: cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0>; + enable-method = "psci"; + next-level-cache = <&l2_0>; + l2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_0>; + + l3_0: l3-cache { + compatible = "cache"; + cache-level = <3>; + cache-unified; + }; + }; + }; + + cpu1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + enable-method = "psci"; + reg = <0x100>; + next-level-cache = <&l2_100>; + + l2_100: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_0>; + }; + }; + + cpu2: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + enable-method = "psci"; + reg = <0x200>; + next-level-cache = <&l2_200>; + + l2_200: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_0>; + }; + }; + + cpu3: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + enable-method = "psci"; + reg = <0x300>; + next-level-cache = <&l2_300>; + + l2_300: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_0>; + }; + }; + }; + + memory@80000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the size */ + reg = <0x0 0x80000000 0x0 0x0>; + }; + + pmu-a55 { + compatible = "arm,cortex-a55-pmu"; + interrupts = ; + }; + + pmu-dsu { + compatible = "arm,dsu-pmu"; + interrupts = ; + cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + tz@8a600000 { + reg = <0x0 0x8a600000 0x0 0x200000>; + no-map; + }; + }; + + soc@0 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0 0 0 0 0x10 0>; + + tlmm: pinctrl@1000000 { + compatible = "qcom,ipq5424-tlmm"; + reg = <0 0x01000000 0 0x300000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 50>; + interrupt-controller; + #interrupt-cells = <2>; + + uart1_pins: uart1-state { + pins = "gpio43", "gpio44"; + function = "uart1"; + drive-strength = <8>; + bias-pull-up; + }; + }; + + gcc: clock-controller@1800000 { + compatible = "qcom,ipq5424-gcc"; + reg = <0 0x01800000 0 0x40000>; + clocks = <&xo_board>, + <&sleep_clk>, + <0>, + <0>, + <0>, + <0>, + <0>; + #clock-cells = <1>; + #reset-cells = <1>; + #interconnect-cells = <1>; + }; + + qupv3: geniqup@1ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0 0x01ac0000 0 0x2000>; + ranges; + clocks = <&gcc GCC_QUPV3_AHB_MST_CLK>, + <&gcc GCC_QUPV3_AHB_SLV_CLK>; + clock-names = "m-ahb", "s-ahb"; + #address-cells = <2>; + #size-cells = <2>; + + uart1: serial@1a84000 { + compatible = "qcom,geni-debug-uart"; + reg = <0 0x01a84000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_UART1_CLK>; + clock-names = "se"; + interrupts = ; + }; + }; + + sdhc: mmc@7804000 { + compatible = "qcom,ipq5424-sdhci", "qcom,sdhci-msm-v5"; + reg = <0 0x07804000 0 0x1000>, <0 0x07805000 0 0x1000>; + reg-names = "hc", "cqhci"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&xo_board>; + clock-names = "iface", "core", "xo"; + + status = "disabled"; + }; + + intc: interrupt-controller@f200000 { + compatible = "arm,gic-v3"; + reg = <0 0xf200000 0 0x10000>, /* GICD */ + <0 0xf240000 0 0x80000>; /* GICR * 4 regions */ + #interrupt-cells = <0x3>; + interrupt-controller; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x20000>; + interrupts = ; + mbi-ranges = <672 128>; + msi-controller; + }; + + timer@f420000 { + compatible = "arm,armv7-timer-mem"; + reg = <0 0xf420000 0 0x1000>; + ranges = <0 0 0 0x10000000>; + #address-cells = <1>; + #size-cells = <1>; + + frame@f421000 { + reg = <0xf421000 0x1000>, + <0xf422000 0x1000>; + interrupts = , + ; + frame-number = <0>; + }; + + frame@f423000 { + reg = <0xf423000 0x1000>; + interrupts = ; + frame-number = <1>; + status = "disabled"; + }; + + frame@f425000 { + reg = <0xf425000 0x1000>, + <0xf426000 0x1000>; + interrupts = ; + frame-number = <2>; + status = "disabled"; + }; + + frame@f427000 { + reg = <0xf427000 0x1000>; + interrupts = ; + frame-number = <3>; + status = "disabled"; + }; + + frame@f429000 { + reg = <0xf429000 0x1000>; + interrupts = ; + frame-number = <4>; + status = "disabled"; + }; + + frame@f42b000 { + reg = <0xf42b000 0x1000>; + interrupts = ; + frame-number = <5>; + status = "disabled"; + }; + + frame@f42d000 { + reg = <0xf42d000 0x1000>; + interrupts = ; + frame-number = <6>; + status = "disabled"; + }; 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Fri, 27 Sep 2024 06:54:12 GMT Received: from hu-srichara-blr.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 26 Sep 2024 23:54:05 -0700 From: Sricharan R To: , , , , , , , , , , , , , , , , , , , , CC: , Subject: [PATCH V2 9/9] arm64: defconfig: Enable IPQ5424 RDP466 base configs Date: Fri, 27 Sep 2024 12:22:44 +0530 Message-ID: <20240927065244.3024604-10-quic_srichara@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240927065244.3024604-1-quic_srichara@quicinc.com> References: <20240927065244.3024604-1-quic_srichara@quicinc.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: kafJFIT8Cnar2ZoqCoNaovVlk9Rhw4MD X-Proofpoint-GUID: kafJFIT8Cnar2ZoqCoNaovVlk9Rhw4MD X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 priorityscore=1501 bulkscore=0 impostorscore=0 suspectscore=0 phishscore=0 adultscore=0 clxscore=1015 malwarescore=0 lowpriorityscore=0 mlxlogscore=737 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2408220000 definitions=main-2409270046 From: Sricharan Ramabadhran Enable GCC, Pinctrl for Qualcomm's IPQ5424 SoC which is required to boot IPQ5424-RDP466 boards to a console shell. Signed-off-by: Sricharan Ramabadhran --- [v2] Fixed subject description. arch/arm64/configs/defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 81ca46e3ab4b..f1043a40846a 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -595,6 +595,7 @@ CONFIG_PINCTRL_IMX93=y CONFIG_PINCTRL_MSM=y CONFIG_PINCTRL_IPQ5018=y CONFIG_PINCTRL_IPQ5332=y +CONFIG_PINCTRL_IPQ5424=y CONFIG_PINCTRL_IPQ8074=y CONFIG_PINCTRL_IPQ6018=y CONFIG_PINCTRL_IPQ9574=y @@ -1304,6 +1305,7 @@ CONFIG_IPQ_APSS_6018=y CONFIG_IPQ_APSS_5018=y CONFIG_IPQ_GCC_5018=y CONFIG_IPQ_GCC_5332=y +CONFIG_IPQ_GCC_5424=y CONFIG_IPQ_GCC_6018=y CONFIG_IPQ_GCC_8074=y CONFIG_IPQ_GCC_9574=y