From patchwork Thu Sep 26 14:31:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrei Stefanescu X-Patchwork-Id: 830854 Received: from EUR02-DB5-obe.outbound.protection.outlook.com (mail-db5eur02on2082.outbound.protection.outlook.com [40.107.249.82]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 18D0A7BB15; Thu, 26 Sep 2024 14:31:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.249.82 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727361118; cv=fail; b=ixvctvm26dAAHsh8CWug5HOG8+7Vj3u7Qd209prEM9l0BoA3XqZYf2tikio+AyH9djWTx7/Xia+cW6hhKy4ceZrezfCC27zJKKbetXrngXEGJKdn5I5qemibzG38uQZ5pa/vhNppA9HIUuPgKswCdncbGR29BpKhou34SqJoncM= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727361118; c=relaxed/simple; bh=WK4Owj4Y4Cm9P4MpXmjHW4vYZ5KrqTdjByDfuUp5bwk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: Content-Type:MIME-Version; b=So+cnFELSk/q7cTs/pVHiWcqTlgdN1XSgfrhpeWzHOlp3J+5gSNiXuJlfTtmqGsUVBgyA61BUSVNdFrwqu3RH+EOZSgCEutSrWl/9HqJy359Z3INNIV+q/4ZhfSb2vR7lw1dkd8AMp5HcAlCjf9DGIEKN+zvugrrvG8ZUN6NspE= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=oss.nxp.com; spf=pass smtp.mailfrom=oss.nxp.com; dkim=pass (2048-bit key) header.d=NXP1.onmicrosoft.com header.i=@NXP1.onmicrosoft.com header.b=JRC5ROS7; arc=fail smtp.client-ip=40.107.249.82 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=oss.nxp.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.nxp.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=NXP1.onmicrosoft.com header.i=@NXP1.onmicrosoft.com header.b="JRC5ROS7" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=EE7p91owIunjYham61i3wuc8vLQkJ06ENzIwjCdD33i3X5/rI1g6Wd7RbecOFy80KxxDj1ehELI+8qM4TcdG0EwB4rDWXcXpCYPtaylzBLQMqt7XQoLxFLurRJuCMeoMo6z30U9ahhCWSpwLMCN5qnUu9IE2C4sNtsQznGjUpaXwypjxor67aQsN0Zn9Mb4wPvdcMUdZxtjSPqnAFP3a7awIB/FXid3uilteGUa2fE0U/SwWejQ55Q9ZwcyT4BQ6WtobBDLjZDG5enMNjQRw2irhXHWl/pclFsBHOBT78JojvCf5NDVAWj91e9TFi4Hr6BI26q4EiOta1EQlesXB4Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=HEHYVemPzQDfpMdhfbuzyQ4zV5E9zOILEQA8q0JwEiU=; b=b/KSQwKbycKb8HI8OSkpvNTv6PgipAqoVxUPG+i8Al7AriwjDWdpOI37ZEoZfZ4iokIdK1wKSfey2tYaig/639fyMHYkqzMcAHg98T/Jna9cpdQEaMN8JgqPbzzGIglQvI+0ZIN/9uq81yr7PEI/2CbSF14E7t2/lonjZHcPIyuMgDrZIwfbv1CnR5YlBr5YBk+4wRAQBhde2ua0vq9f+V1qXkPPPtIj+FFqpePQK5PR6e3ykdGreuJ5HnwfsyZDxp+uTLUraIvLYkvXvjTW8OXQOTbQw7Kj1eu+x/bS7f2Mj+NYCMOxOu1wEAqGcI9bs1GYQsmYsxSNqljoj1nrNQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=oss.nxp.com; dmarc=pass action=none header.from=oss.nxp.com; dkim=pass header.d=oss.nxp.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=NXP1.onmicrosoft.com; s=selector1-NXP1-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=HEHYVemPzQDfpMdhfbuzyQ4zV5E9zOILEQA8q0JwEiU=; b=JRC5ROS7l8dw/uBRp8lwMgaoZZ13ZLmkTikgpHQXwEod/eKLJNw0clX9m5V8ZPrc72/GrGt2qzJFQe0yoQ0EoJLmmlQR3XpEB2QLrd9uCQSK7V1Hu0zT+I+KyEnQ1fAhFQwO/LUEUR55u1FVPiRFa1T/yEHpgcnYQ41kS38EchyWjcK00XrP4elCDDl2BkdZCJ/+iICFNoZbMwW6rNOxG8i0Q4p9WvjSQOh0oL7xbw63eZzj8Cg6rVxsYZND4MRlR463cRwes5sIBP/L8BeWFtXxxXDpln/D/A2QLPd1ef7d0UQxXvyKf9ovYfY3wkpjnNDhurs0NRSTLdY+9dJgTw== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=oss.nxp.com; Received: from AM9PR04MB8487.eurprd04.prod.outlook.com (2603:10a6:20b:41a::6) by GV1PR04MB10485.eurprd04.prod.outlook.com (2603:10a6:150:1d4::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7982.27; Thu, 26 Sep 2024 14:31:49 +0000 Received: from AM9PR04MB8487.eurprd04.prod.outlook.com ([fe80::6d7a:8d2:f020:455]) by AM9PR04MB8487.eurprd04.prod.outlook.com ([fe80::6d7a:8d2:f020:455%5]) with mapi id 15.20.7962.022; Thu, 26 Sep 2024 14:31:49 +0000 From: Andrei Stefanescu To: Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chester Lin , Matthias Brugger , Greg Kroah-Hartman , "Rafael J. Wysocki" Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, NXP S32 Linux Team , Christophe Lizzi , Alberto Ruiz , Enric Balletbo , Andrei Stefanescu , Krzysztof Kozlowski Subject: [PATCH v4 1/4] drivers: provide devm_platform_get_and_ioremap_resource_byname() Date: Thu, 26 Sep 2024 17:31:18 +0300 Message-ID: <20240926143122.1385658-2-andrei.stefanescu@oss.nxp.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240926143122.1385658-1-andrei.stefanescu@oss.nxp.com> References: <20240926143122.1385658-1-andrei.stefanescu@oss.nxp.com> X-ClientProxiedBy: AM0PR02CA0101.eurprd02.prod.outlook.com (2603:10a6:208:154::42) To AM9PR04MB8487.eurprd04.prod.outlook.com (2603:10a6:20b:41a::6) Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM9PR04MB8487:EE_|GV1PR04MB10485:EE_ X-MS-Office365-Filtering-Correlation-Id: b47601cf-143f-4d45-3fa9-08dcde37f4e7 X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|366016|7416014|1800799024|376014|52116014|38350700014; X-Microsoft-Antispam-Message-Info: =?utf-8?q?Zx6ZfeX0HAv4FYokkZz+IoQaskERXS8?= =?utf-8?q?RyNGhU5EOMiQG0BNYqAwrVwfp/cUcRZDZNJjILDEezTKiMef7CTonQOhko7pNMGpW?= =?utf-8?q?bkojXFFTdiqF6l6z16LvvNHH4PjrNYTMVb6mI3Vj4xv4x30j3eQ66a714UvHDC4I1?= =?utf-8?q?MKfdOTRkqcNHGYnYS0XNfNn9h1irw6o9xjeSJLJuHKWDdpEHD1ftrXrrjSasNwwUh?= =?utf-8?q?Bs9GlzEAuIcCnVRq/jr4FUpSSegOYo+gS9Es/m1tXzfICRek5VD+6M+Z6+WpxOjac?= =?utf-8?q?O/36VZ9ICDtyVCyQdxq/191GqnNSrpk0GakU9vmKdEPXy4WcbyQrYhQkVm2BprRIR?= =?utf-8?q?QSDjW4M6BXS8D+av8TzCbWiLY+3nDKecjGzr6UWkET0SRP9WkQ+A0I3Gco6d3q6+V?= =?utf-8?q?vTHBFXKE4Zp1MdBcsLb9QE+GBJYkYVATAbjejQ18uh+Vqls2bufrPljFSicX/2GJI?= =?utf-8?q?zNGrBJLGhtvloz2dA1MZJ3omGs/i5mwIvE9vTTo0TZ6GqxqPjBSOPFrXolsqgEEki?= =?utf-8?q?yKoVLoVpC2Il11oyUVCL43FFeuMb+Ll6LcdLkrKDa2+9GVYLsiX49rtv5ZquMHCst?= =?utf-8?q?VF0T9sGpKnXI5fVpkSD3zH8rFiEMy9Lm1hoc4h4jK5ZpiX+p7sxvf6zOGHA5PYqS/?= =?utf-8?q?/IewUlOL2GGqG7JDmHika4mzWqC0c4vOHvZ0jJiIV5t8jCqnizCY6VWKVMXIRZ4TX?= =?utf-8?q?z1EVWveNaNF3hV2omSNi5X2CQ19t6Lp2aHZONrkGCGIl3rSwX0AUzfEvzpGRkJ9HM?= =?utf-8?q?s9ncVj/YjlnCqb8poCjWt8Pxoz3qB5gSXzsPuGgrHR2dzTdSmKhDehGJRlZHtmcwM?= =?utf-8?q?Y1W7Rmi1DpElrxPLwy9cs2mXREroVllpz5eOR+ST9CnM/72BHBQ2Cbf+IF1jJlHt3?= =?utf-8?q?2U8nIwQRX7sX4RSWUHG0oIH4a9dTN3KbS98Opts7lousN6uZO1BWXArUnICZqRuEP?= =?utf-8?q?VURGrvo8D3M7YlGRTrc8ofuFaOv10ewlTkeIjD55YOiVof5Wt2WFTim+fdMpafRFW?= =?utf-8?q?G9f14Z6tDYG20me7AwjlijI+lpj2MdHWPi4t2oHkvqejrk7u455aWX9rBgFJpxOMJ?= =?utf-8?q?FOmX2uHQZ21JTpGvNkn9r1ULDON13gbuTBGE48UvGQCmUXdDZnhKHL75cWzGWVSFr?= =?utf-8?q?Sqd7TI774+I0yOsWjW9m5PwdnL5Wb8yCvayehDft66T7YpOeybpjldBprCm6AdEja?= =?utf-8?q?BtSvoqjphXX8y8LqI4o2IUfi+R1xep2BR/mYgtMsivAWug+dqkPAXz/X8sjDAcW/5?= =?utf-8?q?2TZP0tbSUejWPJRrhfNtx3yXs/GWFU35T+vEbzB/XkMbwxDr6hvd21TRrLachQWg+?= =?utf-8?q?ISMwBEAVQc6L+GTkoeLgl6YVdsmEarqS2Q=3D=3D?= X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9PR04MB8487.eurprd04.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230040)(366016)(7416014)(1800799024)(376014)(52116014)(38350700014); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?q?1h230QhbSjY9seyc8kM7deinIEGI?= =?utf-8?q?xS/dCstWsXDRhFSzyCkYlUWf4FisRnqRxZ3d1YUXb4vpOm4GCuu0C25rkLdX4Y61k?= =?utf-8?q?DuzJUraOn9ClZvPqNgOcwg8fx0wKH8qx0ItQv8BaXlR+4PDnQ3VL0WnhOKajIqRuN?= =?utf-8?q?BWdWLdzDKGpfUeUULdz2ZRJ3flUbeQQ/yocpV6wSYzi7rRFxiK9DwZUVVx0ulGJdD?= =?utf-8?q?pfUK3kGAAPWupuwf/uFmX9BN/gM4G4PeSRK4c870/oFyTYysBSPiMRWfXy/tKxSNw?= =?utf-8?q?gjkP9b7ysQmtjyq1b+avXq8fs8SyBbd1viwn7cgcXIVEF8CXvNRhfJWAMYcOrNbNd?= =?utf-8?q?/Sdk1shLfCDHR3Sn2aaTxIsal6m+FuWGiowpyncaL9MNHeniD6OqS0aBxV5dp1l6k?= =?utf-8?q?771s/s1BJduqkmwEgncBJ8HUd92h5KexMlwu3GW0R8s/r2rXnWsCn2DhSuN9E0atJ?= =?utf-8?q?zGdsmovs4uOoi4UYTuvwGExB2QMU928kWnEdVVSX2Yn82XZILl7f30iMe0ioJ+2DJ?= =?utf-8?q?JPCBJKiRcyrUIdlfIDXjKD0EJ+jCP8o9DkArdnvFB1W0xxO7WkNsh5V2hNmNhdqB1?= =?utf-8?q?JJf6kQBd8jr9sFIEjsYNJl1SqMlm4TL5UTRhwF+1OC85BJn/4OTfzMeAa2jJhObBx?= =?utf-8?q?5Pq643xGRaPjwOlseUR/7N+karxGTZ14ggSc8X7jz6SC4kSUyxjXGKvaJC8Rubhc3?= =?utf-8?q?iYH9kJKfA9x4LOdnpQbwb8iBnUpEpNb763VcOT/zRAwcS8uDlT6Mk+0pTfBdvOaCS?= =?utf-8?q?b3pahJdyNIG0A2rQi7/0tA0Uu1gT7XE78Rj0U3F0B9TTqCgIa+z+fVVSu1RXhgo5Y?= =?utf-8?q?jIhry+AZ7OR7TddUvwJ/NMHBJ3Vac2N/CYB4/Opy8kWTJVDH08BgL2ocOI7uDs2hT?= =?utf-8?q?MR4DZSvpFSByX5NCToYAsYheUpEOjHFL1NWACmvcAHzmNTSXqMab5DFeAPxcqfyow?= =?utf-8?q?Xa6JPpMNiOkLyyBuvPW9TmbggANgLylSab/X0Imro/hIsdF1qLenDJlOM+Q3YUAlC?= =?utf-8?q?WZBv7BICv/SCJ3EvkrJyFDBbqhC5mSzU6PqgIkmC3UY9ugWvgjvtOcmTP+C3drOc9?= =?utf-8?q?z62hOGDWdJLDrVf9sI1VZh0ifhBjY2HHimGxvz8xliHUWqLAGbL1fIRyJSYGhatpw?= =?utf-8?q?Mcxjc+0eW6KmwB2sdWAlZwNXc0W0ZalJXRIEjME/IkL4zhZubjtAvKI6mJuRyZvk/?= =?utf-8?q?PD/MZb5zmiem7vEGK7HB3h9X9Ji0K6+1BUtkA4dc6QQkaw0/2d4p9JHCuC6wJ7xdG?= =?utf-8?q?lqk/n1+ehUKA6o/zH2Gxeu1lqxRI9rgQ88wnkstA6+sIz+UqRsGR+v8O8LMH/mpJ5?= =?utf-8?q?n7a16JkemWyHMGtxxeB1jarFp/M4lHxm0SKAesxn8bg4wfCWBp4ATY/9k21EfnURY?= =?utf-8?q?9XpkLEOjM95Z7XegSinNzqKQsPq9FWdN6bWdurcHeOsIB6sUroHbIJ+cpauzhgb/C?= =?utf-8?q?v0XpJ6WfXQZoQU4V7tc4AV+tQ0T9JOhUVmkmW+hg81CBSdamM9uDHDlinIESnibCq?= =?utf-8?q?+n6+3SR37bDajV+TbQNi7fhmK3Q/pwI7Fg=3D=3D?= X-OriginatorOrg: oss.nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: b47601cf-143f-4d45-3fa9-08dcde37f4e7 X-MS-Exchange-CrossTenant-AuthSource: AM9PR04MB8487.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Sep 2024 14:31:49.5412 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: J6dh7ApVk6bfBmGDmHtAMwk8x3rRxVQF1grl/stalq3eiNF0ugYzF132S8l0HrqTXuN2MYqF/P0q2UyXpw651TxAI5S2AI+zuKiOf7vXoLU= X-MS-Exchange-Transport-CrossTenantHeadersStamped: GV1PR04MB10485 Similar to commit 890cc39a879906b63912482dfc41944579df2dc6 ("drivers: provide devm_platform_get_and_ioremap_resource()") add a wrapper for "platform_get_resource_byname" and "devm_ioremap_resource". This new wrapper also returns the resource, if any, via a pointer. Suggested-by: Krzysztof Kozlowski Reviewed-by: Matthias Brugger Signed-off-by: Andrei Stefanescu --- drivers/base/platform.c | 27 +++++++++++++++++++++++++++ include/linux/platform_device.h | 13 +++++++++++++ 2 files changed, 40 insertions(+) diff --git a/drivers/base/platform.c b/drivers/base/platform.c index 4c3ee6521ba5..da6827f9462a 100644 --- a/drivers/base/platform.c +++ b/drivers/base/platform.c @@ -108,6 +108,33 @@ devm_platform_get_and_ioremap_resource(struct platform_device *pdev, } EXPORT_SYMBOL_GPL(devm_platform_get_and_ioremap_resource); +/** + * devm_platform_get_and_ioremap_resource_byname - call devm_ioremap_resource() + * for a platform device and get + * a resource by its name + * + * @pdev: platform device to use both for memory resource lookup as well as + * resource management + * @name: resource name + * @res: optional output parameter to store a pointer to the obtained resource. + * + * Return: a pointer to the remapped memory or an ERR_PTR() encoded error code + * on failure. + */ +void __iomem * +devm_platform_get_and_ioremap_resource_byname(struct platform_device *pdev, + const char *name, + struct resource **res) +{ + struct resource *r; + + r = platform_get_resource_byname(pdev, IORESOURCE_MEM, name); + if (res) + *res = r; + return devm_ioremap_resource(&pdev->dev, r); +} +EXPORT_SYMBOL_GPL(devm_platform_get_and_ioremap_resource_byname); + /** * devm_platform_ioremap_resource - call devm_ioremap_resource() for a platform * device diff --git a/include/linux/platform_device.h b/include/linux/platform_device.h index d422db6eec63..ab7f33f3c426 100644 --- a/include/linux/platform_device.h +++ b/include/linux/platform_device.h @@ -68,6 +68,12 @@ platform_find_device_by_driver(struct device *start, extern void __iomem * devm_platform_get_and_ioremap_resource(struct platform_device *pdev, unsigned int index, struct resource **res); + +extern void __iomem * +devm_platform_get_and_ioremap_resource_byname(struct platform_device *pdev, + const char *name, + struct resource **res); + extern void __iomem * devm_platform_ioremap_resource(struct platform_device *pdev, unsigned int index); @@ -83,6 +89,13 @@ devm_platform_get_and_ioremap_resource(struct platform_device *pdev, return ERR_PTR(-EINVAL); } +static inline void __iomem * +devm_platform_get_and_ioremap_resource_byname(struct platform_device *pdev, + const char *name, + struct resource **res) +{ + return ERR_PTR(-EINVAL); +} static inline void __iomem * devm_platform_ioremap_resource(struct platform_device *pdev, From patchwork Thu Sep 26 14:31:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Andrei Stefanescu X-Patchwork-Id: 830853 Received: from EUR02-DB5-obe.outbound.protection.outlook.com (mail-db5eur02on2083.outbound.protection.outlook.com [40.107.249.83]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ADCFE14D70F; Thu, 26 Sep 2024 14:32:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.249.83 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727361126; cv=fail; b=bgab+w8uvgNZD0YFThgBcEgedNB3oo2aUX4BH9b+bw0wt4VFuMG7SneXVUs7daIyvlFWvAKuVbQqz5YS8CrPnT7zHe1HOPKm3a4O0YdNe3Jg2VwarheSDyCu1VNwqgm7gzbWJ+mqdV8Zg1pHIAfArsGrmJxnQ2MImhbrrm5Rk5E= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727361126; c=relaxed/simple; bh=zn7wsbnj3RxoIkyUt7ybOEJXz+bBO8kc8eGuCAJ2Hjc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: Content-Type:MIME-Version; b=GbcJwN4X0CRESrVqdvcQhba0hrRYpjwnAFbki2aEVdoCSYT6sdwinzLkj5jMfm4DCK1lJrE05vkCxAbzKq3yJmaQ06FVr2UoSv2CC8BKf0/LtEEvpn0UR/pYbam5n+9NwZbaA9qk+WuS8MDwMDY3Vo9IfDZ3A9JyCupsWr198oU= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=oss.nxp.com; spf=pass smtp.mailfrom=oss.nxp.com; dkim=pass (2048-bit key) header.d=NXP1.onmicrosoft.com header.i=@NXP1.onmicrosoft.com header.b=Zp4HPmk4; arc=fail smtp.client-ip=40.107.249.83 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=oss.nxp.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.nxp.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=NXP1.onmicrosoft.com header.i=@NXP1.onmicrosoft.com header.b="Zp4HPmk4" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=ES9AOA+FIi4v4QUFVfvrH9Eq0aeAe20G+6LazsyjBWhp51PcrOrct4lmoWhqaAxibkJpFlLn2Agrfni0wPJHn4UT+ZEp0/SmIDIvUkX1RdeBx439msZUNzsHqIdF7dgPaxbQYsu4B1fzvosGpXi7CyRA5Q4qMTMUGTUZmMiK5NtZd/mhmPtyxC1XCc+4okUR4+HP9o+LxcuOdj7x4NcY9NjmS946K9nTAUjTGnzq5eCXsEvs+PgmeJexYXKLU+NMKF37Q4IO4vBbKWh/7w18Q2OKnifru95letQRpgXFs0Z74WAh8icrcd1SlRiXvJlwj9Vv4ATfuupufS0s+RgmzQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Yhl0SuY9l/7AQdpfne3J5b4/aU7cNlKV/TWXWcyG85U=; b=Z0OYgCBxCwEjRbvuCeXHeFBfI1THzLYlClEbzy1YLx8l7B45pxa/IWcmS0jzZrLts8zQ/Pm4YciGp29rqzK+DLl5j+qvWZoDyKnJx1GapIKNOgs+AN2OJPscYhJpDcbWs9avZs8e+J/GcDZ4DWR3o+0Na0cHMft004lKBX1x7xtj3t0j07Lv9bzIN6EC/bj9OKwmq/YIb96grQurGuZt1PzIDCTcNRwpE8Qg8Az/U98lC7ulbcIxUy82/f/usNKEL93Oz23plcaSv0Idjt49bqkg2QYxvStEXubn/DVY5MvrBnpOewsLsOQ73Scv+FzvUOV3OL2Yoe9x7UbvHqwuYQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=oss.nxp.com; dmarc=pass action=none header.from=oss.nxp.com; dkim=pass header.d=oss.nxp.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=NXP1.onmicrosoft.com; s=selector1-NXP1-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Yhl0SuY9l/7AQdpfne3J5b4/aU7cNlKV/TWXWcyG85U=; b=Zp4HPmk4qznIfCLL5FUoRyoZdsQ03KHLUZhVn0EGKQkiqfD++Wesd1yP8WnqyF4cAr7ffPZUCPV7mYfybb8WoWv6Ex6Vn2HXIKlvPILDl9wJ3LcMRq48ae4UbPaHy9cevGTbGDIB86luhgG8XtAp6nlzTUd6oZeswEFF+ptbxc7H6ulQS3hEoZGm+kjjgNWavW0sYSIgbQFkU8RyMuZq4e2ZSQ1CiqgRFH3/4idx3y2KzaraC5ipB0jWKI8eL1nU65CRgeIzTlUULm5pI213qAl2UHnCJYojlICkXGyLXlN4bPyt0d84it27HYXdD8N6YpQv7J66yI5p3faxm1Wpvg== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=oss.nxp.com; Received: from AM9PR04MB8487.eurprd04.prod.outlook.com (2603:10a6:20b:41a::6) by GV1PR04MB10485.eurprd04.prod.outlook.com (2603:10a6:150:1d4::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7982.27; Thu, 26 Sep 2024 14:31:54 +0000 Received: from AM9PR04MB8487.eurprd04.prod.outlook.com ([fe80::6d7a:8d2:f020:455]) by AM9PR04MB8487.eurprd04.prod.outlook.com ([fe80::6d7a:8d2:f020:455%5]) with mapi id 15.20.7962.022; Thu, 26 Sep 2024 14:31:54 +0000 From: Andrei Stefanescu To: Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chester Lin , Matthias Brugger , Greg Kroah-Hartman , "Rafael J. Wysocki" Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, NXP S32 Linux Team , Christophe Lizzi , Alberto Ruiz , Enric Balletbo , Andrei Stefanescu Subject: [PATCH v4 3/4] gpio: siul2-s32g2: add NXP S32G2/S32G3 SoCs support Date: Thu, 26 Sep 2024 17:31:20 +0300 Message-ID: <20240926143122.1385658-4-andrei.stefanescu@oss.nxp.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240926143122.1385658-1-andrei.stefanescu@oss.nxp.com> References: <20240926143122.1385658-1-andrei.stefanescu@oss.nxp.com> X-ClientProxiedBy: AM0PR02CA0101.eurprd02.prod.outlook.com (2603:10a6:208:154::42) To AM9PR04MB8487.eurprd04.prod.outlook.com (2603:10a6:20b:41a::6) Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM9PR04MB8487:EE_|GV1PR04MB10485:EE_ X-MS-Office365-Filtering-Correlation-Id: b0e7123e-929a-4f40-5a4f-08dcde37f79d X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|366016|7416014|1800799024|376014|52116014|38350700014; X-Microsoft-Antispam-Message-Info: =?utf-8?q?jMX3PBBEBNSgYiGhIJr7W7baPak3JoN?= =?utf-8?q?jH9NgZKO2w4Xw10V3BZkoDBB5BW17riI80tQ0zUIol09gQtqPl/n1yosvAOHzQmbJ?= =?utf-8?q?JjX9E/5uJ48aDUphMde4MaZFQ/23pR1GZsFZ2KcDD7cW4axAPhFx8xvOYoFR2Vfcr?= =?utf-8?q?N/BnSxWE0qfPqM7RwCcn+dSKNT+pNp1s/B+sgqLXfK5suDAaNv7CyPl7vsHUqiqrm?= =?utf-8?q?7aYw7eABlkaSwDhZaH+QS0YHDOTBe9/y+Du484E+CDbHwNZcHrWZrPdSrx9icftf1?= =?utf-8?q?7Cr6tgxCkN6T1wqLQl16PAsoRD1B7oHDaORmAYY0IdFsp7CCkwo6QkgKv+hc/n0Ww?= =?utf-8?q?1wTuG0S78bjfC2yE7sKi4sLklxmt0vYAePwU2Fa/6cyg/bIK7JbuBnpeA9VVoiaNV?= =?utf-8?q?xQcWPakNVcJgaJdZJmkDgmCBzdADMF3SUAm8wYUcFUc4i/1sXpPxT64Sg3TjGs9e4?= =?utf-8?q?gdEoyrwjAH3S/TrZVYg1SgM2v6kZIVsuIOenVLy4g+PfijN1390Guc1k4q31Cyngp?= =?utf-8?q?d96WpTomMMqamx4h0tIh82z3AQ1YpjpQOWZdBHuAfq+fttTn1+XJ/ZvWR3ETIjNUs?= =?utf-8?q?obUaK9+FPIs9v1e2ztJyqn8yj8ttv18M6p8NYQ/OHY3DVQauG9RS6oU6zdEMAYLfQ?= =?utf-8?q?XCU8ye+s2h0MkgHfzBDdoj41FkejpEPqGNfuEmJKkThwyNcUWneY5hsQ9JifYyR5Z?= =?utf-8?q?5zekaAM2H/Qp14QfOZTS3z/e/Ma8v3hgE1FCCTWnRCzJONz5H+X/XpapNcIUg2LDJ?= =?utf-8?q?yJlCFEqGldDegZFQzrg8T9BnnnsCDO/lQ6QyXyBt/JNnNzWW9bR+uxsqqyCx8QCVj?= =?utf-8?q?aPuChVfU/Prk3M79OfM90U6RUmO0H9RdXQO0vnM2zj+AohD9WVZTwmmynLBk2PYbZ?= =?utf-8?q?HpWhqbjQcJmPdfDk7Phnj2V7VxSzbz74KMRILCe/sP2D9KlL+mv6WqXFBHss9V8SH?= =?utf-8?q?CKk5cSSuOd0xjNPxjN6MMzH1EZOSl08rHBFpR/JrCsW4Wa4LkvUgYH34ox22JTudj?= =?utf-8?q?87XgBJU5W9AEY9IkRtlj0EFhQ0iZxQwB/18SctQMPOurRjMDua3+XMZz4Mzi55Y06?= =?utf-8?q?bkP0B/gzyhFuU8DvWRinKNuJYSPoQc7YbAIl14hAh8jBBARBb9uliQZy7Y7nfHoXX?= =?utf-8?q?RylnYI1tSE1mHvgfylzO+VDZtoPOuGKr9kf/gkqD5OvYJuAWjbJ/jh1WBHKdAsx8v?= =?utf-8?q?47csN+mP6vSArMBu1qRNIV7hiSDIFwtcCZYLFI9BVgKBhS+tSOey1mmuSRwPz3wUH?= =?utf-8?q?OzDF1CtsX71Z1GmZE/5OeBOPis8hgG5azu+vQ4y8ShywyRQfpeU1xXUE/sWJTyPKm?= =?utf-8?q?y+zt42V2PNKDXFuQudc/VGDQFHuI6ilAug=3D=3D?= X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9PR04MB8487.eurprd04.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230040)(366016)(7416014)(1800799024)(376014)(52116014)(38350700014); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?q?CBKo9l9WzVrus6GsNH9KPDBYF3yf?= =?utf-8?q?4BgcZi+or7iGdhu5Cg6NnsuC5srcxZWu+wCN1fTcbJPF1ZUcfy6O1Z9mbmTiYL0cQ?= =?utf-8?q?ACnRvkCY4aTXvymJtKPjlrGBpYXrBKeje0DP9XiQKg8cAaFCB3Rfn8GoEOG+xxQ24?= =?utf-8?q?gl24vyNqh+sJcPbR5y+Cvk4BVbAqB7yNEvuc9LJwupkkircJ9U+DMKbeSQVVVsAQ6?= =?utf-8?q?NRp+OUKbnV5OtUupv32cci9l2lzuYsGANqmqhVKBW19NsTfNaFoYFTjGFtE7skJBe?= =?utf-8?q?shx4xRsvSiWFhzN7L9L2LlH5scL8gZo+ANXUVxgNI6tmNejdGgUgQIWLmuiH5OZtN?= =?utf-8?q?+PFpn/eZHNkRUilASY+sQzX1sCrzfFJ92QXKvv9pqPnCW+whtln8wctyHpydGhc2F?= =?utf-8?q?DBmOuxEVkuYTi5BP7FO8Of9kEf6tMctnbZADRJ93d3MfYaPPnBuX/EfbTD7R5YHoz?= =?utf-8?q?WGBG93wZMwUEndBloUEAQVEcQ7PhzI4aDQYHMdLHDS6ign3ErhCnY4QrMvlFDPpgK?= =?utf-8?q?W/1VWRixNlJ47M2WmqUbihcOrOFZoOQ3QrYRjuhuxbcHTQERad6f+1Rn4bC5y3kkt?= =?utf-8?q?A6jE4JU2VQHKuPm3vvsGG78OQHBI/WMq7L6s1JvkYVrlyEDbMnsNv9bFq0p9c0jsF?= =?utf-8?q?mOkSjFAMSbGHzHUXd7B3ufNllgxQaOytWT0OWhx3sTQbvwjIq4UARrtFW1RJuD4Ci?= =?utf-8?q?SPl/gaDVoCUWcSR2oslnvRGfbNUGt1oYtlQZAUQ8Mx9a3DISB4xgZlmmcQC86/OHs?= =?utf-8?q?BSIr418T0iO1ogGwPiqP2Ab3N+0SCn/KcnpX9inaW3WZKVpd/hr7Xvg4DUgvXSZ9a?= =?utf-8?q?8X0wa/AW/42AG0n9DD8TSi4HgrsqMbhputr9OFTlCm+mIDCOjE+t4GpXW9CUColDf?= =?utf-8?q?hZpNN1nn/dxmSPDx4HVBRObbCIutFAkHgG3Xm53z1za2esklxP8RD0R+UgQY/9r75?= =?utf-8?q?YP4icw5xmAqOx/L5IjQQXkVLD4iX4NuogWdTGUsyi0vAGwM9ux0+KL+p/wzyWsRo2?= =?utf-8?q?7ufE9q+inH6x0bSKWZJwOiSWnfWzpqh7kEsCS4H3I6pc1hFhRkUDmvGkonKP6tNid?= =?utf-8?q?jnBjYCKdeTQnUF8sjFt46poZ11JNDLS/L2W9P4WLDZBkZMVAInbW70ygPawqbxzIy?= =?utf-8?q?Hv+fpVyRLpzOdLd4AIhk305lGwYxxanlPJJ+fOC2RhQCSjANDo+c655wwqySZMLKm?= =?utf-8?q?juJUUqNb+l9AF4sos6TO+j5FWKSUxqzvQHVvXrNCccfo7oZZlRLhpDoKPnKTvAhEc?= =?utf-8?q?Ulh6ajAR0Pgvt4mK++8uYHOVC40rU7mNMP3vZ02WURKbCUi6fKOjEHe0TsqY+ikSR?= =?utf-8?q?cJgqqMo1uUweOnwfDoayoEvcNEhIrBGVeJJKIby/d0LBZImANqcBPZ37ncjV9YgSt?= =?utf-8?q?xfyi4EtPteQ1qRmirCMSrThlNYKLXhbc9TwqG+lwlo9sezpIjejhsBbSx4UofsbjM?= =?utf-8?q?7TUgPZp/7RLKkKPmg0zfagDo2Kk6lVytIPAwQepFEQl90BDuCw7V/uH63SR50UJ2f?= =?utf-8?q?Y1p4MtDYMT+qUUSkgFwwx45V1MJk2ckKIg=3D=3D?= X-OriginatorOrg: oss.nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: b0e7123e-929a-4f40-5a4f-08dcde37f79d X-MS-Exchange-CrossTenant-AuthSource: AM9PR04MB8487.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Sep 2024 14:31:54.0406 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: SA65Rw8T30HIj0wx8Ob4xjuM+HBinyFg6qzO/T5pVBVMJw9ajRsbQMVd7aT5LOBuFeBf5zA00QrS/TpR2H0e0JK+uhdDdd1K91pVtDEWIMw= X-MS-Exchange-Transport-CrossTenantHeadersStamped: GV1PR04MB10485 Add the GPIO driver for S32G2/S32G3 SoCs. This driver uses the SIUL2 (System Integration Unit Lite2) hardware module. There are two SIUL2 hardware modules present, SIUL2_0(controlling GPIOs 0-101) and SIUL2_1 for the rest. The GPIOs are not fully contiguous, there are some gaps: - GPIO102 up to GPIO111(inclusive) are invalid - GPIO123 up to GPIO143(inclusive) are invalid Some GPIOs are input only(i.e. GPI182) though this restriction is not yet enforced in code. This patch adds basic GPIO functionality(no interrupts, no suspend/resume functions). Signed-off-by: Ghennadi Procopciuc Signed-off-by: Larisa Grigore Signed-off-by: Phu Luu An Signed-off-by: Andrei Stefanescu --- drivers/gpio/Kconfig | 10 + drivers/gpio/Makefile | 1 + drivers/gpio/gpio-siul2-s32g2.c | 576 ++++++++++++++++++++++++++++++++ 3 files changed, 587 insertions(+) create mode 100644 drivers/gpio/gpio-siul2-s32g2.c diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index d93cd4f722b4..ae6aa6f64db3 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -643,6 +643,16 @@ config GPIO_SIOX Say yes here to support SIOX I/O devices. These are units connected via a SIOX bus and have a number of fixed-direction I/O lines. +config GPIO_SIUL2_S32G2 + tristate "GPIO driver for S32G2/S32G3" + depends on ARCH_S32 || COMPILE_TEST + depends on OF_GPIO + select REGMAP_MMIO + help + This enables support for the SIUL2 GPIOs found on the S32G2/S32G3 + chips. Say yes here to enable the SIUL2 to be used as an GPIO + controller for S32G2/S32G3 platforms. + config GPIO_SNPS_CREG bool "Synopsys GPIO via CREG (Control REGisters) driver" depends on ARC || COMPILE_TEST diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 1429e8c0229b..8d5f35689fed 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -150,6 +150,7 @@ obj-$(CONFIG_GPIO_SCH) += gpio-sch.o obj-$(CONFIG_GPIO_SIFIVE) += gpio-sifive.o obj-$(CONFIG_GPIO_SIM) += gpio-sim.o obj-$(CONFIG_GPIO_SIOX) += gpio-siox.o +obj-$(CONFIG_GPIO_SIUL2_S32G2) += gpio-siul2-s32g2.o obj-$(CONFIG_GPIO_SL28CPLD) += gpio-sl28cpld.o obj-$(CONFIG_GPIO_SLOPPY_LOGIC_ANALYZER) += gpio-sloppy-logic-analyzer.o obj-$(CONFIG_GPIO_SODAVILLE) += gpio-sodaville.o diff --git a/drivers/gpio/gpio-siul2-s32g2.c b/drivers/gpio/gpio-siul2-s32g2.c new file mode 100644 index 000000000000..d9c04aacb3cc --- /dev/null +++ b/drivers/gpio/gpio-siul2-s32g2.c @@ -0,0 +1,576 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * SIUL2 GPIO support. + * + * Copyright (c) 2016 Freescale Semiconductor, Inc. + * Copyright 2018-2024 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* PGPDOs are 16bit registers that come in big endian + * order if they are grouped in pairs of two. + * + * For example, the order is PGPDO1, PGPDO0, PGPDO3, PGPDO2... + */ +#define SIUL2_PGPDO(N) (((N) ^ 1) * 2) +#define S32G2_SIUL2_NUM 2 +#define S32G2_PADS_DTS_TAG_LEN 7 + +#define SIUL2_GPIO_16_PAD_SIZE 16 + +/** + * struct siul2_device_data - platform data attached to the compatible. + * @pad_access: access table for I/O pads, consists of S32G2_SIUL2_NUM tables. + * @reset_cnt: reset the pin name counter to zero when switching to SIUL2_1. + */ +struct siul2_device_data { + const struct regmap_access_table **pad_access; + const bool reset_cnt; +}; + +/** + * struct siul2_desc - describes a SIUL2 hw module. + * @pad_access: array of valid I/O pads. + * @opadmap: the regmap of the Parallel GPIO Pad Data Out Register. + * @ipadmap: the regmap of the Parallel GPIO Pad Data In Register. + * @gpio_base: the first GPIO pin. + * @gpio_num: the number of GPIO pins. + */ +struct siul2_desc { + const struct regmap_access_table *pad_access; + struct regmap *opadmap; + struct regmap *ipadmap; + u32 gpio_base; + u32 gpio_num; +}; + +/** + * struct siul2_gpio_dev - describes a group of GPIO pins. + * @platdata: the platform data. + * @siul2: SIUL2_0 and SIUL2_1 modules information. + * @pin_dir_bitmap: the bitmap with pin directions. + * @gc: the GPIO chip. + * @lock: mutual access to bitmaps. + */ +struct siul2_gpio_dev { + const struct siul2_device_data *platdata; + struct siul2_desc siul2[S32G2_SIUL2_NUM]; + unsigned long *pin_dir_bitmap; + struct gpio_chip gc; + raw_spinlock_t lock; +}; + +static const struct regmap_range s32g2_siul20_pad_yes_ranges[] = { + regmap_reg_range(SIUL2_PGPDO(0), SIUL2_PGPDO(0)), + regmap_reg_range(SIUL2_PGPDO(1), SIUL2_PGPDO(1)), + regmap_reg_range(SIUL2_PGPDO(2), SIUL2_PGPDO(2)), + regmap_reg_range(SIUL2_PGPDO(3), SIUL2_PGPDO(3)), + regmap_reg_range(SIUL2_PGPDO(4), SIUL2_PGPDO(4)), + regmap_reg_range(SIUL2_PGPDO(5), SIUL2_PGPDO(5)), + regmap_reg_range(SIUL2_PGPDO(6), SIUL2_PGPDO(6)), +}; + +static const struct regmap_access_table s32g2_siul20_pad_access_table = { + .yes_ranges = s32g2_siul20_pad_yes_ranges, + .n_yes_ranges = ARRAY_SIZE(s32g2_siul20_pad_yes_ranges), +}; + +static const struct regmap_range s32g2_siul21_pad_yes_ranges[] = { + regmap_reg_range(SIUL2_PGPDO(7), SIUL2_PGPDO(7)), + regmap_reg_range(SIUL2_PGPDO(9), SIUL2_PGPDO(9)), + regmap_reg_range(SIUL2_PGPDO(10), SIUL2_PGPDO(10)), + regmap_reg_range(SIUL2_PGPDO(11), SIUL2_PGPDO(11)), +}; + +static const struct regmap_access_table s32g2_siul21_pad_access_table = { + .yes_ranges = s32g2_siul21_pad_yes_ranges, + .n_yes_ranges = ARRAY_SIZE(s32g2_siul21_pad_yes_ranges), +}; + +static const struct regmap_access_table *s32g2_pad_access_table[] = { + &s32g2_siul20_pad_access_table, + &s32g2_siul21_pad_access_table +}; + +static_assert(ARRAY_SIZE(s32g2_pad_access_table) == S32G2_SIUL2_NUM); + +static const struct siul2_device_data s32g2_device_data = { + .pad_access = s32g2_pad_access_table, + .reset_cnt = true, +}; + +static int siul2_get_gpio_pinspec(struct platform_device *pdev, + struct of_phandle_args *pinspec, + unsigned int range_index) +{ + struct device_node *np = pdev->dev.of_node; + + return of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, + range_index, pinspec); +} + +static struct regmap *siul2_offset_to_regmap(struct siul2_gpio_dev *dev, + unsigned int offset, + bool input) +{ + struct siul2_desc *siul2; + size_t i; + + for (i = 0; i < ARRAY_SIZE(dev->siul2); i++) { + siul2 = &dev->siul2[i]; + if (offset >= siul2->gpio_base && + offset - siul2->gpio_base < siul2->gpio_num) + return input ? siul2->ipadmap : siul2->opadmap; + } + + return NULL; +} + +static void siul2_gpio_set_direction(struct siul2_gpio_dev *dev, + unsigned int gpio, int dir) +{ + guard(raw_spinlock_irqsave)(&dev->lock); + + if (dir == GPIO_LINE_DIRECTION_IN) + __clear_bit(gpio, dev->pin_dir_bitmap); + else + __set_bit(gpio, dev->pin_dir_bitmap); +} + +static int siul2_get_direction(struct siul2_gpio_dev *dev, + unsigned int gpio) +{ + return test_bit(gpio, dev->pin_dir_bitmap) ? GPIO_LINE_DIRECTION_OUT : + GPIO_LINE_DIRECTION_IN; +} + +static struct siul2_gpio_dev *to_siul2_gpio_dev(struct gpio_chip *chip) +{ + return container_of(chip, struct siul2_gpio_dev, gc); +} + +static int siul2_gpio_dir_in(struct gpio_chip *chip, unsigned int gpio) +{ + struct siul2_gpio_dev *gpio_dev; + int ret = 0; + + ret = pinctrl_gpio_direction_input(chip, gpio); + if (ret) + return ret; + + gpio_dev = to_siul2_gpio_dev(chip); + siul2_gpio_set_direction(gpio_dev, gpio, GPIO_LINE_DIRECTION_IN); + + return 0; +} + +static int siul2_gpio_get_dir(struct gpio_chip *chip, unsigned int gpio) +{ + return siul2_get_direction(to_siul2_gpio_dev(chip), gpio); +} + +static unsigned int siul2_pin2pad(unsigned int pin) +{ + return pin / SIUL2_GPIO_16_PAD_SIZE; +} + +static u16 siul2_pin2mask(unsigned int pin) +{ + /** + * From Reference manual : + * PGPDOx[PPDOy] = GPDO(x × 16) + (15 - y)[PDO_(x × 16) + (15 - y)] + */ + return BIT(SIUL2_GPIO_16_PAD_SIZE - 1 - pin % SIUL2_GPIO_16_PAD_SIZE); +} + +static void siul2_gpio_set_val(struct gpio_chip *chip, unsigned int offset, + int value) +{ + struct siul2_gpio_dev *gpio_dev = to_siul2_gpio_dev(chip); + unsigned int pad, reg_offset; + struct regmap *regmap; + u16 mask; + + mask = siul2_pin2mask(offset); + pad = siul2_pin2pad(offset); + + reg_offset = SIUL2_PGPDO(pad); + regmap = siul2_offset_to_regmap(gpio_dev, offset, false); + if (!regmap) + return; + + value = value ? mask : 0; + + regmap_update_bits(regmap, reg_offset, mask, value); +} + +static int siul2_gpio_dir_out(struct gpio_chip *chip, unsigned int gpio, + int val) +{ + struct siul2_gpio_dev *gpio_dev; + int ret = 0; + + gpio_dev = to_siul2_gpio_dev(chip); + siul2_gpio_set_val(chip, gpio, val); + + ret = pinctrl_gpio_direction_output(chip, gpio); + if (ret) + return ret; + + siul2_gpio_set_direction(gpio_dev, gpio, GPIO_LINE_DIRECTION_OUT); + + return 0; +} + +static void siul2_gpio_set(struct gpio_chip *chip, unsigned int offset, + int value) +{ + struct siul2_gpio_dev *gpio_dev = to_siul2_gpio_dev(chip); + + if (!gpio_dev) + return; + + if (siul2_get_direction(gpio_dev, offset) == GPIO_LINE_DIRECTION_IN) + return; + + siul2_gpio_set_val(chip, offset, value); +} + +static int siul2_gpio_get(struct gpio_chip *chip, unsigned int offset) +{ + struct siul2_gpio_dev *gpio_dev = to_siul2_gpio_dev(chip); + unsigned int mask, pad, reg_offset, data = 0; + struct regmap *regmap; + + mask = siul2_pin2mask(offset); + pad = siul2_pin2pad(offset); + + reg_offset = SIUL2_PGPDO(pad); + regmap = siul2_offset_to_regmap(gpio_dev, offset, true); + if (!regmap) + return -EINVAL; + + regmap_read(regmap, reg_offset, &data); + + return !!(data & mask); +} + +static const struct regmap_config siul2_regmap_conf = { + .val_bits = 32, + .reg_bits = 32, + .reg_stride = 4, + .cache_type = REGCACHE_FLAT, +}; + +static struct regmap *common_regmap_init(struct platform_device *pdev, + struct regmap_config *conf, + const char *name) +{ + struct device *dev = &pdev->dev; + struct resource *res; + resource_size_t size; + void __iomem *base; + + base = devm_platform_get_and_ioremap_resource_byname(pdev, name, &res); + if (IS_ERR(base)) { + dev_err(&pdev->dev, "Failed to get MEM resource: %s\n", name); + return ERR_PTR(-EINVAL); + } + + size = resource_size(res); + conf->val_bits = conf->reg_stride * 8; + conf->max_register = size - conf->reg_stride; + conf->name = name; + conf->use_raw_spinlock = true; + + if (conf->cache_type != REGCACHE_NONE) + conf->num_reg_defaults_raw = do_div(size, conf->reg_stride); + + return devm_regmap_init_mmio(dev, base, conf); +} + +static bool not_writable(__always_unused struct device *dev, + __always_unused unsigned int reg) +{ + return false; +} + +static struct regmap *init_padregmap(struct platform_device *pdev, + struct siul2_gpio_dev *gpio_dev, + int selector, bool input) +{ + const struct siul2_device_data *platdata = gpio_dev->platdata; + struct regmap_config regmap_conf = siul2_regmap_conf; + char dts_tag[S32G2_PADS_DTS_TAG_LEN]; + int err; + + regmap_conf.reg_stride = 2; + + if (selector != 0 && selector != 1) + return ERR_PTR(-EINVAL); + + regmap_conf.rd_table = platdata->pad_access[selector]; + + err = snprintf(dts_tag, ARRAY_SIZE(dts_tag), "%cpads%d", + input ? 'i' : 'o', selector); + if (err < 0) + return ERR_PTR(-EINVAL); + + if (input) { + regmap_conf.writeable_reg = not_writable; + regmap_conf.cache_type = REGCACHE_NONE; + } else { + regmap_conf.wr_table = platdata->pad_access[selector]; + } + + return common_regmap_init(pdev, ®map_conf, dts_tag); +} + +static int siul2_gpio_pads_init(struct platform_device *pdev, + struct siul2_gpio_dev *gpio_dev) +{ + struct device *dev = &pdev->dev; + size_t i; + + for (i = 0; i < ARRAY_SIZE(gpio_dev->siul2); i++) { + gpio_dev->siul2[i].opadmap = init_padregmap(pdev, gpio_dev, i, + false); + if (IS_ERR(gpio_dev->siul2[i].opadmap)) { + dev_err(dev, + "Failed to initialize opad2%zu regmap config\n", + i); + return PTR_ERR(gpio_dev->siul2[i].opadmap); + } + + gpio_dev->siul2[i].ipadmap = init_padregmap(pdev, gpio_dev, i, + true); + if (IS_ERR(gpio_dev->siul2[i].ipadmap)) { + dev_err(dev, + "Failed to initialize ipad2%zu regmap config\n", + i); + return PTR_ERR(gpio_dev->siul2[i].ipadmap); + } + } + + return 0; +} + +static int siul2_gen_names(struct device *dev, unsigned int cnt, char **names, + char *ch_index, unsigned int *num_index) +{ + unsigned int i; + + for (i = 0; i < cnt; i++) { + if (i != 0 && !(*num_index % 16)) + (*ch_index)++; + + names[i] = devm_kasprintf(dev, GFP_KERNEL, "P%c_%02d", + *ch_index, 0xFU & (*num_index)++); + if (!names[i]) + return -ENOMEM; + } + + return 0; +} + +static int siul2_gpio_remove_reserved_names(struct device *dev, + struct siul2_gpio_dev *gpio_dev, + char **names) +{ + struct device_node *np = dev->of_node; + int num_ranges, i, j, ret; + u32 base_gpio, num_gpio; + + /* Parse the gpio-reserved-ranges to know which GPIOs to exclude. */ + + num_ranges = of_property_count_u32_elems(dev->of_node, + "gpio-reserved-ranges"); + + /* The "gpio-reserved-ranges" is optional. */ + if (num_ranges < 0) + return 0; + num_ranges /= 2; + + for (i = 0; i < num_ranges; i++) { + ret = of_property_read_u32_index(np, "gpio-reserved-ranges", + i * 2, &base_gpio); + if (ret) { + dev_err(dev, "Could not parse the start GPIO: %d\n", + ret); + return ret; + } + + ret = of_property_read_u32_index(np, "gpio-reserved-ranges", + i * 2 + 1, &num_gpio); + if (ret) { + dev_err(dev, "Could not parse num. GPIOs: %d\n", ret); + return ret; + } + + if (base_gpio + num_gpio > gpio_dev->gc.ngpio) { + dev_err(dev, "Reserved GPIOs outside of GPIO range\n"); + return -EINVAL; + } + + /* Remove names set for reserved GPIOs. */ + for (j = base_gpio; j < base_gpio + num_gpio; j++) { + devm_kfree(dev, names[j]); + names[j] = NULL; + } + } + + return 0; +} + +static int siul2_gpio_populate_names(struct device *dev, + struct siul2_gpio_dev *gpio_dev) +{ + unsigned int num_index = 0; + char ch_index = 'A'; + char **names; + int i, ret; + + names = devm_kcalloc(dev, gpio_dev->gc.ngpio, sizeof(*names), + GFP_KERNEL); + if (!names) + return -ENOMEM; + + for (i = 0; i < S32G2_SIUL2_NUM; i++) { + ret = siul2_gen_names(dev, gpio_dev->siul2[i].gpio_num, + names + gpio_dev->siul2[i].gpio_base, + &ch_index, &num_index); + if (ret) { + dev_err(dev, "Could not set names for SIUL2_%d GPIOs\n", + i); + return ret; + } + + if (gpio_dev->platdata->reset_cnt) + num_index = 0; + + ch_index++; + } + + ret = siul2_gpio_remove_reserved_names(dev, gpio_dev, names); + if (ret) + return ret; + + gpio_dev->gc.names = (const char *const *)names; + + return 0; +} + +static int siul2_gpio_probe(struct platform_device *pdev) +{ + struct siul2_gpio_dev *gpio_dev; + struct device *dev = &pdev->dev; + struct of_phandle_args pinspec; + size_t i, bitmap_size; + struct gpio_chip *gc; + int ret = 0; + + gpio_dev = devm_kzalloc(dev, sizeof(*gpio_dev), GFP_KERNEL); + if (!gpio_dev) + return -ENOMEM; + + gpio_dev->platdata = &s32g2_device_data; + + for (i = 0; i < S32G2_SIUL2_NUM; i++) + gpio_dev->siul2[i].pad_access = + gpio_dev->platdata->pad_access[i]; + + ret = siul2_gpio_pads_init(pdev, gpio_dev); + if (ret) + return ret; + + gc = &gpio_dev->gc; + + platform_set_drvdata(pdev, gpio_dev); + + raw_spin_lock_init(&gpio_dev->lock); + + for (i = 0; i < ARRAY_SIZE(gpio_dev->siul2); i++) { + ret = siul2_get_gpio_pinspec(pdev, &pinspec, i); + if (ret) { + dev_err(dev, + "unable to get pinspec %zu from device tree\n", + i); + return -EINVAL; + } + + of_node_put(pinspec.np); + + if (pinspec.args_count != 3) { + dev_err(dev, "Invalid pinspec count: %d\n", + pinspec.args_count); + return -EINVAL; + } + + gpio_dev->siul2[i].gpio_base = pinspec.args[1]; + gpio_dev->siul2[i].gpio_num = pinspec.args[2]; + } + + gc->base = -1; + + /* In some cases, there is a gap between the SIUL GPIOs. */ + gc->ngpio = gpio_dev->siul2[S32G2_SIUL2_NUM - 1].gpio_base + + gpio_dev->siul2[S32G2_SIUL2_NUM - 1].gpio_num; + + ret = siul2_gpio_populate_names(&pdev->dev, gpio_dev); + if (ret) + return ret; + + bitmap_size = BITS_TO_LONGS(gc->ngpio) * + sizeof(*gpio_dev->pin_dir_bitmap); + gpio_dev->pin_dir_bitmap = devm_kzalloc(dev, bitmap_size, GFP_KERNEL); + if (!gpio_dev->pin_dir_bitmap) + return -ENOMEM; + + gc->parent = dev; + gc->label = dev_name(dev); + + gc->set = siul2_gpio_set; + gc->get = siul2_gpio_get; + gc->set_config = gpiochip_generic_config; + gc->request = gpiochip_generic_request; + gc->free = gpiochip_generic_free; + gc->direction_output = siul2_gpio_dir_out; + gc->direction_input = siul2_gpio_dir_in; + gc->get_direction = siul2_gpio_get_dir; + gc->owner = THIS_MODULE; + + ret = devm_gpiochip_add_data(dev, gc, gpio_dev); + if (ret) + return dev_err_probe(dev, ret, "unable to add gpiochip\n"); + + return 0; +} + +static const struct of_device_id siul2_gpio_dt_ids[] = { + { .compatible = "nxp,s32g2-siul2-gpio" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, siul2_gpio_dt_ids); + +static struct platform_driver siul2_gpio_driver = { + .driver = { + .name = "s32g2-siul2-gpio", + .of_match_table = siul2_gpio_dt_ids, + }, + .probe = siul2_gpio_probe, +}; + +module_platform_driver(siul2_gpio_driver); + +MODULE_AUTHOR("NXP"); +MODULE_DESCRIPTION("NXP SIUL2 GPIO"); +MODULE_LICENSE("GPL");