From patchwork Wed Sep 25 14:54:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dhruva Gole X-Patchwork-Id: 830672 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7E46E1D5AD1; Wed, 25 Sep 2024 14:54:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.248 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727276095; cv=none; b=kmVqI8AfHymXBKH6ZFt8ROwmXR56mtokWLpyR+b8ICPusdfiuULyg//sUc7mNTlVdAnQtYswcZoYWzE3NWANIHSD+2c9tUvI5GF4j98g1dkDv8Exr6c3DDpLuoCySAN7tcnL+LD65L+EDhXWMoYROW6X36FFhA9b5Mp8xtPmnkc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727276095; c=relaxed/simple; bh=K16//F0DbPidmtkltMX/58Fp9H3+Gu7z7oJbF7Rw3t8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=KBsGx4kpwKd6/C8CWeGfZPPG9WAl9SCJkw7QR1oZDJoP/0ohm1IYT1niyznrPfCqrObBcQSDEAKSMt8O+UENSyS9//HXcWm8SHrBIcGVGjByhGo0331jnXmpL1HtOyDLrXexhOTUHYZXn8D3LRrtP8E29Y280ssU6lrf9nnZzVw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=nsX2ra+3; arc=none smtp.client-ip=198.47.23.248 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="nsX2ra+3" Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 48PEsmbu062906; Wed, 25 Sep 2024 09:54:48 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1727276088; bh=NK+aFPtpOPuMKEx44hKVNRmBW7EcmS4qirihAf/Pj8U=; h=From:Date:Subject:References:In-Reply-To:To:CC; b=nsX2ra+3Ip62JVHWJymWSjig9RqGPPT78FYvzSFZd9Iz3fVgGIYwp+b8PWY43adKR cT0br7RvvX2DVpqiCtiPMi0NGEIVwl/Q3vUeNaFMKflQPFzyCJbgOG0A1Nxejs311F S/8dmRM61A9yNdGOrXLihg52D+/tq71OoCk1ma54= Received: from DFLE111.ent.ti.com (dfle111.ent.ti.com [10.64.6.32]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 48PEsmwJ101421 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 25 Sep 2024 09:54:48 -0500 Received: from DFLE103.ent.ti.com (10.64.6.24) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 25 Sep 2024 09:54:47 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 25 Sep 2024 09:54:47 -0500 Received: from [127.0.1.1] (lcpd911.dhcp.ti.com [172.24.227.226]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 48PEsYCj110564; Wed, 25 Sep 2024 09:54:44 -0500 From: Dhruva Gole Date: Wed, 25 Sep 2024 20:24:16 +0530 Subject: [PATCH v6 2/6] arm64: dts: ti: k3-am62a7-sk: add 1.4ghz opp entry Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240925-ti-cpufreq-fixes-v5-v6-2-46f41a903e01@ti.com> References: <20240925-ti-cpufreq-fixes-v5-v6-0-46f41a903e01@ti.com> In-Reply-To: <20240925-ti-cpufreq-fixes-v5-v6-0-46f41a903e01@ti.com> To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Rafael J. Wysocki" , Viresh Kumar CC: , , , , Andrew Davis , Bryan Brattlof , Dhruva Gole X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1727276075; l=1133; i=d-gole@ti.com; s=20240919; h=from:subject:message-id; bh=QKNdDE/Q+mzdtPNctGFPfcbWIa4u1MDTUg8/co9DUGU=; b=AtB9POziL6pfK4Jk8OvZ8M+fdXEs8pyd6ZAwhnELOGgOqNUczu4DZBh7EtOObYrlOH179kHX1 CX6f1MnKfkXAra24GkBdBKagqzp2Z8kOmcGHFjkYh9aCsfavJ3fnC82 X-Developer-Key: i=d-gole@ti.com; a=ed25519; pk=k8NnY4RbxVqeqGsYfTHeVn4hPOHkjg7Mii0Ixs4rghM= X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea From: Bryan Brattlof The AM62Ax reference board is capable of supplying 0v85 to the VDD_CORE which allows the Cortex-A53s to operate at 1.4GHz according to chapter 7.5 of the SoC's data sheet[0]. Append the 1.4Ghz entry to the OPP table to enable this OPP [0] https://www.ti.com/lit/ds/symlink/am62a3.pdf Signed-off-by: Bryan Brattlof --- arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts index 67faf46d7a35a5954a5a832b8ab766320b48ea59..a6f0d87a50d8a7ebdb61e609e8071d6681dbec9a 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts @@ -68,6 +68,15 @@ wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 { }; }; + opp-table { + /* Requires VDD_CORE at 0v85 */ + opp-1400000000 { + opp-hz = /bits/ 64 <1400000000>; + opp-supported-hw = <0x01 0x0004>; + clock-latency-ns = <6000000>; + }; + }; + vmain_pd: regulator-0 { /* TPS25750 PD CONTROLLER OUTPUT */ compatible = "regulator-fixed"; From patchwork Wed Sep 25 14:54:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dhruva Gole X-Patchwork-Id: 830671 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 334F514F9D0; Wed, 25 Sep 2024 14:55:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.141 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727276104; cv=none; b=suKTj19m7NvbTrNm2ng3AD/0W7+v10Yi/+Qi8S4jPmFoIuKfG3B0kvuiLToW5y0pr1oGxk7R6x8KyXVmJW87mKXHNaZJoF1ey8wdyEqpIqqK9IbTA6s+h5CEq679ZSpevqYcutLWZKHhvl0Koi2tuSV1QECjRtn+7R7loSrntBI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727276104; c=relaxed/simple; bh=9TdNETtTnsOfwHv1BPX1X4EncEO6xuAjOt7AXgk6a04=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=Hl1poVzZ5wq1MBbGHqKyRcF1MRvdMaD4UYkx6BaNK1scZwhhcil9Z158jL/aPx+uI6/qxMj/Sj0sfqeR/Pv3/wqGT1sh9Ph2PWJjEBkv1RYD89upAMiVpIoSBPYVwpGVusK1OEMHF7qMFCDQmialabAxyL8pE0mWRCnQbSFnfpM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=bAVQuByl; arc=none smtp.client-ip=198.47.19.141 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="bAVQuByl" Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 48PEsuYf073375; Wed, 25 Sep 2024 09:54:56 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1727276096; bh=6kNy+oF+7IH4TdlM7HPfJbKXYAWCEdbMeGLixnsPAxc=; h=From:Date:Subject:References:In-Reply-To:To:CC; b=bAVQuBylmq89/IXa1ie+8ftRNXj01PsrpOl/CwAtE/GlCzKSKpekabhGhNrRJ1Pjg PaeAEEspzYZMThk6QHdrqziyzLUmQDiWkL7v9/oWyRzLxpNP5iO0Y3Jg0uhQQFI7Oo 1vCTrfF2BjX1dKauiVEhEcAVub5lFx6i7rkGhjqk= Received: from DFLE111.ent.ti.com (dfle111.ent.ti.com [10.64.6.32]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 48PEsufj019355 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 25 Sep 2024 09:54:56 -0500 Received: from DFLE101.ent.ti.com (10.64.6.22) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 25 Sep 2024 09:54:56 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 25 Sep 2024 09:54:55 -0500 Received: from [127.0.1.1] (lcpd911.dhcp.ti.com [172.24.227.226]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 48PEsYCl110564; Wed, 25 Sep 2024 09:54:52 -0500 From: Dhruva Gole Date: Wed, 25 Sep 2024 20:24:18 +0530 Subject: [PATCH v6 4/6] arm64: dts: ti: k3-am62p5-sk: add 1.4ghz opp entry Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240925-ti-cpufreq-fixes-v5-v6-4-46f41a903e01@ti.com> References: <20240925-ti-cpufreq-fixes-v5-v6-0-46f41a903e01@ti.com> In-Reply-To: <20240925-ti-cpufreq-fixes-v5-v6-0-46f41a903e01@ti.com> To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Rafael J. Wysocki" , Viresh Kumar CC: , , , , Andrew Davis , Bryan Brattlof , Dhruva Gole X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1727276075; l=1070; i=d-gole@ti.com; s=20240919; h=from:subject:message-id; bh=J2V9iMpCezlqmgozhrln6pQnlfb3x2eF+J3i+JcTGx0=; b=ia9CW9/0ztWYQ+kII9d3XGkREIhnseM8u/xF9AuocdCAwMoZbrecJZ9dCbDOuDaC2Ab95EDfX RLjZ7sm3mqDBcDI7qB9dZvAxqziVfLEW0+vKgZ7JLzH+Z4cLW/N8TdQ X-Developer-Key: i=d-gole@ti.com; a=ed25519; pk=k8NnY4RbxVqeqGsYfTHeVn4hPOHkjg7Mii0Ixs4rghM= X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea From: Bryan Brattlof The AM62Px reference board is capable of supplying 0v85 to the VDD_CORE which allows the Cortex-A53s to operate at 1.4GHz according to chapter 6.6 of the SoC's data sheet[0] . Append the 1.4Ghz entry to the OPP table to enable this frequency [0] https://www.ti.com/lit/ds/symlink/am62p-q1.pdf Signed-off-by: Bryan Brattlof --- arch/arm64/boot/dts/ti/k3-am62p5-sk.dts | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts index 3efa12bb72546291e2fda79695edf577bbb134a1..7f3dc39e12bc9ca4a746ff092f946b84a36404b3 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts @@ -128,6 +128,15 @@ led-0 { }; }; + opp-table { + /* Requires VDD_CORE at 0v85 */ + opp-1400000000 { + opp-hz = /bits/ 64 <1400000000>; + opp-supported-hw = <0x01 0x0004>; + clock-latency-ns = <6000000>; + }; + }; + tlv320_mclk: clk-0 { #clock-cells = <0>; compatible = "fixed-clock"; From patchwork Wed Sep 25 14:54:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dhruva Gole X-Patchwork-Id: 830670 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EF666188934; Wed, 25 Sep 2024 14:55:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.248 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727276111; cv=none; b=cfvKHGEF6Ni6347E2VlME9x65+PB703O+I3cgSXi3EiAyg8PeCFQkaLJ+LDk2jHDox4oRMEBhqq4I/VjaoBn6xw7XHZnAwrbrp/NDtqVe0JI2wPPfaYA/XDngv3aJCfAibfkW7cyifcipqaxeWj5kc690QKXPWmijlAac25fokI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727276111; c=relaxed/simple; bh=xdbK3sX33TuJDpUjLbXTCDI0D2SFxjFhg9r0p9JHT54=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=SnXCM9KIJMfasgy/5X14fBtKkyulCNGOxQHeNQd9P2QUUlVpjenmzGjqgGNjWr7rXUZRi7zGbrWNJYN+3ypHvI5zimMhQOSwXVw0Ge/9n43K+ELJfBWhLItAlwppmFif+/Ph1Ld28tl2d6Vt3ugh5WPR7MGbAv9w0TyRf1eG9mM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=CDvtJlod; arc=none smtp.client-ip=198.47.23.248 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="CDvtJlod" Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 48PEt4j0062997; Wed, 25 Sep 2024 09:55:04 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1727276104; bh=SoE3frTgrrAbkkW+0hWzW5YqidptuOBpjGiZMGx02Ew=; h=From:Date:Subject:References:In-Reply-To:To:CC; b=CDvtJlodjAiDT7Nhnkp/7jYUbnMMzvkawKosGqASR/HqCJ1dsLuM6sWKATA2dHRnY oy2cqf05zgXHk4P8vbvNUGlgpYww7nNURikWbXxltfgF80lIvro4Bg2K5KtsQcAneo MzNGEktsZCQ/ks2QZwAXroZCZ4OmRZP5G0g7ofTo= Received: from DFLE113.ent.ti.com (dfle113.ent.ti.com [10.64.6.34]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 48PEt4D3092264 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 25 Sep 2024 09:55:04 -0500 Received: from DFLE112.ent.ti.com (10.64.6.33) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 25 Sep 2024 09:55:04 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 25 Sep 2024 09:55:04 -0500 Received: from [127.0.1.1] (lcpd911.dhcp.ti.com [172.24.227.226]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 48PEsYCn110564; Wed, 25 Sep 2024 09:55:00 -0500 From: Dhruva Gole Date: Wed, 25 Sep 2024 20:24:20 +0530 Subject: [PATCH v6 6/6] cpufreq: ti-cpufreq: Update efuse/rev offsets in AM62 family Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240925-ti-cpufreq-fixes-v5-v6-6-46f41a903e01@ti.com> References: <20240925-ti-cpufreq-fixes-v5-v6-0-46f41a903e01@ti.com> In-Reply-To: <20240925-ti-cpufreq-fixes-v5-v6-0-46f41a903e01@ti.com> To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Rafael J. Wysocki" , Viresh Kumar CC: , , , , Andrew Davis , Bryan Brattlof , Dhruva Gole X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1727276075; l=2875; i=d-gole@ti.com; s=20240919; h=from:subject:message-id; bh=xdbK3sX33TuJDpUjLbXTCDI0D2SFxjFhg9r0p9JHT54=; b=NmSRfzqh6TLYqUwObdIiSB6IE4akueqjdw/lEC4Fha1Jn88KcxDq7HkAmiVYRgZFBN5G6+uWR jR+3L1vtZzvDViVVX6hXPF+4Cc+vwrPq8p8x5/NQfUR3hut2Ojara8K X-Developer-Key: i=d-gole@ti.com; a=ed25519; pk=k8NnY4RbxVqeqGsYfTHeVn4hPOHkjg7Mii0Ixs4rghM= X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea With the Silicon revision being taken directly from socinfo, there's no longer any need for reading any SOC register for revision from this driver. Hence, we do not require any rev_offset for AM62 family of devices. The efuse offset should be 0x0 for AM625 as well, as the syscon register being used from DT refers to the efuse_offset directly. However, to maintain the backward compatibility with old devicetree, also add condition to handle the case where we have the wrong offset and add the older efuse_offset value there such that we don't end up reading the wrong register offset. Signed-off-by: Dhruva Gole --- drivers/cpufreq/ti-cpufreq.c | 23 +++++++++++++++++------ 1 file changed, 17 insertions(+), 6 deletions(-) diff --git a/drivers/cpufreq/ti-cpufreq.c b/drivers/cpufreq/ti-cpufreq.c index ba621ce1cdda694c98867422dbb7f10c0df2afef..8a97b95b4c44a76b12cab76ddc0f9a5b8ae73f84 100644 --- a/drivers/cpufreq/ti-cpufreq.c +++ b/drivers/cpufreq/ti-cpufreq.c @@ -313,10 +313,9 @@ static const struct soc_device_attribute k3_cpufreq_soc[] = { static struct ti_cpufreq_soc_data am625_soc_data = { .efuse_xlate = am625_efuse_xlate, - .efuse_offset = 0x0018, + .efuse_offset = 0x0, .efuse_mask = 0x07c0, .efuse_shift = 0x6, - .rev_offset = 0x0014, .multi_regulator = false, }; @@ -325,7 +324,6 @@ static struct ti_cpufreq_soc_data am62a7_soc_data = { .efuse_offset = 0x0, .efuse_mask = 0x07c0, .efuse_shift = 0x6, - .rev_offset = 0x0014, .multi_regulator = false, }; @@ -334,7 +332,6 @@ static struct ti_cpufreq_soc_data am62p5_soc_data = { .efuse_offset = 0x0, .efuse_mask = 0x07c0, .efuse_shift = 0x6, - .rev_offset = 0x0014, .multi_regulator = false, }; @@ -349,11 +346,25 @@ static int ti_cpufreq_get_efuse(struct ti_cpufreq_data *opp_data, u32 *efuse_value) { struct device *dev = opp_data->cpu_dev; + struct device_node *np = opp_data->opp_node; u32 efuse; int ret; - ret = regmap_read(opp_data->syscon, opp_data->soc_data->efuse_offset, - &efuse); + /* + * The following check is used as a way to check if this is an older devicetree + * being used where the entire wkup_conf node was marked as "syscon", + * "simple-mfd". + * Since this bug only affects AM625, make sure it enters this condition + * only for that SoC. + */ + if (of_device_is_compatible(np, "simple-mfd") && + of_device_is_compatible(np, "ti,am625")) { + ret = regmap_read(opp_data->syscon, opp_data->soc_data->efuse_offset + 0x0018, + &efuse); + } else { + ret = regmap_read(opp_data->syscon, opp_data->soc_data->efuse_offset, + &efuse); + } if (opp_data->soc_data->quirks & TI_QUIRK_SYSCON_MAY_BE_MISSING && ret == -EIO) { /* not a syscon register! */ void __iomem *regs = ioremap(OMAP3_SYSCON_BASE +