From patchwork Thu Nov 21 05:02:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 179902 Delivered-To: patch@linaro.org Received: by 2002:a92:38d5:0:0:0:0:0 with SMTP id g82csp3086274ilf; Wed, 20 Nov 2019 21:02:52 -0800 (PST) X-Google-Smtp-Source: APXvYqzAUj1cOv9vE2q/7m6C+/97MH3fsf+Q617EgWKTA49z+IutEFJU7EKqHqBoOrS2ivK6+RsN X-Received: by 2002:a1c:9d89:: with SMTP id g131mr7744598wme.81.1574312572439; Wed, 20 Nov 2019 21:02:52 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1574312572; cv=none; d=google.com; s=arc-20160816; b=ePNlj34g2NDp+RsvlEXcPyMteBA2xR7gIVGNh+G/k4IbfSnAsh2q9vJipsdrFhRQn6 kkeDSJ0iz6aOOEkxNhbV1k4IAKvDpor3hL4pp6fKC5C9J0fQDzX55VnYhLbum4gUQvd7 DsyFxDJTuzTJ7K00sw36soq/3z5CrJqKmePCh70opmR4PIHXwRJNsXYCWWcPL5wqUSrc Lk9BN6Qp6Et2UcEMivsrrysL9BitB2/F0M95iEDjOcnsZv5jpkyLUoRzMVpnToabzh85 mrA9bPCwYDNNR/j90i9JfvmlPu3/2shdDdpjBAjQCkv6MeVuP7Dg3WdUzmVGTBXtOWuK 4byw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=DtiLQsPJOZDwwzL7UIwFduxFgA2Qjdi+hVrUPDyEOqE=; b=qyBSP+hYqfaiUJJvCtBIYhxfjcpdPQIPmHR0qM7fdQIIY1SALVnKQLQar88y47+oql xkDb7S7LNXT5lh/2PVVjFncr0u9poBUnDXh10zE+qAoBE7wBD8fVJehgguCzbJQj2xuh HBlF2/Kens0Np7nUkRRsBPBOo4hhb8X08FYLGMm1/BzR2lMHttDMk8HtpItPPyDst+qu FFFOTwPWfOMnDe2fXl+LyGNIH1k+Ip0czzWAgHF1pl1F14ZFisr8BCfnslxZm/PgmYDJ b/jYNBkHbqT1iu7N3/QHfr0xbawEFm9yHMFHR+UM9qIEM5uODpMni8isNyhuFGt6Mhf6 o3Ag== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id be24si1324467edb.156.2019.11.20.21.02.52; Wed, 20 Nov 2019 21:02:52 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726976AbfKUFCu (ORCPT + 26 others); Thu, 21 Nov 2019 00:02:50 -0500 Received: from mx2.suse.de ([195.135.220.15]:36394 "EHLO mx1.suse.de" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1725904AbfKUFCX (ORCPT ); Thu, 21 Nov 2019 00:02:23 -0500 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (unknown [195.135.220.254]) by mx1.suse.de (Postfix) with ESMTP id F1E1DAFF6; Thu, 21 Nov 2019 05:02:18 +0000 (UTC) From: =?utf-8?q?Andreas_F=C3=A4rber?= To: linux-realtek-soc@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, =?utf-8?q?Andreas_F=C3=A4rber?= , Aleix Roca Nonell , James Tai , Thomas Gleixner , Jason Cooper , Marc Zyngier Subject: [PATCH v5 2/9] irqchip: Add Realtek RTD1295 mux driver Date: Thu, 21 Nov 2019 06:02:01 +0100 Message-Id: <20191121050208.11324-3-afaerber@suse.de> X-Mailer: git-send-email 2.16.4 In-Reply-To: <20191121050208.11324-1-afaerber@suse.de> References: <20191121050208.11324-1-afaerber@suse.de> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This irq mux driver implements the RTD1295 SoC's non-linear mapping between status and enable bits. Based in part on QNAP's arch/arm/mach-rtk119x/rtk_irq_mux.c and Synology's drivers/irqchip/irq-rtk.c code. Signed-off-by: Andreas Färber Cc: Aleix Roca Nonell Signed-off-by: James Tai Signed-off-by: Andreas Färber --- v4 -> v5: * Renamed enable/disable to unmask/mask (Marc) * Factored out ack (Marc) * Clear all interrupts just in case * Added and mapped WDOG_NMI * Suppress mapping NMIs and reserved bits (Marc) * Dropped mask checks in mask/unmask (Marc) * Dropped mask check in interrupt handler * Renamed misc bits by inserting MIS_ for consistency * Duplicate irq_chip into rtd1195_mux_data * Renamed irq_chip from long rtd1195-mux to iso/misc, tidying /proc/interrupts v3 -> v4: * Drop no-op .irq_set_affinity callback (Thomas) * Clear all interrupts (James) * Updated SPDX-License-identifier * Use tabular formatting (Thomas) * Adopt different braces style (Thomas) * Use raw_spinlock_t (Thomas) * Shortened callback from isr_to_scpu_int_en_mask to isr_to_int_en_mask (Thomas) * Fixed of_iomap() error handling to not use IS_ERR() * Don't mask unmapped NMIs by checking for a non-zero mask * Cache SCPU_INT_EN to avoid superfluous reads (Thomas) * Renamed functions and variables from rtd119x to rtd1195 v2 -> v3: * Adopted spin_lock_irq{save,restore}() (Marc) * Adopted single-write masking (Marc) * Adopted misc compatible string * Introduced explicit bit mapping * Adopted looped processing of pending interrupts (Marc) * Replaced unmask implementation with UMSK_ISR write * Introduced enable/disable ops and dropped no longer needed UART0 quirk v1 -> v2: * Renamed struct fields to avoid ambiguity (Marc) * Refactored offset lookup to avoid per-compatible init functions * Inserted white lines to clarify balanced locking (Marc) * Dropped forwarding of set_affinity to GIC (Marc) * Added spinlocks for consistency (Marc) * Limited initialization quirk to iso mux * Fixed spinlock initialization (Andrew) drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-rtd1195-mux.c | 291 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 292 insertions(+) create mode 100644 drivers/irqchip/irq-rtd1195-mux.c -- 2.16.4 diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index e806dda690ea..d678881eebc8 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -104,3 +104,4 @@ obj-$(CONFIG_MADERA_IRQ) += irq-madera.o obj-$(CONFIG_LS1X_IRQ) += irq-ls1x.o obj-$(CONFIG_TI_SCI_INTR_IRQCHIP) += irq-ti-sci-intr.o obj-$(CONFIG_TI_SCI_INTA_IRQCHIP) += irq-ti-sci-inta.o +obj-$(CONFIG_ARCH_REALTEK) += irq-rtd1195-mux.o diff --git a/drivers/irqchip/irq-rtd1195-mux.c b/drivers/irqchip/irq-rtd1195-mux.c new file mode 100644 index 000000000000..0e86973aafca --- /dev/null +++ b/drivers/irqchip/irq-rtd1195-mux.c @@ -0,0 +1,291 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Realtek RTD1295 IRQ mux + * + * Copyright (c) 2017-2019 Andreas Färber + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define UMSK_ISR_WRITE_DATA BIT(0) +#define ISR_WRITE_DATA BIT(0) + +struct rtd1195_irq_mux_info { + const char *name; + unsigned int isr_offset; + unsigned int umsk_isr_offset; + unsigned int scpu_int_en_offset; + const u32 *isr_to_int_en_mask; +}; + +#define SCPU_INT_EN_RSV_MASK 0 +#define SCPU_INT_EN_NMI_MASK GENMASK(31, 0) + +struct rtd1195_irq_mux_data { + void __iomem *reg_isr; + void __iomem *reg_umsk_isr; + void __iomem *reg_scpu_int_en; + const struct rtd1195_irq_mux_info *info; + int irq; + u32 scpu_int_en; + struct irq_chip chip; + struct irq_domain *domain; + raw_spinlock_t lock; +}; + +static void rtd1195_mux_irq_handle(struct irq_desc *desc) +{ + struct rtd1195_irq_mux_data *mux = irq_desc_get_handler_data(desc); + struct irq_chip *chip = irq_desc_get_chip(desc); + u32 isr; + int i; + + chained_irq_enter(chip, desc); + + isr = readl_relaxed(mux->reg_isr); + + while (isr) { + i = __ffs(isr); + isr &= ~BIT(i); + + generic_handle_irq(irq_find_mapping(mux->domain, i)); + } + + chained_irq_exit(chip, desc); +} + +static void rtd1195_mux_ack_irq(struct irq_data *data) +{ + struct rtd1195_irq_mux_data *mux = irq_data_get_irq_chip_data(data); + + writel_relaxed(BIT(data->hwirq) & ~ISR_WRITE_DATA, mux->reg_isr); +} + +static void rtd1195_mux_mask_irq(struct irq_data *data) +{ + struct rtd1195_irq_mux_data *mux = irq_data_get_irq_chip_data(data); + u32 mask = mux->info->isr_to_int_en_mask[data->hwirq]; + unsigned long flags; + + raw_spin_lock_irqsave(&mux->lock, flags); + + mux->scpu_int_en &= ~mask; + writel_relaxed(mux->scpu_int_en, mux->reg_scpu_int_en); + + raw_spin_unlock_irqrestore(&mux->lock, flags); +} + +static void rtd1195_mux_unmask_irq(struct irq_data *data) +{ + struct rtd1195_irq_mux_data *mux = irq_data_get_irq_chip_data(data); + u32 mask = mux->info->isr_to_int_en_mask[data->hwirq]; + unsigned long flags; + + raw_spin_lock_irqsave(&mux->lock, flags); + + mux->scpu_int_en |= mask; + writel_relaxed(mux->scpu_int_en, mux->reg_scpu_int_en); + + raw_spin_unlock_irqrestore(&mux->lock, flags); +} + +static const struct irq_chip rtd1195_mux_irq_chip = { + .irq_ack = rtd1195_mux_ack_irq, + .irq_mask = rtd1195_mux_mask_irq, + .irq_unmask = rtd1195_mux_unmask_irq, +}; + +static int rtd1195_mux_irq_domain_map(struct irq_domain *d, + unsigned int irq, irq_hw_number_t hw) +{ + struct rtd1195_irq_mux_data *mux = d->host_data; + u32 mask; + + if (BIT(hw) == ISR_WRITE_DATA) + return -EINVAL; + + mask = mux->info->isr_to_int_en_mask[hw]; + if (mask == SCPU_INT_EN_RSV_MASK) + return -EINVAL; + + if (mask == SCPU_INT_EN_NMI_MASK) + return -ENOTSUPP; + + irq_set_chip_and_handler(irq, &mux->chip, handle_level_irq); + irq_set_chip_data(irq, mux); + irq_set_probe(irq); + + return 0; +} + +static const struct irq_domain_ops rtd1195_mux_irq_domain_ops = { + .xlate = irq_domain_xlate_onecell, + .map = rtd1195_mux_irq_domain_map, +}; + +enum rtd1295_iso_isr_bits { + RTD1295_ISO_ISR_UR0_SHIFT = 2, + RTD1295_ISO_ISR_IRDA_SHIFT = 5, + RTD1295_ISO_ISR_I2C0_SHIFT = 8, + RTD1295_ISO_ISR_I2C1_SHIFT = 11, + RTD1295_ISO_ISR_RTC_HSEC_SHIFT = 12, + RTD1295_ISO_ISR_RTC_ALARM_SHIFT = 13, + RTD1295_ISO_ISR_GPIOA_SHIFT = 19, + RTD1295_ISO_ISR_GPIODA_SHIFT = 20, + RTD1295_ISO_ISR_GPHY_DV_SHIFT = 29, + RTD1295_ISO_ISR_GPHY_AV_SHIFT = 30, + RTD1295_ISO_ISR_I2C1_REQ_SHIFT = 31, +}; + +static const u32 rtd1295_iso_isr_to_scpu_int_en_mask[32] = { + [RTD1295_ISO_ISR_UR0_SHIFT] = BIT(2), + [RTD1295_ISO_ISR_IRDA_SHIFT] = BIT(5), + [RTD1295_ISO_ISR_I2C0_SHIFT] = BIT(8), + [RTD1295_ISO_ISR_I2C1_SHIFT] = BIT(11), + [RTD1295_ISO_ISR_RTC_HSEC_SHIFT] = BIT(12), + [RTD1295_ISO_ISR_RTC_ALARM_SHIFT] = BIT(13), + [RTD1295_ISO_ISR_GPIOA_SHIFT] = BIT(19), + [RTD1295_ISO_ISR_GPIODA_SHIFT] = BIT(20), + [RTD1295_ISO_ISR_GPHY_DV_SHIFT] = BIT(29), + [RTD1295_ISO_ISR_GPHY_AV_SHIFT] = BIT(30), + [RTD1295_ISO_ISR_I2C1_REQ_SHIFT] = BIT(31), +}; + +enum rtd1295_misc_isr_bits { + RTD1295_MIS_ISR_WDOG_NMI_SHIFT = 2, + RTD1295_MIS_ISR_UR1_SHIFT = 3, + RTD1295_MIS_ISR_UR1_TO_SHIFT = 5, + RTD1295_MIS_ISR_UR2_SHIFT = 8, + RTD1295_MIS_ISR_RTC_MIN_SHIFT = 10, + RTD1295_MIS_ISR_RTC_HOUR_SHIFT = 11, + RTD1295_MIS_ISR_RTC_DATA_SHIFT = 12, + RTD1295_MIS_ISR_UR2_TO_SHIFT = 13, + RTD1295_MIS_ISR_I2C5_SHIFT = 14, + RTD1295_MIS_ISR_I2C4_SHIFT = 15, + RTD1295_MIS_ISR_GPIOA_SHIFT = 19, + RTD1295_MIS_ISR_GPIODA_SHIFT = 20, + RTD1295_MIS_ISR_LSADC0_SHIFT = 21, + RTD1295_MIS_ISR_LSADC1_SHIFT = 22, + RTD1295_MIS_ISR_I2C3_SHIFT = 23, + RTD1295_MIS_ISR_SC0_SHIFT = 24, + RTD1295_MIS_ISR_I2C2_SHIFT = 26, + RTD1295_MIS_ISR_GSPI_SHIFT = 27, + RTD1295_MIS_ISR_FAN_SHIFT = 29, +}; + +static const u32 rtd1295_misc_isr_to_scpu_int_en_mask[32] = { + [RTD1295_MIS_ISR_UR1_SHIFT] = BIT(3), + [RTD1295_MIS_ISR_UR1_TO_SHIFT] = BIT(5), + [RTD1295_MIS_ISR_UR2_TO_SHIFT] = BIT(6), + [RTD1295_MIS_ISR_UR2_SHIFT] = BIT(7), + [RTD1295_MIS_ISR_RTC_MIN_SHIFT] = BIT(10), + [RTD1295_MIS_ISR_RTC_HOUR_SHIFT] = BIT(11), + [RTD1295_MIS_ISR_RTC_DATA_SHIFT] = BIT(12), + [RTD1295_MIS_ISR_I2C5_SHIFT] = BIT(14), + [RTD1295_MIS_ISR_I2C4_SHIFT] = BIT(15), + [RTD1295_MIS_ISR_GPIOA_SHIFT] = BIT(19), + [RTD1295_MIS_ISR_GPIODA_SHIFT] = BIT(20), + [RTD1295_MIS_ISR_LSADC0_SHIFT] = BIT(21), + [RTD1295_MIS_ISR_LSADC1_SHIFT] = BIT(22), + [RTD1295_MIS_ISR_SC0_SHIFT] = BIT(24), + [RTD1295_MIS_ISR_I2C2_SHIFT] = BIT(26), + [RTD1295_MIS_ISR_GSPI_SHIFT] = BIT(27), + [RTD1295_MIS_ISR_I2C3_SHIFT] = BIT(28), + [RTD1295_MIS_ISR_FAN_SHIFT] = BIT(29), + [RTD1295_MIS_ISR_WDOG_NMI_SHIFT] = SCPU_INT_EN_NMI_MASK, +}; + +static const struct rtd1195_irq_mux_info rtd1295_iso_irq_mux_info = { + .name = "iso", + .isr_offset = 0x0, + .umsk_isr_offset = 0x4, + .scpu_int_en_offset = 0x40, + .isr_to_int_en_mask = rtd1295_iso_isr_to_scpu_int_en_mask, +}; + +static const struct rtd1195_irq_mux_info rtd1295_misc_irq_mux_info = { + .name = "misc", + .umsk_isr_offset = 0x8, + .isr_offset = 0xc, + .scpu_int_en_offset = 0x80, + .isr_to_int_en_mask = rtd1295_misc_isr_to_scpu_int_en_mask, +}; + +static const struct of_device_id rtd1295_irq_mux_dt_matches[] = { + { + .compatible = "realtek,rtd1295-iso-irq-mux", + .data = &rtd1295_iso_irq_mux_info, + }, + { + .compatible = "realtek,rtd1295-misc-irq-mux", + .data = &rtd1295_misc_irq_mux_info, + }, + { + } +}; + +static int __init rtd1195_irq_mux_init(struct device_node *node, + struct device_node *parent) +{ + struct rtd1195_irq_mux_data *mux; + const struct of_device_id *match; + const struct rtd1195_irq_mux_info *info; + void __iomem *base; + + match = of_match_node(rtd1295_irq_mux_dt_matches, node); + if (!match) + return -EINVAL; + + info = match->data; + if (!info) + return -EINVAL; + + base = of_iomap(node, 0); + if (!base) + return -EIO; + + mux = kzalloc(sizeof(*mux), GFP_KERNEL); + if (!mux) + return -ENOMEM; + + mux->info = info; + mux->reg_isr = base + info->isr_offset; + mux->reg_umsk_isr = base + info->umsk_isr_offset; + mux->reg_scpu_int_en = base + info->scpu_int_en_offset; + mux->chip = rtd1195_mux_irq_chip; + mux->chip.name = info->name; + + mux->irq = irq_of_parse_and_map(node, 0); + if (mux->irq <= 0) { + kfree(mux); + return -EINVAL; + } + + raw_spin_lock_init(&mux->lock); + + /* Disable (mask) all interrupts */ + writel_relaxed(mux->scpu_int_en, mux->reg_scpu_int_en); + + /* Ack (clear) all interrupts - not all are in UMSK_ISR, so use ISR */ + writel_relaxed(~ISR_WRITE_DATA, mux->reg_isr); + + mux->domain = irq_domain_add_linear(node, 32, + &rtd1195_mux_irq_domain_ops, mux); + if (!mux->domain) { + kfree(mux); + return -ENOMEM; + } + + irq_set_chained_handler_and_data(mux->irq, rtd1195_mux_irq_handle, mux); + + return 0; +} +IRQCHIP_DECLARE(rtd1295_iso_mux, "realtek,rtd1295-iso-irq-mux", rtd1195_irq_mux_init); +IRQCHIP_DECLARE(rtd1295_misc_mux, "realtek,rtd1295-misc-irq-mux", rtd1195_irq_mux_init); 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[209.132.180.67]) by mx.google.com with ESMTP id c19si1181088edt.387.2019.11.20.21.02.24; Wed, 20 Nov 2019 21:02:24 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726500AbfKUFCV (ORCPT + 26 others); Thu, 21 Nov 2019 00:02:21 -0500 Received: from mx2.suse.de ([195.135.220.15]:36406 "EHLO mx1.suse.de" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1725956AbfKUFCU (ORCPT ); Thu, 21 Nov 2019 00:02:20 -0500 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (unknown [195.135.220.254]) by mx1.suse.de (Postfix) with ESMTP id 3B77BB00A; Thu, 21 Nov 2019 05:02:19 +0000 (UTC) From: =?utf-8?q?Andreas_F=C3=A4rber?= To: linux-realtek-soc@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, =?utf-8?q?Andreas_F=C3=A4rber?= , Thomas Gleixner , Jason Cooper , Marc Zyngier Subject: [PATCH v5 3/9] irqchip: rtd1195-mux: Implement irq_get_irqchip_state Date: Thu, 21 Nov 2019 06:02:02 +0100 Message-Id: <20191121050208.11324-4-afaerber@suse.de> X-Mailer: git-send-email 2.16.4 In-Reply-To: <20191121050208.11324-1-afaerber@suse.de> References: <20191121050208.11324-1-afaerber@suse.de> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Implement the .irq_get_irqchip_state callback to retrieve pending, active and masked interrupt status. Signed-off-by: Andreas Färber --- v5: New drivers/irqchip/irq-rtd1195-mux.c | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) -- 2.16.4 diff --git a/drivers/irqchip/irq-rtd1195-mux.c b/drivers/irqchip/irq-rtd1195-mux.c index 0e86973aafca..2f1bcfd9d5d6 100644 --- a/drivers/irqchip/irq-rtd1195-mux.c +++ b/drivers/irqchip/irq-rtd1195-mux.c @@ -7,6 +7,7 @@ #include #include +#include #include #include #include @@ -96,10 +97,45 @@ static void rtd1195_mux_unmask_irq(struct irq_data *data) raw_spin_unlock_irqrestore(&mux->lock, flags); } +static int rtd1195_mux_get_irqchip_state(struct irq_data *data, + enum irqchip_irq_state which, bool *state) +{ + struct rtd1195_irq_mux_data *mux = irq_data_get_irq_chip_data(data); + u32 val; + + switch (which) { + case IRQCHIP_STATE_PENDING: + /* + * UMSK_ISR provides the unmasked pending interrupts, + * except UART and I2C. + */ + val = readl_relaxed(mux->reg_umsk_isr); + *state = !!(val & BIT(data->hwirq)); + break; + case IRQCHIP_STATE_ACTIVE: + /* + * ISR provides the masked pending interrupts, + * including UART and I2C. + */ + val = readl_relaxed(mux->reg_isr); + *state = !!(val & BIT(data->hwirq)); + break; + case IRQCHIP_STATE_MASKED: + val = mux->info->isr_to_int_en_mask[data->hwirq]; + *state = !(mux->scpu_int_en & val); + break; + default: + return -EINVAL; + } + + return 0; +} + static const struct irq_chip rtd1195_mux_irq_chip = { .irq_ack = rtd1195_mux_ack_irq, .irq_mask = rtd1195_mux_mask_irq, .irq_unmask = rtd1195_mux_unmask_irq, + .irq_get_irqchip_state = rtd1195_mux_get_irqchip_state, }; static int rtd1195_mux_irq_domain_map(struct irq_domain *d, From patchwork Thu Nov 21 05:02:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 179896 Delivered-To: patch@linaro.org Received: by 2002:a92:38d5:0:0:0:0:0 with SMTP id g82csp3086029ilf; Wed, 20 Nov 2019 21:02:38 -0800 (PST) X-Google-Smtp-Source: APXvYqxa1dMi+zhwvoDUNymnAMXEy0HCnRH+mIaCLeHJYg1rtwEYzowS+DQ+SEuR7djnZgWLdrue X-Received: by 2002:adf:f386:: with SMTP id m6mr7969459wro.201.1574312558213; Wed, 20 Nov 2019 21:02:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1574312558; cv=none; d=google.com; s=arc-20160816; b=oxdzpMPH+i5bjFr88LzUlrQcaU/PoTOUKSuK0yWcbcRhkGwb7FYPXSnkTN7f0Hw6B7 XTM9UcHHCgkcN8mjEnQjsphmFnzigZUuO2eGn1mfrojwRLYvukVHVMIMim1/jx5Rqsi/ KboZd5hC0PEcwRDN6yuSaxLRzleUfD0GxPbOQJO7pUBF8Xu6skMVODvR9i2uCF2vf1A3 JpO3SKR24BcaLQ9I+GtrulMPm1pZJ7cnBguytYLA5pIPxg0phFc3IIFK7oK1AmhXbn70 swhkE6RUHWKHx2eP23LScON429dm5by6eej5XPSABJyQEqskI4y/HZtQskBTTd5XZShV yrPg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=k+S+3zAThxPQfZJBt50I15a1IVgv5l9y1Silgh8WwbA=; b=MzJh8Lmmdj5MaTFa8f1fEr58ytjoJ62sz6tgtXmj+brBrGVDnGxL5WdV9ucQIm9dcA 7DElZuT/MY6RBUgco3baI29uag88jepsX50YvZxlZR/WrsYnTjKAMkfu3Negy7/WceQ4 vd+MoyVp4Cc8hn8QHvwMiHpzKK8fi5pTYWgpead9roKtHftxghGr24Rk8wiVyD+ijV7v sEq/mEyqKzHrQU+/oB5G3lfEac08IF74ilMeHMl3fUE1EwYvdzhg3vApJjhuyaBlEHzq nTRauJ9S9DKQ5X4heGfDH5QCzCIsflGDvSDVBOKudV1hYiHFAleDGZRydGkWXXpaIOgq 23sg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id h20si1499395edj.48.2019.11.20.21.02.37; Wed, 20 Nov 2019 21:02:38 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726722AbfKUFCY (ORCPT + 26 others); Thu, 21 Nov 2019 00:02:24 -0500 Received: from mx2.suse.de ([195.135.220.15]:36428 "EHLO mx1.suse.de" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726165AbfKUFCV (ORCPT ); Thu, 21 Nov 2019 00:02:21 -0500 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (unknown [195.135.220.254]) by mx1.suse.de (Postfix) with ESMTP id A2994B016; Thu, 21 Nov 2019 05:02:19 +0000 (UTC) From: =?utf-8?q?Andreas_F=C3=A4rber?= To: linux-realtek-soc@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, =?utf-8?q?Andreas_F=C3=A4rber?= , Rob Herring , Mark Rutland , devicetree@vger.kernel.org Subject: [PATCH v5 4/9] arm64: dts: realtek: rtd129x: Add irq muxes and UART interrupts Date: Thu, 21 Nov 2019 06:02:03 +0100 Message-Id: <20191121050208.11324-5-afaerber@suse.de> X-Mailer: git-send-email 2.16.4 In-Reply-To: <20191121050208.11324-1-afaerber@suse.de> References: <20191121050208.11324-1-afaerber@suse.de> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add iso and misc IRQ mux DT nodes to RTD129x SoC family. Update the UART DT nodes with interrupts from these muxes, so that UART0 can be used without earlycon. Signed-off-by: Andreas Färber --- v4 -> v5: Unchanged v3 -> v4: * Rebased onto chip-info and r-bus * Dropped schema-violating second interrupts for UART1 and UART2 v2 -> v3: * Added nodes to rtd129x.dtsi instead of rtd1295.dtsi * Adopted misc compatible string * Renamed node label from irq_mux to misc_irq_mux for clarity v1 -> v2: * Rebased arch/arm64/boot/dts/realtek/rtd129x.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) -- 2.16.4 diff --git a/arch/arm64/boot/dts/realtek/rtd129x.dtsi b/arch/arm64/boot/dts/realtek/rtd129x.dtsi index 7d56c9f5d48a..188b4f256917 100644 --- a/arch/arm64/boot/dts/realtek/rtd129x.dtsi +++ b/arch/arm64/boot/dts/realtek/rtd129x.dtsi @@ -86,6 +86,14 @@ #reset-cells = <1>; }; + iso_irq_mux: interrupt-controller@7000 { + compatible = "realtek,rtd1295-iso-irq-mux"; + reg = <0x7000 0x100>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + }; + iso_reset: reset-controller@7088 { compatible = "snps,dw-low-reset"; reg = <0x7088 0x4>; @@ -105,6 +113,8 @@ reg-io-width = <4>; clock-frequency = <27000000>; resets = <&iso_reset RTD1295_ISO_RSTN_UR0>; + interrupt-parent = <&iso_irq_mux>; + interrupts = <2>; status = "disabled"; }; @@ -115,6 +125,14 @@ <0x171d8 0x4>; }; + misc_irq_mux: interrupt-controller@1b000 { + compatible = "realtek,rtd1295-misc-irq-mux"; + reg = <0x1b000 0x100>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + }; + uart1: serial@1b200 { compatible = "snps,dw-apb-uart"; reg = <0x1b200 0x100>; @@ -122,6 +140,8 @@ reg-io-width = <4>; clock-frequency = <432000000>; resets = <&reset2 RTD1295_RSTN_UR1>; + interrupt-parent = <&misc_irq_mux>; + interrupts = <3>; status = "disabled"; }; @@ -132,6 +152,8 @@ reg-io-width = <4>; clock-frequency = <432000000>; resets = <&reset2 RTD1295_RSTN_UR2>; + interrupt-parent = <&misc_irq_mux>; + interrupts = <8>; status = "disabled"; }; }; From patchwork Thu Nov 21 05:02:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 179899 Delivered-To: patch@linaro.org Received: by 2002:a92:38d5:0:0:0:0:0 with SMTP id g82csp3086054ilf; Wed, 20 Nov 2019 21:02:39 -0800 (PST) X-Google-Smtp-Source: APXvYqwKPsrvUbppCRcsTGnpPb+GvA/SixImioTks9q834lBnWbU6F7bt307fFE9yQy/bO6f2bjY X-Received: by 2002:a17:906:1503:: with SMTP id b3mr10498117ejd.78.1574312559408; Wed, 20 Nov 2019 21:02:39 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1574312559; cv=none; d=google.com; s=arc-20160816; b=N5QayZ1RnyHTLOXLTIWCqhwPvbTpip7Abl+5NuU1AYcsE/P5PHp72DP/HlKGXQYT12 WgaDtQWEg627isA40nBe1jKPG+dBnYYx0ujYgmOy95TuZOl/Ic+DAXO8m/EWrf1D/cEZ nRG5EnYJfEkeTCC9qwJtIxJXl+Fi/TEUZ/kSY+UxfxnlrFltdvoeN24zjyivs7KAG4EV +OGx2udl5izOwQQXMJO1W79ZYbEHL+m4nw59O6HJykV3Kv7+mfmnQuRx1qVVr5pgxkr7 TF18tYbKx1c6ljlx4APKc2B3Bl6D/XK3T0+b+kvY4FkDDAQ0aQQhiJHGVZK7tkyosR4Z dryg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=tPFrHcrEL512NJSLuFz+jc8VnoCWwkgY7ZM8N29Zm9E=; b=zmGrVuJGXvT4EmHT3uxPfP91MeE75vM1wlJ18q2DMYxZFsYjAh5CPZ0OWsvVwM86sd CsJJi3S2dc6550tLskkTBFIC7ZNcp98mlnMxFsXe1nASrrn63QOZaX3I/17aWsjz+mlj lHpePeCmXL7IyiPMkJJSW2hvC4DJZW4tW8TJh8Bay54pu5chPXR2Mf3yR4MuusOke4wT 4fAEfxw2YPz++JYu9iWJtKCh8UWxzurNOmjkjG8O9XMdkt3VlmCAXxIF/uY2VNrhDUnc bguDJ70HwzjN4mwnmQt3PjxPp5MvDNp1JJeX8LCKS+6Nf+djxarc/6inXRWupLSjlBYC pg2w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id h20si1499395edj.48.2019.11.20.21.02.39; Wed, 20 Nov 2019 21:02:39 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726840AbfKUFCg (ORCPT + 26 others); Thu, 21 Nov 2019 00:02:36 -0500 Received: from mx2.suse.de ([195.135.220.15]:36442 "EHLO mx1.suse.de" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1725819AbfKUFCX (ORCPT ); Thu, 21 Nov 2019 00:02:23 -0500 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (unknown [195.135.220.254]) by mx1.suse.de (Postfix) with ESMTP id 13172B01C; Thu, 21 Nov 2019 05:02:20 +0000 (UTC) From: =?utf-8?q?Andreas_F=C3=A4rber?= To: linux-realtek-soc@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, =?utf-8?q?Andreas_F=C3=A4rber?= , Thomas Gleixner , Jason Cooper , Marc Zyngier Subject: [PATCH v5 5/9] irqchip: rtd1195-mux: Add RTD1195 definitions Date: Thu, 21 Nov 2019 06:02:04 +0100 Message-Id: <20191121050208.11324-6-afaerber@suse.de> X-Mailer: git-send-email 2.16.4 In-Reply-To: <20191121050208.11324-1-afaerber@suse.de> References: <20191121050208.11324-1-afaerber@suse.de> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add compatible strings and bit mappings for Realtek RTD1195 SoC. Signed-off-by: Andreas Färber --- v4 -> v5: * Mapped WDOG_NMI * Filled in irq_chip names v3 -> v4: * Use tabular formatting (Thomas) * Adopt different braces style (Thomas) * Updated with shortened isr_to_int_en_mask callback name (Thomas) * Renamed functions and variables from rtd119x_ to rtd1195_ * Renamed enum values from RTD119X_ to RTD1195_ v3: New drivers/irqchip/irq-rtd1195-mux.c | 104 +++++++++++++++++++++++++++++++++++++- 1 file changed, 103 insertions(+), 1 deletion(-) -- 2.16.4 diff --git a/drivers/irqchip/irq-rtd1195-mux.c b/drivers/irqchip/irq-rtd1195-mux.c index 2f1bcfd9d5d6..e3e2e42d9df2 100644 --- a/drivers/irqchip/irq-rtd1195-mux.c +++ b/drivers/irqchip/irq-rtd1195-mux.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-or-later /* - * Realtek RTD1295 IRQ mux + * Realtek RTD1195/RTD1295 IRQ mux * * Copyright (c) 2017-2019 Andreas Färber */ @@ -166,6 +166,82 @@ static const struct irq_domain_ops rtd1195_mux_irq_domain_ops = { .map = rtd1195_mux_irq_domain_map, }; +enum rtd1195_iso_isr_bits { + RTD1195_ISO_ISR_TC3_SHIFT = 1, + RTD1195_ISO_ISR_UR0_SHIFT = 2, + RTD1195_ISO_ISR_IRDA_SHIFT = 5, + RTD1195_ISO_ISR_WDOG_NMI_SHIFT = 7, + RTD1195_ISO_ISR_I2C0_SHIFT = 8, + RTD1195_ISO_ISR_TC4_SHIFT = 9, + RTD1195_ISO_ISR_I2C6_SHIFT = 10, + RTD1195_ISO_ISR_RTC_HSEC_SHIFT = 12, + RTD1195_ISO_ISR_RTC_ALARM_SHIFT = 13, + RTD1195_ISO_ISR_VFD_WDONE_SHIFT = 14, + RTD1195_ISO_ISR_VFD_ARDKPADA_SHIFT = 15, + RTD1195_ISO_ISR_VFD_ARDKPADDA_SHIFT = 16, + RTD1195_ISO_ISR_VFD_ARDSWA_SHIFT = 17, + RTD1195_ISO_ISR_VFD_ARDSWDA_SHIFT = 18, + RTD1195_ISO_ISR_GPIOA_SHIFT = 19, + RTD1195_ISO_ISR_GPIODA_SHIFT = 20, + RTD1195_ISO_ISR_CEC_SHIFT = 22, +}; + +static const u32 rtd1195_iso_isr_to_scpu_int_en_mask[32] = { + [RTD1195_ISO_ISR_UR0_SHIFT] = BIT(2), + [RTD1195_ISO_ISR_IRDA_SHIFT] = BIT(5), + [RTD1195_ISO_ISR_I2C0_SHIFT] = BIT(8), + [RTD1195_ISO_ISR_I2C6_SHIFT] = BIT(10), + [RTD1195_ISO_ISR_RTC_HSEC_SHIFT] = BIT(12), + [RTD1195_ISO_ISR_RTC_ALARM_SHIFT] = BIT(13), + [RTD1195_ISO_ISR_VFD_WDONE_SHIFT] = BIT(14), + [RTD1195_ISO_ISR_VFD_ARDKPADA_SHIFT] = BIT(15), + [RTD1195_ISO_ISR_VFD_ARDKPADDA_SHIFT] = BIT(16), + [RTD1195_ISO_ISR_VFD_ARDSWA_SHIFT] = BIT(17), + [RTD1195_ISO_ISR_VFD_ARDSWDA_SHIFT] = BIT(18), + [RTD1195_ISO_ISR_GPIOA_SHIFT] = BIT(19), + [RTD1195_ISO_ISR_GPIODA_SHIFT] = BIT(20), + [RTD1195_ISO_ISR_CEC_SHIFT] = BIT(22), +}; + +enum rtd1195_misc_isr_bits { + RTD1195_MIS_ISR_WDOG_NMI_SHIFT = 2, + RTD1195_MIS_ISR_UR1_SHIFT = 3, + RTD1195_MIS_ISR_I2C1_SHIFT = 4, + RTD1195_MIS_ISR_UR1_TO_SHIFT = 5, + RTD1195_MIS_ISR_TC0_SHIFT = 6, + RTD1195_MIS_ISR_TC1_SHIFT = 7, + RTD1195_MIS_ISR_RTC_HSEC_SHIFT = 9, + RTD1195_MIS_ISR_RTC_MIN_SHIFT = 10, + RTD1195_MIS_ISR_RTC_HOUR_SHIFT = 11, + RTD1195_MIS_ISR_RTC_DATE_SHIFT = 12, + RTD1195_MIS_ISR_I2C5_SHIFT = 14, + RTD1195_MIS_ISR_I2C4_SHIFT = 15, + RTD1195_MIS_ISR_GPIOA_SHIFT = 19, + RTD1195_MIS_ISR_GPIODA_SHIFT = 20, + RTD1195_MIS_ISR_LSADC_SHIFT = 21, + RTD1195_MIS_ISR_I2C3_SHIFT = 23, + RTD1195_MIS_ISR_I2C2_SHIFT = 26, + RTD1195_MIS_ISR_GSPI_SHIFT = 27, +}; + +static const u32 rtd1195_misc_isr_to_scpu_int_en_mask[32] = { + [RTD1195_MIS_ISR_UR1_SHIFT] = BIT(3), + [RTD1195_MIS_ISR_I2C1_SHIFT] = BIT(4), + [RTD1195_MIS_ISR_UR1_TO_SHIFT] = BIT(5), + [RTD1195_MIS_ISR_RTC_MIN_SHIFT] = BIT(10), + [RTD1195_MIS_ISR_RTC_HOUR_SHIFT] = BIT(11), + [RTD1195_MIS_ISR_RTC_DATE_SHIFT] = BIT(12), + [RTD1195_MIS_ISR_I2C5_SHIFT] = BIT(14), + [RTD1195_MIS_ISR_I2C4_SHIFT] = BIT(15), + [RTD1195_MIS_ISR_GPIOA_SHIFT] = BIT(19), + [RTD1195_MIS_ISR_GPIODA_SHIFT] = BIT(20), + [RTD1195_MIS_ISR_LSADC_SHIFT] = BIT(21), + [RTD1195_MIS_ISR_I2C2_SHIFT] = BIT(26), + [RTD1195_MIS_ISR_GSPI_SHIFT] = BIT(27), + [RTD1195_MIS_ISR_I2C3_SHIFT] = BIT(28), + [RTD1195_MIS_ISR_WDOG_NMI_SHIFT] = SCPU_INT_EN_NMI_MASK, +}; + enum rtd1295_iso_isr_bits { RTD1295_ISO_ISR_UR0_SHIFT = 2, RTD1295_ISO_ISR_IRDA_SHIFT = 5, @@ -238,6 +314,14 @@ static const u32 rtd1295_misc_isr_to_scpu_int_en_mask[32] = { [RTD1295_MIS_ISR_WDOG_NMI_SHIFT] = SCPU_INT_EN_NMI_MASK, }; +static const struct rtd1195_irq_mux_info rtd1195_iso_irq_mux_info = { + .name = "iso", + .isr_offset = 0x0, + .umsk_isr_offset = 0x4, + .scpu_int_en_offset = 0x40, + .isr_to_int_en_mask = rtd1195_iso_isr_to_scpu_int_en_mask, +}; + static const struct rtd1195_irq_mux_info rtd1295_iso_irq_mux_info = { .name = "iso", .isr_offset = 0x0, @@ -246,6 +330,14 @@ static const struct rtd1195_irq_mux_info rtd1295_iso_irq_mux_info = { .isr_to_int_en_mask = rtd1295_iso_isr_to_scpu_int_en_mask, }; +static const struct rtd1195_irq_mux_info rtd1195_misc_irq_mux_info = { + .name = "misc", + .umsk_isr_offset = 0x8, + .isr_offset = 0xc, + .scpu_int_en_offset = 0x80, + .isr_to_int_en_mask = rtd1195_misc_isr_to_scpu_int_en_mask, +}; + static const struct rtd1195_irq_mux_info rtd1295_misc_irq_mux_info = { .name = "misc", .umsk_isr_offset = 0x8, @@ -255,10 +347,18 @@ static const struct rtd1195_irq_mux_info rtd1295_misc_irq_mux_info = { }; static const struct of_device_id rtd1295_irq_mux_dt_matches[] = { + { + .compatible = "realtek,rtd1195-iso-irq-mux", + .data = &rtd1195_iso_irq_mux_info, + }, { .compatible = "realtek,rtd1295-iso-irq-mux", .data = &rtd1295_iso_irq_mux_info, }, + { + .compatible = "realtek,rtd1195-misc-irq-mux", + .data = &rtd1195_misc_irq_mux_info, + }, { .compatible = "realtek,rtd1295-misc-irq-mux", .data = &rtd1295_misc_irq_mux_info, @@ -323,5 +423,7 @@ static int __init rtd1195_irq_mux_init(struct device_node *node, return 0; } +IRQCHIP_DECLARE(rtd1195_iso_mux, "realtek,rtd1195-iso-irq-mux", rtd1195_irq_mux_init); IRQCHIP_DECLARE(rtd1295_iso_mux, "realtek,rtd1295-iso-irq-mux", rtd1195_irq_mux_init); +IRQCHIP_DECLARE(rtd1195_misc_mux, "realtek,rtd1195-misc-irq-mux", rtd1195_irq_mux_init); IRQCHIP_DECLARE(rtd1295_misc_mux, "realtek,rtd1295-misc-irq-mux", rtd1195_irq_mux_init); From patchwork Thu Nov 21 05:02:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 179901 Delivered-To: patch@linaro.org Received: by 2002:a92:38d5:0:0:0:0:0 with SMTP id g82csp3086221ilf; Wed, 20 Nov 2019 21:02:49 -0800 (PST) X-Google-Smtp-Source: APXvYqxSK/jrc4ov9MGty2zY2LD/Gsgu8stnWW8AyRMLwZu/Tr8WMsIKqWAGKptk2p7hOKz0OF3j X-Received: by 2002:a17:906:d96c:: with SMTP id rp12mr11026977ejb.253.1574312569474; Wed, 20 Nov 2019 21:02:49 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1574312569; cv=none; d=google.com; s=arc-20160816; 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[209.132.180.67]) by mx.google.com with ESMTP id be24si1324467edb.156.2019.11.20.21.02.49; Wed, 20 Nov 2019 21:02:49 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726614AbfKUFCX (ORCPT + 26 others); Thu, 21 Nov 2019 00:02:23 -0500 Received: from mx2.suse.de ([195.135.220.15]:36450 "EHLO mx1.suse.de" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726343AbfKUFCW (ORCPT ); Thu, 21 Nov 2019 00:02:22 -0500 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (unknown [195.135.220.254]) by mx1.suse.de (Postfix) with ESMTP id 7B1F3B052; Thu, 21 Nov 2019 05:02:20 +0000 (UTC) From: =?utf-8?q?Andreas_F=C3=A4rber?= To: linux-realtek-soc@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, =?utf-8?q?Andreas_F=C3=A4rber?= , Rob Herring , Mark Rutland , devicetree@vger.kernel.org Subject: [PATCH v5 6/9] ARM: dts: rtd1195: Add irq muxes and UART interrupts Date: Thu, 21 Nov 2019 06:02:05 +0100 Message-Id: <20191121050208.11324-7-afaerber@suse.de> X-Mailer: git-send-email 2.16.4 In-Reply-To: <20191121050208.11324-1-afaerber@suse.de> References: <20191121050208.11324-1-afaerber@suse.de> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add iso and misc IRQ mux DT nodes for the Realtek RTD1195 SoC. Update the UART DT nodes with interrupts from those muxes, so that UART0 can be used without earlycon. Signed-off-by: Andreas Färber --- v4 -> v5: Unchanged v4: New arch/arm/boot/dts/rtd1195.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) -- 2.16.4 diff --git a/arch/arm/boot/dts/rtd1195.dtsi b/arch/arm/boot/dts/rtd1195.dtsi index db1171c5adfa..ee7761ae4ee0 100644 --- a/arch/arm/boot/dts/rtd1195.dtsi +++ b/arch/arm/boot/dts/rtd1195.dtsi @@ -118,6 +118,14 @@ #reset-cells = <1>; }; + iso_irq_mux: interrupt-controller@7000 { + compatible = "realtek,rtd1195-iso-irq-mux"; + reg = <0x7000 0x100>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + }; + iso_reset: reset-controller@7088 { compatible = "snps,dw-low-reset"; reg = <0x7088 0x4>; @@ -137,6 +145,8 @@ reg-io-width = <4>; resets = <&iso_reset RTD1195_ISO_RSTN_UR0>; clock-frequency = <27000000>; + interrupt-parent = <&iso_irq_mux>; + interrupts = <2>; status = "disabled"; }; @@ -145,6 +155,14 @@ reg = <0x1a200 0x8>; }; + misc_irq_mux: interrupt-controller@1b000 { + compatible = "realtek,rtd1195-misc-irq-mux"; + reg = <0x1b000 0x100>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + }; + uart1: serial@1b200 { compatible = "snps,dw-apb-uart"; reg = <0x1b200 0x100>; @@ -152,6 +170,8 @@ reg-io-width = <4>; resets = <&reset2 RTD1195_RSTN_UR1>; clock-frequency = <27000000>; + interrupt-parent = <&misc_irq_mux>; + interrupts = <3>; status = "disabled"; }; }; From patchwork Thu Nov 21 05:02:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 179897 Delivered-To: patch@linaro.org Received: by 2002:a92:38d5:0:0:0:0:0 with SMTP id g82csp3086044ilf; Wed, 20 Nov 2019 21:02:38 -0800 (PST) X-Google-Smtp-Source: APXvYqy2gWARJJUDgm9k96YoDdnQoWEOkSfxmhjSHfOwXluK0mlXshlloKRoXozX9hBoQLKQMNVz X-Received: by 2002:a5d:5273:: with SMTP id l19mr7011052wrc.175.1574312558670; Wed, 20 Nov 2019 21:02:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1574312558; cv=none; d=google.com; s=arc-20160816; b=E/q4HtWNDLtEzHUVarLhtd2ywPvMnAEwxPQIorjWn1MQUbVHtnZMgSa5tEbbwocD1r THG5ewdt8LhR+2Ji+Oz1n/96ae/rjGzpyOtkKfOs4dqdD93FGwqKN09dJDSaSEbswm29 RhhhZhF9+/P59VbgCgsnYysenTaiLqzShzGsiZt+SsqruPeUAQi27SE7fapL3CUzpbg6 fiMe8dUqq9MbNptfKYsxvX7SmJvg6wbY9t8TzluKpfvS3fd4bs/FrnM+wSIMwiadWyOX uL2QVaf+Kxs/WPCgQVVDQ9nFxqZHeM9xgwLp/4kiiIh73l5IeVD5RwJLJpBloSfh6dcG zOhA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=dXE7vG0O6MTsN6nKoUqqzhV+wsZQQWwdBiC0XXliD3I=; b=LiJTWo9HSRWOIPqgdPwo838bOjirnQAA172Ff2cnSz+4hEkFFcFJ6Marj3J5Skt4JG Epyln1E5cKCa58cIyIMx49fBczVxHLFhqCDpaJ0P+WgjcEdD3sZJe8H+FZIB2Zu5QLiP 51Ys0zMxjuIA8SEMZM48CtKAoX4lWYFtD/5yJgyY897D6rgy0DxPv6D/0ZkmZHD2X2ip 24OIdaipEriwrW/YPY0CwBzLTuxnHOpZOsPUsA7FnEhb7NC1c5qMhMRP65m4cAumgFVg tG0j54cZrJTQmxlW89IlA1/i2jDhymoD11BZ5n8YgjT5jFFd1LezbRZOMOi3XiA2jv1h vEhA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id h20si1499395edj.48.2019.11.20.21.02.38; Wed, 20 Nov 2019 21:02:38 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726762AbfKUFC0 (ORCPT + 26 others); Thu, 21 Nov 2019 00:02:26 -0500 Received: from mx2.suse.de ([195.135.220.15]:36468 "EHLO mx1.suse.de" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726454AbfKUFCW (ORCPT ); Thu, 21 Nov 2019 00:02:22 -0500 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (unknown [195.135.220.254]) by mx1.suse.de (Postfix) with ESMTP id E6FE5B14A; Thu, 21 Nov 2019 05:02:20 +0000 (UTC) From: =?utf-8?q?Andreas_F=C3=A4rber?= To: linux-realtek-soc@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, =?utf-8?q?Andreas_F=C3=A4rber?= , Thomas Gleixner , Jason Cooper , Marc Zyngier , Rob Herring , Mark Rutland , devicetree@vger.kernel.org Subject: [PATCH v5 7/9] dt-bindings: interrupt-controller: rtd1195-mux: Add RTD1395 Date: Thu, 21 Nov 2019 06:02:06 +0100 Message-Id: <20191121050208.11324-8-afaerber@suse.de> X-Mailer: git-send-email 2.16.4 In-Reply-To: <20191121050208.11324-1-afaerber@suse.de> References: <20191121050208.11324-1-afaerber@suse.de> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add compatible strings for Realtek RTD1395 SoC. Signed-off-by: Andreas Färber --- v4 -> v5: Unchanged v4: New .../devicetree/bindings/interrupt-controller/realtek,rtd1195-mux.yaml | 2 ++ 1 file changed, 2 insertions(+) -- 2.16.4 diff --git a/Documentation/devicetree/bindings/interrupt-controller/realtek,rtd1195-mux.yaml b/Documentation/devicetree/bindings/interrupt-controller/realtek,rtd1195-mux.yaml index 5cf3a28cedba..7c2a31548d46 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/realtek,rtd1195-mux.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/realtek,rtd1195-mux.yaml @@ -19,6 +19,8 @@ properties: - realtek,rtd1195-iso-irq-mux - realtek,rtd1295-misc-irq-mux - realtek,rtd1295-iso-irq-mux + - realtek,rtd1395-misc-irq-mux + - realtek,rtd1395-iso-irq-mux reg: maxItems: 1 From patchwork Thu Nov 21 05:02:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 179900 Delivered-To: patch@linaro.org Received: by 2002:a92:38d5:0:0:0:0:0 with SMTP id g82csp3086212ilf; Wed, 20 Nov 2019 21:02:49 -0800 (PST) X-Google-Smtp-Source: APXvYqzRv0C67bIiuLr2H0kSCE3xJyIzBLELtoBZsg2Nwp5557dbT+TpIxqP6PecrHzdCZnPB94n X-Received: by 2002:adf:f5cf:: with SMTP id k15mr3274098wrp.265.1574312569016; Wed, 20 Nov 2019 21:02:49 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1574312569; cv=none; d=google.com; s=arc-20160816; b=II9zsY/pRcbjqnez6WM2xd3lzlWOH9bt6+iXiGIFPmzLdivzQjc46jbONCqqMU7xbC mpTbEwJ8oENnfXlaDG8ckYqkr5co3mpUCFp5ajPORtOx9W+TkAUNeGZATYum//gHCos4 UC2gTGBxjCMhr2KZfZm/04gWNy7zYcdInZY93e5HdG3NCTbREY68PVRruk0G5nMFI02t AB+RrxzLZh2dNAUDNIk/X8k9muTxBJVWF0/E5P4fTlB/iD27/I6RaHZO+eKOKCVQSNEz ZSn8uGdMro28LdEbGSkVnSYnQVerZvm4SqkENX5OEe6UixCKVoy6ZHgGUSZtw71OsC76 k6rA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=NzjmkiZyGUYHWVA692PcCaVgof5no1lUVQvv6VnkckA=; b=i4BXIhQtnXX/+xKU9KPIoajfcfhpXrpgCJZzZE8p9ePaQcLAJHegLSbAhVVa32p2Ej WjuJLReCHsFG5Tbk6L99xViDNCJA1yLUBV3wMrfclu6cUJW+y6zcAlFKczdSlM/HOjmj C8RwOZMzS6mL7ajPKv4qusFgshuLswVKwUgqMcXilmN/5VZaCYcv8Hl90/0Mp6b+lluI bXUVSDtDMePstEjcLSqm+3AzcsdIlEwu5SzCqU/1RCH6gKbeWovXBEibawoO2ipoJuQW yQG0L0xBNiFdFtVRw0ZLUxUzShTuaVedcqW4PtLNR6d+wFNdYhVkw2Q94TwB0LyNxj+R 8+TA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id be24si1324467edb.156.2019.11.20.21.02.48; Wed, 20 Nov 2019 21:02:48 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726944AbfKUFCo (ORCPT + 26 others); Thu, 21 Nov 2019 00:02:44 -0500 Received: from mx2.suse.de ([195.135.220.15]:36480 "EHLO mx1.suse.de" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1725956AbfKUFCX (ORCPT ); Thu, 21 Nov 2019 00:02:23 -0500 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (unknown [195.135.220.254]) by mx1.suse.de (Postfix) with ESMTP id 5B27CB15E; Thu, 21 Nov 2019 05:02:21 +0000 (UTC) From: =?utf-8?q?Andreas_F=C3=A4rber?= To: linux-realtek-soc@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, =?utf-8?q?Andreas_F=C3=A4rber?= , Thomas Gleixner , Jason Cooper , Marc Zyngier Subject: [PATCH v5 8/9] irqchip: rtd1195-mux: Add RTD1395 definitions Date: Thu, 21 Nov 2019 06:02:07 +0100 Message-Id: <20191121050208.11324-9-afaerber@suse.de> X-Mailer: git-send-email 2.16.4 In-Reply-To: <20191121050208.11324-1-afaerber@suse.de> References: <20191121050208.11324-1-afaerber@suse.de> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add compatible strings and bit mappings for Realtek RTD1395 SoC. Based on BPI-M4-bsp linux-rtk/drivers/irqchip/irq-rtd139x.h. Signed-off-by: Andreas Färber --- @Realtek: Does RTD1395 still have the WDOG_NMI misc interrupt at bit 2? v4 -> v5: * Renamed misc bits from MISC_ to MIS_ for consistency * Filled in irq_chip names v4: New drivers/irqchip/irq-rtd1195-mux.c | 85 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 84 insertions(+), 1 deletion(-) -- 2.16.4 diff --git a/drivers/irqchip/irq-rtd1195-mux.c b/drivers/irqchip/irq-rtd1195-mux.c index e3e2e42d9df2..e0264759c0a8 100644 --- a/drivers/irqchip/irq-rtd1195-mux.c +++ b/drivers/irqchip/irq-rtd1195-mux.c @@ -1,7 +1,8 @@ // SPDX-License-Identifier: GPL-2.0-or-later /* - * Realtek RTD1195/RTD1295 IRQ mux + * Realtek RTD1195/RTD1295/RTD1395 IRQ mux * + * Copyright (C) 2017 Realtek Semiconductor Corporation * Copyright (c) 2017-2019 Andreas Färber */ @@ -314,6 +315,62 @@ static const u32 rtd1295_misc_isr_to_scpu_int_en_mask[32] = { [RTD1295_MIS_ISR_WDOG_NMI_SHIFT] = SCPU_INT_EN_NMI_MASK, }; +enum rtd1395_iso_isr_bits { + RTD1395_ISO_ISR_UR0_SHIFT = 2, + RTD1395_ISO_ISR_IRDA_SHIFT = 5, + RTD1395_ISO_ISR_I2C0_SHIFT = 8, + RTD1395_ISO_ISR_I2C1_SHIFT = 11, + RTD1395_ISO_ISR_RTC_HSEC_SHIFT = 12, + RTD1395_ISO_ISR_RTC_ALARM_SHIFT = 13, + RTD1395_ISO_ISR_LSADC0_SHIFT = 16, + RTD1395_ISO_ISR_LSADC1_SHIFT = 17, + RTD1395_ISO_ISR_GPIOA_SHIFT = 19, + RTD1395_ISO_ISR_GPIODA_SHIFT = 20, + RTD1395_ISO_ISR_GPHY_HV_SHIFT = 28, + RTD1395_ISO_ISR_GPHY_DV_SHIFT = 29, + RTD1395_ISO_ISR_GPHY_AV_SHIFT = 30, + RTD1395_ISO_ISR_I2C1_REQ_SHIFT = 31, +}; + +static const u32 rtd1395_iso_isr_to_scpu_int_en_mask[32] = { + [RTD1395_ISO_ISR_UR0_SHIFT] = BIT(2), + [RTD1395_ISO_ISR_IRDA_SHIFT] = BIT(5), + [RTD1395_ISO_ISR_I2C0_SHIFT] = BIT(8), + [RTD1395_ISO_ISR_I2C1_SHIFT] = BIT(11), + [RTD1395_ISO_ISR_RTC_HSEC_SHIFT] = BIT(12), + [RTD1395_ISO_ISR_RTC_ALARM_SHIFT] = BIT(13), + [RTD1395_ISO_ISR_LSADC0_SHIFT] = BIT(16), + [RTD1395_ISO_ISR_LSADC1_SHIFT] = BIT(17), + [RTD1395_ISO_ISR_GPIOA_SHIFT] = BIT(19), + [RTD1395_ISO_ISR_GPIODA_SHIFT] = BIT(20), + [RTD1395_ISO_ISR_GPHY_HV_SHIFT] = BIT(28), + [RTD1395_ISO_ISR_GPHY_DV_SHIFT] = BIT(29), + [RTD1395_ISO_ISR_GPHY_AV_SHIFT] = BIT(30), + [RTD1395_ISO_ISR_I2C1_REQ_SHIFT] = BIT(31), +}; + +enum rtd1395_misc_isr_bits { + RTD1395_MIS_ISR_UR1_SHIFT = 3, + RTD1395_MIS_ISR_UR1_TO_SHIFT = 5, + RTD1395_MIS_ISR_UR2_SHIFT = 8, + RTD1395_MIS_ISR_UR2_TO_SHIFT = 13, + RTD1395_MIS_ISR_I2C5_SHIFT = 14, + RTD1395_MIS_ISR_SC0_SHIFT = 24, + RTD1395_MIS_ISR_SPI_SHIFT = 27, + RTD1395_MIS_ISR_FAN_SHIFT = 29, +}; + +static const u32 rtd1395_misc_isr_to_scpu_int_en_mask[32] = { + [RTD1395_MIS_ISR_UR1_SHIFT] = BIT(3), + [RTD1395_MIS_ISR_UR1_TO_SHIFT] = BIT(5), + [RTD1395_MIS_ISR_UR2_TO_SHIFT] = BIT(6), + [RTD1395_MIS_ISR_UR2_SHIFT] = BIT(7), + [RTD1395_MIS_ISR_I2C5_SHIFT] = BIT(14), + [RTD1395_MIS_ISR_SC0_SHIFT] = BIT(24), + [RTD1395_MIS_ISR_SPI_SHIFT] = BIT(27), + [RTD1395_MIS_ISR_FAN_SHIFT] = BIT(29), +}; + static const struct rtd1195_irq_mux_info rtd1195_iso_irq_mux_info = { .name = "iso", .isr_offset = 0x0, @@ -330,6 +387,14 @@ static const struct rtd1195_irq_mux_info rtd1295_iso_irq_mux_info = { .isr_to_int_en_mask = rtd1295_iso_isr_to_scpu_int_en_mask, }; +static const struct rtd1195_irq_mux_info rtd1395_iso_irq_mux_info = { + .name = "iso", + .isr_offset = 0x0, + .umsk_isr_offset = 0x4, + .scpu_int_en_offset = 0x40, + .isr_to_int_en_mask = rtd1395_iso_isr_to_scpu_int_en_mask, +}; + static const struct rtd1195_irq_mux_info rtd1195_misc_irq_mux_info = { .name = "misc", .umsk_isr_offset = 0x8, @@ -346,6 +411,14 @@ static const struct rtd1195_irq_mux_info rtd1295_misc_irq_mux_info = { .isr_to_int_en_mask = rtd1295_misc_isr_to_scpu_int_en_mask, }; +static const struct rtd1195_irq_mux_info rtd1395_misc_irq_mux_info = { + .name = "misc", + .umsk_isr_offset = 0x8, + .isr_offset = 0xc, + .scpu_int_en_offset = 0x80, + .isr_to_int_en_mask = rtd1395_misc_isr_to_scpu_int_en_mask, +}; + static const struct of_device_id rtd1295_irq_mux_dt_matches[] = { { .compatible = "realtek,rtd1195-iso-irq-mux", @@ -355,6 +428,10 @@ static const struct of_device_id rtd1295_irq_mux_dt_matches[] = { .compatible = "realtek,rtd1295-iso-irq-mux", .data = &rtd1295_iso_irq_mux_info, }, + { + .compatible = "realtek,rtd1395-iso-irq-mux", + .data = &rtd1395_iso_irq_mux_info, + }, { .compatible = "realtek,rtd1195-misc-irq-mux", .data = &rtd1195_misc_irq_mux_info, @@ -363,6 +440,10 @@ static const struct of_device_id rtd1295_irq_mux_dt_matches[] = { .compatible = "realtek,rtd1295-misc-irq-mux", .data = &rtd1295_misc_irq_mux_info, }, + { + .compatible = "realtek,rtd1395-misc-irq-mux", + .data = &rtd1395_misc_irq_mux_info, + }, { } }; @@ -425,5 +506,7 @@ static int __init rtd1195_irq_mux_init(struct device_node *node, } IRQCHIP_DECLARE(rtd1195_iso_mux, "realtek,rtd1195-iso-irq-mux", rtd1195_irq_mux_init); IRQCHIP_DECLARE(rtd1295_iso_mux, "realtek,rtd1295-iso-irq-mux", rtd1195_irq_mux_init); +IRQCHIP_DECLARE(rtd1395_iso_mux, "realtek,rtd1395-iso-irq-mux", rtd1195_irq_mux_init); IRQCHIP_DECLARE(rtd1195_misc_mux, "realtek,rtd1195-misc-irq-mux", rtd1195_irq_mux_init); IRQCHIP_DECLARE(rtd1295_misc_mux, "realtek,rtd1295-misc-irq-mux", rtd1195_irq_mux_init); +IRQCHIP_DECLARE(rtd1395_misc_mux, "realtek,rtd1395-misc-irq-mux", rtd1195_irq_mux_init);