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[185.246.87.17]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-378e780e029sm18111177f8f.116.2024.09.20.10.33.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Sep 2024 10:33:25 -0700 (PDT) From: Guillaume Stols Date: Fri, 20 Sep 2024 17:33:21 +0000 Subject: [PATCH v2 01/10] dt-bindings: iio: adc: ad7606: Set the correct polarity Precedence: bulk X-Mailing-List: linux-fbdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240920-ad7606_add_iio_backend_support-v2-1-0e78782ae7d0@baylibre.com> References: <20240920-ad7606_add_iio_backend_support-v2-0-0e78782ae7d0@baylibre.com> In-Reply-To: <20240920-ad7606_add_iio_backend_support-v2-0-0e78782ae7d0@baylibre.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Greg Kroah-Hartman , "Rafael J. Wysocki" , Jonathan Corbet , Michal Marek Cc: linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org, Michael Hennerich , linux-fbdev@vger.kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, aardelean@baylibre.com, dlechner@baylibre.com, Guillaume Stols , jstephan@baylibre.com X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1726853604; l=1589; i=gstols@baylibre.com; s=20240417; h=from:subject:message-id; bh=uENmI3rs41AFbgjmBszj8S7B3YSrnm8W4+Uer1rxq3M=; b=ug+14LFXj6CWSaVkJuf+L5f8lS/xq25/LJaZBpFEqNbdM4jOGg5GZaKDYL/bnhPFGtSTJGmaH bMa9L6gp56sBruZTu8Ridfm0IlZo/ORFm/MwwuUtmb4ueBxBuiCwzYN X-Developer-Key: i=gstols@baylibre.com; a=ed25519; pk=XvMm5WHuV67sGYOJZqIYzXndbaJOlNd8Q6li6vnb4Cs= According to the datasheet, "Data is clocked in from SDI on the falling edge of SCLK, while data is clocked out on DOUTA on the rising edge of SCLK". Also, even if not stated textually in the datasheet, it is made clear on the diagrams that sclk idles at high. So the documentation is erroneously stating that spi-cpha is required, and the example is erroneously setting both spi-cpol and spi-cpha. Fixes: 416f882c3b40 ("dt-bindings: iio: adc: Migrate AD7606 documentation to yaml") Fixes: 6e33a125df66 ("dt-bindings: iio: adc: Add docs for AD7606 ADC") Signed-off-by: Guillaume Stols --- Documentation/devicetree/bindings/iio/adc/adi,ad7606.yaml | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7606.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad7606.yaml index 69408cae3db9..75334a033539 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7606.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7606.yaml @@ -29,8 +29,6 @@ properties: reg: maxItems: 1 - spi-cpha: true - spi-cpol: true avcc-supply: true @@ -117,7 +115,7 @@ properties: required: - compatible - reg - - spi-cpha + - spi-cpol - avcc-supply - vdrive-supply - interrupts @@ -185,7 +183,6 @@ examples: reg = <0>; spi-max-frequency = <1000000>; spi-cpol; - spi-cpha; avcc-supply = <&adc_vref>; vdrive-supply = <&vdd_supply>; From patchwork Fri Sep 20 17:33:22 2024 Content-Type: text/plain; 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[185.246.87.17]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-378e780e029sm18111177f8f.116.2024.09.20.10.33.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Sep 2024 10:33:26 -0700 (PDT) From: Guillaume Stols Date: Fri, 20 Sep 2024 17:33:22 +0000 Subject: [PATCH v2 02/10] dt-bindings: iio: adc: ad7606: Make corrections on spi conditions Precedence: bulk X-Mailing-List: linux-fbdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240920-ad7606_add_iio_backend_support-v2-2-0e78782ae7d0@baylibre.com> References: <20240920-ad7606_add_iio_backend_support-v2-0-0e78782ae7d0@baylibre.com> In-Reply-To: <20240920-ad7606_add_iio_backend_support-v2-0-0e78782ae7d0@baylibre.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Greg Kroah-Hartman , "Rafael J. Wysocki" , Jonathan Corbet , Michal Marek Cc: linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org, Michael Hennerich , linux-fbdev@vger.kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, aardelean@baylibre.com, dlechner@baylibre.com, Guillaume Stols , jstephan@baylibre.com X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1726853604; l=1644; i=gstols@baylibre.com; s=20240417; h=from:subject:message-id; bh=Gpgaed0fCeEh53ecEHuIgZfypb2UgiAkN/j7SoFe7Ho=; b=TEO0GprJjLt+G0XFAyfPx9EJ3qWaJ5oHGsul+rDAxLSlHhq8TWpvRCQGyTEd4h7/dIVPUpAw8 Zk/P+IcUfGLCFSykIPx8R75jfakMwCOfO9gUA8dXFwV8DMP03H/XJLt X-Developer-Key: i=gstols@baylibre.com; a=ed25519; pk=XvMm5WHuV67sGYOJZqIYzXndbaJOlNd8Q6li6vnb4Cs= The SPI conditions are not always required, because there is also a parallel interface. The way used to detect that the SPI interface is used is to check if the reg value is between 0 and 256. There is also a correction on the spi-cpha that is not required when SPI interface is selected, while spi-cpol is. Signed-off-by: Guillaume Stols --- .../devicetree/bindings/iio/adc/adi,ad7606.yaml | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7606.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad7606.yaml index 75334a033539..12995ebcddc2 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7606.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7606.yaml @@ -112,18 +112,32 @@ properties: assumed that the pins are hardwired to VDD. type: boolean + parallel-interface: + description: + If the parallel interface is used, be it directly or through a backend, + this property must be defined. + type: boolean + required: - compatible - reg - - spi-cpol - avcc-supply - vdrive-supply - interrupts - adi,conversion-start-gpios -allOf: - - $ref: /schemas/spi/spi-peripheral-props.yaml# +oneOf: + - required: + - parallel-interface + - allOf: + - properties: + parallel-interface: false + spi-cpol: true + - $ref: /schemas/spi/spi-peripheral-props.yaml# + - required: + - spi-cpol +allOf: - if: properties: compatible: From patchwork Fri Sep 20 17:33:23 2024 Content-Type: text/plain; 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[185.246.87.17]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-378e780e029sm18111177f8f.116.2024.09.20.10.33.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Sep 2024 10:33:28 -0700 (PDT) From: Guillaume Stols Date: Fri, 20 Sep 2024 17:33:23 +0000 Subject: [PATCH v2 03/10] dt-bindings: iio: adc: ad7606: Add iio backend bindings Precedence: bulk X-Mailing-List: linux-fbdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240920-ad7606_add_iio_backend_support-v2-3-0e78782ae7d0@baylibre.com> References: <20240920-ad7606_add_iio_backend_support-v2-0-0e78782ae7d0@baylibre.com> In-Reply-To: <20240920-ad7606_add_iio_backend_support-v2-0-0e78782ae7d0@baylibre.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Greg Kroah-Hartman , "Rafael J. Wysocki" , Jonathan Corbet , Michal Marek Cc: linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org, Michael Hennerich , linux-fbdev@vger.kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, aardelean@baylibre.com, dlechner@baylibre.com, Guillaume Stols , jstephan@baylibre.com X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1726853604; l=3763; i=gstols@baylibre.com; s=20240417; h=from:subject:message-id; bh=hCvBf/Yi5is31u2E+lcg/efeEZpWLiB9YIEAE1XR084=; b=agNRyK65OgqM6pe57O+QNJm7EyEBxOjsJAmCn1CfbjhAt22bewNPyXm80YHbvFl3vHOwMRyPE AjVKmBGuplHASaJXpQR8nny+XZiJ7rgvsgcwicb4FSXoKfc1IPRFvXl X-Developer-Key: i=gstols@baylibre.com; a=ed25519; pk=XvMm5WHuV67sGYOJZqIYzXndbaJOlNd8Q6li6vnb4Cs= Add the required properties for iio-backend support, as well as an example and the conditions to mutually exclude interruption and conversion trigger with iio-backend. The iio-backend's function is to controls the communication, and thus the interruption pin won't be available anymore. As a consequence, the conversion pin must be controlled externally since we will miss information about when every single conversion cycle (i.e conversion + data transfer) ends, hence a PWM is introduced to trigger the conversions. Signed-off-by: Guillaume Stols --- .../devicetree/bindings/iio/adc/adi,ad7606.yaml | 76 +++++++++++++++++++++- 1 file changed, 74 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7606.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad7606.yaml index 12995ebcddc2..74a8680904b1 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7606.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7606.yaml @@ -118,13 +118,32 @@ properties: this property must be defined. type: boolean + pwms: + description: + In case the conversion is triggered by a PWM instead of a GPIO plugged to + the CONVST pin, the PWM must be referenced. + minItems: 1 + maxItems: 2 + + pwm-names: + description: + The name of each PWM, the first is connected to CONVST, and the second is + connected to CONVST2 if CONVST2 is available and not connected to CONVST1. + minItems: 1 + maxItems: 2 + + io-backends: + description: + A reference to the iio-backend, which is responsible handling the BUSY + pin's falling edge and communication. + An example of backend can be found at + http://analogdevicesinc.github.io/hdl/library/axi_ad7606x/index.html + required: - compatible - reg - avcc-supply - vdrive-supply - - interrupts - - adi,conversion-start-gpios oneOf: - required: @@ -138,6 +157,34 @@ oneOf: - spi-cpol allOf: + - if: + properties: + pwms: false + then: + required: + - adi,conversion-start-gpios + + - if: + properties: + adi,conversion-start-gpios: false + then: + required: + - pwms + + - if: + properties: + interrupts: false + then: + required: + - io-backends + + - if: + properties: + io-backends: false + then: + required: + - interrupts + - if: properties: compatible: @@ -179,12 +226,37 @@ allOf: adi,sw-mode: false else: properties: + pwms: + maxItems: 1 + pwm-names: + maxItems: 1 adi,conversion-start-gpios: maxItems: 1 unevaluatedProperties: false examples: + - | + #include + / { + adi_adc { + compatible = "adi,ad7606b"; + parallel-interface; + pwms = <&axi_pwm_gen 0 0>; + + avcc-supply = <&adc_vref>; + vdrive-supply = <&vdd_supply>; + + reset-gpios = <&gpio0 91 GPIO_ACTIVE_HIGH>; + standby-gpios = <&gpio0 90 GPIO_ACTIVE_LOW>; + adi,range-gpios = <&gpio0 89 GPIO_ACTIVE_HIGH>; + adi,oversampling-ratio-gpios = <&gpio0 88 GPIO_ACTIVE_HIGH + &gpio0 87 GPIO_ACTIVE_HIGH + &gpio0 86 GPIO_ACTIVE_HIGH>; + io-backends = <&iio_backend>; + }; + }; + - | #include #include From patchwork Fri Sep 20 17:33:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guillaume Stols X-Patchwork-Id: 830156 Received: from mail-wm1-f41.google.com (mail-wm1-f41.google.com [209.85.128.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AB934183CDB for ; Fri, 20 Sep 2024 17:33:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.41 ARC-Seal: i=1; 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[185.246.87.17]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-378e780e029sm18111177f8f.116.2024.09.20.10.33.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Sep 2024 10:33:29 -0700 (PDT) From: Guillaume Stols Date: Fri, 20 Sep 2024 17:33:24 +0000 Subject: [PATCH v2 04/10] Documentation: iio: Document ad7606 driver Precedence: bulk X-Mailing-List: linux-fbdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240920-ad7606_add_iio_backend_support-v2-4-0e78782ae7d0@baylibre.com> References: <20240920-ad7606_add_iio_backend_support-v2-0-0e78782ae7d0@baylibre.com> In-Reply-To: <20240920-ad7606_add_iio_backend_support-v2-0-0e78782ae7d0@baylibre.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Greg Kroah-Hartman , "Rafael J. Wysocki" , Jonathan Corbet , Michal Marek Cc: linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org, Michael Hennerich , linux-fbdev@vger.kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, aardelean@baylibre.com, dlechner@baylibre.com, Guillaume Stols , jstephan@baylibre.com X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1726853604; l=5870; i=gstols@baylibre.com; s=20240417; h=from:subject:message-id; bh=MNConsB8RtKRmfEYoKydnt/84vrlE2Mq9EcIOlWCuLs=; b=18ypvfqV/x/g59tvFVsyzS25i/Plu+/9XYnRWPEjWNK3YmvBta7f/I6ig/AZNpQtPxFjmT6r/ GP+HYtSyy1BDFpI5zmHpEXudGR7jFAbUi/lUdxE7qYeNOuAa7APV2dP X-Developer-Key: i=gstols@baylibre.com; a=ed25519; pk=XvMm5WHuV67sGYOJZqIYzXndbaJOlNd8Q6li6vnb4Cs= The Analog Devices Inc. AD7606 (and similar chips) are complex ADCs that will benefit from a detailed driver documentation. This documents the current features supported by the driver. Signed-off-by: Guillaume Stols --- Documentation/iio/ad7606.rst | 143 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 143 insertions(+) diff --git a/Documentation/iio/ad7606.rst b/Documentation/iio/ad7606.rst new file mode 100644 index 000000000000..270a49aae685 --- /dev/null +++ b/Documentation/iio/ad7606.rst @@ -0,0 +1,143 @@ +.. SPDX-License-Identifier: GPL-2.0-only + +============= +AD7606 driver +============= + +ADC driver for Analog Devices Inc. AD7606 and similar devices. The module name +is ``ad7606``. + +Supported devices +================= + +The following chips are supported by this driver: + +* `AD7605 `_ +* `AD7606 `_ +* `AD7606B `_ +* `AD7616 `_ + +Supported features +================== + +SPI wiring modes +---------------- + +ad7606x ADCs can output data on several SDO lines (1/2/4/8). The driver +currently supports only 1 SDO line. + +Parallel wiring mode +-------------------- + +AD7606x ADC have also a parallel interface, with 16 lines (that can be reduced +to 8 in byte mode). The parallel interface is selected by declaring the device +as platform in the device tree (with no io-backends node defined, see below). + +IIO-backend mode +---------------- + +This mode allows to reach the best sample rates, but it requires an external +hardware (eg HDL or APU) to handle the low level communication. +The backend mode is enabled when through the definition of the "io-backends" +property in the device tree. + +The reference configuration for the current implementation of IIO-backend mode +is the HDL reference provided by ADI: +https://wiki.analog.com/resources/eval/user-guides/ad7606x-fmc/hdl + +This implementation embeds an IIO-backend compatible IP (adi-axi-adc) and a PWM +connected to the conversion trigger pin. + ++---+ +---------------------------- +| | +-------+ |AD76xx +| A | controls | | | +| D |-------------->| PWM |-------------->| cnvst +| 7 | | | | +| 6 | +-------+ | +| 0 | controls +-----------+-----------+ | +| 6 |---------->| | |<--| frstdata +| | | Backend | Backend |<--| busy +| D | | Driver | | | +| R | | | |-->| clk +| I | requests |+---------+| DMA | | +| V |----------->| Buffer ||<---- |<=>| DATA +| E | |+---------+| | | +| R | +-----------+-----------+ | +| |-------------------------------------->| reset/configuration gpios ++---+ +----------------------------- + + +Software and hardware modes +--------------------------- + +While all the AD7606 series parts can be configured using GPIOs, some of them +can be configured using register. + +The chips that support software mode have more values available for configuring +the device, as well as more settings, and allow to control the range and +calibration per channel. + +The following settings are available per channel in software mode: + - Scale + +Also, there is a broader choice of oversampling ratios in software mode. + +Conversion triggering +--------------------- + +The conversion can be triggered by two distinct ways: + + - A GPIO is connected to the conversion trigger pin, and this GPIO is controlled + by the driver directly. In this configuration, the driver sets back the + conversion trigger pin to high as soon as it has read all the conversions. + + - An external source is connected to the conversion trigger pin. In the + current implementation, it must be a PWM. In this configuration, the driver + does not control directly the conversion trigger pin. Instead, it can + control the PWM's frequency. This trigger is enabled only for iio-backend. + +Reference voltage +----------------- + +2 possible reference voltage sources are supported: + + - Internal reference (2.5V) + - External reference (2.5V) + +The source is determined by the device tree. If ``refin-supply`` is present, +then the external reference is used, otherwise the internal reference is used. + +Oversampling +------------ + +This family supports oversampling to improve SNR. +In software mode, the following ratios are available: +1 (oversampling disabled)/2/4/8/16/32/64/128/256. + +Unimplemented features +---------------------- + +- 2/4/8 SDO lines +- CRC indication +- Calibration + +Device buffers +============== + +IIO triggered buffer +-------------------- + +This driver supports IIO triggered buffers, with a "built in" trigger, i.e the +trigger is allocated and linked by the driver, and a new conversion is triggered +as soon as the samples are transferred, and a timestamp channel is added to make +up for the potential jitter induced by the delays in the interrupt handling. + +IIO backend buffer +------------------ + +When IIO backend is used, the trigger is not needed, and the sample rate is +considered as stable, hence there is no timestamp channel. The communication is +delegated to an external logic, called a backend, and the backend's driver +handles the buffer. When this mode is enabled, the driver cannot control the +conversion pin, because the busy pin is bound to the backend. + From patchwork Fri Sep 20 17:33:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guillaume Stols X-Patchwork-Id: 829894 Received: from mail-wr1-f54.google.com (mail-wr1-f54.google.com [209.85.221.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 67FE7184544 for ; Fri, 20 Sep 2024 17:33:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726853614; cv=none; b=kfLWYZhde/V79sGDfHoB1Y3qwUX75vW3LbrImtBi+zPUH2penHHchzROAhTqXqCfn44/zfBx1BU+tOZq2tjy8uHZ1vOUba/tOZUgLAm1PLoJEKekiK5tCmb3+qLSDp7I/TkWNGRqvI/Ur5h/qLJysT+mMHF7qUJCri4CrxLMRGI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726853614; c=relaxed/simple; bh=MT8c2AhQeYsYs8cmaeLRhGYDwFnuTuG5PMmK88lsU/w=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=NsjvXQWSMquAXEiJ3+WKPSySJOjFmF2AFpkVgxyLORs5jTbHElrzaoSwRbLFe1c/PBIRvD3J2Cxk0vRFP5LnH2biXHyUDaBI5mjSG8ZXptFhH+kMGRu1UOdh5+NItCWLLeriAJYQGjcLuCxz4gmxGz7XdwJ4WGUSZ/H4o2rxYi4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=aQkYC+x3; arc=none smtp.client-ip=209.85.221.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="aQkYC+x3" Received: by mail-wr1-f54.google.com with SMTP id ffacd0b85a97d-378f600e090so1372714f8f.3 for ; Fri, 20 Sep 2024 10:33:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1726853611; x=1727458411; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=IvmqOfkNyg3mbwnmFu/TPFnKJdY4EPfohFTJPCL4F8Y=; b=aQkYC+x3nmYkQiwfkLLlrAY9myG48sneyTRn7dc8Vlb+2yhglq7xGY+jPiyVvA9AG2 Bxwvhe/gt5rnLT6F5fELA+/KKT7yM3ZBnVK2xr+bzXrSpd6Ry6SqVEwEAeSIAW38LMNv LkDENwkjdNTrmsMahz1Y6CF6i1bqnBwSUiWecje5190/JTP+LrzXKX52DmSb0yGNn8MR Y+YnbmjxW9EhaH/jYyUPAQ2Dp93f7zMsOG8F1NmVwFYt7yu2kuCr260XTd6lXa76XXUD T90eNh23Xs58zGtIWJO5E+cdBPVFW1sHPGhDbDg0vC2ql0BibVWoBvLoX8tl7QRg40tC MYMA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726853611; x=1727458411; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IvmqOfkNyg3mbwnmFu/TPFnKJdY4EPfohFTJPCL4F8Y=; b=q4CM4Pn8jDIqkirAfys7FZF9Uz4aqKKVrWPyvI87RYi2diEKKZsMdKlBditjHzbLkC /BbwXTPID2gWRjdInJcJIcvbMGCsJVfO+ytK59M6JddpwSCESVtId7VRZf4td3YjlYJ6 wgF5yKOcyeW+oSBeUdVIVW30QJsXRqMPuqbV8COunq0rIi8i3ikPB6IikbVeyPc3m8A5 fHI4yomrO1c6HwG8i94QhM2mMskP92sOdXL2HXRkxpa6qdWi0O1rDiKN0EDabCcYI2D2 mOf7U7B8aO0OF5obU8tdy4kxbNytTbEXOHglsWB0oSZgAnhh/qOoV7t+siifOxZQRxe/ zGhw== X-Forwarded-Encrypted: i=1; AJvYcCUsZsvIGNzm4xSqkofGarSSQfFLNsMr/JH5V6ehSXnaO4eZZOgSK1yxQ9i436cp3cqSTNQt7Rern4bWIw==@vger.kernel.org X-Gm-Message-State: AOJu0Yx09gURIpWYefWwBBB5b6dZw7IiUmJLYZ9JvltuuiQKzrlVlCb6 h5muzuKbsuvo7eU1uWCgO90eVFx1yOmnNLjV5P7U/ksR1F+NFSl06miaUl+7+UyNGGG/sQR/mfl V X-Google-Smtp-Source: AGHT+IGelVRMsQTQSU+xPNgg15Ho2GXpbX1Ln0t5hXane5n5dnYSSMSr6M1qKp+vzCMN00YqqNJH7A== X-Received: by 2002:a5d:64c1:0:b0:374:c3e4:d6c5 with SMTP id ffacd0b85a97d-37a431a7142mr2209005f8f.57.1726853610516; Fri, 20 Sep 2024 10:33:30 -0700 (PDT) Received: from [127.0.1.1] (frhb82016ds.ikexpress.com. [185.246.87.17]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-378e780e029sm18111177f8f.116.2024.09.20.10.33.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Sep 2024 10:33:29 -0700 (PDT) From: Guillaume Stols Date: Fri, 20 Sep 2024 17:33:25 +0000 Subject: [PATCH v2 05/10] iio: adc: ad7606: Sort includes in alphabetical order Precedence: bulk X-Mailing-List: linux-fbdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240920-ad7606_add_iio_backend_support-v2-5-0e78782ae7d0@baylibre.com> References: <20240920-ad7606_add_iio_backend_support-v2-0-0e78782ae7d0@baylibre.com> In-Reply-To: <20240920-ad7606_add_iio_backend_support-v2-0-0e78782ae7d0@baylibre.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Greg Kroah-Hartman , "Rafael J. Wysocki" , Jonathan Corbet , Michal Marek Cc: linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org, Michael Hennerich , linux-fbdev@vger.kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, aardelean@baylibre.com, dlechner@baylibre.com, Guillaume Stols , jstephan@baylibre.com X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1726853604; l=1335; i=gstols@baylibre.com; s=20240417; h=from:subject:message-id; bh=MT8c2AhQeYsYs8cmaeLRhGYDwFnuTuG5PMmK88lsU/w=; b=RzKFmBn040UGa7yTM6JsY9KvnbH6tbRt6zQy0B5hwTYpOEClvNSZL5i5J1VqCH8LtQie0TnTj KJNP6vwN65QAQSfYhmEy1TLwWy0uoRdjGXz0EvvNOQOcvsKe8ZRPfaM X-Developer-Key: i=gstols@baylibre.com; a=ed25519; pk=XvMm5WHuV67sGYOJZqIYzXndbaJOlNd8Q6li6vnb4Cs= Some of the includes were not in alphabetical order, this commit fixes it. Signed-off-by: Guillaume Stols --- drivers/iio/adc/ad7606_par.c | 6 +++--- drivers/iio/adc/ad7606_spi.c | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/iio/adc/ad7606_par.c b/drivers/iio/adc/ad7606_par.c index 02d8c309304e..d651639c45eb 100644 --- a/drivers/iio/adc/ad7606_par.c +++ b/drivers/iio/adc/ad7606_par.c @@ -5,13 +5,13 @@ * Copyright 2011 Analog Devices Inc. */ +#include +#include +#include #include #include -#include #include #include -#include -#include #include #include "ad7606.h" diff --git a/drivers/iio/adc/ad7606_spi.c b/drivers/iio/adc/ad7606_spi.c index 62ec12195307..d3fbc7c7a823 100644 --- a/drivers/iio/adc/ad7606_spi.c +++ b/drivers/iio/adc/ad7606_spi.c @@ -5,10 +5,10 @@ * Copyright 2011 Analog Devices Inc. */ +#include #include #include #include -#include #include #include "ad7606.h" From patchwork Fri Sep 20 17:33:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guillaume Stols X-Patchwork-Id: 829893 Received: from mail-wr1-f41.google.com (mail-wr1-f41.google.com [209.85.221.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 66D0A185931 for ; Fri, 20 Sep 2024 17:33:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726853617; cv=none; b=VCAa39y4ZHUle+odngemfeXDr2hjX/mI/k/yhqRJG6IDHxAUe2JEd15g7IpfXa2qNhzpa4jr+Asiy0UC1qJiu5Eo5nUkjYHdyp2NoiRnnSTsArL+qSEKgpg5j6bzB3nd4vt3iT0c9FneHNNK4oZapG+W4kzTSXtDJr5rARobZe0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726853617; c=relaxed/simple; bh=rGbKHqnx/NA9Sx5Ie+fz9ZIrDMgsKImoOwwJ/a9nWEA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=T4MzsFFA/A0nhGpUhnFYf02BBCmU6BfluJSonFCO078L7CabQouG/aLo6MzzHezv5Rimo97jb37eSkQhDELB4HFnUaLaLuaRmq4Nwzk/q6Fr/OZ1SqO33o3NX8cyV0YxST7QBzDQpDLZIYMDOZiURxCwuAxt6b0ZlO+QF69obys= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=lcZ5ZSx3; arc=none smtp.client-ip=209.85.221.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="lcZ5ZSx3" Received: by mail-wr1-f41.google.com with SMTP id ffacd0b85a97d-374ba74e9b6so1738711f8f.0 for ; Fri, 20 Sep 2024 10:33:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1726853612; x=1727458412; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=q92/JWErx+OZicU+GXTVjk0ikMmmaNiLFbmb1mbQCF8=; b=lcZ5ZSx3X+NOYytTj1CsSi6NYOjIYpjwDxz8T7GmhLpmt9LF4HxEEBp2RTNsBV+SeQ wV6LAwgm43QbLlALPQtTLlNGEVv0LAhqAUwF8I9W5pWYlQkIy2OXnZMdQ8wuZjq+3UAI ZGvUXKuvF+qStbXRdaMG+sbUQh4lbqKBxHQnNXA8ajuZk9GdL+hsO1nmEhGFA37mcLDi oTvZgHg3EVg+HXrU1FADN0Fqplxrai2QWeL8vUkqZuJ3j/4DLZl4YDlfW1XDGrVbiOPo zy0CrEP/HLPCeXN8yHlXiXku3cvfq6CfPbMvLW7NIOES0XmBw6HWfh3YfwSSUPN+SRb2 oehw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726853612; x=1727458412; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=q92/JWErx+OZicU+GXTVjk0ikMmmaNiLFbmb1mbQCF8=; b=gtQvGWFT5rbyE10i3tgsBZssqzYn6UvrSEA4tFNUN6Qja6dFtgpMzSLSgxvSTQzkpi GU0I0V1SLueDQDJRj76xoPvbevDbGD55VXefQG48Yy+m3HGtcX4jjzT8ao534VUow5vK p1p0VtZX7iiCs45P2zWF5e7G+YbSiDxqtUY0KKDULQPbZE5OEdapA7QY8LHCIx3LQaV3 4Xwx/geQUq2r01ykzwfNqKccuDMNHRKO1oQvlUOdQ+FNTb06z2w8LCM17HDHayiETKON BcPAFk2lrwbvq+kTqlCtfaBOXmufgR0rE0qxq55eqHqQwIsTzB6XZ9hCXq79VgNb/5GW bFLA== X-Forwarded-Encrypted: i=1; AJvYcCWjGWoKjVPWU0ceMylDFzDZYyE7VGX2RXCs8L21uBEOjSQoVAcW/87reDjYTAuwXdpGDlrC6/+TaXF4mQ==@vger.kernel.org X-Gm-Message-State: AOJu0YwpwG+bK3zhkIXowQuYL25MJ/lBWdeJOEIFPCp2MY7zSDrQC1fX SP+xe6RFUbjfUvRmoShQD82HrbS4Dnpqy+C/VKWgcO43TqjosCgBsG5sXhSxMmM2c4u+gjuH7nS 4 X-Google-Smtp-Source: AGHT+IHiFZeHsSAWFx9ZmboLVADpTy9yI48Qwebf1x7tovVKQWe7xonWk4njrIIeah5oZxGPUzQOeg== X-Received: by 2002:a5d:6a04:0:b0:374:c847:831 with SMTP id ffacd0b85a97d-37a4238ce3fmr2862998f8f.55.1726853611434; Fri, 20 Sep 2024 10:33:31 -0700 (PDT) Received: from [127.0.1.1] (frhb82016ds.ikexpress.com. [185.246.87.17]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-378e780e029sm18111177f8f.116.2024.09.20.10.33.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Sep 2024 10:33:31 -0700 (PDT) From: Guillaume Stols Date: Fri, 20 Sep 2024 17:33:26 +0000 Subject: [PATCH v2 06/10] iio: adc: ad7606: Add PWM support for conversion trigger Precedence: bulk X-Mailing-List: linux-fbdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240920-ad7606_add_iio_backend_support-v2-6-0e78782ae7d0@baylibre.com> References: <20240920-ad7606_add_iio_backend_support-v2-0-0e78782ae7d0@baylibre.com> In-Reply-To: <20240920-ad7606_add_iio_backend_support-v2-0-0e78782ae7d0@baylibre.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Greg Kroah-Hartman , "Rafael J. Wysocki" , Jonathan Corbet , Michal Marek Cc: linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org, Michael Hennerich , linux-fbdev@vger.kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, aardelean@baylibre.com, dlechner@baylibre.com, Guillaume Stols , jstephan@baylibre.com X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1726853604; l=9213; i=gstols@baylibre.com; s=20240417; h=from:subject:message-id; bh=rGbKHqnx/NA9Sx5Ie+fz9ZIrDMgsKImoOwwJ/a9nWEA=; b=bDWDXc/YIQSmgXwpX8pQ6d5eIK4VDK4epDWqaauFUN31lfe/Gg4bl648rgftOEsmybgyKbF+j doPHbau3CQ+BDipDW/NAh0aNBm85/QAh45dfVAvCpjFVxGpnFSctq+u X-Developer-Key: i=gstols@baylibre.com; a=ed25519; pk=XvMm5WHuV67sGYOJZqIYzXndbaJOlNd8Q6li6vnb4Cs= Until now, the conversion were triggered by setting high the GPIO connected to the convst pin. This commit gives the possibility to connect the convst pin to a PWM. Connecting a PWM allows to have a better control on the samplerate, but it must be handled with care, as it is completely decorrelated of the driver's busy pin handling. Hence it is not recommended to be used "as is" but must be exploited in conjonction with IIO backend, and for now only a sampling frequency of 2 kHz is available. Signed-off-by: Guillaume Stols --- drivers/iio/adc/ad7606.c | 170 ++++++++++++++++++++++++++++++++++++++++------- drivers/iio/adc/ad7606.h | 2 + 2 files changed, 148 insertions(+), 24 deletions(-) diff --git a/drivers/iio/adc/ad7606.c b/drivers/iio/adc/ad7606.c index 9b457472d49c..b98057138295 100644 --- a/drivers/iio/adc/ad7606.c +++ b/drivers/iio/adc/ad7606.c @@ -13,11 +13,13 @@ #include #include #include +#include #include #include #include #include #include +#include #include #include @@ -83,6 +85,80 @@ static int ad7606_reg_access(struct iio_dev *indio_dev, } } +static int ad7606_pwm_set_high(struct ad7606_state *st) +{ + struct pwm_state cnvst_pwm_state; + + if (!st->cnvst_pwm) + return -EINVAL; + pwm_get_state(st->cnvst_pwm, &cnvst_pwm_state); + cnvst_pwm_state.enabled = true; + cnvst_pwm_state.duty_cycle = cnvst_pwm_state.period; + + return pwm_apply_might_sleep(st->cnvst_pwm, &cnvst_pwm_state); +} + +static int ad7606_pwm_set_low(struct ad7606_state *st) +{ + struct pwm_state cnvst_pwm_state; + + if (!st->cnvst_pwm) + return -EINVAL; + pwm_get_state(st->cnvst_pwm, &cnvst_pwm_state); + cnvst_pwm_state.enabled = true; + cnvst_pwm_state.duty_cycle = 0; + + return pwm_apply_might_sleep(st->cnvst_pwm, &cnvst_pwm_state); +} + +static int ad7606_pwm_set_swing(struct ad7606_state *st) +{ + struct pwm_state cnvst_pwm_state; + + if (!st->cnvst_pwm) + return -EINVAL; + + pwm_get_state(st->cnvst_pwm, &cnvst_pwm_state); + cnvst_pwm_state.enabled = true; + cnvst_pwm_state.duty_cycle = cnvst_pwm_state.period / 2; + + return pwm_apply_might_sleep(st->cnvst_pwm, &cnvst_pwm_state); +} + +static bool ad7606_pwm_is_swinging(struct ad7606_state *st) +{ + struct pwm_state cnvst_pwm_state; + + if (!st->cnvst_pwm) + return false; + pwm_get_state(st->cnvst_pwm, &cnvst_pwm_state); + return cnvst_pwm_state.duty_cycle != cnvst_pwm_state.period && + cnvst_pwm_state.duty_cycle != 0; +} + +static int ad7606_set_sampling_freq(struct ad7606_state *st, unsigned long freq) +{ + struct pwm_state cnvst_pwm_state; + bool is_swinging = ad7606_pwm_is_swinging(st); + bool is_high; + + if (freq == 0) + return -EINVAL; + + /* Retrieve the previous state. */ + pwm_get_state(st->cnvst_pwm, &cnvst_pwm_state); + is_high = cnvst_pwm_state.duty_cycle == cnvst_pwm_state.period; + + cnvst_pwm_state.period = DIV_ROUND_UP_ULL(NSEC_PER_SEC, freq); + cnvst_pwm_state.polarity = PWM_POLARITY_NORMAL; + if (is_high) + cnvst_pwm_state.duty_cycle = cnvst_pwm_state.period; + else if (is_swinging) + cnvst_pwm_state.duty_cycle = cnvst_pwm_state.period / 2; + + return pwm_apply_might_sleep(st->cnvst_pwm, &cnvst_pwm_state); +} + static int ad7606_read_samples(struct ad7606_state *st) { unsigned int num = st->chip_info->num_channels - 1; @@ -117,9 +193,22 @@ static irqreturn_t ad7606_trigger_handler(int irq, void *p) static int ad7606_scan_direct(struct iio_dev *indio_dev, unsigned int ch) { struct ad7606_state *st = iio_priv(indio_dev); + + struct pwm_state cnvst_pwm_state; int ret; + bool pwm_swings = false; - gpiod_set_value(st->gpio_convst, 1); + if (st->gpio_convst) { + gpiod_set_value(st->gpio_convst, 1); + } else { + pwm_get_state(st->cnvst_pwm, &cnvst_pwm_state); + /* Keep the current PWM state to set it back. */ + if (ad7606_pwm_is_swinging(st)) + pwm_swings = true; + ret = ad7606_pwm_set_high(st); + if (!ret) + return ret; + } ret = wait_for_completion_timeout(&st->completion, msecs_to_jiffies(1000)); if (!ret) { @@ -130,7 +219,12 @@ static int ad7606_scan_direct(struct iio_dev *indio_dev, unsigned int ch) ret = ad7606_read_samples(st); if (ret == 0) ret = st->data[ch]; - + if (!st->gpio_convst) { + if (!pwm_swings) + ret = ad7606_pwm_set_low(st); + else + ret = ad7606_pwm_set_swing(st); + } error_ret: gpiod_set_value(st->gpio_convst, 0); @@ -395,8 +489,9 @@ static int ad7606_request_gpios(struct ad7606_state *st) { struct device *dev = st->dev; - st->gpio_convst = devm_gpiod_get(dev, "adi,conversion-start", - GPIOD_OUT_LOW); + st->gpio_convst = devm_gpiod_get_optional(dev, "adi,conversion-start", + GPIOD_OUT_LOW); + if (IS_ERR(st->gpio_convst)) return PTR_ERR(st->gpio_convst); @@ -465,6 +560,7 @@ static int ad7606_buffer_postenable(struct iio_dev *indio_dev) struct ad7606_state *st = iio_priv(indio_dev); gpiod_set_value(st->gpio_convst, 1); + ad7606_pwm_set_swing(st); return 0; } @@ -474,6 +570,7 @@ static int ad7606_buffer_predisable(struct iio_dev *indio_dev) struct ad7606_state *st = iio_priv(indio_dev); gpiod_set_value(st->gpio_convst, 0); + ad7606_pwm_set_low(st); return 0; } @@ -521,6 +618,11 @@ static const struct iio_trigger_ops ad7606_trigger_ops = { .validate_device = iio_trigger_validate_own_device, }; +static void ad7606_pwm_disable(void *data) +{ + pwm_disable(data); +} + int ad7606_probe(struct device *dev, int irq, void __iomem *base_address, const char *name, unsigned int id, const struct ad7606_bus_ops *bops) @@ -611,20 +713,47 @@ int ad7606_probe(struct device *dev, int irq, void __iomem *base_address, return ret; } - st->trig = devm_iio_trigger_alloc(dev, "%s-dev%d", - indio_dev->name, - iio_device_id(indio_dev)); - if (!st->trig) - return -ENOMEM; - - st->trig->ops = &ad7606_trigger_ops; - iio_trigger_set_drvdata(st->trig, indio_dev); - ret = devm_iio_trigger_register(dev, st->trig); - if (ret) - return ret; - - indio_dev->trig = iio_trigger_get(st->trig); + /* If convst pin is not defined, setup PWM. */ + if (!st->gpio_convst) { + st->cnvst_pwm = devm_pwm_get(dev, NULL); + if (IS_ERR(st->cnvst_pwm)) + return PTR_ERR(st->cnvst_pwm); + /* + * PWM is not disabled when sampling stops, but instead its duty cycle is set + * to 0% to be sure we have a "low" state. After we unload the driver, let's + * disable the PWM. + */ + ret = devm_add_action_or_reset(dev, ad7606_pwm_disable, + st->cnvst_pwm); + if (ret) + return ret; + /* + * Set the sampling rate to 2 kHz so to be sure that the interruption can be + * handled between within a single pulse. + */ + ret = ad7606_set_sampling_freq(st, 2 * KILO); + if (ret) + return ret; + } else { + st->trig = devm_iio_trigger_alloc(dev, "%s-dev%d", + indio_dev->name, + iio_device_id(indio_dev)); + if (!st->trig) + return -ENOMEM; + st->trig->ops = &ad7606_trigger_ops; + iio_trigger_set_drvdata(st->trig, indio_dev); + ret = devm_iio_trigger_register(dev, st->trig); + if (ret) + return ret; + indio_dev->trig = iio_trigger_get(st->trig); + ret = devm_iio_triggered_buffer_setup(dev, indio_dev, + &iio_pollfunc_store_time, + &ad7606_trigger_handler, + &ad7606_buffer_ops); + if (ret) + return ret; + } ret = devm_request_threaded_irq(dev, irq, NULL, &ad7606_interrupt, @@ -633,13 +762,6 @@ int ad7606_probe(struct device *dev, int irq, void __iomem *base_address, if (ret) return ret; - ret = devm_iio_triggered_buffer_setup(dev, indio_dev, - &iio_pollfunc_store_time, - &ad7606_trigger_handler, - &ad7606_buffer_ops); - if (ret) - return ret; - return devm_iio_device_register(dev, indio_dev); } EXPORT_SYMBOL_NS_GPL(ad7606_probe, IIO_AD7606); diff --git a/drivers/iio/adc/ad7606.h b/drivers/iio/adc/ad7606.h index 6649e84d25de..c13dda444526 100644 --- a/drivers/iio/adc/ad7606.h +++ b/drivers/iio/adc/ad7606.h @@ -65,6 +65,7 @@ struct ad7606_chip_info { * @bops bus operations (SPI or parallel) * @range voltage range selection, selects which scale to apply * @oversampling oversampling selection + * @cnvst_pwm pointer to the PWM device connected to the cnvst pin * @base_address address from where to read data in parallel operation * @sw_mode_en software mode enabled * @scale_avail pointer to the array which stores the available scales @@ -94,6 +95,7 @@ struct ad7606_state { const struct ad7606_bus_ops *bops; unsigned int range[16]; unsigned int oversampling; + struct pwm_device *cnvst_pwm; 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[185.246.87.17]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-378e780e029sm18111177f8f.116.2024.09.20.10.33.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Sep 2024 10:33:31 -0700 (PDT) From: Guillaume Stols Date: Fri, 20 Sep 2024 17:33:27 +0000 Subject: [PATCH v2 07/10] iio: adc: ad7606: Add compatibility to fw_nodes Precedence: bulk X-Mailing-List: linux-fbdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240920-ad7606_add_iio_backend_support-v2-7-0e78782ae7d0@baylibre.com> References: <20240920-ad7606_add_iio_backend_support-v2-0-0e78782ae7d0@baylibre.com> In-Reply-To: <20240920-ad7606_add_iio_backend_support-v2-0-0e78782ae7d0@baylibre.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Greg Kroah-Hartman , "Rafael J. Wysocki" , Jonathan Corbet , Michal Marek Cc: linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org, Michael Hennerich , linux-fbdev@vger.kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, aardelean@baylibre.com, dlechner@baylibre.com, Guillaume Stols , jstephan@baylibre.com X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1726853604; l=14598; i=gstols@baylibre.com; s=20240417; h=from:subject:message-id; bh=fuWeZdZAtXd8rMGyPZJvoL1he1KOv88DgrMKYX9gf5A=; b=dbMIwK0lwOnaaMdTebmlSP9dy4cLxLrx9/I8U1qI/hBlefobVsgli89cD96H91ZdchZJPxhik 5cmLe6R7qozDRWGrCGMcseX9pBF0dBx5Bvge0212Q2Xky88dJkEdb+w X-Developer-Key: i=gstols@baylibre.com; a=ed25519; pk=XvMm5WHuV67sGYOJZqIYzXndbaJOlNd8Q6li6vnb4Cs= On the parallel version, the current implementation is only compatible with id tables and won't work with fw_nodes, this commit intends to fix it. Also, chip info is moved in the .h file so to be accessible to all the driver files that can set a pointer to the corresponding chip as the driver data. Signed-off-by: Guillaume Stols --- drivers/iio/adc/ad7606.c | 208 ++++++++++++++++++++++++------------------- drivers/iio/adc/ad7606.h | 34 +++++-- drivers/iio/adc/ad7606_par.c | 29 +++--- drivers/iio/adc/ad7606_spi.c | 31 ++++--- 4 files changed, 173 insertions(+), 129 deletions(-) diff --git a/drivers/iio/adc/ad7606.c b/drivers/iio/adc/ad7606.c index b98057138295..7f2ff1674638 100644 --- a/drivers/iio/adc/ad7606.c +++ b/drivers/iio/adc/ad7606.c @@ -51,6 +51,116 @@ static const unsigned int ad7616_oversampling_avail[8] = { 1, 2, 4, 8, 16, 32, 64, 128, }; +static const struct iio_chan_spec ad7605_channels[] = { + IIO_CHAN_SOFT_TIMESTAMP(4), + AD7605_CHANNEL(0), + AD7605_CHANNEL(1), + AD7605_CHANNEL(2), + AD7605_CHANNEL(3), +}; + +static const struct iio_chan_spec ad7606_channels[] = { + IIO_CHAN_SOFT_TIMESTAMP(8), + AD7606_CHANNEL(0), + AD7606_CHANNEL(1), + AD7606_CHANNEL(2), + AD7606_CHANNEL(3), + AD7606_CHANNEL(4), + AD7606_CHANNEL(5), + AD7606_CHANNEL(6), + AD7606_CHANNEL(7), +}; + +/* + * The current assumption that this driver makes for AD7616, is that it's + * working in Hardware Mode with Serial, Burst and Sequencer modes activated. + * To activate them, following pins must be pulled high: + * -SER/PAR + * -SEQEN + * And following pins must be pulled low: + * -WR/BURST + * -DB4/SER1W + */ +static const struct iio_chan_spec ad7616_channels[] = { + IIO_CHAN_SOFT_TIMESTAMP(16), + AD7606_CHANNEL(0), + AD7606_CHANNEL(1), + AD7606_CHANNEL(2), + AD7606_CHANNEL(3), + AD7606_CHANNEL(4), + AD7606_CHANNEL(5), + AD7606_CHANNEL(6), + AD7606_CHANNEL(7), + AD7606_CHANNEL(8), + AD7606_CHANNEL(9), + AD7606_CHANNEL(10), + AD7606_CHANNEL(11), + AD7606_CHANNEL(12), + AD7606_CHANNEL(13), + AD7606_CHANNEL(14), + AD7606_CHANNEL(15), +}; + +const struct ad7606_chip_info ad7605_4_info = { + .channels = ad7605_channels, + .num_channels = 5, + .name = "ad7605-4", + .id = ID_AD7605_4, +}; +EXPORT_SYMBOL_NS_GPL(ad7605_4_info, IIO_AD7606); + +const struct ad7606_chip_info ad7606_8_info = { + .channels = ad7606_channels, + .num_channels = 9, + .oversampling_avail = ad7606_oversampling_avail, + .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail), + .name = "ad7606-8", + .id = ID_AD7606_8, +}; +EXPORT_SYMBOL_NS_GPL(ad7606_8_info, IIO_AD7606); + +const struct ad7606_chip_info ad7606_6_info = { + .channels = ad7606_channels, + .num_channels = 7, + .oversampling_avail = ad7606_oversampling_avail, + .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail), + .name = "ad7606-6", + .id = ID_AD7606_6, +}; +EXPORT_SYMBOL_NS_GPL(ad7606_6_info, IIO_AD7606); + +const struct ad7606_chip_info ad7606_4_info = { + .channels = ad7606_channels, + .num_channels = 5, + .oversampling_avail = ad7606_oversampling_avail, + .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail), + .name = "ad7606-4", + .id = ID_AD7606_4, +}; +EXPORT_SYMBOL_NS_GPL(ad7606_4_info, IIO_AD7606); + +const struct ad7606_chip_info ad7606b_info = { + .channels = ad7606_channels, + .num_channels = 9, + .oversampling_avail = ad7606_oversampling_avail, + .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail), + .name = "ad7606B", + .id = ID_AD7606B, +}; +EXPORT_SYMBOL_NS_GPL(ad7606b_info, IIO_AD7606); + +const struct ad7606_chip_info ad7616_info = { + .channels = ad7616_channels, + .num_channels = 17, + .oversampling_avail = ad7616_oversampling_avail, + .oversampling_num = ARRAY_SIZE(ad7616_oversampling_avail), + .os_req_reset = true, + .init_delay_ms = 15, + .name = "ad7616", + .id = ID_AD7616, +}; +EXPORT_SYMBOL_NS_GPL(ad7616_info, IIO_AD7606); + int ad7606_reset(struct ad7606_state *st) { if (st->gpio_reset) { @@ -395,96 +505,6 @@ static const struct attribute_group ad7606_attribute_group_range = { .attrs = ad7606_attributes_range, }; -static const struct iio_chan_spec ad7605_channels[] = { - IIO_CHAN_SOFT_TIMESTAMP(4), - AD7605_CHANNEL(0), - AD7605_CHANNEL(1), - AD7605_CHANNEL(2), - AD7605_CHANNEL(3), -}; - -static const struct iio_chan_spec ad7606_channels[] = { - IIO_CHAN_SOFT_TIMESTAMP(8), - AD7606_CHANNEL(0), - AD7606_CHANNEL(1), - AD7606_CHANNEL(2), - AD7606_CHANNEL(3), - AD7606_CHANNEL(4), - AD7606_CHANNEL(5), - AD7606_CHANNEL(6), - AD7606_CHANNEL(7), -}; - -/* - * The current assumption that this driver makes for AD7616, is that it's - * working in Hardware Mode with Serial, Burst and Sequencer modes activated. - * To activate them, following pins must be pulled high: - * -SER/PAR - * -SEQEN - * And following pins must be pulled low: - * -WR/BURST - * -DB4/SER1W - */ -static const struct iio_chan_spec ad7616_channels[] = { - IIO_CHAN_SOFT_TIMESTAMP(16), - AD7606_CHANNEL(0), - AD7606_CHANNEL(1), - AD7606_CHANNEL(2), - AD7606_CHANNEL(3), - AD7606_CHANNEL(4), - AD7606_CHANNEL(5), - AD7606_CHANNEL(6), - AD7606_CHANNEL(7), - AD7606_CHANNEL(8), - AD7606_CHANNEL(9), - AD7606_CHANNEL(10), - AD7606_CHANNEL(11), - AD7606_CHANNEL(12), - AD7606_CHANNEL(13), - AD7606_CHANNEL(14), - AD7606_CHANNEL(15), -}; - -static const struct ad7606_chip_info ad7606_chip_info_tbl[] = { - /* More devices added in future */ - [ID_AD7605_4] = { - .channels = ad7605_channels, - .num_channels = 5, - }, - [ID_AD7606_8] = { - .channels = ad7606_channels, - .num_channels = 9, - .oversampling_avail = ad7606_oversampling_avail, - .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail), - }, - [ID_AD7606_6] = { - .channels = ad7606_channels, - .num_channels = 7, - .oversampling_avail = ad7606_oversampling_avail, - .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail), - }, - [ID_AD7606_4] = { - .channels = ad7606_channels, - .num_channels = 5, - .oversampling_avail = ad7606_oversampling_avail, - .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail), - }, - [ID_AD7606B] = { - .channels = ad7606_channels, - .num_channels = 9, - .oversampling_avail = ad7606_oversampling_avail, - .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail), - }, - [ID_AD7616] = { - .channels = ad7616_channels, - .num_channels = 17, - .oversampling_avail = ad7616_oversampling_avail, - .oversampling_num = ARRAY_SIZE(ad7616_oversampling_avail), - .os_req_reset = true, - .init_delay_ms = 15, - }, -}; - static int ad7606_request_gpios(struct ad7606_state *st) { struct device *dev = st->dev; @@ -624,7 +644,7 @@ static void ad7606_pwm_disable(void *data) } int ad7606_probe(struct device *dev, int irq, void __iomem *base_address, - const char *name, unsigned int id, + const struct ad7606_chip_info *chip_info, const struct ad7606_bus_ops *bops) { struct ad7606_state *st; @@ -653,7 +673,7 @@ int ad7606_probe(struct device *dev, int irq, void __iomem *base_address, return dev_err_probe(dev, ret, "Failed to enable specified AVcc supply\n"); - st->chip_info = &ad7606_chip_info_tbl[id]; + st->chip_info = chip_info; if (st->chip_info->oversampling_num) { st->oversampling_avail = st->chip_info->oversampling_avail; @@ -676,7 +696,7 @@ int ad7606_probe(struct device *dev, int irq, void __iomem *base_address, indio_dev->info = &ad7606_info_no_os_or_range; } indio_dev->modes = INDIO_DIRECT_MODE; - indio_dev->name = name; + indio_dev->name = chip_info->name; indio_dev->channels = st->chip_info->channels; indio_dev->num_channels = st->chip_info->num_channels; @@ -758,7 +778,7 @@ int ad7606_probe(struct device *dev, int irq, void __iomem *base_address, NULL, &ad7606_interrupt, IRQF_TRIGGER_FALLING | IRQF_ONESHOT, - name, indio_dev); + chip_info->name, indio_dev); if (ret) return ret; diff --git a/drivers/iio/adc/ad7606.h b/drivers/iio/adc/ad7606.h index c13dda444526..18c87fe9a41a 100644 --- a/drivers/iio/adc/ad7606.h +++ b/drivers/iio/adc/ad7606.h @@ -38,8 +38,19 @@ AD760X_CHANNEL(num, BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE),\ 0, BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO)) +enum ad7606_supported_device_ids { + ID_AD7605_4, + ID_AD7606_8, + ID_AD7606_6, + ID_AD7606_4, + ID_AD7606B, + ID_AD7616, +}; + /** * struct ad7606_chip_info - chip specific information + * @name device name + * @id device id * @channels: channel specification * @num_channels: number of channels * @oversampling_avail pointer to the array which stores the available @@ -50,6 +61,8 @@ * after a restart */ struct ad7606_chip_info { + enum ad7606_supported_device_ids id; + const char *name; const struct iio_chan_spec *channels; unsigned int num_channels; const unsigned int *oversampling_avail; @@ -150,19 +163,22 @@ struct ad7606_bus_ops { }; int ad7606_probe(struct device *dev, int irq, void __iomem *base_address, - const char *name, unsigned int id, + const struct ad7606_chip_info *info, const struct ad7606_bus_ops *bops); int ad7606_reset(struct ad7606_state *st); -enum ad7606_supported_device_ids { - ID_AD7605_4, - ID_AD7606_8, - ID_AD7606_6, - ID_AD7606_4, - ID_AD7606B, - ID_AD7616, -}; +extern const struct ad7606_chip_info ad7605_4_info; + +extern const struct ad7606_chip_info ad7606_8_info; + +extern const struct ad7606_chip_info ad7606_6_info; + +extern const struct ad7606_chip_info ad7606_4_info; + +extern const struct ad7606_chip_info ad7606b_info; + +extern const struct ad7606_chip_info ad7616_info; #ifdef CONFIG_PM_SLEEP extern const struct dev_pm_ops ad7606_pm_ops; diff --git a/drivers/iio/adc/ad7606_par.c b/drivers/iio/adc/ad7606_par.c index d651639c45eb..7bac39033955 100644 --- a/drivers/iio/adc/ad7606_par.c +++ b/drivers/iio/adc/ad7606_par.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include @@ -89,12 +90,20 @@ static const struct ad7606_bus_ops ad7606_par8_bops = { static int ad7606_par_probe(struct platform_device *pdev) { - const struct platform_device_id *id = platform_get_device_id(pdev); + const struct ad7606_chip_info *chip_info; + const struct platform_device_id *id; struct resource *res; void __iomem *addr; resource_size_t remap_size; int irq; + if (dev_fwnode(&pdev->dev)) { + chip_info = device_get_match_data(&pdev->dev); + } else { + id = platform_get_device_id(pdev); + chip_info = (const struct ad7606_chip_info *)id->driver_data; + } + irq = platform_get_irq(pdev, 0); if (irq < 0) return irq; @@ -106,25 +115,25 @@ static int ad7606_par_probe(struct platform_device *pdev) remap_size = resource_size(res); return ad7606_probe(&pdev->dev, irq, addr, - id->name, id->driver_data, + chip_info, remap_size > 1 ? &ad7606_par16_bops : &ad7606_par8_bops); } static const struct platform_device_id ad7606_driver_ids[] = { - { .name = "ad7605-4", .driver_data = ID_AD7605_4, }, - { .name = "ad7606-4", .driver_data = ID_AD7606_4, }, - { .name = "ad7606-6", .driver_data = ID_AD7606_6, }, - { .name = "ad7606-8", .driver_data = ID_AD7606_8, }, + { .name = "ad7605-4", .driver_data = (kernel_ulong_t)&ad7605_4_info, }, + { .name = "ad7606-4", .driver_data = (kernel_ulong_t)&ad7606_4_info, }, + { .name = "ad7606-6", .driver_data = (kernel_ulong_t)&ad7606_6_info, }, + { .name = "ad7606-8", .driver_data = (kernel_ulong_t)&ad7606_8_info, }, { } }; MODULE_DEVICE_TABLE(platform, ad7606_driver_ids); static const struct of_device_id ad7606_of_match[] = { - { .compatible = "adi,ad7605-4" }, - { .compatible = "adi,ad7606-4" }, - { .compatible = "adi,ad7606-6" }, - { .compatible = "adi,ad7606-8" }, + { .compatible = "adi,ad7605-4", .data = &ad7605_4_info }, + { .compatible = "adi,ad7606-4", .data = &ad7606_4_info }, + { .compatible = "adi,ad7606-6", .data = &ad7606_6_info }, + { .compatible = "adi,ad7606-8", .data = &ad7606_8_info }, { } }; MODULE_DEVICE_TABLE(of, ad7606_of_match); diff --git a/drivers/iio/adc/ad7606_spi.c b/drivers/iio/adc/ad7606_spi.c index d3fbc7c7a823..719f9e09a5f7 100644 --- a/drivers/iio/adc/ad7606_spi.c +++ b/drivers/iio/adc/ad7606_spi.c @@ -307,10 +307,10 @@ static const struct ad7606_bus_ops ad7606B_spi_bops = { static int ad7606_spi_probe(struct spi_device *spi) { - const struct spi_device_id *id = spi_get_device_id(spi); + const struct ad7606_chip_info *chip_info = spi_get_device_match_data(spi); const struct ad7606_bus_ops *bops; - switch (id->driver_data) { + switch (chip_info->id) { case ID_AD7616: bops = &ad7616_spi_bops; break; @@ -323,28 +323,27 @@ static int ad7606_spi_probe(struct spi_device *spi) } return ad7606_probe(&spi->dev, spi->irq, NULL, - id->name, id->driver_data, - bops); + chip_info, bops); } static const struct spi_device_id ad7606_id_table[] = { - { "ad7605-4", ID_AD7605_4 }, - { "ad7606-4", ID_AD7606_4 }, - { "ad7606-6", ID_AD7606_6 }, - { "ad7606-8", ID_AD7606_8 }, - { "ad7606b", ID_AD7606B }, - { "ad7616", ID_AD7616 }, + { "ad7605-4", (kernel_ulong_t)&ad7605_4_info }, + { "ad7606-4", (kernel_ulong_t)&ad7606_4_info }, + { "ad7606-6", (kernel_ulong_t)&ad7606_6_info }, + { "ad7606-8", (kernel_ulong_t)&ad7606_8_info }, + { "ad7606b", (kernel_ulong_t)&ad7606b_info }, + { "ad7616", (kernel_ulong_t)&ad7616_info }, { } }; MODULE_DEVICE_TABLE(spi, ad7606_id_table); static const struct of_device_id ad7606_of_match[] = { - { .compatible = "adi,ad7605-4" }, - { .compatible = "adi,ad7606-4" }, - { .compatible = "adi,ad7606-6" }, - { .compatible = "adi,ad7606-8" }, - { .compatible = "adi,ad7606b" }, - { .compatible = "adi,ad7616" }, + { .compatible = "adi,ad7605-4", &ad7605_4_info }, + { .compatible = "adi,ad7606-4", &ad7606_4_info }, + { .compatible = "adi,ad7606-6", &ad7606_6_info }, + { .compatible = "adi,ad7606-8", &ad7606_8_info }, + { .compatible = "adi,ad7606b", &ad7606b_info }, + { .compatible = "adi,ad7616", &ad7616_info }, { } }; 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[185.246.87.17]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-378e780e029sm18111177f8f.116.2024.09.20.10.33.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Sep 2024 10:33:32 -0700 (PDT) From: Guillaume Stols Date: Fri, 20 Sep 2024 17:33:28 +0000 Subject: [PATCH v2 08/10] iio: adc: ad7606: Fix typo in the driver name Precedence: bulk X-Mailing-List: linux-fbdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240920-ad7606_add_iio_backend_support-v2-8-0e78782ae7d0@baylibre.com> References: <20240920-ad7606_add_iio_backend_support-v2-0-0e78782ae7d0@baylibre.com> In-Reply-To: <20240920-ad7606_add_iio_backend_support-v2-0-0e78782ae7d0@baylibre.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Greg Kroah-Hartman , "Rafael J. Wysocki" , Jonathan Corbet , Michal Marek Cc: linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org, Michael Hennerich , linux-fbdev@vger.kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, aardelean@baylibre.com, dlechner@baylibre.com, Guillaume Stols , jstephan@baylibre.com X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1726853604; l=850; i=gstols@baylibre.com; s=20240417; h=from:subject:message-id; bh=/nFr02cbGV/HLOGxoDoh9Czsnmb68Qnp31k+zurckyM=; b=pNTsUJlZfFEP/HO0ji9WkgAo+v4qOc4w20bUCtoLmxrAZu6+aGumyRnqR5haGad0FgtIzazpL 3Kis6U4Z6eJBUUizWeNa3B/95tWRh354UGbF1pqBN+QQ7zvLmdoRwDV X-Developer-Key: i=gstols@baylibre.com; a=ed25519; pk=XvMm5WHuV67sGYOJZqIYzXndbaJOlNd8Q6li6vnb4Cs= The parallel driver's name is ad7606_par and not ad7606_parallel. Fixes: 0046a46a8f93 ("staging/ad7606: Actually build the interface modules") Signed-off-by: Guillaume Stols --- drivers/iio/adc/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index 97ece1a4b7e3..4ab1a3092d88 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -229,7 +229,7 @@ config AD7606_IFACE_PARALLEL ad7605-4, ad7606, ad7606-6, ad7606-4 analog to digital converters (ADC). To compile this driver as a module, choose M here: the - module will be called ad7606_parallel. + module will be called ad7606_par. config AD7606_IFACE_SPI tristate "Analog Devices AD7606 ADC driver with spi interface support" From patchwork Fri Sep 20 17:33:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guillaume Stols X-Patchwork-Id: 830153 Received: from mail-wm1-f52.google.com (mail-wm1-f52.google.com [209.85.128.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BFDC4184543 for ; Fri, 20 Sep 2024 17:33:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726853620; cv=none; b=lxX7pg5CD2Qi9by+SITaslybWPMQNK9m2LIIQRNRqQxqb4Jp9SYjSdoBBPt3kvmZ95h9xl4F6UwhRA1CZI804suMD7G/wuSc/TmhVMp+qQkuGKuEz7je9Hl1LWE4hlq1mTKFjH7AGKEI6SD5UcisWfQZ/cUTTocOg3lrgs1O7QY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726853620; c=relaxed/simple; bh=oq1q/NzJfEdQoqtBhTXNe9ONaDj41XLOLIawsgCIdd8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ZXGm6lAHEc5Zr3uCPNYK2n58oryOILTtxhprOGRYXR3mapxRMTRWKcJR0Q8JIk9C8Xjctm50LHIofufQlz9QM7pZM4LvDnrjOWqJSkIRVQrZ/LMN2lavSrx6F93HqkxGpLtghXlyCahapgSfruiy8ZZUs4J3erVou0ReX/h+FsQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=zXGyZFmH; arc=none smtp.client-ip=209.85.128.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="zXGyZFmH" Received: by mail-wm1-f52.google.com with SMTP id 5b1f17b1804b1-42ca4e0299eso18662545e9.2 for ; Fri, 20 Sep 2024 10:33:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1726853615; x=1727458415; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=kLZnexWwOCOJyKY1ie+tZ2lwaSXrVIbed+TIq2zB4TM=; b=zXGyZFmH/WA4EWNYOF9RUK+vSuzrzWxUxXz64rcKsW5DTx6RqNkGCbOylxe1Tb4VzH AkZD/RpLhvjd2SKLyPNHe0C9TtyK0ENve2yoUlbK7SuMnrvNnKYQkhEQ07tHb1n9FN5C if5aTyo+b9Bez8TXkMhTCklB+T30h6ofvD4PxUxYN7mw5s8MuxIkDsu1EYkVL7R5zTPw cGv+Lsrtu0dC3v6C7yXJspuHTC7c0MnO2wift6RL2Jc7IRzD4qEzjFBG9N4pNxoIO4hl HfCVm1EtlC5Od9syi7wGPO4vohGansga/Xm4MWX+agPEN5Xgk3b3ZhXCDPUgeaVFRYEE LrFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726853615; x=1727458415; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kLZnexWwOCOJyKY1ie+tZ2lwaSXrVIbed+TIq2zB4TM=; b=C38Enq0wHoQB4T+9/HYEoIMOquaN+ZuywCFqkTm9mIC0wl3JBjyqPAowOVQCvPPo92 9pfGHOWPLpjfAmZkn1CvLk4LV26O7eyuYa93oi8bcdmNSU8ixmc+cCMHtmHlhz0Qwib2 7WTqTQrzwm242drgsO+e/Nx07zxNZDM3ZHMlpJ5q0T7dK2ZFtqQnF1UODMCYkYNaf1J1 aj70pYeom1g0/8QOp7aDPQKiibTl5rAR0Q1mCIDjP1maHk/iHjRM/aaHYCufW/lJsMn2 eCKIdCErzShGB2fjU0mdPTQEt1Mj7978P/tfXpvk1N10+T5KDy9F/ssFwNUDvAkuvm3b 5yhg== X-Forwarded-Encrypted: i=1; AJvYcCXVaapG8Pi2d/qW+UnVPnJAAX1PAYVGccb6o/fsH72K6RMkhXv3J9/IJyesTBeB5x+tkaZu6/b9YX4npA==@vger.kernel.org X-Gm-Message-State: AOJu0YwQArpzyL8272kmXGQVjzbmi4r/QihoyNEypWwnsyLkpVshG2Gn EHPjOQ/psJt9VWv0JJyQ25xLKY2zNxfdwJ6tKjMi14hUhs7XjQ/z8iBcAWPyp5A00JLBiKnpAkU D X-Google-Smtp-Source: AGHT+IHRqwfSRwCNWamNToJaGpWUDBjEwXhaz+zI66pN8+3VxydOa3lG6s44mAyPEDyvsz00F8g0Kw== X-Received: by 2002:adf:e58c:0:b0:374:c6a7:5bd2 with SMTP id ffacd0b85a97d-37a4313fef7mr1927548f8f.21.1726853614507; Fri, 20 Sep 2024 10:33:34 -0700 (PDT) Received: from [127.0.1.1] (frhb82016ds.ikexpress.com. [185.246.87.17]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-378e780e029sm18111177f8f.116.2024.09.20.10.33.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Sep 2024 10:33:34 -0700 (PDT) From: Guillaume Stols Date: Fri, 20 Sep 2024 17:33:29 +0000 Subject: [PATCH v2 09/10] iio: adc: ad7606: Add iio-backend support Precedence: bulk X-Mailing-List: linux-fbdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240920-ad7606_add_iio_backend_support-v2-9-0e78782ae7d0@baylibre.com> References: <20240920-ad7606_add_iio_backend_support-v2-0-0e78782ae7d0@baylibre.com> In-Reply-To: <20240920-ad7606_add_iio_backend_support-v2-0-0e78782ae7d0@baylibre.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Greg Kroah-Hartman , "Rafael J. Wysocki" , Jonathan Corbet , Michal Marek Cc: linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org, Michael Hennerich , linux-fbdev@vger.kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, aardelean@baylibre.com, dlechner@baylibre.com, Guillaume Stols , jstephan@baylibre.com X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1726853604; l=14580; i=gstols@baylibre.com; s=20240417; h=from:subject:message-id; bh=oq1q/NzJfEdQoqtBhTXNe9ONaDj41XLOLIawsgCIdd8=; b=SGthrUVrmseDOaiOn9+/Q4L+Cz/5RKwNTT++JdFZ1uwHM+3zEcSAir2M+jpv5pCEmcYXQ2qc4 sxx3ji7LU2yAmPJ0lxaxlR/An7GUnxrSmx4ZL0gnXoyueFJzXU/SCur X-Developer-Key: i=gstols@baylibre.com; a=ed25519; pk=XvMm5WHuV67sGYOJZqIYzXndbaJOlNd8Q6li6vnb4Cs= - Basic support for iio backend. - Supports IIO_CHAN_INFO_SAMP_FREQ R/W. - Only hardware mode is available, and that IIO_CHAN_INFO_RAW is not supported if iio-backend mode is selected. Signed-off-by: Guillaume Stols --- drivers/iio/adc/Kconfig | 2 + drivers/iio/adc/ad7606.c | 94 +++++++++++++++++++++++++++++++++++++------- drivers/iio/adc/ad7606.h | 15 +++++++ drivers/iio/adc/ad7606_par.c | 91 ++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 187 insertions(+), 15 deletions(-) diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index 4ab1a3092d88..9b52d5b2c592 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -224,9 +224,11 @@ config AD7606_IFACE_PARALLEL tristate "Analog Devices AD7606 ADC driver with parallel interface support" depends on HAS_IOPORT select AD7606 + select IIO_BACKEND help Say yes here to build parallel interface support for Analog Devices: ad7605-4, ad7606, ad7606-6, ad7606-4 analog to digital converters (ADC). + It also support iio_backended devices for AD7606B. To compile this driver as a module, choose M here: the module will be called ad7606_par. diff --git a/drivers/iio/adc/ad7606.c b/drivers/iio/adc/ad7606.c index 7f2ff1674638..f710445bdc22 100644 --- a/drivers/iio/adc/ad7606.c +++ b/drivers/iio/adc/ad7606.c @@ -21,6 +21,7 @@ #include #include +#include #include #include #include @@ -271,7 +272,15 @@ static int ad7606_set_sampling_freq(struct ad7606_state *st, unsigned long freq) static int ad7606_read_samples(struct ad7606_state *st) { - unsigned int num = st->chip_info->num_channels - 1; + unsigned int num = st->chip_info->num_channels; + + /* + * Timestamp channel does not contain sample, and no timestamp channel if + * backend is used. + */ + if (!st->back) + num--; + u16 *data = st->data; return st->bops->read_block(st->dev, num, data); @@ -319,11 +328,14 @@ static int ad7606_scan_direct(struct iio_dev *indio_dev, unsigned int ch) if (!ret) return ret; } - ret = wait_for_completion_timeout(&st->completion, - msecs_to_jiffies(1000)); - if (!ret) { - ret = -ETIMEDOUT; - goto error_ret; + + if (!st->back) { + ret = wait_for_completion_timeout(&st->completion, + msecs_to_jiffies(1000)); + if (!ret) { + ret = -ETIMEDOUT; + goto error_ret; + } } ret = ad7606_read_samples(st); @@ -349,6 +361,7 @@ static int ad7606_read_raw(struct iio_dev *indio_dev, { int ret, ch = 0; struct ad7606_state *st = iio_priv(indio_dev); + struct pwm_state cnvst_pwm_state; switch (m) { case IIO_CHAN_INFO_RAW: @@ -369,6 +382,10 @@ static int ad7606_read_raw(struct iio_dev *indio_dev, case IIO_CHAN_INFO_OVERSAMPLING_RATIO: *val = st->oversampling; return IIO_VAL_INT; + case IIO_CHAN_INFO_SAMP_FREQ: + pwm_get_state(st->cnvst_pwm, &cnvst_pwm_state); + *val = DIV_ROUND_CLOSEST_ULL(NSEC_PER_SEC, cnvst_pwm_state.period); + return IIO_VAL_INT; } return -EINVAL; } @@ -458,6 +475,8 @@ static int ad7606_write_raw(struct iio_dev *indio_dev, return ret; return 0; + case IIO_CHAN_INFO_SAMP_FREQ: + return ad7606_set_sampling_freq(st, val); default: return -EINVAL; } @@ -595,14 +614,49 @@ static int ad7606_buffer_predisable(struct iio_dev *indio_dev) return 0; } +static int ad7606_pwm_buffer_postenable(struct iio_dev *indio_dev) +{ + struct ad7606_state *st = iio_priv(indio_dev); + + return ad7606_pwm_set_swing(st); +} + +static int ad7606_pwm_buffer_predisable(struct iio_dev *indio_dev) +{ + struct ad7606_state *st = iio_priv(indio_dev); + + return ad7606_pwm_set_low(st); +} + +static int ad7606_update_scan_mode(struct iio_dev *indio_dev, + const unsigned long *scan_mask) +{ + struct ad7606_state *st = iio_priv(indio_dev); + + /* The update scan mode is only for iio backend compatible drivers. + * If the specific update_scan_mode is not defined in the bus ops, + * just do nothing and return 0. + */ + if (st->bops->update_scan_mode) + return st->bops->update_scan_mode(indio_dev, scan_mask); + else + return 0; +} + static const struct iio_buffer_setup_ops ad7606_buffer_ops = { .postenable = &ad7606_buffer_postenable, .predisable = &ad7606_buffer_predisable, }; +static const struct iio_buffer_setup_ops ad7606_pwm_buffer_ops = { + .postenable = &ad7606_pwm_buffer_postenable, + .predisable = &ad7606_pwm_buffer_predisable, +}; + static const struct iio_info ad7606_info_no_os_or_range = { .read_raw = &ad7606_read_raw, .validate_trigger = &ad7606_validate_trigger, + .update_scan_mode = &ad7606_update_scan_mode, }; static const struct iio_info ad7606_info_os_and_range = { @@ -610,6 +664,7 @@ static const struct iio_info ad7606_info_os_and_range = { .write_raw = &ad7606_write_raw, .attrs = &ad7606_attribute_group_os_and_range, .validate_trigger = &ad7606_validate_trigger, + .update_scan_mode = &ad7606_update_scan_mode, }; static const struct iio_info ad7606_info_os_range_and_debug = { @@ -618,6 +673,7 @@ static const struct iio_info ad7606_info_os_range_and_debug = { .debugfs_reg_access = &ad7606_reg_access, .attrs = &ad7606_attribute_group_os_and_range, .validate_trigger = &ad7606_validate_trigger, + .update_scan_mode = &ad7606_update_scan_mode, }; static const struct iio_info ad7606_info_os = { @@ -625,6 +681,7 @@ static const struct iio_info ad7606_info_os = { .write_raw = &ad7606_write_raw, .attrs = &ad7606_attribute_group_os, .validate_trigger = &ad7606_validate_trigger, + .update_scan_mode = &ad7606_update_scan_mode, }; static const struct iio_info ad7606_info_range = { @@ -632,6 +689,7 @@ static const struct iio_info ad7606_info_range = { .write_raw = &ad7606_write_raw, .attrs = &ad7606_attribute_group_range, .validate_trigger = &ad7606_validate_trigger, + .update_scan_mode = &ad7606_update_scan_mode, }; static const struct iio_trigger_ops ad7606_trigger_ops = { @@ -700,8 +758,6 @@ int ad7606_probe(struct device *dev, int irq, void __iomem *base_address, indio_dev->channels = st->chip_info->channels; indio_dev->num_channels = st->chip_info->num_channels; - init_completion(&st->completion); - ret = ad7606_reset(st); if (ret) dev_warn(st->dev, "failed to RESET: no RESET GPIO specified\n"); @@ -774,14 +830,22 @@ int ad7606_probe(struct device *dev, int irq, void __iomem *base_address, if (ret) return ret; } - ret = devm_request_threaded_irq(dev, irq, - NULL, - &ad7606_interrupt, - IRQF_TRIGGER_FALLING | IRQF_ONESHOT, - chip_info->name, indio_dev); - if (ret) - return ret; + if (st->bops->iio_backend_config) { + ret = st->bops->iio_backend_config(dev, indio_dev); + if (ret) + return ret; + indio_dev->setup_ops = &ad7606_pwm_buffer_ops; + } else { + init_completion(&st->completion); + ret = devm_request_threaded_irq(dev, irq, + NULL, + &ad7606_interrupt, + IRQF_TRIGGER_FALLING | IRQF_ONESHOT, + chip_info->name, indio_dev); + if (ret) + return ret; + } return devm_iio_device_register(dev, indio_dev); } EXPORT_SYMBOL_NS_GPL(ad7606_probe, IIO_AD7606); diff --git a/drivers/iio/adc/ad7606.h b/drivers/iio/adc/ad7606.h index 18c87fe9a41a..53cd8eb4898e 100644 --- a/drivers/iio/adc/ad7606.h +++ b/drivers/iio/adc/ad7606.h @@ -34,6 +34,12 @@ BIT(IIO_CHAN_INFO_SCALE), \ BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO)) +#define AD7606_BI_CHANNEL(num) \ + AD760X_CHANNEL(num, 0, \ + BIT(IIO_CHAN_INFO_SCALE), \ + BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO)) + #define AD7616_CHANNEL(num) \ AD760X_CHANNEL(num, BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE),\ 0, BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO)) @@ -59,6 +65,7 @@ enum ad7606_supported_device_ids { * @os_req_reset some devices require a reset to update oversampling * @init_delay_ms required delay in miliseconds for initialization * after a restart + * @has_backend defines if a backend is available for the given chip */ struct ad7606_chip_info { enum ad7606_supported_device_ids id; @@ -69,6 +76,7 @@ struct ad7606_chip_info { unsigned int oversampling_num; bool os_req_reset; unsigned long init_delay_ms; + bool has_backend; }; /** @@ -115,6 +123,7 @@ struct ad7606_state { unsigned int num_scales; const unsigned int *oversampling_avail; unsigned int num_os_ratios; + struct iio_backend *back; int (*write_scale)(struct iio_dev *indio_dev, int ch, int val); int (*write_os)(struct iio_dev *indio_dev, int val); @@ -139,16 +148,21 @@ struct ad7606_state { /** * struct ad7606_bus_ops - driver bus operations + * @iio_backend_config function pointer for configuring the iio_backend for + * the compatibles that use it * @read_block function pointer for reading blocks of data * @sw_mode_config: pointer to a function which configured the device * for software mode * @reg_read function pointer for reading spi register * @reg_write function pointer for writing spi register * @write_mask function pointer for write spi register with mask + * @update_scan_mode function pointer for handling the calls to iio_info's update_scan + * mode when enabling/disabling channels. * @rd_wr_cmd pointer to the function which calculates the spi address */ struct ad7606_bus_ops { /* more methods added in future? */ + int (*iio_backend_config)(struct device *dev, struct iio_dev *indio_dev); int (*read_block)(struct device *dev, int num, void *data); int (*sw_mode_config)(struct iio_dev *indio_dev); int (*reg_read)(struct ad7606_state *st, unsigned int addr); @@ -159,6 +173,7 @@ struct ad7606_bus_ops { unsigned int addr, unsigned long mask, unsigned int val); + int (*update_scan_mode)(struct iio_dev *indio_dev, const unsigned long *scan_mask); u16 (*rd_wr_cmd)(int addr, char isWriteOp); }; diff --git a/drivers/iio/adc/ad7606_par.c b/drivers/iio/adc/ad7606_par.c index 7bac39033955..564284ede997 100644 --- a/drivers/iio/adc/ad7606_par.c +++ b/drivers/iio/adc/ad7606_par.c @@ -3,6 +3,8 @@ * AD7606 Parallel Interface ADC driver * * Copyright 2011 Analog Devices Inc. + * Copyright 2024 Analog Devices Inc. + * Copyright 2024 BayLibre SAS. */ #include @@ -15,8 +17,80 @@ #include #include +#include + #include "ad7606.h" +static const struct iio_chan_spec ad7606b_bi_channels[] = { + AD7606_BI_CHANNEL(0), + AD7606_BI_CHANNEL(1), + AD7606_BI_CHANNEL(2), + AD7606_BI_CHANNEL(3), + AD7606_BI_CHANNEL(4), + AD7606_BI_CHANNEL(5), + AD7606_BI_CHANNEL(6), + AD7606_BI_CHANNEL(7), +}; + +static int ad7606_bi_update_scan_mode(struct iio_dev *indio_dev, const unsigned long *scan_mask) +{ + struct ad7606_state *st = iio_priv(indio_dev); + unsigned int c, ret; + + for (c = 0; c < indio_dev->num_channels; c++) { + if (test_bit(c, scan_mask)) + ret = iio_backend_chan_enable(st->back, c); + else + ret = iio_backend_chan_disable(st->back, c); + if (ret) + return ret; + } + + return 0; +} + +static int ad7606_bi_setup_iio_backend(struct device *dev, struct iio_dev *indio_dev) +{ + struct ad7606_state *st = iio_priv(indio_dev); + unsigned int ret, c; + struct iio_backend_data_fmt data = { + .sign_extend = true, + .enable = true, + }; + + st->back = devm_iio_backend_get(dev, NULL); + if (IS_ERR(st->back)) + return PTR_ERR(st->back); + + /* If the device is iio_backend powered the PWM is mandatory */ + if (!st->cnvst_pwm) + return -EINVAL; + + ret = devm_iio_backend_request_buffer(dev, st->back, indio_dev); + if (ret) + return ret; + + ret = devm_iio_backend_enable(dev, st->back); + if (ret) + return ret; + + for (c = 0; c < indio_dev->num_channels; c++) { + ret = iio_backend_data_format_set(st->back, c, &data); + if (ret) + return ret; + } + + indio_dev->channels = ad7606b_bi_channels; + indio_dev->num_channels = 8; + + return 0; +} + +static const struct ad7606_bus_ops ad7606_bi_bops = { + .iio_backend_config = ad7606_bi_setup_iio_backend, + .update_scan_mode = ad7606_bi_update_scan_mode, +}; + static int ad7606_par16_read_block(struct device *dev, int count, void *buf) { @@ -96,9 +170,23 @@ static int ad7606_par_probe(struct platform_device *pdev) void __iomem *addr; resource_size_t remap_size; int irq; + struct iio_backend *back; + /* + * If a firmware node is available (ACPI or DT), platform_device_id is null + * and we must use get_match_data. + */ if (dev_fwnode(&pdev->dev)) { chip_info = device_get_match_data(&pdev->dev); + back = devm_iio_backend_get(&pdev->dev, NULL); + if (!IS_ERR(back)) + /* + * If a backend is available in the device tree, call the core + * probe with backend bops, otherwise use the former bops. + */ + return ad7606_probe(&pdev->dev, 0, NULL, + chip_info, + &ad7606_bi_bops); } else { id = platform_get_device_id(pdev); chip_info = (const struct ad7606_chip_info *)id->driver_data; @@ -125,6 +213,7 @@ static const struct platform_device_id ad7606_driver_ids[] = { { .name = "ad7606-4", .driver_data = (kernel_ulong_t)&ad7606_4_info, }, { .name = "ad7606-6", .driver_data = (kernel_ulong_t)&ad7606_6_info, }, { .name = "ad7606-8", .driver_data = (kernel_ulong_t)&ad7606_8_info, }, + { .name = "ad7606b", .driver_data = (kernel_ulong_t)&ad7606b_info, }, { } }; MODULE_DEVICE_TABLE(platform, ad7606_driver_ids); @@ -134,6 +223,7 @@ static const struct of_device_id ad7606_of_match[] = { { .compatible = "adi,ad7606-4", .data = &ad7606_4_info }, { .compatible = "adi,ad7606-6", .data = &ad7606_6_info }, { .compatible = "adi,ad7606-8", .data = &ad7606_8_info }, + { .compatible = "adi,ad7606b", .data = &ad7606b_info }, { } }; MODULE_DEVICE_TABLE(of, ad7606_of_match); @@ -153,3 +243,4 @@ MODULE_AUTHOR("Michael Hennerich "); MODULE_DESCRIPTION("Analog Devices AD7606 ADC"); MODULE_LICENSE("GPL v2"); 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[185.246.87.17]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-378e780e029sm18111177f8f.116.2024.09.20.10.33.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Sep 2024 10:33:34 -0700 (PDT) From: Guillaume Stols Date: Fri, 20 Sep 2024 17:33:30 +0000 Subject: [PATCH v2 10/10] iio: adc: ad7606: Disable PWM usage for non backend version Precedence: bulk X-Mailing-List: linux-fbdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240920-ad7606_add_iio_backend_support-v2-10-0e78782ae7d0@baylibre.com> References: <20240920-ad7606_add_iio_backend_support-v2-0-0e78782ae7d0@baylibre.com> In-Reply-To: <20240920-ad7606_add_iio_backend_support-v2-0-0e78782ae7d0@baylibre.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Greg Kroah-Hartman , "Rafael J. Wysocki" , Jonathan Corbet , Michal Marek Cc: linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org, Michael Hennerich , linux-fbdev@vger.kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, aardelean@baylibre.com, dlechner@baylibre.com, Guillaume Stols , jstephan@baylibre.com X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1726853604; l=1655; i=gstols@baylibre.com; s=20240417; h=from:subject:message-id; bh=jH5AF1NUj11MGOXs+0oMMIR7SvlyPmokhbLME9mMNMs=; b=kSnZJIrPGfSq6YzbLJZ9p9mO7w2NOsG/iZXur554ypRAWkxnTvW2tYn3jiMYak1kdPyCLhejb hUajOoIJbZlAmnbA5Lm007KmnnbAvokXAsLS7hGMF50KRMfdAOuPIXg X-Developer-Key: i=gstols@baylibre.com; a=ed25519; pk=XvMm5WHuV67sGYOJZqIYzXndbaJOlNd8Q6li6vnb4Cs= Since the pwm was introduced before backend, there was an example use whit triggered buffers. However, using it may be dangerous, because if the PWM goes too fast, a new conversion can be triggered before the transmission is over, whit the associated mess in the buffers. Until a solution is found to mitigate this risk, for instante CRC support, the PWM will be disabled. Signed-off-by: Guillaume Stols --- drivers/iio/adc/ad7606.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/iio/adc/ad7606.c b/drivers/iio/adc/ad7606.c index f710445bdc22..0c12ca237ee9 100644 --- a/drivers/iio/adc/ad7606.c +++ b/drivers/iio/adc/ad7606.c @@ -599,7 +599,6 @@ static int ad7606_buffer_postenable(struct iio_dev *indio_dev) struct ad7606_state *st = iio_priv(indio_dev); gpiod_set_value(st->gpio_convst, 1); - ad7606_pwm_set_swing(st); return 0; } @@ -609,7 +608,6 @@ static int ad7606_buffer_predisable(struct iio_dev *indio_dev) struct ad7606_state *st = iio_priv(indio_dev); gpiod_set_value(st->gpio_convst, 0); - ad7606_pwm_set_low(st); return 0; } @@ -838,6 +836,12 @@ int ad7606_probe(struct device *dev, int irq, void __iomem *base_address, indio_dev->setup_ops = &ad7606_pwm_buffer_ops; } else { init_completion(&st->completion); + + /* Reserve the PWM use only for backend (force gpio_convst definition) */ + if (!st->gpio_convst) + return dev_err_probe(dev, -EINVAL, + "No backend, connect convst to a GPIO"); + ret = devm_request_threaded_irq(dev, irq, NULL, &ad7606_interrupt,