From patchwork Sun Nov 17 07:21:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 179570 Delivered-To: patch@linaro.org Received: by 2002:a92:38d5:0:0:0:0:0 with SMTP id g82csp1380680ilf; Sat, 16 Nov 2019 23:21:53 -0800 (PST) X-Google-Smtp-Source: APXvYqxahCIcCLD+bHz+EsDdGfxhJtErRsQRsPlOkNMFC4wQEoeRIOHDuD7sx8G1gOesyGSrDueV X-Received: by 2002:a17:906:d96e:: with SMTP id rp14mr15775021ejb.14.1573975313869; Sat, 16 Nov 2019 23:21:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1573975313; cv=none; d=google.com; s=arc-20160816; b=iZoenAow1xR+DFEubkpND6DHFWYmVxlTGvZxbHodufkwpJB+UKNhYO0c4SGHO83gPO 6re9qvGQY0hDkzSw+V1rNuUdc9arG+5nfkfTqKVM/xioi71X0p2iQ+qNnrdN88/gIcv8 ST4jFOWZT8J+tclX4VhBIfYJX1RLJVpIKjk2w4I4Xjysi856p1jDEp6wyYPU9+9EyhrT j1DwmzbRGKJdNJA0kLoEr8XemN3SaQY2K/K425/Tl3F1mAjZfhnPRWXWytG8QRihNf8j xqq9ZyUuyhlZHbOMZs0dn9L0FGhuDADbUje92hNwrLa/AbCBDVwflUGwr4NrGcVetD9o CK7w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=ePBfLWZ2vfIZpbAlr95BTl6wia/1eyw+9jnS9E+xRAM=; b=I9yuGChMgeM0mTigspLpr17C8yyMhC2EqmwOL6Yhgl5kGWdT0QaQYt73HW/j6uG5bZ 7BuFbmrKNYz9LS/KOLGZcFCJAnrRLxVy7L+oe1n11WPq60/WMlcLLTMVWvVGGF478WHo Qd+PdDp1iFUojdiJcGUQC9lxYp//6zAYXXGuGt8b7u30cpT3sdAsjVysZH/ttFH1JJ5h K0sN3Cn5Gm1OGhrOT1GcSodVFS/gg1wpP2kNVlUeKQQpUpnBomSXzDulVqiAb/HTu31K qUsy3ZQuy0EMCk6eaMvdAMayBDKZHjQeNDwhpZsSgfXzB4nfT6ahAoHre0tR4sbIh5zu uzTA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id ks14si8713115ejb.87.2019.11.16.23.21.53; Sat, 16 Nov 2019 23:21:53 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726032AbfKQHVV (ORCPT + 26 others); Sun, 17 Nov 2019 02:21:21 -0500 Received: from mx2.suse.de ([195.135.220.15]:40734 "EHLO mx1.suse.de" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1725880AbfKQHVU (ORCPT ); Sun, 17 Nov 2019 02:21:20 -0500 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (unknown [195.135.220.254]) by mx1.suse.de (Postfix) with ESMTP id 07A6EB12D; Sun, 17 Nov 2019 07:21:19 +0000 (UTC) From: =?utf-8?q?Andreas_F=C3=A4rber?= To: linux-realtek-soc@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, =?utf-8?q?Andreas_F=C3=A4rber?= , Rob Herring , Mark Rutland , devicetree@vger.kernel.org Subject: [PATCH v3 1/8] dt-bindings: arm: realtek: Add RTD1195 and MeLE X1000 Date: Sun, 17 Nov 2019 08:21:02 +0100 Message-Id: <20191117072109.20402-2-afaerber@suse.de> X-Mailer: git-send-email 2.16.4 In-Reply-To: <20191117072109.20402-1-afaerber@suse.de> References: <20191117072109.20402-1-afaerber@suse.de> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add bindings for Realtek RTD1195 SoC and MeLE X1000 TV box. Reviewed-by: Rob Herring Signed-off-by: Andreas Färber --- v1 -> v2 -> v3: Unchanged Documentation/devicetree/bindings/arm/realtek.yaml | 6 ++++++ 1 file changed, 6 insertions(+) -- 2.16.4 diff --git a/Documentation/devicetree/bindings/arm/realtek.yaml b/Documentation/devicetree/bindings/arm/realtek.yaml index ab59de17152d..091616880d25 100644 --- a/Documentation/devicetree/bindings/arm/realtek.yaml +++ b/Documentation/devicetree/bindings/arm/realtek.yaml @@ -14,6 +14,12 @@ properties: const: '/' compatible: oneOf: + # RTD1195 SoC based boards + - items: + - enum: + - mele,x1000 # MeLE X1000 + - const: realtek,rtd1195 + # RTD1293 SoC based boards - items: - enum: From patchwork Sun Nov 17 07:21:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 179563 Delivered-To: patch@linaro.org Received: by 2002:a92:38d5:0:0:0:0:0 with SMTP id g82csp1380408ilf; Sat, 16 Nov 2019 23:21:33 -0800 (PST) X-Google-Smtp-Source: APXvYqw2ZBbgMhcawPE4X7Ixo12IE/XrHOQqN3Ej4MDGU4K6E1X84Yweanbx4QHc9Rpa4lrk6v3V X-Received: by 2002:a17:906:6dcf:: with SMTP id j15mr16157041ejt.104.1573975293842; Sat, 16 Nov 2019 23:21:33 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1573975293; cv=none; d=google.com; s=arc-20160816; b=I19gzxPMKMfKMjlHMg7M7Loz1ZVgxJtg1M7IM8W9wZvxsG3eZv648bAwEP4Qb2hOed fiv8F0V7OBdPPf7qU0yKljl/zPm/akNNaaRY7hcZzm0QqgZM1jZLjQay02b7Ezwk+NCh JNyMq3+slBeBpIPPjp933VipqxztZMDDo3By+MJxmKzwj5tF00nNc+CcrVUv0mf790Mr RTWLfLPSBiKF/NisaYRZi/63l6IR0ewEavchGki08VEXiJLXPvV1HQtwREVpieovudhm ZSckfjUNctgrKxZv9ARTSAlQNzlj85ReiLsEShDlxq+TVRnLOZFRLiFBk8buC0cc5cPU faFQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=TumL4ZCNcMXddkAYqjm06THVgNFJBGfu9nrzrtN5PnI=; b=I2RBgGBks8mgcctoqZhFqnWb4dxu2My4kfAPDzjhxCDIqmbBgwZLUWh7+P1Zey78+n NJdFVDQu5aDMqIvyUUPUsrd5fTZT150JjmpekqLILi2PwVbVHXZIjuPPci7ALLbNmsBt xvQlc6Cu68W9HurBcYeFDhMo1PXdneTp5JIlu61n8S9d8d/pMujhHBBRsdYsyeYPqR2M 3Uw6wmNZjG+R6Azi3hJLW4dZEvuA2jt301T8sj9iROcHCoeOWcTacmEqSfr04Rq+u9rz lIwp3dtTMTR6wcOmmX2aZa3ath0lQWgKEYaRVetgs+7WbCGA3g/fJW57DFSfdrHua5hd C2Yw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id q20si9182013eja.339.2019.11.16.23.21.33; Sat, 16 Nov 2019 23:21:33 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726104AbfKQHVW (ORCPT + 26 others); Sun, 17 Nov 2019 02:21:22 -0500 Received: from mx2.suse.de ([195.135.220.15]:40748 "EHLO mx1.suse.de" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1725909AbfKQHVW (ORCPT ); Sun, 17 Nov 2019 02:21:22 -0500 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (unknown [195.135.220.254]) by mx1.suse.de (Postfix) with ESMTP id CA4DFB22C; Sun, 17 Nov 2019 07:21:19 +0000 (UTC) From: =?utf-8?q?Andreas_F=C3=A4rber?= To: linux-realtek-soc@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, =?utf-8?q?Andreas_F=C3=A4rber?= , Russell King Subject: [PATCH v3 2/8] ARM: Prepare Realtek RTD1195 Date: Sun, 17 Nov 2019 08:21:03 +0100 Message-Id: <20191117072109.20402-3-afaerber@suse.de> X-Mailer: git-send-email 2.16.4 In-Reply-To: <20191117072109.20402-1-afaerber@suse.de> References: <20191117072109.20402-1-afaerber@suse.de> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Introduce ARCH_REALTEK Kconfig option also for 32-bit Arm. Override the text offset to cope with boot ROM occupying first 0xa800 bytes and further reservations up to 0xf4000 (compare Device Tree). Add a custom machine_desc to enforce memory carveout for I/O registers. Signed-off-by: Andreas Färber --- v2 -> v3: * Fixed r-bus size in .reserve from 0x100000 to 0x70000 (James) v1 -> v2: * Dropped selection of COMMON_CLK (Arnd) * Dropped selection of AMBA, SCU, TWD * Added comment about text offset to distinguish from HTC comment above * Added machine_desc with .reserve to exclude peripheral spaces (Rob) arch/arm/Kconfig | 2 ++ arch/arm/Makefile | 3 +++ arch/arm/mach-realtek/Kconfig | 11 +++++++++++ arch/arm/mach-realtek/Makefile | 2 ++ arch/arm/mach-realtek/rtd1195.c | 37 +++++++++++++++++++++++++++++++++++++ 5 files changed, 55 insertions(+) create mode 100644 arch/arm/mach-realtek/Kconfig create mode 100644 arch/arm/mach-realtek/Makefile create mode 100644 arch/arm/mach-realtek/rtd1195.c -- 2.16.4 diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 9771b56e79f1..cd37b5e9f86d 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -699,6 +699,8 @@ source "arch/arm/mach-qcom/Kconfig" source "arch/arm/mach-rda/Kconfig" +source "arch/arm/mach-realtek/Kconfig" + source "arch/arm/mach-realview/Kconfig" source "arch/arm/mach-rockchip/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index db857d07114f..16d41efea7f2 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -148,6 +148,8 @@ head-y := arch/arm/kernel/head$(MMUEXT).o textofs-y := 0x00008000 # We don't want the htc bootloader to corrupt kernel during resume textofs-$(CONFIG_PM_H1940) := 0x00108000 +# RTD1195 has Boot ROM at start of address space +textofs-$(CONFIG_ARCH_REALTEK) := 0x00108000 # SA1111 DMA bug: we don't want the kernel to live in precious DMA-able memory ifeq ($(CONFIG_ARCH_SA1100),y) textofs-$(CONFIG_SA1111) := 0x00208000 @@ -207,6 +209,7 @@ machine-$(CONFIG_ARCH_PICOXCELL) += picoxcell machine-$(CONFIG_ARCH_PXA) += pxa machine-$(CONFIG_ARCH_QCOM) += qcom machine-$(CONFIG_ARCH_RDA) += rda +machine-$(CONFIG_ARCH_REALTEK) += realtek machine-$(CONFIG_ARCH_REALVIEW) += realview machine-$(CONFIG_ARCH_ROCKCHIP) += rockchip machine-$(CONFIG_ARCH_RPC) += rpc diff --git a/arch/arm/mach-realtek/Kconfig b/arch/arm/mach-realtek/Kconfig new file mode 100644 index 000000000000..19fdcf093fd1 --- /dev/null +++ b/arch/arm/mach-realtek/Kconfig @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +menuconfig ARCH_REALTEK + bool "Realtek SoCs" + depends on ARCH_MULTI_V7 + select ARM_GIC + select ARM_GLOBAL_TIMER + select CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK + select GENERIC_IRQ_CHIP + select RESET_CONTROLLER + help + This enables support for the Realtek RTD1195 SoC family. diff --git a/arch/arm/mach-realtek/Makefile b/arch/arm/mach-realtek/Makefile new file mode 100644 index 000000000000..5382d5bbdd3c --- /dev/null +++ b/arch/arm/mach-realtek/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +obj-y += rtd1195.o diff --git a/arch/arm/mach-realtek/rtd1195.c b/arch/arm/mach-realtek/rtd1195.c new file mode 100644 index 000000000000..b31a4066be87 --- /dev/null +++ b/arch/arm/mach-realtek/rtd1195.c @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Realtek RTD1195 + * + * Copyright (c) 2017-2019 Andreas Färber + */ + +#include +#include + +static void __init rtd1195_memblock_remove(phys_addr_t base, phys_addr_t size) +{ + int ret; + + ret = memblock_remove(base, size); + if (ret) + pr_err("Failed to remove memblock %pa (%d)\n", &base, ret); +} + +static void __init rtd1195_reserve(void) +{ + /* Exclude peripheral register spaces from RAM */ + rtd1195_memblock_remove(0x18000000, 0x00070000); + rtd1195_memblock_remove(0x18100000, 0x01000000); +} + +static const char *const rtd1195_dt_compat[] __initconst = { + "realtek,rtd1195", + NULL +}; + +DT_MACHINE_START(rtd1195, "Realtek RTD1195") + .dt_compat = rtd1195_dt_compat, + .reserve = rtd1195_reserve, + .l2c_aux_val = 0x0, + .l2c_aux_mask = ~0x0, +MACHINE_END From patchwork Sun Nov 17 07:21:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 179564 Delivered-To: patch@linaro.org Received: by 2002:a92:38d5:0:0:0:0:0 with SMTP id g82csp1380415ilf; Sat, 16 Nov 2019 23:21:34 -0800 (PST) X-Google-Smtp-Source: APXvYqxZH99s+V2hoEHonKrJT8F5GMJmp6lyWA+Zx1qMX/+tkFYk97HTPZbbG7IvbbKqvO3a4XH9 X-Received: by 2002:a17:906:e087:: with SMTP id gh7mr12048474ejb.278.1573975294241; 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[209.132.180.67]) by mx.google.com with ESMTP id q20si9182013eja.339.2019.11.16.23.21.34; Sat, 16 Nov 2019 23:21:34 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726157AbfKQHVX (ORCPT + 26 others); Sun, 17 Nov 2019 02:21:23 -0500 Received: from mx2.suse.de ([195.135.220.15]:40768 "EHLO mx1.suse.de" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1725959AbfKQHVW (ORCPT ); Sun, 17 Nov 2019 02:21:22 -0500 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (unknown [195.135.220.254]) by mx1.suse.de (Postfix) with ESMTP id 71337B23E; Sun, 17 Nov 2019 07:21:20 +0000 (UTC) From: =?utf-8?q?Andreas_F=C3=A4rber?= To: linux-realtek-soc@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, =?utf-8?q?Andreas_F=C3=A4rber?= , Rob Herring , Mark Rutland , devicetree@vger.kernel.org Subject: [PATCH v3 3/8] ARM: dts: Prepare Realtek RTD1195 and MeLE X1000 Date: Sun, 17 Nov 2019 08:21:04 +0100 Message-Id: <20191117072109.20402-4-afaerber@suse.de> X-Mailer: git-send-email 2.16.4 In-Reply-To: <20191117072109.20402-1-afaerber@suse.de> References: <20191117072109.20402-1-afaerber@suse.de> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add Device Trees for Realtek RTD1195 SoC and MeLE X1000 TV box. Reuse the existing RTD1295 watchdog compatible for now. Reviewed-by: Rob Herring [AF: Fixed r-bus size, fixed GIC CPU mask, updated memreserve] Signed-off-by: Andreas Färber --- v2 -> v3: * Fixed r-bus size in /soc ranges from 0x1000000 to 0x70000 (James) * Adjusted /memreserve/ to close gap from 0xa800 to 0xc000 for full 0x100000 * Changed arch timer from GIC_CPU_MASK_RAW(0xf) to GIC_CPU_MASK_SIMPLE(2) squashed from RTD1395 v1 series v1 -> v2: * Dropped /memreserve/ and reserved-memory nodes for peripherals and NOR (Rob) * Carved them out from memory reg instead (Rob) * Converted some /memreserve/s to reserved-memory nodes arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/rtd1195-mele-x1000.dts | 31 ++++++++ arch/arm/boot/dts/rtd1195.dtsi | 127 +++++++++++++++++++++++++++++++ 3 files changed, 160 insertions(+) create mode 100644 arch/arm/boot/dts/rtd1195-mele-x1000.dts create mode 100644 arch/arm/boot/dts/rtd1195.dtsi -- 2.16.4 diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 08011dc8c7a6..4853a13c8cf2 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -865,6 +865,8 @@ dtb-$(CONFIG_ARCH_QCOM) += \ dtb-$(CONFIG_ARCH_RDA) += \ rda8810pl-orangepi-2g-iot.dtb \ rda8810pl-orangepi-i96.dtb +dtb-$(CONFIG_ARCH_REALTEK) += \ + rtd1195-mele-x1000.dtb dtb-$(CONFIG_ARCH_REALVIEW) += \ arm-realview-pb1176.dtb \ arm-realview-pb11mp.dtb \ diff --git a/arch/arm/boot/dts/rtd1195-mele-x1000.dts b/arch/arm/boot/dts/rtd1195-mele-x1000.dts new file mode 100644 index 000000000000..834b430e6250 --- /dev/null +++ b/arch/arm/boot/dts/rtd1195-mele-x1000.dts @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +/* + * Copyright (c) 2017-2019 Andreas Färber + */ + +/dts-v1/; + +#include "rtd1195.dtsi" + +/ { + compatible = "mele,x1000", "realtek,rtd1195"; + model = "MeLE X1000"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x18000000>, + <0x19100000 0x26f00000>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/rtd1195.dtsi b/arch/arm/boot/dts/rtd1195.dtsi new file mode 100644 index 000000000000..4e3866fe8f6e --- /dev/null +++ b/arch/arm/boot/dts/rtd1195.dtsi @@ -0,0 +1,127 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +/* + * Copyright (c) 2017-2019 Andreas Färber + */ + +/memreserve/ 0x00000000 0x0000a800; /* boot code */ +/memreserve/ 0x0000a800 0x000f5800; +/memreserve/ 0x17fff000 0x00001000; + +#include + +/ { + compatible = "realtek,rtd1195"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x0>; + clock-frequency = <1000000000>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x1>; + clock-frequency = <1000000000>; + }; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + rpc_comm: rpc@b000 { + reg = <0x0000b000 0x1000>; + }; + + audio@1b00000 { + reg = <0x01b00000 0x400000>; + }; + + rpc_ringbuf: rpc@1ffe000 { + reg = <0x01ffe000 0x4000>; + }; + + secure@10000000 { + reg = <0x10000000 0x100000>; + no-map; + }; + }; + + arm-pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = , + ; + interrupt-affinity = <&cpu0>, <&cpu1>; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + clock-frequency = <27000000>; + }; + + osc27M: osc { + compatible = "fixed-clock"; + clock-frequency = <27000000>; + #clock-cells = <0>; + clock-output-names = "osc27M"; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x18000000 0x18000000 0x00070000>, + <0x18100000 0x18100000 0x01000000>, + <0x40000000 0x40000000 0xc0000000>; + + wdt: watchdog@18007680 { + compatible = "realtek,rtd1295-watchdog"; + reg = <0x18007680 0x100>; + clocks = <&osc27M>; + }; + + uart0: serial@18007800 { + compatible = "snps,dw-apb-uart"; + reg = <0x18007800 0x400>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <27000000>; + status = "disabled"; + }; + + uart1: serial@1801b200 { + compatible = "snps,dw-apb-uart"; + reg = <0x1801b200 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <27000000>; + status = "disabled"; + }; + + gic: interrupt-controller@ff011000 { + compatible = "arm,cortex-a7-gic"; + reg = <0xff011000 0x1000>, + <0xff012000 0x2000>; + interrupt-controller; + #interrupt-cells = <3>; + }; + }; +}; From patchwork Sun Nov 17 07:21:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 179569 Delivered-To: patch@linaro.org Received: by 2002:a92:38d5:0:0:0:0:0 with SMTP id g82csp1380608ilf; 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[209.132.180.67]) by mx.google.com with ESMTP id br3si9141770ejb.436.2019.11.16.23.21.48; Sat, 16 Nov 2019 23:21:48 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726316AbfKQHVo (ORCPT + 26 others); Sun, 17 Nov 2019 02:21:44 -0500 Received: from mx2.suse.de ([195.135.220.15]:40782 "EHLO mx1.suse.de" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726047AbfKQHVW (ORCPT ); Sun, 17 Nov 2019 02:21:22 -0500 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (unknown [195.135.220.254]) by mx1.suse.de (Postfix) with ESMTP id D5C95B25F; Sun, 17 Nov 2019 07:21:20 +0000 (UTC) From: =?utf-8?q?Andreas_F=C3=A4rber?= To: linux-realtek-soc@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, =?utf-8?q?Andreas_F=C3=A4rber?= , Rob Herring , Mark Rutland , devicetree@vger.kernel.org Subject: [PATCH v3 4/8] ARM: dts: rtd1195: Introduce r-bus Date: Sun, 17 Nov 2019 08:21:05 +0100 Message-Id: <20191117072109.20402-5-afaerber@suse.de> X-Mailer: git-send-email 2.16.4 In-Reply-To: <20191117072109.20402-1-afaerber@suse.de> References: <20191117072109.20402-1-afaerber@suse.de> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Model Realtek's register bus in DT. Signed-off-by: Andreas Färber --- v3: from RTD1395 v1 * Fixed r-bus size from 0x100000 to 0x70000 in reg and ranges (James) * Renamed bus node from r-bus to bus (Rob) arch/arm/boot/dts/rtd1195.dtsi | 52 ++++++++++++++++++++++++------------------ 1 file changed, 30 insertions(+), 22 deletions(-) -- 2.16.4 diff --git a/arch/arm/boot/dts/rtd1195.dtsi b/arch/arm/boot/dts/rtd1195.dtsi index 4e3866fe8f6e..f5174f828a28 100644 --- a/arch/arm/boot/dts/rtd1195.dtsi +++ b/arch/arm/boot/dts/rtd1195.dtsi @@ -92,28 +92,36 @@ <0x18100000 0x18100000 0x01000000>, <0x40000000 0x40000000 0xc0000000>; - wdt: watchdog@18007680 { - compatible = "realtek,rtd1295-watchdog"; - reg = <0x18007680 0x100>; - clocks = <&osc27M>; - }; - - uart0: serial@18007800 { - compatible = "snps,dw-apb-uart"; - reg = <0x18007800 0x400>; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <27000000>; - status = "disabled"; - }; - - uart1: serial@1801b200 { - compatible = "snps,dw-apb-uart"; - reg = <0x1801b200 0x100>; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <27000000>; - status = "disabled"; + rbus: bus@18000000 { + compatible = "simple-bus"; + reg = <0x18000000 0x70000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x18000000 0x70000>; + + wdt: watchdog@7680 { + compatible = "realtek,rtd1295-watchdog"; + reg = <0x7680 0x100>; + clocks = <&osc27M>; + }; + + uart0: serial@7800 { + compatible = "snps,dw-apb-uart"; + reg = <0x7800 0x400>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <27000000>; + status = "disabled"; + }; + + uart1: serial@1b200 { + compatible = "snps,dw-apb-uart"; + reg = <0x1b200 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <27000000>; + status = "disabled"; + }; }; gic: interrupt-controller@ff011000 { From patchwork Sun Nov 17 07:21:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 179567 Delivered-To: patch@linaro.org Received: by 2002:a92:38d5:0:0:0:0:0 with SMTP id g82csp1380448ilf; Sat, 16 Nov 2019 23:21:36 -0800 (PST) X-Google-Smtp-Source: APXvYqyuiCvm7DIBHClhsuE6mpLj0syjElUL7zDHwu66tqUybTI2CfLhSnLNKvJ6eUpfVnEKFtx2 X-Received: by 2002:a17:906:c57:: with SMTP id t23mr16079154ejf.240.1573975296307; Sat, 16 Nov 2019 23:21:36 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1573975296; cv=none; d=google.com; s=arc-20160816; b=CL4+RimVemQUSMTYaeWlqtDiso7er/sCtEnlhxQ09A/gKkBNAjGD9ZDkmdiBV/Elwb 2z2DNLIV8V7I/Yh37qypj57bS5WyPZOQr2c+ppFTofZ+TYWmwvRKWc3hQ5+Zr8RzrPPg LT2YrcRqWoc6u715djAxR9BqrdaiUUWIZPKVSrIzz57z87vdV1BU0ice5weartYH2zPl xAvkONc8vbL1I3GbocjNwGNgBjy8HL/OFLYIvxIkMNwtFQ40wKSNU1nEVX7w9WzOFXlw ogSzIPsJoJnaWsRx8qnV7H2anEm/CYKAGa+k0jxPi4NpIvyC4RYi/Xasx+k1XE8hapS7 t7Vw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=KU2C+bG1Ml8PB4zUJ4MneWG/dNVNqhcuPBGu8Tqa/Yc=; b=XHd+wI+eUHDLIHTZJAPGFDtkbFgmUl607bO219+R3dTNP4qS6fv1hc0Vvkt3rDL7SI RYWnWwIYzVN53ple/hFV9vaD4tGs9ryfQ9lpv0KpFyxkC+QTsABaHsGkvH1d8J0sLqyb msCeeBQ+uFJJKmqIKizsxmXQFhnRoWvkh0jU3oOIsL/zq+T1J6ISfmbA7Xlf6wo+3d47 X5hKwxI4ncuQxEIsOkRRfXfSiJePc5AUxVZCq/g/fd06n/21U5u9AitatoaKREtYt7UV 3snZ/s3+YLIjZrLxdKWD8adAB/h2lgZJAzCZLd464+6szaDgu/GTdrHwDDP+w8tepOV7 iKsA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id q20si9182013eja.339.2019.11.16.23.21.36; Sat, 16 Nov 2019 23:21:36 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726257AbfKQHVb (ORCPT + 26 others); Sun, 17 Nov 2019 02:21:31 -0500 Received: from mx2.suse.de ([195.135.220.15]:40812 "EHLO mx1.suse.de" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1725909AbfKQHVX (ORCPT ); Sun, 17 Nov 2019 02:21:23 -0500 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (unknown [195.135.220.254]) by mx1.suse.de (Postfix) with ESMTP id 41726B315; Sun, 17 Nov 2019 07:21:22 +0000 (UTC) From: =?utf-8?q?Andreas_F=C3=A4rber?= To: linux-realtek-soc@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, =?utf-8?q?Andreas_F=C3=A4rber?= , Rob Herring , Mark Rutland , devicetree@vger.kernel.org Subject: [PATCH v3 7/8] ARM: dts: rtd1195: Add UART resets Date: Sun, 17 Nov 2019 08:21:08 +0100 Message-Id: <20191117072109.20402-8-afaerber@suse.de> X-Mailer: git-send-email 2.16.4 In-Reply-To: <20191117072109.20402-1-afaerber@suse.de> References: <20191117072109.20402-1-afaerber@suse.de> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Associate the UART nodes with the corresponding reset controller bits. Signed-off-by: Andreas Färber --- v3: from RTD1295 reset v2 * Rebased onto r-bus arch/arm/boot/dts/rtd1195.dtsi | 3 +++ 1 file changed, 3 insertions(+) -- 2.16.4 diff --git a/arch/arm/boot/dts/rtd1195.dtsi b/arch/arm/boot/dts/rtd1195.dtsi index e0f133a1354f..4eec45244132 100644 --- a/arch/arm/boot/dts/rtd1195.dtsi +++ b/arch/arm/boot/dts/rtd1195.dtsi @@ -8,6 +8,7 @@ /memreserve/ 0x17fff000 0x00001000; #include +#include / { compatible = "realtek,rtd1195"; @@ -134,6 +135,7 @@ reg = <0x7800 0x400>; reg-shift = <2>; reg-io-width = <4>; + resets = <&iso_reset RTD1195_ISO_RSTN_UR0>; clock-frequency = <27000000>; status = "disabled"; }; @@ -143,6 +145,7 @@ reg = <0x1b200 0x100>; reg-shift = <2>; reg-io-width = <4>; + resets = <&reset2 RTD1195_RSTN_UR1>; clock-frequency = <27000000>; status = "disabled"; }; From patchwork Sun Nov 17 07:21:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 179566 Delivered-To: patch@linaro.org Received: by 2002:a92:38d5:0:0:0:0:0 with SMTP id g82csp1380432ilf; Sat, 16 Nov 2019 23:21:35 -0800 (PST) X-Google-Smtp-Source: APXvYqy8rjQ1GBYjDe7ON+juyUNkjjIPFQZEnlrFHkGJZAxrfHGbeiHJoITkZpufC5atIfUg2biE X-Received: by 2002:a17:906:1342:: with SMTP id x2mr16158121ejb.304.1573975295484; Sat, 16 Nov 2019 23:21:35 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1573975295; cv=none; d=google.com; s=arc-20160816; b=I2l2ao6JFNXkBMF/Fj6mdSUJIJKYxj/KxjhxTSjw+6lB5L58srZ5/ITrsgHDdDratd LFVFK3zxnGq2Nbj6vV1XDjctiO2a0kTXy3c3MpeIArZ2vTwhhptxbMS6F9nr1h/bS/xg r5l8qQUZBFbzplEi2pP1Lx11+HCVF6usV+Kyb8wsZEctadQnUk6P+kWSPeYZO5hvuAvj 8vsYRHjQTtiQt+XoIyARAA7tQ5QelIlxUTdMtbnGahLPv6502a0i1UJmbFmwmfENBCqg /EBVkamXv5I31B9vL42ti0tgpnOZKgGIQNT7wNlPLwaqFnG2SLP+DlQEg3++BBwkMDSx kxRQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=HjqRwP8ArD57XZgZHFi7uv9wq/Vh7HoVCAtLDhEKBao=; b=e2I4raIZSqioI9Gp/iM7VDp/Ar4Tmd+SPJNJM+uOrDq16ju69U42m34OenTufO3vOn UgdkKsllf8IjkjQYKDIbNdEUfQnt40sOaWCCjzJ2nfYAzN3WZPm93sFmv8knNJNMmRdN C0xF65OopPpzWDJGb8LywyomU9BnRJPvMoQysTHto6JklVx45i47MC0S63+C9rdJKgQr 5Y5NhhbIlqcHmcqgtwmEr6LQTx/Da52pwzBNNDoI6tXyWGS0mlNPSFwknNvuQBjGmAW+ qvStRk1JM8OpRg1ZjxMiiePFUgodnnp3dzriw0Ox6SILtwoqdw6LLmSUHp5T3rTpWoyL mlfg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id q20si9182013eja.339.2019.11.16.23.21.35; Sat, 16 Nov 2019 23:21:35 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726234AbfKQHV0 (ORCPT + 26 others); Sun, 17 Nov 2019 02:21:26 -0500 Received: from mx2.suse.de ([195.135.220.15]:40824 "EHLO mx1.suse.de" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726134AbfKQHVY (ORCPT ); Sun, 17 Nov 2019 02:21:24 -0500 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (unknown [195.135.220.254]) by mx1.suse.de (Postfix) with ESMTP id 9E238B317; Sun, 17 Nov 2019 07:21:22 +0000 (UTC) From: =?utf-8?q?Andreas_F=C3=A4rber?= To: linux-realtek-soc@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, =?utf-8?q?Andreas_F=C3=A4rber?= , Russell King Subject: [PATCH v3 8/8] ARM: realtek: Enable RTD1195 arch timer Date: Sun, 17 Nov 2019 08:21:09 +0100 Message-Id: <20191117072109.20402-9-afaerber@suse.de> X-Mailer: git-send-email 2.16.4 In-Reply-To: <20191117072109.20402-1-afaerber@suse.de> References: <20191117072109.20402-1-afaerber@suse.de> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Without this magic write the timer doesn't work and boot gets stuck. Signed-off-by: Andreas Färber --- What is the name of the register 0xff018000? Is 0x1 a BIT(0) write, or how are the register bits defined? Is this a reset or a clock gate? How should we model it in DT? v2 -> v3: Unchanged v2: New arch/arm/mach-realtek/rtd1195.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) -- 2.16.4 diff --git a/arch/arm/mach-realtek/rtd1195.c b/arch/arm/mach-realtek/rtd1195.c index b31a4066be87..0532379c74f5 100644 --- a/arch/arm/mach-realtek/rtd1195.c +++ b/arch/arm/mach-realtek/rtd1195.c @@ -5,6 +5,9 @@ * Copyright (c) 2017-2019 Andreas Färber */ +#include +#include +#include #include #include @@ -24,6 +27,18 @@ static void __init rtd1195_reserve(void) rtd1195_memblock_remove(0x18100000, 0x01000000); } +static void __init rtd1195_init_time(void) +{ + void __iomem *base; + + base = ioremap(0xff018000, 4); + writel(0x1, base); + iounmap(base); + + of_clk_init(NULL); + timer_probe(); +} + static const char *const rtd1195_dt_compat[] __initconst = { "realtek,rtd1195", NULL @@ -31,6 +46,7 @@ static const char *const rtd1195_dt_compat[] __initconst = { DT_MACHINE_START(rtd1195, "Realtek RTD1195") .dt_compat = rtd1195_dt_compat, + .init_time = rtd1195_init_time, .reserve = rtd1195_reserve, .l2c_aux_val = 0x0, .l2c_aux_mask = ~0x0,