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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42bb6e355dfsm232251365e9.46.2024.09.05.06.01.03 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Sep 2024 06:01:03 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/25] target/arm: Allow setting the FPCR.EBF bit for FEAT_EBF16 Date: Thu, 5 Sep 2024 14:00:36 +0100 Message-Id: <20240905130100.298768-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240905130100.298768-1-peter.maydell@linaro.org> References: <20240905130100.298768-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org FEAT_EBF16 adds one new bit to the FPCR floating point control register. Allow this bit to be read and written when the ID registers indicate the presence of the feature. Note that because this new bit is not in FPSCR_FPCR_MASK the bit is not visible in the AArch32 FPSCR, and FPSCR writes do not affect it. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu-features.h | 5 +++++ target/arm/cpu.h | 1 + target/arm/vfp_helper.c | 8 ++++++-- 3 files changed, 12 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index c59ca104fe1..cfb82c23cad 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -556,6 +556,11 @@ static inline bool isar_feature_aa64_bf16(const ARMISARegisters *id) return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, BF16) != 0; } +static inline bool isar_feature_aa64_ebf16(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, BF16) > 1; +} + static inline bool isar_feature_aa64_rcpc_8_3(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) != 0; diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 9a3fd595621..f065756c5c7 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1707,6 +1707,7 @@ void vfp_set_fpscr(CPUARMState *env, uint32_t val); #define FPCR_OFE (1 << 10) /* Overflow exception trap enable */ #define FPCR_UFE (1 << 11) /* Underflow exception trap enable */ #define FPCR_IXE (1 << 12) /* Inexact exception trap enable */ +#define FPCR_EBF (1 << 13) /* Extended BFloat16 behaviors */ #define FPCR_IDE (1 << 15) /* Input Denormal exception trap enable */ #define FPCR_LEN_MASK (7 << 16) /* LEN, A-profile only */ #define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */ diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c index b3698da8ca7..203d37303bd 100644 --- a/target/arm/vfp_helper.c +++ b/target/arm/vfp_helper.c @@ -254,6 +254,10 @@ static void vfp_set_fpcr_masked(CPUARMState *env, uint32_t val, uint32_t mask) val &= ~FPCR_FZ16; } + if (!cpu_isar_feature(aa64_ebf16, cpu)) { + val &= ~FPCR_EBF; + } + vfp_set_fpcr_to_host(env, val, mask); if (mask & (FPCR_LEN_MASK | FPCR_STRIDE_MASK)) { @@ -278,12 +282,12 @@ static void vfp_set_fpcr_masked(CPUARMState *env, uint32_t val, uint32_t mask) * We don't implement trapped exception handling, so the * trap enable bits, IDE|IXE|UFE|OFE|DZE|IOE are all RAZ/WI (not RES0!) * - * The FPCR bits we keep in vfp.fpcr are AHP, DN, FZ, RMode + * The FPCR bits we keep in vfp.fpcr are AHP, DN, FZ, RMode, EBF * and FZ16. Len, Stride and LTPSIZE we just handled. Store those bits * there, and zero any of the other FPCR bits and the RES0 and RAZ/WI * bits. */ - val &= FPCR_AHP | FPCR_DN | FPCR_FZ | FPCR_RMODE_MASK | FPCR_FZ16; + val &= FPCR_AHP | FPCR_DN | FPCR_FZ | FPCR_RMODE_MASK | FPCR_FZ16 | FPCR_EBF; env->vfp.fpcr &= ~mask; env->vfp.fpcr |= val; } From patchwork Thu Sep 5 13:00:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 825654 Delivered-To: patch@linaro.org Received: by 2002:adf:a345:0:b0:367:895a:4699 with SMTP id d5csp288410wrb; Thu, 5 Sep 2024 06:05:56 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXXfl8Zux1/y4JyioE/1k02o73q0Mm9GnURrRdSTcPPW/YGfwIYYX+9y6MsASXQkadxysCRuQ==@linaro.org X-Google-Smtp-Source: AGHT+IEn7mf4gT5HCgclqxojbVt1JMPR0Umnc1+3JO+RigPsM/AlTuYOfeQ+0LcL5/TUl0SmZfOd X-Received: by 2002:a05:6102:3ec8:b0:498:d495:2cd7 with SMTP id ada2fe7eead31-49a779b5f33mr17290001137.14.1725541556203; Thu, 05 Sep 2024 06:05:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1725541556; cv=none; d=google.com; s=arc-20160816; b=i7sDB8efhbfctHnR8dcaonOYMpVo6o3wJoKJOsuQII6iBOnioE4R16Kn2b4xCBOv59 QNvzF3oS9KhK51COOqjSkfvW6Gybgh9s5Y38+OZvwYN3w0mfqwDU0Fj29XQBkDhSHWYm OhHj65BC55j9W70orAUkZ1WYBz+0G+tPCe+ddAcCkJZXR7JXmQndVq3jtZ5OzF+nuCti ozm737SfeITgdhD+HWqB5Dv+WRcNDBPoGnnUdGvmriKgk9Nqk+SEaXqhaJSOaorSqXlg GscRkXvUNPkFflkqyLhxUoEC7+eEFtagcLvmJNSQdPOY3clidWFh+4u+uvLR5Ff/aonO LPeg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=2ZZJRnDQpXVmhxlb1bFCeHBKJRVNNn9/NPG2id8LS9Y=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=Zv7y5qTZb9H2fMTysq/MeaC7hOQrWrtAbW/T2h4BhAGdfsVP1Bc4bmAd92BNqZwNQv q7ICBhDZYuYpTaqtYY675MMs8o0fOJeWWbN7ij1Dcy9+5nT3fuaP8vf7dkiPcLkhv5S8 bdb3JVwqp/EAsPzM2KmDEx11SFOD/cwX0uQ/MXHoaEhXXG5/NhJ64Yg2oNE9+VXNze49 LHi9f/cOG0hF1WafUvl7DE5T96JTtJ5ZpYLnTnQIOYcYEOOKgtITBF8AK+l+MkrxKoow o1hFjOW8l2CTnWKytXNLfJsTaw/islJJ1THkFFUNnEzSR/aBKqhrEXuNbkF79+W+OZN6 UonA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=qfLd2VjI; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42bb6e355dfsm232251365e9.46.2024.09.05.06.01.04 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Sep 2024 06:01:04 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 02/25] target/arm: Pass env pointer through to sme_bfmopa helper Date: Thu, 5 Sep 2024 14:00:37 +0100 Message-Id: <20240905130100.298768-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240905130100.298768-1-peter.maydell@linaro.org> References: <20240905130100.298768-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org To implement the FEAT_EBF16 semantics, we are going to need the CPUARMState env pointer in every helper function which calls bfdotadd(). Pass the env pointer through from generated code to the sme_bfmopa helper. (We'll add the code that uses it when we've adjusted all the helpers to have access to the env pointer.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/tcg/helper-sme.h | 4 ++-- target/arm/tcg/sme_helper.c | 4 ++-- target/arm/tcg/translate-sme.c | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/target/arm/tcg/helper-sme.h b/target/arm/tcg/helper-sme.h index d22bf9d21b0..59ecaa15485 100644 --- a/target/arm/tcg/helper-sme.h +++ b/target/arm/tcg/helper-sme.h @@ -126,8 +126,8 @@ DEF_HELPER_FLAGS_7(sme_fmopa_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_7(sme_fmopa_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_6(sme_bfmopa, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_7(sme_bfmopa, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_FLAGS_6(sme_smopa_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_6(sme_umopa_s, TCG_CALL_NO_RWG, diff --git a/target/arm/tcg/sme_helper.c b/target/arm/tcg/sme_helper.c index 02106809ce1..289ffabbfbe 100644 --- a/target/arm/tcg/sme_helper.c +++ b/target/arm/tcg/sme_helper.c @@ -1079,8 +1079,8 @@ void HELPER(sme_fmopa_h)(void *vza, void *vzn, void *vzm, void *vpn, } } -void HELPER(sme_bfmopa)(void *vza, void *vzn, void *vzm, void *vpn, - void *vpm, uint32_t desc) +void HELPER(sme_bfmopa)(void *vza, void *vzn, void *vzm, + void *vpn, void *vpm, CPUARMState *env, uint32_t desc) { intptr_t row, col, oprsz = simd_maxsz(desc); uint32_t neg = simd_data(desc) * 0x80008000u; diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c index ae42ddef7b3..3ceb32e8bd9 100644 --- a/target/arm/tcg/translate-sme.c +++ b/target/arm/tcg/translate-sme.c @@ -363,7 +363,7 @@ TRANS_FEAT(FMOPA_d, aa64_sme_f64f64, do_outprod_fpst, a, MO_64, FPST_FPCR, gen_helper_sme_fmopa_d) /* TODO: FEAT_EBF16 */ -TRANS_FEAT(BFMOPA, aa64_sme, do_outprod, a, MO_32, gen_helper_sme_bfmopa) +TRANS_FEAT(BFMOPA, aa64_sme, do_outprod_env, a, MO_32, gen_helper_sme_bfmopa) TRANS_FEAT(SMOPA_s, aa64_sme, do_outprod, a, MO_32, gen_helper_sme_smopa_s) TRANS_FEAT(UMOPA_s, aa64_sme, do_outprod, a, MO_32, gen_helper_sme_umopa_s) From patchwork Thu Sep 5 13:00:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 825638 Delivered-To: patch@linaro.org Received: by 2002:adf:a345:0:b0:367:895a:4699 with SMTP id d5csp286362wrb; Thu, 5 Sep 2024 06:03:07 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVBZeX6qU34/sSRvi1arH4DsDIZEsgBSHWtZcJKff46Mx2dOG+W+zRoLVuo/7dO0ax6FmU2rQ==@linaro.org X-Google-Smtp-Source: AGHT+IExxXz3vFXCQLuxLEtV0C6XKO1v2s0Bk9gaUwXe8HzhjkMQ6aoasaKDRqBzUYf0XCfjDrQ5 X-Received: by 2002:a05:690c:6289:b0:6d6:94b2:f3cb with SMTP id 00721157ae682-6d694c2368emr171357687b3.36.1725541387501; Thu, 05 Sep 2024 06:03:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1725541387; cv=none; d=google.com; s=arc-20160816; b=hT1/7ui9ozE/DDuZa68MEYLveD2zTQSSSfZg084SzSv3qUK5Fwnoxt61+rJEVJhGJq 0cWcJOYkuD8hsny72J7RSzyKD1zvLscxL3MRAVRjr2V3UTJr3sCwMGngdtRgOrfU+wxX o4pf62fZRv7oW2v7ir+2TnRtCj+hEK84mEdR94/ihodLHDZ7BUP8nolFnpXjJbIX0dAR gZ8tM5mIwWl8S/j4apVwCdGhFdtykYTcHew0yHG7sTswDTAnXMciH/fptHoiTKTD4yz4 +g1lhecFL8jqtX7tq8c9KyDb6+G01WDtEKtoJf7nsGXqgyJN4wdnX1q5PnxISGlf+JSy vVhg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=h0CxkySph+MQbg69T6EA+5mDqJ97s/mpfxkBm+Lr8aM=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=zcuMc7TWg7ntE91n5J9rwt+SIC439vTQdP2wL19GAHOfZUwtOL/CKuyM4MYTe5sT+7 7DTE4leLa0Qrethuu8loXWeyijlOgJmCesPVUnhFNwK9YYvkLpDc4MhNBuoz0MSv6LdR WtChhKHVO7rrN+/vlNSDlSCSzQPoBr9gbDSdDLtKNgLSsLfEOCKIK5TLbFm36Kowf+Yl 5TErVdbLDwZAWgKuhctPKzFhBgImQRoc9VHuyOJq0rgycAsB+yA1nwy5GIDB3FWDcAcB /PhDECGjw1kJv7+0DzFjsZ8oXfgerwt1cRH7KWWd9Ztij/I9qyEF1IEeq1U5VnP5looH 5HXg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=sNQ09Rao; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42bb6e355dfsm232251365e9.46.2024.09.05.06.01.04 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Sep 2024 06:01:04 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 03/25] target/arm: Pass env pointer through to gvec_bfdot helper Date: Thu, 5 Sep 2024 14:00:38 +0100 Message-Id: <20240905130100.298768-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240905130100.298768-1-peter.maydell@linaro.org> References: <20240905130100.298768-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Pass the env pointer through to the gvec_bfdot helper, so we can use it to add support for FEAT_EBF16. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper.h | 4 ++-- target/arm/tcg/translate-a64.c | 27 ++++++++++++++++++++++++- target/arm/tcg/translate-neon.c | 35 +++++++++++++++++++++++++++++++-- target/arm/tcg/translate-sve.c | 15 +++++++++++++- target/arm/tcg/vec_helper.c | 3 ++- 5 files changed, 77 insertions(+), 7 deletions(-) diff --git a/target/arm/helper.h b/target/arm/helper.h index 970d059dec5..4466e796cb0 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -1027,8 +1027,8 @@ DEF_HELPER_FLAGS_5(gvec_ummla_b, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(gvec_usmmla_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_bfdot, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_6(gvec_bfdot, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_FLAGS_5(gvec_bfdot_idx, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 4684e7eb6ea..3813c75895b 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -735,6 +735,22 @@ static void gen_gvec_op4_ool(DisasContext *s, bool is_q, int rd, int rn, is_q ? 16 : 8, vec_full_reg_size(s), data, fn); } +/* + * Expand a 4-operand operation using an out-of-line helper that takes + * a pointer to the CPU env. + */ +static void gen_gvec_op4_env(DisasContext *s, bool is_q, int rd, int rn, + int rm, int ra, int data, + gen_helper_gvec_4_ptr *fn) +{ + tcg_gen_gvec_4_ptr(vec_full_reg_offset(s, rd), + vec_full_reg_offset(s, rn), + vec_full_reg_offset(s, rm), + vec_full_reg_offset(s, ra), + tcg_env, + is_q ? 16 : 8, vec_full_reg_size(s), data, fn); +} + /* * Expand a 4-operand + fpstatus pointer + simd data value operation using * an out-of-line helper. @@ -5608,10 +5624,19 @@ static bool do_dot_vector(DisasContext *s, arg_qrrr_e *a, return true; } +static bool do_dot_vector_env(DisasContext *s, arg_qrrr_e *a, + gen_helper_gvec_4_ptr *fn) +{ + if (fp_access_check(s)) { + gen_gvec_op4_env(s, a->q, a->rd, a->rn, a->rm, a->rd, 0, fn); + } + return true; +} + TRANS_FEAT(SDOT_v, aa64_dp, do_dot_vector, a, gen_helper_gvec_sdot_b) TRANS_FEAT(UDOT_v, aa64_dp, do_dot_vector, a, gen_helper_gvec_udot_b) TRANS_FEAT(USDOT_v, aa64_i8mm, do_dot_vector, a, gen_helper_gvec_usdot_b) -TRANS_FEAT(BFDOT_v, aa64_bf16, do_dot_vector, a, gen_helper_gvec_bfdot) +TRANS_FEAT(BFDOT_v, aa64_bf16, do_dot_vector_env, a, gen_helper_gvec_bfdot) TRANS_FEAT(BFMMLA, aa64_bf16, do_dot_vector, a, gen_helper_gvec_bfmmla) TRANS_FEAT(SMMLA, aa64_i8mm, do_dot_vector, a, gen_helper_gvec_smmla_b) TRANS_FEAT(UMMLA, aa64_i8mm, do_dot_vector, a, gen_helper_gvec_ummla_b) diff --git a/target/arm/tcg/translate-neon.c b/target/arm/tcg/translate-neon.c index 915c9e56db5..454380f01d7 100644 --- a/target/arm/tcg/translate-neon.c +++ b/target/arm/tcg/translate-neon.c @@ -148,6 +148,37 @@ static bool do_neon_ddda(DisasContext *s, int q, int vd, int vn, int vm, return true; } +static bool do_neon_ddda_env(DisasContext *s, int q, int vd, int vn, int vm, + int data, gen_helper_gvec_4_ptr *fn_gvec) +{ + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (((vd | vn | vm) & 0x10) && !dc_isar_feature(aa32_simd_r32, s)) { + return false; + } + + /* + * UNDEF accesses to odd registers for each bit of Q. + * Q will be 0b111 for all Q-reg instructions, otherwise + * when we have mixed Q- and D-reg inputs. + */ + if (((vd & 1) * 4 | (vn & 1) * 2 | (vm & 1)) & q) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + int opr_sz = q ? 16 : 8; + tcg_gen_gvec_4_ptr(vfp_reg_offset(1, vd), + vfp_reg_offset(1, vn), + vfp_reg_offset(1, vm), + vfp_reg_offset(1, vd), + tcg_env, + opr_sz, opr_sz, data, fn_gvec); + return true; +} + static bool do_neon_ddda_fpst(DisasContext *s, int q, int vd, int vn, int vm, int data, ARMFPStatusFlavour fp_flavour, gen_helper_gvec_4_ptr *fn_gvec_ptr) @@ -266,8 +297,8 @@ static bool trans_VDOT_b16(DisasContext *s, arg_VDOT_b16 *a) if (!dc_isar_feature(aa32_bf16, s)) { return false; } - return do_neon_ddda(s, a->q * 7, a->vd, a->vn, a->vm, 0, - gen_helper_gvec_bfdot); + return do_neon_ddda_env(s, a->q * 7, a->vd, a->vn, a->vm, 0, + gen_helper_gvec_bfdot); } static bool trans_VFML(DisasContext *s, arg_VFML *a) diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index a72c2620960..e1dd6617e8b 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -252,6 +252,19 @@ static bool gen_gvec_fpst_zzzz(DisasContext *s, gen_helper_gvec_4_ptr *fn, return ret; } +static bool gen_gvec_env_zzzz(DisasContext *s, gen_helper_gvec_4_ptr *fn, + int rd, int rn, int rm, int ra, + int data) +{ + return gen_gvec_ptr_zzzz(s, fn, rd, rn, rm, ra, data, tcg_env); +} + +static bool gen_gvec_env_arg_zzzz(DisasContext *s, gen_helper_gvec_4_ptr *fn, + arg_rrrr_esz *a, int data) +{ + return gen_gvec_env_zzzz(s, fn, a->rd, a->rn, a->rm, a->ra, data); +} + /* Invoke an out-of-line helper on 4 Zregs, 1 Preg, plus fpst. */ static bool gen_gvec_fpst_zzzzp(DisasContext *s, gen_helper_gvec_5_ptr *fn, int rd, int rn, int rm, int ra, int pg, @@ -7113,7 +7126,7 @@ TRANS_FEAT_NONSTREAMING(USMMLA, aa64_sve_i8mm, gen_gvec_ool_arg_zzzz, TRANS_FEAT_NONSTREAMING(UMMLA, aa64_sve_i8mm, gen_gvec_ool_arg_zzzz, gen_helper_gvec_ummla_b, a, 0) -TRANS_FEAT(BFDOT_zzzz, aa64_sve_bf16, gen_gvec_ool_arg_zzzz, +TRANS_FEAT(BFDOT_zzzz, aa64_sve_bf16, gen_gvec_env_arg_zzzz, gen_helper_gvec_bfdot, a, 0) TRANS_FEAT(BFDOT_zzxz, aa64_sve_bf16, gen_gvec_ool_arg_zzxz, gen_helper_gvec_bfdot_idx, a) diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c index 98604d170fd..01b36fdd786 100644 --- a/target/arm/tcg/vec_helper.c +++ b/target/arm/tcg/vec_helper.c @@ -2814,7 +2814,8 @@ float32 bfdotadd(float32 sum, uint32_t e1, uint32_t e2) return t1; } -void HELPER(gvec_bfdot)(void *vd, void *vn, void *vm, void *va, uint32_t desc) +void HELPER(gvec_bfdot)(void *vd, void *vn, void *vm, void *va, + CPUARMState *env, uint32_t desc) { intptr_t i, opr_sz = simd_oprsz(desc); float32 *d = vd, *a = va; From patchwork Thu Sep 5 13:00:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 825634 Delivered-To: patch@linaro.org Received: by 2002:adf:a345:0:b0:367:895a:4699 with SMTP id d5csp285943wrb; Thu, 5 Sep 2024 06:02:30 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVPDHawSdq3Af/G4bbuNUqQmZ2CQaZWDW6nRg1fUK8kw4//U/UV+0Rjbhaqlf2/iBdlQ7KmnQ==@linaro.org X-Google-Smtp-Source: AGHT+IEzHpkKm03qBLR1yT/0vCZRVavuyVJJQr+DJK4iUT6kAehGw3PamLhTwMxzYnQobRiT+A5r X-Received: by 2002:a05:6808:14d1:b0:3db:2cf3:36e with SMTP id 5614622812f47-3e00cb979ccmr11136139b6e.28.1725541350673; Thu, 05 Sep 2024 06:02:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1725541350; cv=none; d=google.com; s=arc-20160816; b=oH41zbt4wLkbD1pWFGYD55FDef3b+nKoZ/DX2amJJ/v78BYUsCRI7P6Ue9Xqe/doHn IW7pUWwTXFTWw2nGOFDA7+7Rq2XRbLZibQgCDff+h8XfW4dmuDHDbYU7kJ9mDxjGMg6K KpHsCrfw7GktoRJ+QJo3qfJqvT5UzidZ1I1x7ttUJgMYCcVAXzGGANBAzy5qWI7KVWSM MuzFp1TcwyHFOtgpZUqog+9Qk/ytTbi/6y308ExqNVC8ricw02ie+anFzcpCQyMTeAt7 JmkAiK0lx+19O5hAGQbTDW+EWC0SaST2RzWWsLqArnoTyvCb2fi8N/DwFzo3jSmmGTwp 2F4w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=UEvZ92Ysmoac5/8gCPMIYUSdZILiX6VcaOGkdAF88AA=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=Vyy1mB/fNBwWw8KLrCHZ8v7eANkEGL+bxPNuhZxTG+d0ex5jTcJK17yt7uY3AmsmhM al/JjKIm+QL4RTFEjoVjsl5pd0H5YSRg0CARefQXmsTBiIDlGZ/knWFKvLAeEANWdKNl t7K8hypeOkKOCsXLbKNRG4t3AQXNqLf/eBsrvEdqOL+cA1HNsaLR3AT+SHa+3WyD7Ewy ILdq30D50uYY4ldOOmtS+zFKUz71x+rMKS4trkuCK4ibpNMjd6aMt0WGuhlEhqcV33Ks YQM5bfbNacAxWQHEwE/B/3d0roxu+Fb2X4goj3j8M/GkhVf0TIQRWN2IDcxt84EDQ0kJ 5O/A==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PNbvC6MD; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42bb6e355dfsm232251365e9.46.2024.09.05.06.01.05 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Sep 2024 06:01:05 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 04/25] target/arm: Pass env pointer through to gvec_bfdot_idx helper Date: Thu, 5 Sep 2024 14:00:39 +0100 Message-Id: <20240905130100.298768-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240905130100.298768-1-peter.maydell@linaro.org> References: <20240905130100.298768-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Pass the env pointer through to the gvec_bfdot_idx helper, so we can use it to add support for FEAT_EBF16. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper.h | 4 ++-- target/arm/tcg/translate-a64.c | 11 ++++++++++- target/arm/tcg/translate-neon.c | 4 ++-- target/arm/tcg/translate-sve.c | 8 +++++++- target/arm/tcg/vec_helper.c | 2 +- 5 files changed, 22 insertions(+), 7 deletions(-) diff --git a/target/arm/helper.h b/target/arm/helper.h index 4466e796cb0..e197b5b1d2c 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -1029,8 +1029,8 @@ DEF_HELPER_FLAGS_5(gvec_usmmla_b, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(gvec_bfdot, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_FLAGS_5(gvec_bfdot_idx, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_6(gvec_bfdot_idx, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_FLAGS_5(gvec_bfmmla, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 3813c75895b..c7876513c72 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -6410,13 +6410,22 @@ static bool do_dot_vector_idx(DisasContext *s, arg_qrrx_e *a, return true; } +static bool do_dot_vector_idx_env(DisasContext *s, arg_qrrx_e *a, + gen_helper_gvec_4_ptr *fn) +{ + if (fp_access_check(s)) { + gen_gvec_op4_env(s, a->q, a->rd, a->rn, a->rm, a->rd, a->idx, fn); + } + return true; +} + TRANS_FEAT(SDOT_vi, aa64_dp, do_dot_vector_idx, a, gen_helper_gvec_sdot_idx_b) TRANS_FEAT(UDOT_vi, aa64_dp, do_dot_vector_idx, a, gen_helper_gvec_udot_idx_b) TRANS_FEAT(SUDOT_vi, aa64_i8mm, do_dot_vector_idx, a, gen_helper_gvec_sudot_idx_b) TRANS_FEAT(USDOT_vi, aa64_i8mm, do_dot_vector_idx, a, gen_helper_gvec_usdot_idx_b) -TRANS_FEAT(BFDOT_vi, aa64_bf16, do_dot_vector_idx, a, +TRANS_FEAT(BFDOT_vi, aa64_bf16, do_dot_vector_idx_env, a, gen_helper_gvec_bfdot_idx) static bool trans_BFMLAL_vi(DisasContext *s, arg_qrrx_e *a) diff --git a/target/arm/tcg/translate-neon.c b/target/arm/tcg/translate-neon.c index 454380f01d7..7de157c539c 100644 --- a/target/arm/tcg/translate-neon.c +++ b/target/arm/tcg/translate-neon.c @@ -391,8 +391,8 @@ static bool trans_VDOT_b16_scal(DisasContext *s, arg_VDOT_b16_scal *a) if (!dc_isar_feature(aa32_bf16, s)) { return false; } - return do_neon_ddda(s, a->q * 6, a->vd, a->vn, a->vm, a->index, - gen_helper_gvec_bfdot_idx); + return do_neon_ddda_env(s, a->q * 6, a->vd, a->vn, a->vm, a->index, + gen_helper_gvec_bfdot_idx); } static bool trans_VFML_scalar(DisasContext *s, arg_VFML_scalar *a) diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index e1dd6617e8b..eb77c943c8f 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -265,6 +265,12 @@ static bool gen_gvec_env_arg_zzzz(DisasContext *s, gen_helper_gvec_4_ptr *fn, return gen_gvec_env_zzzz(s, fn, a->rd, a->rn, a->rm, a->ra, data); } +static bool gen_gvec_env_arg_zzxz(DisasContext *s, gen_helper_gvec_4_ptr *fn, + arg_rrxr_esz *a) +{ + return gen_gvec_env_zzzz(s, fn, a->rd, a->rn, a->rm, a->ra, a->index); +} + /* Invoke an out-of-line helper on 4 Zregs, 1 Preg, plus fpst. */ static bool gen_gvec_fpst_zzzzp(DisasContext *s, gen_helper_gvec_5_ptr *fn, int rd, int rn, int rm, int ra, int pg, @@ -7128,7 +7134,7 @@ TRANS_FEAT_NONSTREAMING(UMMLA, aa64_sve_i8mm, gen_gvec_ool_arg_zzzz, TRANS_FEAT(BFDOT_zzzz, aa64_sve_bf16, gen_gvec_env_arg_zzzz, gen_helper_gvec_bfdot, a, 0) -TRANS_FEAT(BFDOT_zzxz, aa64_sve_bf16, gen_gvec_ool_arg_zzxz, +TRANS_FEAT(BFDOT_zzxz, aa64_sve_bf16, gen_gvec_env_arg_zzxz, gen_helper_gvec_bfdot_idx, a) TRANS_FEAT_NONSTREAMING(BFMMLA, aa64_sve_bf16, gen_gvec_ool_arg_zzzz, diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c index 01b36fdd786..a2c62a86d84 100644 --- a/target/arm/tcg/vec_helper.c +++ b/target/arm/tcg/vec_helper.c @@ -2828,7 +2828,7 @@ void HELPER(gvec_bfdot)(void *vd, void *vn, void *vm, void *va, } void HELPER(gvec_bfdot_idx)(void *vd, void *vn, void *vm, - void *va, uint32_t desc) + void *va, CPUARMState *env, uint32_t desc) { intptr_t i, j, opr_sz = simd_oprsz(desc); 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42bb6e355dfsm232251365e9.46.2024.09.05.06.01.06 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Sep 2024 06:01:06 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 05/25] target/arm: Pass env pointer through to gvec_bfmmla helper Date: Thu, 5 Sep 2024 14:00:40 +0100 Message-Id: <20240905130100.298768-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240905130100.298768-1-peter.maydell@linaro.org> References: <20240905130100.298768-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Pass the env pointer through to the gvec_bfmmla helper, so we can use it to add support for FEAT_EBF16. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper.h | 4 ++-- target/arm/tcg/translate-a64.c | 2 +- target/arm/tcg/translate-neon.c | 4 ++-- target/arm/tcg/translate-sve.c | 2 +- target/arm/tcg/vec_helper.c | 3 ++- 5 files changed, 8 insertions(+), 7 deletions(-) diff --git a/target/arm/helper.h b/target/arm/helper.h index e197b5b1d2c..b463be38c52 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -1032,8 +1032,8 @@ DEF_HELPER_FLAGS_6(gvec_bfdot, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(gvec_bfdot_idx, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_FLAGS_5(gvec_bfmmla, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_6(gvec_bfmmla, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_FLAGS_6(gvec_bfmlal, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, ptr, i32) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index c7876513c72..6d5f12e8f55 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -5637,7 +5637,7 @@ TRANS_FEAT(SDOT_v, aa64_dp, do_dot_vector, a, gen_helper_gvec_sdot_b) TRANS_FEAT(UDOT_v, aa64_dp, do_dot_vector, a, gen_helper_gvec_udot_b) TRANS_FEAT(USDOT_v, aa64_i8mm, do_dot_vector, a, gen_helper_gvec_usdot_b) TRANS_FEAT(BFDOT_v, aa64_bf16, do_dot_vector_env, a, gen_helper_gvec_bfdot) -TRANS_FEAT(BFMMLA, aa64_bf16, do_dot_vector, a, gen_helper_gvec_bfmmla) +TRANS_FEAT(BFMMLA, aa64_bf16, do_dot_vector_env, a, gen_helper_gvec_bfmmla) TRANS_FEAT(SMMLA, aa64_i8mm, do_dot_vector, a, gen_helper_gvec_smmla_b) TRANS_FEAT(UMMLA, aa64_i8mm, do_dot_vector, a, gen_helper_gvec_ummla_b) TRANS_FEAT(USMMLA, aa64_i8mm, do_dot_vector, a, gen_helper_gvec_usmmla_b) diff --git a/target/arm/tcg/translate-neon.c b/target/arm/tcg/translate-neon.c index 7de157c539c..13cd31aad42 100644 --- a/target/arm/tcg/translate-neon.c +++ b/target/arm/tcg/translate-neon.c @@ -3730,8 +3730,8 @@ static bool trans_VMMLA_b16(DisasContext *s, arg_VMMLA_b16 *a) if (!dc_isar_feature(aa32_bf16, s)) { return false; } - return do_neon_ddda(s, 7, a->vd, a->vn, a->vm, 0, - gen_helper_gvec_bfmmla); + return do_neon_ddda_env(s, 7, a->vd, a->vn, a->vm, 0, + gen_helper_gvec_bfmmla); } static bool trans_VFMA_b16(DisasContext *s, arg_VFMA_b16 *a) diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index eb77c943c8f..9e2536dfe99 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -7137,7 +7137,7 @@ TRANS_FEAT(BFDOT_zzzz, aa64_sve_bf16, gen_gvec_env_arg_zzzz, TRANS_FEAT(BFDOT_zzxz, aa64_sve_bf16, gen_gvec_env_arg_zzxz, gen_helper_gvec_bfdot_idx, a) -TRANS_FEAT_NONSTREAMING(BFMMLA, aa64_sve_bf16, gen_gvec_ool_arg_zzzz, +TRANS_FEAT_NONSTREAMING(BFMMLA, aa64_sve_bf16, gen_gvec_env_arg_zzzz, gen_helper_gvec_bfmmla, a, 0) static bool do_BFMLAL_zzzw(DisasContext *s, arg_rrrr_esz *a, bool sel) diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c index a2c62a86d84..616ec54bb77 100644 --- a/target/arm/tcg/vec_helper.c +++ b/target/arm/tcg/vec_helper.c @@ -2847,7 +2847,8 @@ void HELPER(gvec_bfdot_idx)(void *vd, void *vn, void *vm, clear_tail(d, opr_sz, simd_maxsz(desc)); } -void HELPER(gvec_bfmmla)(void *vd, void *vn, void *vm, void *va, uint32_t desc) +void HELPER(gvec_bfmmla)(void *vd, void *vn, void *vm, void *va, + CPUARMState *env, uint32_t desc) { intptr_t s, opr_sz = simd_oprsz(desc); float32 *d = vd, *a = va; From patchwork Thu Sep 5 13:00:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 825655 Delivered-To: patch@linaro.org Received: by 2002:adf:a345:0:b0:367:895a:4699 with SMTP id d5csp288557wrb; Thu, 5 Sep 2024 06:06:08 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXZ+mXLGsgCVqPahV4GHNVmms1ROte9txE2lWl8dY1zf85+z1soNV2uATmTx0KJcl/y4+IWbQ==@linaro.org X-Google-Smtp-Source: AGHT+IH9L1Xm+q4Hu7E1n1OUqnLNOrDOxqoft1HA3nL+6RBxWYVN+M0Kotg2AtSES4CStSKrcCt1 X-Received: by 2002:a05:620a:818b:b0:7a1:e49b:9461 with SMTP id af79cd13be357-7a9888f0d34mr741270885a.26.1725541568299; Thu, 05 Sep 2024 06:06:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1725541568; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42bb6e355dfsm232251365e9.46.2024.09.05.06.01.06 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Sep 2024 06:01:07 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 06/25] target/arm: Prepare bfdotadd() callers for FEAT_EBF support Date: Thu, 5 Sep 2024 14:00:41 +0100 Message-Id: <20240905130100.298768-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240905130100.298768-1-peter.maydell@linaro.org> References: <20240905130100.298768-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org We use bfdotadd() in four callsites for various helper functions. Currently this all assumes that we have the FPCR.EBF=0 semantics. For FPCR.EBF=1 we will need to: * call a different routine to bfdotadd() because we need to do a fused multiply-add rather than separate multiply and add steps * use a different float_status that honours the FPCR rounding mode and denormal-flushing fields * pass in an extra float_status that has been set up to perform round-to-odd rounding To prepare for this, refactor all the callsites so that instead of for (...) { x = bfdotadd(...); } they are: float_status fpst, fpst_odd; if (is_ebf(env, &fpst, &fpst_odd)) { for (...) { x = bfdotadd_ebf(..., &fpst, &fpst_odd); } } else { for (...) { x = bfdotadd(..., &fpst); } } For the moment the is_ebf() function always returns false, sets up fpst for EBF=0 semantics and never sets up fpst_odd; bfdotadd_ebf() will assert if called. We'll fill in the handling for EBF=1 in the next commit. This change should be a zero-behaviour-change refactor. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/tcg/vec_internal.h | 37 ++++++++- target/arm/tcg/sme_helper.c | 74 ++++++++++++------ target/arm/tcg/vec_helper.c | 139 +++++++++++++++++++++++++--------- 3 files changed, 189 insertions(+), 61 deletions(-) diff --git a/target/arm/tcg/vec_internal.h b/target/arm/tcg/vec_internal.h index 3ca1b94ccf9..094f5c169ca 100644 --- a/target/arm/tcg/vec_internal.h +++ b/target/arm/tcg/vec_internal.h @@ -223,13 +223,46 @@ int64_t do_sqrdmlah_d(int64_t, int64_t, int64_t, bool, bool); * bfdotadd: * @sum: addend * @e1, @e2: multiplicand vectors + * @fpst: floating-point status to use * * BFloat16 2-way dot product of @e1 & @e2, accumulating with @sum. * The @e1 and @e2 operands correspond to the 32-bit source vector * slots and contain two Bfloat16 values each. * - * Corresponds to the ARM pseudocode function BFDotAdd. + * Corresponds to the ARM pseudocode function BFDotAdd, specialized + * for the FPCR.EBF == 0 case. */ -float32 bfdotadd(float32 sum, uint32_t e1, uint32_t e2); +float32 bfdotadd(float32 sum, uint32_t e1, uint32_t e2, float_status *fpst); +/** + * bfdotadd_ebf: + * @sum: addend + * @e1, @e2: multiplicand vectors + * @fpst: floating-point status to use + * @fpst_odd: floating-point status to use for round-to-odd operations + * + * BFloat16 2-way dot product of @e1 & @e2, accumulating with @sum. + * The @e1 and @e2 operands correspond to the 32-bit source vector + * slots and contain two Bfloat16 values each. + * + * Corresponds to the ARM pseudocode function BFDotAdd, specialized + * for the FPCR.EBF == 1 case. + */ +float32 bfdotadd_ebf(float32 sum, uint32_t e1, uint32_t e2, + float_status *fpst, float_status *fpst_odd); + +/** + * is_ebf: + * @env: CPU state + * @statusp: pointer to floating point status to fill in + * @oddstatusp: pointer to floating point status to fill in for round-to-odd + * + * Determine whether a BFDotAdd operation should use FPCR.EBF = 0 + * or FPCR.EBF = 1 semantics. On return, has initialized *statusp + * and *oddstatusp to suitable float_status arguments to use with either + * bfdotadd() or bfdotadd_ebf(). + * Returns true for EBF = 1, false for EBF = 0. (The caller should use this + * to decide whether to call bfdotadd() or bfdotadd_ebf().) + */ +bool is_ebf(CPUARMState *env, float_status *statusp, float_status *oddstatusp); #endif /* TARGET_ARM_VEC_INTERNAL_H */ diff --git a/target/arm/tcg/sme_helper.c b/target/arm/tcg/sme_helper.c index 289ffabbfbe..8cf12654e56 100644 --- a/target/arm/tcg/sme_helper.c +++ b/target/arm/tcg/sme_helper.c @@ -1085,32 +1085,62 @@ void HELPER(sme_bfmopa)(void *vza, void *vzn, void *vzm, intptr_t row, col, oprsz = simd_maxsz(desc); uint32_t neg = simd_data(desc) * 0x80008000u; uint16_t *pn = vpn, *pm = vpm; + float_status fpst, fpst_odd; - for (row = 0; row < oprsz; ) { - uint16_t prow = pn[H2(row >> 4)]; - do { - void *vza_row = vza + tile_vslice_offset(row); - uint32_t n = *(uint32_t *)(vzn + H1_4(row)); + if (is_ebf(env, &fpst, &fpst_odd)) { + for (row = 0; row < oprsz; ) { + uint16_t prow = pn[H2(row >> 4)]; + do { + void *vza_row = vza + tile_vslice_offset(row); + uint32_t n = *(uint32_t *)(vzn + H1_4(row)); - n = f16mop_adj_pair(n, prow, neg); + n = f16mop_adj_pair(n, prow, neg); - for (col = 0; col < oprsz; ) { - uint16_t pcol = pm[H2(col >> 4)]; - do { - if (prow & pcol & 0b0101) { - uint32_t *a = vza_row + H1_4(col); - uint32_t m = *(uint32_t *)(vzm + H1_4(col)); + for (col = 0; col < oprsz; ) { + uint16_t pcol = pm[H2(col >> 4)]; + do { + if (prow & pcol & 0b0101) { + uint32_t *a = vza_row + H1_4(col); + uint32_t m = *(uint32_t *)(vzm + H1_4(col)); - m = f16mop_adj_pair(m, pcol, 0); - *a = bfdotadd(*a, n, m); - } - col += 4; - pcol >>= 4; - } while (col & 15); - } - row += 4; - prow >>= 4; - } while (row & 15); + m = f16mop_adj_pair(m, pcol, 0); + *a = bfdotadd_ebf(*a, n, m, &fpst, &fpst_odd); + } + col += 4; + pcol >>= 4; + } while (col & 15); + } + row += 4; + prow >>= 4; + } while (row & 15); + } + } else { + for (row = 0; row < oprsz; ) { + uint16_t prow = pn[H2(row >> 4)]; + do { + void *vza_row = vza + tile_vslice_offset(row); + uint32_t n = *(uint32_t *)(vzn + H1_4(row)); + + n = f16mop_adj_pair(n, prow, neg); + + for (col = 0; col < oprsz; ) { + uint16_t pcol = pm[H2(col >> 4)]; + do { + if (prow & pcol & 0b0101) { + uint32_t *a = vza_row + H1_4(col); + uint32_t m = *(uint32_t *)(vzm + H1_4(col)); + + m = f16mop_adj_pair(m, pcol, 0); + *a = bfdotadd(*a, n, m, &fpst); + } + col += 4; + pcol >>= 4; + } while (col & 15); + } + row += 4; + prow >>= 4; + } while (row & 15); + } } } diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c index 616ec54bb77..b0de74b55f1 100644 --- a/target/arm/tcg/vec_helper.c +++ b/target/arm/tcg/vec_helper.c @@ -2790,39 +2790,58 @@ DO_MMLA_B(gvec_usmmla_b, do_usmmla_b) * BFloat16 Dot Product */ -float32 bfdotadd(float32 sum, uint32_t e1, uint32_t e2) +bool is_ebf(CPUARMState *env, float_status *statusp, float_status *oddstatusp) { /* FPCR is ignored for BFDOT and BFMMLA. */ - float_status bf_status = { + *statusp = (float_status){ .tininess_before_rounding = float_tininess_before_rounding, .float_rounding_mode = float_round_to_odd_inf, .flush_to_zero = true, .flush_inputs_to_zero = true, .default_nan_mode = true, }; + + return false; +} + +float32 bfdotadd(float32 sum, uint32_t e1, uint32_t e2, float_status *fpst) +{ float32 t1, t2; /* * Extract each BFloat16 from the element pair, and shift * them such that they become float32. */ - t1 = float32_mul(e1 << 16, e2 << 16, &bf_status); - t2 = float32_mul(e1 & 0xffff0000u, e2 & 0xffff0000u, &bf_status); - t1 = float32_add(t1, t2, &bf_status); - t1 = float32_add(sum, t1, &bf_status); + t1 = float32_mul(e1 << 16, e2 << 16, fpst); + t2 = float32_mul(e1 & 0xffff0000u, e2 & 0xffff0000u, fpst); + t1 = float32_add(t1, t2, fpst); + t1 = float32_add(sum, t1, fpst); return t1; } +float32 bfdotadd_ebf(float32 sum, uint32_t e1, uint32_t e2, + float_status *fpst, float_status *fpst_odd) +{ + g_assert_not_reached(); +} + void HELPER(gvec_bfdot)(void *vd, void *vn, void *vm, void *va, CPUARMState *env, uint32_t desc) { intptr_t i, opr_sz = simd_oprsz(desc); float32 *d = vd, *a = va; uint32_t *n = vn, *m = vm; + float_status fpst, fpst_odd; - for (i = 0; i < opr_sz / 4; ++i) { - d[i] = bfdotadd(a[i], n[i], m[i]); + if (is_ebf(env, &fpst, &fpst_odd)) { + for (i = 0; i < opr_sz / 4; ++i) { + d[i] = bfdotadd_ebf(a[i], n[i], m[i], &fpst, &fpst_odd); + } + } else { + for (i = 0; i < opr_sz / 4; ++i) { + d[i] = bfdotadd(a[i], n[i], m[i], &fpst); + } } clear_tail(d, opr_sz, simd_maxsz(desc)); } @@ -2836,12 +2855,23 @@ void HELPER(gvec_bfdot_idx)(void *vd, void *vn, void *vm, intptr_t eltspersegment = MIN(16 / 4, elements); float32 *d = vd, *a = va; uint32_t *n = vn, *m = vm; + float_status fpst, fpst_odd; - for (i = 0; i < elements; i += eltspersegment) { - uint32_t m_idx = m[i + H4(index)]; + if (is_ebf(env, &fpst, &fpst_odd)) { + for (i = 0; i < elements; i += eltspersegment) { + uint32_t m_idx = m[i + H4(index)]; - for (j = i; j < i + eltspersegment; j++) { - d[j] = bfdotadd(a[j], n[j], m_idx); + for (j = i; j < i + eltspersegment; j++) { + d[j] = bfdotadd_ebf(a[j], n[j], m_idx, &fpst, &fpst_odd); + } + } + } else { + for (i = 0; i < elements; i += eltspersegment) { + uint32_t m_idx = m[i + H4(index)]; + + for (j = i; j < i + eltspersegment; j++) { + d[j] = bfdotadd(a[j], n[j], m_idx, &fpst); + } } } clear_tail(d, opr_sz, simd_maxsz(desc)); @@ -2853,37 +2883,72 @@ void HELPER(gvec_bfmmla)(void *vd, void *vn, void *vm, void *va, intptr_t s, opr_sz = simd_oprsz(desc); float32 *d = vd, *a = va; uint32_t *n = vn, *m = vm; + float_status fpst, fpst_odd; - for (s = 0; s < opr_sz / 4; s += 4) { - float32 sum00, sum01, sum10, sum11; + if (is_ebf(env, &fpst, &fpst_odd)) { + for (s = 0; s < opr_sz / 4; s += 4) { + float32 sum00, sum01, sum10, sum11; - /* - * Process the entire segment at once, writing back the - * results only after we've consumed all of the inputs. - * - * Key to indices by column: - * i j i k j k - */ - sum00 = a[s + H4(0 + 0)]; - sum00 = bfdotadd(sum00, n[s + H4(0 + 0)], m[s + H4(0 + 0)]); - sum00 = bfdotadd(sum00, n[s + H4(0 + 1)], m[s + H4(0 + 1)]); + /* + * Process the entire segment at once, writing back the + * results only after we've consumed all of the inputs. + * + * Key to indices by column: + * i j i k j k + */ + sum00 = a[s + H4(0 + 0)]; + sum00 = bfdotadd_ebf(sum00, n[s + H4(0 + 0)], m[s + H4(0 + 0)], &fpst, &fpst_odd); + sum00 = bfdotadd_ebf(sum00, n[s + H4(0 + 1)], m[s + H4(0 + 1)], &fpst, &fpst_odd); - sum01 = a[s + H4(0 + 1)]; - sum01 = bfdotadd(sum01, n[s + H4(0 + 0)], m[s + H4(2 + 0)]); - sum01 = bfdotadd(sum01, n[s + H4(0 + 1)], m[s + H4(2 + 1)]); + sum01 = a[s + H4(0 + 1)]; + sum01 = bfdotadd_ebf(sum01, n[s + H4(0 + 0)], m[s + H4(2 + 0)], &fpst, &fpst_odd); + sum01 = bfdotadd_ebf(sum01, n[s + H4(0 + 1)], m[s + H4(2 + 1)], &fpst, &fpst_odd); - sum10 = a[s + H4(2 + 0)]; - sum10 = bfdotadd(sum10, n[s + H4(2 + 0)], m[s + H4(0 + 0)]); - sum10 = bfdotadd(sum10, n[s + H4(2 + 1)], m[s + H4(0 + 1)]); + sum10 = a[s + H4(2 + 0)]; + sum10 = bfdotadd_ebf(sum10, n[s + H4(2 + 0)], m[s + H4(0 + 0)], &fpst, &fpst_odd); + sum10 = bfdotadd_ebf(sum10, n[s + H4(2 + 1)], m[s + H4(0 + 1)], &fpst, &fpst_odd); - sum11 = a[s + H4(2 + 1)]; - sum11 = bfdotadd(sum11, n[s + H4(2 + 0)], m[s + H4(2 + 0)]); - sum11 = bfdotadd(sum11, n[s + H4(2 + 1)], m[s + H4(2 + 1)]); + sum11 = a[s + H4(2 + 1)]; + sum11 = bfdotadd_ebf(sum11, n[s + H4(2 + 0)], m[s + H4(2 + 0)], &fpst, &fpst_odd); + sum11 = bfdotadd_ebf(sum11, n[s + H4(2 + 1)], m[s + H4(2 + 1)], &fpst, &fpst_odd); - d[s + H4(0 + 0)] = sum00; - d[s + H4(0 + 1)] = sum01; - d[s + H4(2 + 0)] = sum10; - d[s + H4(2 + 1)] = sum11; + d[s + H4(0 + 0)] = sum00; + d[s + H4(0 + 1)] = sum01; + d[s + H4(2 + 0)] = sum10; + d[s + H4(2 + 1)] = sum11; + } + } else { + for (s = 0; s < opr_sz / 4; s += 4) { + float32 sum00, sum01, sum10, sum11; + + /* + * Process the entire segment at once, writing back the + * results only after we've consumed all of the inputs. + * + * Key to indices by column: + * i j i k j k + */ + sum00 = a[s + H4(0 + 0)]; + sum00 = bfdotadd(sum00, n[s + H4(0 + 0)], m[s + H4(0 + 0)], &fpst); + sum00 = bfdotadd(sum00, n[s + H4(0 + 1)], m[s + H4(0 + 1)], &fpst); + + sum01 = a[s + H4(0 + 1)]; + sum01 = bfdotadd(sum01, n[s + H4(0 + 0)], m[s + H4(2 + 0)], &fpst); + sum01 = bfdotadd(sum01, n[s + H4(0 + 1)], m[s + H4(2 + 1)], &fpst); + + sum10 = a[s + H4(2 + 0)]; + sum10 = bfdotadd(sum10, n[s + H4(2 + 0)], m[s + H4(0 + 0)], &fpst); + sum10 = bfdotadd(sum10, n[s + H4(2 + 1)], m[s + H4(0 + 1)], &fpst); + + sum11 = a[s + H4(2 + 1)]; + sum11 = bfdotadd(sum11, n[s + H4(2 + 0)], m[s + H4(2 + 0)], &fpst); + sum11 = bfdotadd(sum11, n[s + H4(2 + 1)], m[s + H4(2 + 1)], &fpst); + + d[s + H4(0 + 0)] = sum00; + d[s + H4(0 + 1)] = sum01; + d[s + H4(2 + 0)] = sum10; + d[s + H4(2 + 1)] = sum11; + } } clear_tail(d, opr_sz, simd_maxsz(desc)); } From patchwork Thu Sep 5 13:00:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 825651 Delivered-To: patch@linaro.org Received: by 2002:adf:a345:0:b0:367:895a:4699 with SMTP id d5csp288214wrb; Thu, 5 Sep 2024 06:05:42 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUg19PvY0BytXDr2NxrJ62CK4ztKKpalCiTFG29j2GFea97FXvsZ0hS24fLIAAAvDbAbIxKUQ==@linaro.org X-Google-Smtp-Source: AGHT+IG3TcUvZn9/IWdgwVL3dex96Ym/ginDSA+xZhWZu66acq/tOKq4NG0f/JByuRAz/9jyePAA X-Received: by 2002:a0c:f802:0:b0:6c3:510e:900b with SMTP id 6a1803df08f44-6c518efff0emr84799276d6.16.1725541542326; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42bb6e355dfsm232251365e9.46.2024.09.05.06.01.07 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Sep 2024 06:01:07 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 07/25] target/arm: Implement FPCR.EBF=1 semantics for bfdotadd() Date: Thu, 5 Sep 2024 14:00:42 +0100 Message-Id: <20240905130100.298768-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240905130100.298768-1-peter.maydell@linaro.org> References: <20240905130100.298768-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Implement the FPCR.EBF=1 semantics for bfdotadd() operations: * is_ebf() sets up fpst and fpst_odd * bfdotadd_ebf() implements the fused paired-multiply-and-add operation that we need The paired-multiply-and-add is similar to f16_dotadd() and we use the same trick here as in that function, but the inputs here are bfloat16 rather than float16. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/tcg/vec_helper.c | 57 +++++++++++++++++++++++++++++++++++-- 1 file changed, 54 insertions(+), 3 deletions(-) diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c index b0de74b55f1..22ddb968817 100644 --- a/target/arm/tcg/vec_helper.c +++ b/target/arm/tcg/vec_helper.c @@ -2792,7 +2792,20 @@ DO_MMLA_B(gvec_usmmla_b, do_usmmla_b) bool is_ebf(CPUARMState *env, float_status *statusp, float_status *oddstatusp) { - /* FPCR is ignored for BFDOT and BFMMLA. */ + /* + * For BFDOT, BFMMLA, etc, the behaviour depends on FPCR.EBF. + * For EBF = 0, we ignore the FPCR bits which determine rounding + * mode and denormal-flushing, and we do unfused multiplies and + * additions with intermediate rounding of all products and sums. + * For EBF = 1, we honour FPCR rounding mode and denormal-flushing bits, + * and we perform a fused two-way sum-of-products without intermediate + * rounding of the products. + * In either case, we don't set fp exception flags. + * + * EBF is AArch64 only, so even if it's set in the FPCR it has + * no effect on AArch32 instructions. + */ + bool ebf = is_a64(env) && env->vfp.fpcr & FPCR_EBF; *statusp = (float_status){ .tininess_before_rounding = float_tininess_before_rounding, .float_rounding_mode = float_round_to_odd_inf, @@ -2801,7 +2814,18 @@ bool is_ebf(CPUARMState *env, float_status *statusp, float_status *oddstatusp) .default_nan_mode = true, }; - return false; + if (ebf) { + float_status *fpst = &env->vfp.fp_status; + set_flush_to_zero(get_flush_to_zero(fpst), statusp); + set_flush_inputs_to_zero(get_flush_inputs_to_zero(fpst), statusp); + set_float_rounding_mode(get_float_rounding_mode(fpst), statusp); + + /* EBF=1 needs to do a step with round-to-odd semantics */ + *oddstatusp = *statusp; + set_float_rounding_mode(float_round_to_odd, oddstatusp); + } + + return ebf; } float32 bfdotadd(float32 sum, uint32_t e1, uint32_t e2, float_status *fpst) @@ -2823,7 +2847,34 @@ float32 bfdotadd(float32 sum, uint32_t e1, uint32_t e2, float_status *fpst) float32 bfdotadd_ebf(float32 sum, uint32_t e1, uint32_t e2, float_status *fpst, float_status *fpst_odd) { - g_assert_not_reached(); + /* + * Compare f16_dotadd() in sme_helper.c, but here we have + * bfloat16 inputs. In particular that means that we do not + * want the FPCR.FZ16 flush semantics, so we use the normal + * float_status for the input handling here. + */ + float64 e1r = float32_to_float64(e1 << 16, fpst); + float64 e1c = float32_to_float64(e1 & 0xffff0000u, fpst); + float64 e2r = float32_to_float64(e2 << 16, fpst); + float64 e2c = float32_to_float64(e2 & 0xffff0000u, fpst); + float64 t64; + float32 t32; + + /* + * The ARM pseudocode function FPDot performs both multiplies + * and the add with a single rounding operation. Emulate this + * by performing the first multiply in round-to-odd, then doing + * the second multiply as fused multiply-add, and rounding to + * float32 all in one step. + */ + t64 = float64_mul(e1r, e2r, fpst_odd); + t64 = float64r32_muladd(e1c, e2c, t64, 0, fpst); + + /* This conversion is exact, because we've already rounded. */ + t32 = float64_to_float32(t64, fpst); + + /* The final accumulation step is not fused. */ + return float32_add(sum, t32, fpst); } void HELPER(gvec_bfdot)(void *vd, void *vn, void *vm, void *va, From patchwork Thu Sep 5 13:00:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 825642 Delivered-To: patch@linaro.org Received: by 2002:adf:a345:0:b0:367:895a:4699 with SMTP id d5csp286811wrb; Thu, 5 Sep 2024 06:03:43 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWYLgBAMr5+8Pclsy/2uyNCAIe4qs8wPwU0RNN4hFUUITqv1+iNUQtJcvq7N5U3zDsDVs2uNA==@linaro.org X-Google-Smtp-Source: AGHT+IEK272RW8j4y1P5eh5wLu12jk51bfM9FZdBtlIoAicesCpSKqjnWsUsD7nCIDTlAamBQKQW X-Received: by 2002:a05:600c:5494:b0:426:5dd0:a1e4 with SMTP id 5b1f17b1804b1-42bbb20568fmr144785675e9.8.1725541423632; Thu, 05 Sep 2024 06:03:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1725541423; cv=none; d=google.com; s=arc-20160816; b=a8/q/Y2v5951oK3jAQBCSRnywyzW8Li48XFMnThlTico07A5mlKg5vf7BVoL0MpeEY PsUgSCDe8fC2XhOnb3n2G6+S98C0wNrdUMFUn1Fa4Ak8yWzP6hUAbLAuHxN3O4fkftS+ xeQC+06HveQd0wDVSbWaqEqqqv/bTrbiZ7mEHpeRkw0RohT1m9iUgJN3UqxmwLg1fe6y aef4wLCvXT3uN8vPKX6iN0YA+1CCa2V9qLKdjAuBDFoNI4OSAR9w7nxCX5ehDDhzSQg3 W0oWvLQr74lxc4bSDo7rIZjsN1pqxC1o5IRm2GQ9oFW0c8//1I1Hb+NUi2zaWuz7wNJz 2uvg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=UEqv69UXTmYHkRInh7zHHsDNkedM/XSTNS7ye2GCeVk=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=N1+nsbaFvXT9lVxlJVyJEGbrR7UXiYgeYSHLedi70hqzeXALxuoYXpvMB0wtXzBp0M IkPFfvynboSBl/eMhqRmqqOsCNd7J1npweIDYefXRVNhi8cpE832WJ1MbysBlZ/HAATq FTQHm8nO8fQaoeQ+08zJzPr8ew4xdZT6c0pH+ov54OyQ5sy4CKCmYsD2AOGJm5RHOmmZ 73VMnZrRoqNWs0uecQtbzNANgw9POXbUtpSf0p9YGOnGbiD37ax/c80Z2bPAjLqhxknH rfOzCZy5AeWWW5uTJS4p3t4p8phwy3fiddlKE/SHh0tjgpnQwnanTjQgt8lSODE10v61 IDTQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=EBVZnsKR; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42bb6e355dfsm232251365e9.46.2024.09.05.06.01.08 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Sep 2024 06:01:08 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/25] target/arm: Enable FEAT_EBF16 in the "max" CPU Date: Thu, 5 Sep 2024 14:00:43 +0100 Message-Id: <20240905130100.298768-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240905130100.298768-1-peter.maydell@linaro.org> References: <20240905130100.298768-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Now that we've implemented the required behaviour for FEAT_EBF16, we can enable it for the "max" CPU type, list it in our documentation, and delete a TODO comment about it being missing. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- docs/system/arm/emulation.rst | 1 + target/arm/tcg/cpu64.c | 4 ++-- target/arm/tcg/translate-sme.c | 1 - 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 3ab6e726679..35f52a54b1c 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -45,6 +45,7 @@ the following architecture extensions: - FEAT_DotProd (Advanced SIMD dot product instructions) - FEAT_DoubleFault (Double Fault Extension) - FEAT_E0PD (Preventing EL0 access to halves of address maps) +- FEAT_EBF16 (AArch64 Extended BFloat16 instructions) - FEAT_ECV (Enhanced Counter Virtualization) - FEAT_EL0 (Support for execution at EL0) - FEAT_EL1 (Support for execution at EL1) diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index fe232eb3069..79258a7c928 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1160,7 +1160,7 @@ void aarch64_max_tcg_initfn(Object *obj) t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1); /* FEAT_FRINTTS */ t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1); /* FEAT_SB */ t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); /* FEAT_SPECRES */ - t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1); /* FEAT_BF16 */ + t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 2); /* FEAT_BF16, FEAT_EBF16 */ t = FIELD_DP64(t, ID_AA64ISAR1, DGH, 1); /* FEAT_DGH */ t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); /* FEAT_I8MM */ cpu->isar.id_aa64isar1 = t; @@ -1244,7 +1244,7 @@ void aarch64_max_tcg_initfn(Object *obj) t = FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1); t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* FEAT_SVE_PMULL128 */ t = FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1); /* FEAT_SVE_BitPerm */ - t = FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 1); /* FEAT_BF16 */ + t = FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 2); /* FEAT_BF16, FEAT_EBF16 */ t = FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1); /* FEAT_SVE_SHA3 */ t = FIELD_DP64(t, ID_AA64ZFR0, SM4, 1); /* FEAT_SVE_SM4 */ t = FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1); /* FEAT_I8MM */ diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c index 3ceb32e8bd9..01ece570164 100644 --- a/target/arm/tcg/translate-sme.c +++ b/target/arm/tcg/translate-sme.c @@ -362,7 +362,6 @@ TRANS_FEAT(FMOPA_s, aa64_sme, do_outprod_fpst, a, TRANS_FEAT(FMOPA_d, aa64_sme_f64f64, do_outprod_fpst, a, MO_64, FPST_FPCR, gen_helper_sme_fmopa_d) -/* TODO: FEAT_EBF16 */ TRANS_FEAT(BFMOPA, aa64_sme, do_outprod_env, a, MO_32, gen_helper_sme_bfmopa) TRANS_FEAT(SMOPA_s, aa64_sme, do_outprod, a, MO_32, gen_helper_sme_smopa_s) From patchwork Thu Sep 5 13:00:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 825639 Delivered-To: patch@linaro.org Received: by 2002:adf:a345:0:b0:367:895a:4699 with SMTP id d5csp286508wrb; Thu, 5 Sep 2024 06:03:17 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWyU9n2/i64+/sWTaVFVaWs1tRR3SRb+bYhX85ysUTdb4LvSEeXqBW3M+lX/gIzLOIOtg0SSQ==@linaro.org X-Google-Smtp-Source: AGHT+IFIVNDVe0ejp/6/FsWfp1Gj52znDsnnbX+YPYr2eZaU8G47h20z6uIG4yGtkX2zdVWqP2a0 X-Received: by 2002:a5d:6e42:0:b0:374:c56c:fbc7 with SMTP id ffacd0b85a97d-376dd15a895mr4934141f8f.15.1725541397739; Thu, 05 Sep 2024 06:03:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1725541397; cv=none; d=google.com; s=arc-20160816; b=OITGks12O68g1Hc/HFWwx6fY7OulgUJINK082plzKqOVeN//f0FdXwa5RCSA7U0sWD S4HPgd1fTLDlrA+CPG40UYVUHwDQdArNaXoNVut2M3vb+ToJ16LKR7Q2EfwELmt70cBD LPqcfukDfC8F8Sb48TEJUOxw2EURll3kgty13pIE8YOJVjafoBJqSRQ68JlKJ5wH5Kcd pSTFLolmgVj08ilN3t+8bCzuI29BC90Ln13yWV2o0vvdYaxBU9Wcst8CfWov3aYjUCOf muMHvdqYfhOw+89DWw3RR2Oc2LZaJrqsc6+9//M0Bp3joUtT4CIoF7iZnycq3RgE5I3C UzHQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=x5PrsaI8e8/02sXu3878r/Hk09KLGVkhl986RODv/XE=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=GUcHH7Qbo/YVoEjWIlwZ1rQrrcirYu3DxpKQYQ1eyFDPkrUZDcsJ/A69yLxMFNMzJP cweV8f5BtXIucRugg9ziJa8wtf/EluFy2NUJvvICEczzS8FaPTzRdXKC0kavVChqd2q2 JUQac/Gn0Hz/u5mvkG4/hx8c0Zft8puD4GFqu4LkBp8baoHsWBR9tr5zcxw4UIAExd/Z iC33GuJmFOlGs9zZS7wpNceeW0tyky2MC8RsZrk0Adls+omRHwl7LfqSsMOt644E8hVc ZvT39+0XuEpy0qjPm+S1NpUcpdkJaTuaLikZZjIHr1Ah4wF+1SMhs0obt8Y8luLXPk27 /beg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=sba6Ax62; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42bb6e355dfsm232251365e9.46.2024.09.05.06.01.09 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Sep 2024 06:01:09 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 09/25] accel/tcg: Remove dead code from rr_cpu_thread_fn() Date: Thu, 5 Sep 2024 14:00:44 +0100 Message-Id: <20240905130100.298768-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240905130100.298768-1-peter.maydell@linaro.org> References: <20240905130100.298768-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The main loop in rr_cpu_thread_fn() can never terminate, so the code at the end of the function to clean up the RCU subsystem is dead code. Replace it with g_assert_not_reached(). (This is different from the other cpu_thread_fn for e.g. MTTCG or for the KVM accelerator -- those can exit, if the vCPU they are responsible for is unplugged. But the RR cpu thread fn handles all CPUs in the system in a round-robin way, so even if one is unplugged it keeps looping.) Resolves: Coverity CID 1547782 Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20240815143634.3413679-1-peter.maydell@linaro.org --- accel/tcg/tcg-accel-ops-rr.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/accel/tcg/tcg-accel-ops-rr.c b/accel/tcg/tcg-accel-ops-rr.c index c59c77da4b3..8ebadf8e9e1 100644 --- a/accel/tcg/tcg-accel-ops-rr.c +++ b/accel/tcg/tcg-accel-ops-rr.c @@ -302,9 +302,7 @@ static void *rr_cpu_thread_fn(void *arg) rr_deal_with_unplugged_cpus(); } - rcu_remove_force_rcu_notifier(&force_rcu); - rcu_unregister_thread(); - return NULL; + g_assert_not_reached(); } void rr_start_vcpu_thread(CPUState *cpu) From patchwork Thu Sep 5 13:00:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 825653 Delivered-To: patch@linaro.org Received: by 2002:adf:a345:0:b0:367:895a:4699 with SMTP id d5csp288325wrb; Thu, 5 Sep 2024 06:05:49 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVJWSJm1KeKLjTn18/t4A2XxJaW8U2f8yOMHFf5a7+SdkOPGH2XYQBc5BQwxHt3rtQmCRR6cw==@linaro.org X-Google-Smtp-Source: AGHT+IEQNgwNv2Pqf0KT1V+0gMcPQq3/Va/dgrXO3Bo7z3Nrq4PQ8Jf4U592xFvP2+2onLK8B9iP X-Received: by 2002:a05:690c:ed3:b0:6cf:8d6f:2bef with SMTP id 00721157ae682-6da17523a8fmr159044677b3.7.1725541549378; Thu, 05 Sep 2024 06:05:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1725541549; cv=none; d=google.com; s=arc-20160816; b=dmz3F+GkkVjLBeJIt1E2TEEsl4d78+OEStM37ROHr4SXfjCbMK6Rg427pZsesSTNH/ nPem41riSoMyv4VEaWLOjXv0KuzR45/nhyX53e+9HovetQ9GkOjIe/H6eDWVSz+asqq6 qyGSKgnefWDZnNOlJkXbHIkDQD9TscmJSuvQCDCp+sWaC69N9f1YIumI0XxW5jENXvVr Ay9CFc6dqUwicUu4dfuziVQcz0qIOG9OzylJYc8Sp+OHZ17d6DsKbsWAcZkoxLbaGI+v xaM29W6A1Q6LoffV3r9IQi/230ljj8Rvdhtjs+4GhsHTIqW7Zhf7Mp1WtYMua9xVRpfV YPVQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=D0tvKCCy0OvI0M0Fet5YgAPP444KsPJZWgtcRcxhpMM=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=cNkatkpVpr6dEtZUHtNBJ6fITxYETQCWra/nnK3BpUPQzw+DgLLo9zggBb4neAbjzV kAgOkSQY++DiieNvVySjXAs9Y+l74SGe+kdaWGKE8ZATL+h/xC1bpC2y6wccZtrN+y6J iqBMN6yh7snPSmBVTYuLv7YUbJZ/Nz7l0HWRkZbUjfl/m0oa/KlIkNzYYCLuBCWr0zP2 BAIzahOcFCboKPIddbytmgoFnvgpQS8MBo3FGXJeANZSnLvUecse7VoJSTAe63LjGsuG aeIUAUuTwrAO3K1mvmhjbWQyTHuI0WY86i7IZpc10TWYOl3Vby8wr/IQ4zuVQARjezdm ifgw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="h/jMEudq"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42bb6e355dfsm232251365e9.46.2024.09.05.06.01.09 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Sep 2024 06:01:10 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 10/25] hw: add compat machines for 9.2 Date: Thu, 5 Sep 2024 14:00:45 +0100 Message-Id: <20240905130100.298768-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240905130100.298768-1-peter.maydell@linaro.org> References: <20240905130100.298768-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Cornelia Huck Add 9.2 machine types for arm/i440fx/m68k/q35/s390x/spapr. Signed-off-by: Cornelia Huck Reviewed-by: Daniel P. Berrangé Reviewed-by: Eric Auger Signed-off-by: Peter Maydell Message-id: 20240816161350.3706332-2-peter.maydell@linaro.org Message-id: 20240816103723.2325982-1-cohuck@redhat.com Signed-off-by: Peter Maydell --- include/hw/boards.h | 3 +++ include/hw/i386/pc.h | 3 +++ hw/arm/virt.c | 11 +++++++++-- hw/core/machine.c | 3 +++ hw/i386/pc.c | 3 +++ hw/i386/pc_piix.c | 15 ++++++++++++--- hw/i386/pc_q35.c | 13 +++++++++++-- hw/m68k/virt.c | 11 +++++++++-- hw/ppc/spapr.c | 17 ++++++++++++++--- hw/s390x/s390-virtio-ccw.c | 14 +++++++++++++- 10 files changed, 80 insertions(+), 13 deletions(-) diff --git a/include/hw/boards.h b/include/hw/boards.h index 48ff6d8b93f..9a492770cbb 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -732,6 +732,9 @@ struct MachineState { } \ type_init(machine_initfn##_register_types) +extern GlobalProperty hw_compat_9_1[]; +extern const size_t hw_compat_9_1_len; + extern GlobalProperty hw_compat_9_0[]; extern const size_t hw_compat_9_0_len; diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index 4e55d7ef6ea..14ee06287da 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -215,6 +215,9 @@ void pc_system_parse_ovmf_flash(uint8_t *flash_ptr, size_t flash_size); /* sgx.c */ void pc_machine_init_sgx_epc(PCMachineState *pcms); +extern GlobalProperty pc_compat_9_1[]; +extern const size_t pc_compat_9_1_len; + extern GlobalProperty pc_compat_9_0[]; extern const size_t pc_compat_9_0_len; diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 687fe0bb8bc..a5d3ad9bf9e 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -3301,10 +3301,17 @@ static void machvirt_machine_init(void) } type_init(machvirt_machine_init); -static void virt_machine_9_1_options(MachineClass *mc) +static void virt_machine_9_2_options(MachineClass *mc) { } -DEFINE_VIRT_MACHINE_AS_LATEST(9, 1) +DEFINE_VIRT_MACHINE_AS_LATEST(9, 2) + +static void virt_machine_9_1_options(MachineClass *mc) +{ + virt_machine_9_2_options(mc); + compat_props_add(mc->compat_props, hw_compat_9_1, hw_compat_9_1_len); +} +DEFINE_VIRT_MACHINE(9, 1) static void virt_machine_9_0_options(MachineClass *mc) { diff --git a/hw/core/machine.c b/hw/core/machine.c index 27dcda02483..adaba17ebac 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -34,6 +34,9 @@ #include "hw/virtio/virtio-iommu.h" #include "audio/audio.h" +GlobalProperty hw_compat_9_1[] = {}; +const size_t hw_compat_9_1_len = G_N_ELEMENTS(hw_compat_9_1); + GlobalProperty hw_compat_9_0[] = { {"arm-cpu", "backcompat-cntfrq", "true" }, { "scsi-hd", "migrate-emulated-scsi-request", "false" }, diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 7779c88a91e..ba0ff511836 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -79,6 +79,9 @@ { "qemu64-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\ { "athlon-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, }, +GlobalProperty pc_compat_9_1[] = {}; +const size_t pc_compat_9_1_len = G_N_ELEMENTS(pc_compat_9_1); + GlobalProperty pc_compat_9_0[] = { { TYPE_X86_CPU, "x-amd-topoext-features-only", "false" }, { TYPE_X86_CPU, "x-l1-cache-per-thread", "false" }, diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 347afa4c370..2bf6865d405 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -474,13 +474,24 @@ static void pc_i440fx_machine_options(MachineClass *m) "Use a different south bridge than PIIX3"); } -static void pc_i440fx_machine_9_1_options(MachineClass *m) +static void pc_i440fx_machine_9_2_options(MachineClass *m) { pc_i440fx_machine_options(m); m->alias = "pc"; m->is_default = true; } +DEFINE_I440FX_MACHINE(9, 2); + +static void pc_i440fx_machine_9_1_options(MachineClass *m) +{ + pc_i440fx_machine_9_2_options(m); + m->alias = NULL; + m->is_default = false; + compat_props_add(m->compat_props, hw_compat_9_1, hw_compat_9_1_len); + compat_props_add(m->compat_props, pc_compat_9_1, pc_compat_9_1_len); +} + DEFINE_I440FX_MACHINE(9, 1); static void pc_i440fx_machine_9_0_options(MachineClass *m) @@ -488,8 +499,6 @@ static void pc_i440fx_machine_9_0_options(MachineClass *m) PCMachineClass *pcmc = PC_MACHINE_CLASS(m); pc_i440fx_machine_9_1_options(m); - m->alias = NULL; - m->is_default = false; m->smbios_memory_device_size = 16 * GiB; compat_props_add(m->compat_props, hw_compat_9_0, hw_compat_9_0_len); diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index f2d8edfa846..8319b6d45ee 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -356,19 +356,28 @@ static void pc_q35_machine_options(MachineClass *m) pc_q35_compat_defaults, pc_q35_compat_defaults_len); } -static void pc_q35_machine_9_1_options(MachineClass *m) +static void pc_q35_machine_9_2_options(MachineClass *m) { pc_q35_machine_options(m); m->alias = "q35"; } +DEFINE_Q35_MACHINE(9, 2); + +static void pc_q35_machine_9_1_options(MachineClass *m) +{ + pc_q35_machine_9_2_options(m); + m->alias = NULL; + compat_props_add(m->compat_props, hw_compat_9_1, hw_compat_9_1_len); + compat_props_add(m->compat_props, pc_compat_9_1, pc_compat_9_1_len); +} + DEFINE_Q35_MACHINE(9, 1); static void pc_q35_machine_9_0_options(MachineClass *m) { PCMachineClass *pcmc = PC_MACHINE_CLASS(m); pc_q35_machine_9_1_options(m); - m->alias = NULL; m->smbios_memory_device_size = 16 * GiB; compat_props_add(m->compat_props, hw_compat_9_0, hw_compat_9_0_len); compat_props_add(m->compat_props, pc_compat_9_0, pc_compat_9_0_len); diff --git a/hw/m68k/virt.c b/hw/m68k/virt.c index cda199af8fa..ea5c4a5a570 100644 --- a/hw/m68k/virt.c +++ b/hw/m68k/virt.c @@ -366,10 +366,17 @@ type_init(virt_machine_register_types) #define DEFINE_VIRT_MACHINE(major, minor) \ DEFINE_VIRT_MACHINE_IMPL(false, major, minor) -static void virt_machine_9_1_options(MachineClass *mc) +static void virt_machine_9_2_options(MachineClass *mc) { } -DEFINE_VIRT_MACHINE_AS_LATEST(9, 1) +DEFINE_VIRT_MACHINE_AS_LATEST(9, 2) + +static void virt_machine_9_1_options(MachineClass *mc) +{ + virt_machine_9_2_options(mc); + compat_props_add(mc->compat_props, hw_compat_9_1, hw_compat_9_1_len); +} +DEFINE_VIRT_MACHINE(9, 1) static void virt_machine_9_0_options(MachineClass *mc) { diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 370d7c35d3a..8aa3ce7449b 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -4838,14 +4838,25 @@ static void spapr_machine_latest_class_options(MachineClass *mc) DEFINE_SPAPR_MACHINE_IMPL(false, major, minor, _, tag) /* - * pseries-9.1 + * pseries-9.2 */ -static void spapr_machine_9_1_class_options(MachineClass *mc) +static void spapr_machine_9_2_class_options(MachineClass *mc) { /* Defaults for the latest behaviour inherited from the base class */ } -DEFINE_SPAPR_MACHINE_AS_LATEST(9, 1); +DEFINE_SPAPR_MACHINE_AS_LATEST(9, 2); + +/* + * pseries-9.1 + */ +static void spapr_machine_9_1_class_options(MachineClass *mc) +{ + spapr_machine_9_2_class_options(mc); + compat_props_add(mc->compat_props, hw_compat_9_1, hw_compat_9_1_len); +} + +DEFINE_SPAPR_MACHINE(9, 1); /* * pseries-9.0 diff --git a/hw/s390x/s390-virtio-ccw.c b/hw/s390x/s390-virtio-ccw.c index c483ff8064d..18240a0fd8b 100644 --- a/hw/s390x/s390-virtio-ccw.c +++ b/hw/s390x/s390-virtio-ccw.c @@ -871,14 +871,26 @@ static const TypeInfo ccw_machine_info = { DEFINE_CCW_MACHINE_IMPL(false, major, minor) +static void ccw_machine_9_2_instance_options(MachineState *machine) +{ +} + +static void ccw_machine_9_2_class_options(MachineClass *mc) +{ +} +DEFINE_CCW_MACHINE_AS_LATEST(9, 2); + static void ccw_machine_9_1_instance_options(MachineState *machine) { + ccw_machine_9_2_instance_options(machine); } static void ccw_machine_9_1_class_options(MachineClass *mc) { + ccw_machine_9_2_class_options(mc); + compat_props_add(mc->compat_props, hw_compat_9_1, hw_compat_9_1_len); } -DEFINE_CCW_MACHINE_AS_LATEST(9, 1); +DEFINE_CCW_MACHINE(9, 1); static void ccw_machine_9_0_instance_options(MachineState *machine) { From patchwork Thu Sep 5 13:00:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 825633 Delivered-To: patch@linaro.org Received: by 2002:adf:a345:0:b0:367:895a:4699 with SMTP id d5csp285897wrb; Thu, 5 Sep 2024 06:02:27 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXlqA2nWJ91CZi+CdJKeqN54ZYFzLQnZqNzLdeBIAotHmBYZunZisND8ZQNPYtbX8CPv3rkYA==@linaro.org X-Google-Smtp-Source: AGHT+IFxH/cglNjMRoLs6yO38CHFzf9BDGOnr/Z44qOCv69lU8hYUHrAR5d/d5lOQa07FPG2nrfz X-Received: by 2002:a05:6902:e0c:b0:e1a:b04d:673 with SMTP id 3f1490d57ef6-e1ab04d0883mr13615806276.55.1725541347747; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42bb6e355dfsm232251365e9.46.2024.09.05.06.01.10 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Sep 2024 06:01:10 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 11/25] hw/arm/smmuv3: Update comment documenting "stage" property Date: Thu, 5 Sep 2024 14:00:46 +0100 Message-Id: <20240905130100.298768-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240905130100.298768-1-peter.maydell@linaro.org> References: <20240905130100.298768-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org When we added support for nested (stage 1 + stage 2) translation to the SMMU in commit 58377c363291d we forgot to update the comment that documents the valid values of the "stage" property. Add the new "nested" value to it. Fixes: 58377c363291d ("hw/arm/smmuv3: Support and advertise nesting") Signed-off-by: Peter Maydell Reviewed-by: Eric Auger Reviewed-by: Daniel P. Berrangé Message-id: 20240816161350.3706332-3-peter.maydell@linaro.org --- hw/arm/smmuv3.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 39719763897..4c49b5a885f 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -1981,6 +1981,7 @@ static Property smmuv3_properties[] = { * Stages of translation advertised. * "1": Stage 1 * "2": Stage 2 + * "nested": Both stage 1 and stage 2 * Defaults to stage 1 */ DEFINE_PROP_STRING("stage", SMMUv3State, stage), From patchwork Thu Sep 5 13:00:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 825652 Delivered-To: patch@linaro.org Received: by 2002:adf:a345:0:b0:367:895a:4699 with SMTP id d5csp288317wrb; Thu, 5 Sep 2024 06:05:49 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCX7unvYIN26rX57AN7loLbl76mySv1Oo7X4JY2ptWMFOgt43boGFErs98TjxFads77x2mCSrQ==@linaro.org X-Google-Smtp-Source: AGHT+IGhHTK4LJ98g/lRilIeS8kua3kx+gbSCmCwC7ji72FiPUx4+PVSkEojMfOBWyTiQ+x1UmAD X-Received: by 2002:a05:620a:472b:b0:79c:c3d:9c22 with SMTP id af79cd13be357-7a98888f53bmr1060917685a.8.1725541548737; Thu, 05 Sep 2024 06:05:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1725541548; cv=none; d=google.com; s=arc-20240605; b=EsSIdN9rz7fUzZkN/0yhqu30vtpeqIW/BNNd9I8n5AwlCKSTZ/DpShLzqHxIQmMHIS 3uChWOfac4OhnVV+CPNoX2/GwacvS7kXHciWjtc3T9u9f1EANutdEwXATipht86TjtsI Z1TSCSxzMnWR8vz44+I181Lor/4wlQ+CTdiw2uZHjPig0F3yG+5COIOkEGyhe38g58J6 uV7kcgOlZV+yqrkAjfPpGv/+TlLS+IywisW+Q93INN4d52whZ8cc8/3GQNWUj/qJgfNg G+99RBiiABTZicScS8rjqdCIoT1eb/L3docXzTDGtkW1VHDceaMOda+wFofub4v27d68 beHg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=nOfGgKkVr27UMgs8upuHdRZMRcRcWoHqPVmmA3MjBFY=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=dD5T7Gn/BLT4btcjb4uWowXx9Rqlm8xVTVr+L7LV4teESRICslBLyfweOv73Kmpucb Wo+IJV2Z/n4R8Ardc5Pnj4HiPv9lecbTXDaiamu5xB3vLe8pz/EBovHR3mXi7fi3cxXG 0ivjTNuSX/KdPDxLdYI4lXaNbZnr1ecm2u6+OdTRvIlUIixKEpDKbsmaKb5cxhdL4TOy FEpsBjsQtTF+m2ePhRjkv35aShRPNRPis/ooSYEF1H04nQSCXWItXEHunf0rzvpxMVDn UaTmnPH1aZftdAfzM25qNxeB72KuYM/GG4jd+RvC+DY8hWvywvZzgX4d5YhXQtguIISP mQHA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=sEh+tkn7; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42bb6e355dfsm232251365e9.46.2024.09.05.06.01.10 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Sep 2024 06:01:11 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 12/25] hw/arm/virt: Default to two-stage SMMU from virt-9.2 Date: Thu, 5 Sep 2024 14:00:47 +0100 Message-Id: <20240905130100.298768-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240905130100.298768-1-peter.maydell@linaro.org> References: <20240905130100.298768-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Now that our SMMU model supports enabling both stages of translation at once, we can enable this in the virt board. This is no change in behaviour for guests, because if they simply ignore stage 2 and never configure it then it has no effect. For the usual backwards compatibility reasons we enable this only for machine types starting with 9.2. (Note that the SMMU is disabled by default on the virt board and is only created if the user passes the 'iommu=smmuv3' machine option.) Signed-off-by: Peter Maydell Reviewed-by: Eric Auger Reviewed-by: Daniel P. Berrangé Message-id: 20240816161350.3706332-4-peter.maydell@linaro.org --- include/hw/arm/virt.h | 1 + hw/arm/virt.c | 8 ++++++++ 2 files changed, 9 insertions(+) diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index a4d937ed45a..aca4f8061b1 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -134,6 +134,7 @@ struct VirtMachineClass { bool no_cpu_topology; bool no_tcg_lpa2; bool no_ns_el2_virt_timer_irq; + bool no_nested_smmu; }; struct VirtMachineState { diff --git a/hw/arm/virt.c b/hw/arm/virt.c index a5d3ad9bf9e..7934b236516 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1408,6 +1408,7 @@ static void create_pcie_irq_map(const MachineState *ms, static void create_smmu(const VirtMachineState *vms, PCIBus *bus) { + VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); char *node; const char compat[] = "arm,smmu-v3"; int irq = vms->irqmap[VIRT_SMMU]; @@ -1424,6 +1425,9 @@ static void create_smmu(const VirtMachineState *vms, dev = qdev_new(TYPE_ARM_SMMUV3); + if (!vmc->no_nested_smmu) { + object_property_set_str(OBJECT(dev), "stage", "nested", &error_fatal); + } object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus), &error_abort); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); @@ -3308,8 +3312,12 @@ DEFINE_VIRT_MACHINE_AS_LATEST(9, 2) static void virt_machine_9_1_options(MachineClass *mc) { + VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); + virt_machine_9_2_options(mc); compat_props_add(mc->compat_props, hw_compat_9_1, hw_compat_9_1_len); + /* 9.1 and earlier have only a stage-1 SMMU, not a nested s1+2 one */ + vmc->no_nested_smmu = true; } DEFINE_VIRT_MACHINE(9, 1) From patchwork Thu Sep 5 13:00:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 825647 Delivered-To: patch@linaro.org Received: by 2002:adf:a345:0:b0:367:895a:4699 with SMTP id d5csp287870wrb; Thu, 5 Sep 2024 06:05:11 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWw9lJp4/JWKBH7x8Ek3MtVtJ04+yxhVeDaGFcoQsm7vA1eNSeXfDrDOwx2VgWCWaJ+/25C1A==@linaro.org X-Google-Smtp-Source: AGHT+IGHzP/9nwu4WcR6YB24LqrV6upxHQDYMscQCrmQui+a816OnCxUZCFPOY6uFVDkT3x+izmZ X-Received: by 2002:a5d:4601:0:b0:374:baeb:2ec with SMTP id ffacd0b85a97d-3776f452f5bmr4144067f8f.19.1725541511101; Thu, 05 Sep 2024 06:05:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1725541511; cv=none; d=google.com; s=arc-20160816; b=Sr+NIrhx8acEMuAlCe0IZaRQwHepkMWzJcmlz1GaiKiBhh3pOINBigZz83GgJ30iR2 BqV69NsegC1jHXtr+pfWKL9GU76LZgEU3edkbAciR+LwNccn0JLXDqfqZw/YosO1jR19 kV/ywdg1f+y9DPdwrHbRU6IEZc6bNi0AGkuj4MHjHNCdbrw3NarEOEIcZT0T3+GoHyAl hQVNr1xMbm84X+E7aUGNyUTb6ce7aylX9eJJYmR1nV+aVhQ1Ah9OqkxwxEACUwfSHZt9 4oA8Enb8h9XIxb5qKE0q7brFakqalR6MTnw9T/GgIpuEi5inLPHqBY47hHe4czfQn7w8 ClKw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=/1zEM1x6OVqIhqR0ynhG68F5R1rKfetSPpPKrgmLcWE=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=kCngURjXe1FOSDqaFFrqr4MCJ4GxlAbnU9oWKeZtrpl3qw4ovKbci+24xQZ6nedQLE e28OfJ5XG5xEsIpavaBZUAsT3Y4cUzBNTpQ4I+zITMVvoVmTp5QEreXpVFDzzplDSiV6 IrfKUBGNAQWuwOHIQOVS6TS2VEt5LesmS47mtuaJyXuphqo+86vrHwz8RJrQEjIIPSFU FJvKaDk0LkZW/y1CNKGSwBgqfsNwqD7k40LTinI9797Fwz3ZcfgkxsGZ0XyVuKx/7c3Q woRshPZPm8Q8YFdXiAQs8KUdy746BdgA/wIutIEF2r43fQHArFcjEzVLDgGYHVVa5dl0 iDbQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Vo8NTsrL; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42bb6e355dfsm232251365e9.46.2024.09.05.06.01.11 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Sep 2024 06:01:11 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 13/25] hw/arm/sbsa-ref: Use two-stage SMMU Date: Thu, 5 Sep 2024 14:00:48 +0100 Message-Id: <20240905130100.298768-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240905130100.298768-1-peter.maydell@linaro.org> References: <20240905130100.298768-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Now that our SMMU model supports enabling both stages of translation at once, we can enable this in the sbsa-ref board. Existing guest code that only programs stage 1 and doesn't care about stage 2 should continue to run with the same behaviour, but guests that do want to do nested SMMU configurations can now do so. Signed-off-by: Peter Maydell Reviewed-by: Eric Auger Reviewed-by: Daniel P. Berrangé Reviewed-by: Marcin Juszkiewicz Message-id: 20240816161350.3706332-5-peter.maydell@linaro.org --- hw/arm/sbsa-ref.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index ae37a923015..396abe9c1bd 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -621,6 +621,7 @@ static void create_smmu(const SBSAMachineState *sms, PCIBus *bus) dev = qdev_new(TYPE_ARM_SMMUV3); + object_property_set_str(OBJECT(dev), "stage", "nested", &error_abort); object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus), &error_abort); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); From patchwork Thu Sep 5 13:00:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 825636 Delivered-To: patch@linaro.org Received: by 2002:adf:a345:0:b0:367:895a:4699 with SMTP id d5csp286276wrb; Thu, 5 Sep 2024 06:03:00 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWOtCGK80fahzJdfvy8zV/o+M5UMQNdNgpBMhDI0lbwNdiEYpxgyqlvpqVk9pnuR0fCd2m5DQ==@linaro.org X-Google-Smtp-Source: AGHT+IH4wRxPpInFZN7OqyZBQYa38okspb6XCZtopEw+7v382h0sKGEW6U6pok8yoqegKLw3vdG4 X-Received: by 2002:a05:690c:85:b0:675:a51b:fafd with SMTP id 00721157ae682-6db2373caafmr69857197b3.31.1725541380664; Thu, 05 Sep 2024 06:03:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1725541380; cv=none; d=google.com; s=arc-20160816; b=FNIjoE+nfptZ7ve6EOLnA8oa/WL8ABY0C1jxHET+p88NYkO1GsWrKojUN4POTSFAgk WXuDnEfnlxgTbXLCaCw5KoXOxMi2BS0cRbPlT+5bCvTzUKwQdZjBeEzjDR7Tq9L87jhz 4z3zX0tvqAeOXEfGU7/bsCYTusJ15v6NhiTb3aaF6gx8bxWyKs61/Z6Ruj4/1ZsL6ir3 BSC6Nrd6IFKTZ3V6wdZpRPoWI3OH+5PWNz8oem+eXMwszXmJIEYB518P73OyfSbfJGtD wh5rHJFTM0IkNCy4yefhnVFBoZrx8A/cIPHG8aYryVWxxX3bq/KZv2lVYt7N9hyQ7wRK lZgA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Vp6jqJWQJM20UmlkjdFnqB0qa1tAd5oRc0QPjbGe4sk=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=uCQz38FaZqchmqXTVWEcQWIiqF6B3d6MibtD+EqzfbqfkgKoM1NUD9WipRCuaAzMGl xdaH9eEILY0nxMjw5NB4iQ4B+vhAm2g6OltFJyvwRhHcxh6qzFL4kZNN3iRo6T8QIopZ sW6DRzgG1gR7/a5qDcndihJQMluFTzDOcW46w6HfDSTkXyGE1p4FqNRP8XR0pxO9p9UK J4jx3Sy/fqP2piKPq2YjyjbD/BPOU8omNQsLM1BTao40y6vqP5Bpb91A+rvMyesFqJSf fsEFno/2/Jax+5AXiVToh7QVQB++oLKBZVC2f846erE/1US1ugbC9aVqssaMy6jE/Wh6 3NSg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=bC14IM1x; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42bb6e355dfsm232251365e9.46.2024.09.05.06.01.12 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Sep 2024 06:01:12 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 14/25] hw/misc/xlnx-versal-cfu: destroy fifo in finalize Date: Thu, 5 Sep 2024 14:00:49 +0100 Message-Id: <20240905130100.298768-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240905130100.298768-1-peter.maydell@linaro.org> References: <20240905130100.298768-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Since the TYPE_XNLX_VERSAL_CFU_FDRO device creates a FIFO in its instance_init method, we must destroy the FIFO in instance_finalize to avoid a memory leak for the QOM introspection "instantiate-examine-finalize" cycle: Direct leak of 8192 byte(s) in 1 object(s) allocated from: #0 0x55ec89eae7ee in malloc (/mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/asan/qemu-system-aarch64+0x294d7ee) (BuildId: 6d508874816cc47d17c8dd775e8f809ae520e8cb) #1 0x7f697018f738 in g_malloc debian/build/deb/../../../glib/gmem.c:128:13 #2 0x55ec8d98d98d in fifo8_create util/fifo8.c:27:18 #3 0x55ec8aa2a624 in fifo32_create /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/include/qemu/fifo32.h:35:5 #4 0x55ec8aa2a33c in cfu_fdro_init hw/misc/xlnx-versal-cfu.c:397:5 #5 0x55ec8ce75da1 in object_init_with_type qom/object.c:420:9 #6 0x55ec8ce5d07b in object_initialize_with_type qom/object.c:562:5 #7 0x55ec8ce5e91d in object_new_with_type qom/object.c:782:5 #8 0x55ec8ce5e9f1 in object_new qom/object.c:797:12 #9 0x55ec8d65c81d in qmp_device_list_properties qom/qom-qmp-cmds.c:144:11 Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias Reviewed-by: Francisco Iglesias Reviewed-by: Alistair Francis Message-id: 20240822162127.705879-2-peter.maydell@linaro.org --- hw/misc/xlnx-versal-cfu.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/hw/misc/xlnx-versal-cfu.c b/hw/misc/xlnx-versal-cfu.c index 6bb82e51c15..2284b407eab 100644 --- a/hw/misc/xlnx-versal-cfu.c +++ b/hw/misc/xlnx-versal-cfu.c @@ -397,6 +397,13 @@ static void cfu_fdro_init(Object *obj) fifo32_create(&s->fdro_data, 8 * KiB / sizeof(uint32_t)); } +static void cfu_fdro_finalize(Object *obj) +{ + XlnxVersalCFUFDRO *s = XLNX_VERSAL_CFU_FDRO(obj); + + fifo32_destroy(&s->fdro_data); +} + static void cfu_fdro_reset_enter(Object *obj, ResetType type) { XlnxVersalCFUFDRO *s = XLNX_VERSAL_CFU_FDRO(obj); @@ -539,6 +546,7 @@ static const TypeInfo cfu_fdro_info = { .instance_size = sizeof(XlnxVersalCFUFDRO), .class_init = cfu_fdro_class_init, .instance_init = cfu_fdro_init, + .instance_finalize = cfu_fdro_finalize, .interfaces = (InterfaceInfo[]) { { TYPE_XLNX_CFI_IF }, { } From patchwork Thu Sep 5 13:00:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 825644 Delivered-To: patch@linaro.org Received: by 2002:adf:a345:0:b0:367:895a:4699 with SMTP id d5csp286834wrb; Thu, 5 Sep 2024 06:03:45 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVu/TaQsGiCBerJlPq1IbOKNBDwx4IwbgGqQ/POLoJJ0mUNLGza5oYWo4sWF7/plREpV8aJJg==@linaro.org X-Google-Smtp-Source: AGHT+IEHl4INHYpw9W2zQPtwvc/DJ9FX0H+xM2in6HZrKPdUA9Umce98sXFFb9EuwSdOPea0ygsQ X-Received: by 2002:a05:600c:3584:b0:42b:afd8:7568 with SMTP id 5b1f17b1804b1-42bdc64e498mr128345315e9.23.1725541425137; Thu, 05 Sep 2024 06:03:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1725541425; cv=none; d=google.com; s=arc-20160816; b=MAwFRLtLMK3FM5U1yWmC587F8ZcBhTxa0P2K5F5fEHZxLrFXrEjzgG09WkJIgFiAUP Az1cn3C0OxAqdKnitZ9Io4+V7EuMX4A+xlJnmJhwDYcjltZ/T26MKK00en6bMVYTSukg iJ1W/fCQHxlAQ0DmxBzCaZxkAd7tmuqoIkkgN/fI+ngeEidsmSk/sU3YdDwrksABKOAh 0/tIVRJG7EBbcWGVFr2UxyrkSnVh7N3uwlvJyNE5uouhbEN/v5fjmEEwo4ZsevstwqRM /ZsxK/7UpObZaDLTqN/QxNYlaacg9EFVyXoVdH9e63mv8s1UnsHjG9UDyK5noPW++P/T /lhA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=y0cwAM8oBFk44DfdOjrDHqS5VWYwMHEPi8SwQKNFB24=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=j/qMbf73BdlLKCktmoF1ektm4Ko++7ZpIVF4agpLygTibkZtP/3P+Hc53HpoUQ16xD vxVSt7rDThIGyZQY4hR4D0zEhPN5h9YV5NFheFV9IrObPu8Itjr02Orljz+zIt3QdGW0 zRsSe6pJUS5OxYuNrgCOl7S6k4cP0OY5hrdIXfRnyucYIWyWnmCVqTocg+/gzmIt4Keo nRo/NH95O1bAxGr+sjM+uhpw+rrCzMTcjrCXOvlrK/tqlVC13tbd+DcaPXFNeSpc1Ty2 9XN8P2Ujt75UVOTIxx3XL3CCjEy1YNgGydpRng0nDwGA+4H0bkeeIHj7CGNFpGyCavCQ OZBg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=AjkOTaSU; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42bb6e355dfsm232251365e9.46.2024.09.05.06.01.12 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Sep 2024 06:01:12 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 15/25] hw/misc/xlnx-versal-trng: Free s->prng in finalize, not unrealize Date: Thu, 5 Sep 2024 14:00:50 +0100 Message-Id: <20240905130100.298768-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240905130100.298768-1-peter.maydell@linaro.org> References: <20240905130100.298768-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The TYPE_XLNX_VERSAL_TRNG device creates s->prng with g_rand_new() in its init method, but it frees it in its unrealize method. This results in a leak in the QOM introspection "initialize-inspect-finalize" lifecycle: Direct leak of 2500 byte(s) in 1 object(s) allocated from: #0 0x55ec89eae9d8 in __interceptor_calloc (/mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/asan/qemu-system-aarch64+0x294d9d8) (BuildId: 6d5 08874816cc47d17c8dd775e8f809ae520e8cb) #1 0x7f697018fc50 in g_malloc0 debian/build/deb/../../../glib/gmem.c:161:13 #2 0x7f6970197738 in g_rand_new_with_seed_array debian/build/deb/../../../glib/grand.c:202:17 #3 0x7f6970197816 in g_rand_new debian/build/deb/../../../glib/grand.c:286:10 #4 0x55ec8aa3656a in trng_init hw/misc/xlnx-versal-trng.c:624:15 #5 0x55ec8ce75da1 in object_init_with_type qom/object.c:420:9 #6 0x55ec8ce5d07b in object_initialize_with_type qom/object.c:562:5 #7 0x55ec8ce5e91d in object_new_with_type qom/object.c:782:5 #8 0x55ec8ce5e9f1 in object_new qom/object.c:797:12 #9 0x55ec8d65c81d in qmp_device_list_properties qom/qom-qmp-cmds.c:144:11 Move the free to finalize so it matches where we are initing s->prng. Since that's the only thing our unrealize method was doing, this essentially switches the whole function to be a finalize implementation. Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias Reviewed-by: Francisco Iglesias Reviewed-by: Alistair Francis Message-id: 20240822162127.705879-3-peter.maydell@linaro.org --- hw/misc/xlnx-versal-trng.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/misc/xlnx-versal-trng.c b/hw/misc/xlnx-versal-trng.c index 51eb7600414..c0d1dde8708 100644 --- a/hw/misc/xlnx-versal-trng.c +++ b/hw/misc/xlnx-versal-trng.c @@ -624,9 +624,9 @@ static void trng_init(Object *obj) s->prng = g_rand_new(); } -static void trng_unrealize(DeviceState *dev) +static void trng_finalize(Object *obj) { - XlnxVersalTRng *s = XLNX_VERSAL_TRNG(dev); + XlnxVersalTRng *s = XLNX_VERSAL_TRNG(obj); g_rand_free(s->prng); s->prng = NULL; @@ -689,7 +689,6 @@ static void trng_class_init(ObjectClass *klass, void *data) ResettableClass *rc = RESETTABLE_CLASS(klass); dc->vmsd = &vmstate_trng; - dc->unrealize = trng_unrealize; rc->phases.hold = trng_reset_hold; /* Clone uint64 property with set allowed after realized */ @@ -706,6 +705,7 @@ static const TypeInfo trng_info = { .instance_size = sizeof(XlnxVersalTRng), .class_init = trng_class_init, .instance_init = trng_init, + .instance_finalize = trng_finalize, }; static void trng_register_types(void) From patchwork Thu Sep 5 13:00:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 825631 Delivered-To: patch@linaro.org Received: by 2002:adf:a345:0:b0:367:895a:4699 with SMTP id d5csp285567wrb; Thu, 5 Sep 2024 06:02:03 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUdTqp3N0nkTq1cmRqdE+IH2TVHJf3T6q13xT9xNMeYg84z6h9vvohisTA6MOH1D2A0mk+tig==@linaro.org X-Google-Smtp-Source: AGHT+IHfBAwJ4KaYi7SnAoCJUX0sZmzyY6BbHYGbzfAwY8BNzIikJH07cjPNzx4bPvs3rm1CdFKA X-Received: by 2002:a05:6902:707:b0:e1d:f5c:97d6 with SMTP id 3f1490d57ef6-e1d0f5c9a14mr7515308276.51.1725541323386; Thu, 05 Sep 2024 06:02:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1725541323; cv=none; d=google.com; s=arc-20160816; b=KmASRRWqX7bR6gNHaE0Nzptkgdp7yaVE5OH12k9QgmU6LLcmIXaMREhyCH+/WEStJP jtuhlp7LBSG1z6xHJVeiPx9WzitkmW+ftD3Gr9esPirFaZ2UHd0v9Z9t/uuQzNwaSXie pAio4SEUmhAB2kr30QRBwkTDPVL3lBkBFZ0cpnm1T/ZWTjhc26ZNoFWgLrpggrFtWUDX jimdY68h2UeMzpQEpkccDqL3z8NJgI9ynrvWj+5xP/0mh089J6o9Ft4MIVPNVc1LH1ps ANYWzCER0xMkpnbUyyudifegMPQC34PTdAyf3SlIJDeXVssbc7LGjKQuLi7ubjK66VaR 6hRQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=b1yg3Idz1Ekq5+f2VLIMP8Rh4xmuLplWauidI9V+Kp4=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=i3Z1+Ic4RXWb4v7EsSbhf/lQQcPNf3ZuBYG8tAmdflT421OdxtyBNpibiAjZ174c55 4IGLN7pHcMRrR1I5SvAlbPKrlPdnoZL1QgukdfGvfMmTABtESLMtY8xKAa1Aj0ploh66 bnvS2skHKMD9wDdvjVYOuyHdsXRDF9bAVw8u8zDE2ZBpFz7wSEOej+PvYzsq33ntMicf hyg+NcUO2y6hzVJNaFGszy+KrhtMjqxPjzjKe8TVwGbkLDMNubLV6m+58c0wrfghHDGu Pjq9MQWvuRG2m/W6H0TC2z8fIp8K1TqGjRwAge/TdXP/713t1rc247rWvzvRWzsZQPXg 8sxQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="vKopu4/A"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42bb6e355dfsm232251365e9.46.2024.09.05.06.01.13 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Sep 2024 06:01:13 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 16/25] hw/nvram/xlnx-bbram: Call register_finalize_block Date: Thu, 5 Sep 2024 14:00:51 +0100 Message-Id: <20240905130100.298768-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240905130100.298768-1-peter.maydell@linaro.org> References: <20240905130100.298768-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The TYPE_XLNX_BBRAM device creates a register block with register_init_block32() in its instance_init method; we must therefore destroy it in our instance_finalize method to avoid a leak in the QOM introspection "init-inspect-finalize" lifecycle: Direct leak of 304 byte(s) in 1 object(s) allocated from: #0 0x5641518ca9d8 in __interceptor_calloc (/mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/asan/qemu-system-aarch64+0x294d9d8) (BuildId: 4a6 18cb63d57d5a19ed45cfc262b08da47eaafe5) #1 0x7ff1aab31c50 in g_malloc0 debian/build/deb/../../../glib/gmem.c:161:13 #2 0x564151cffc5d in register_init_block hw/core/register.c:248:34 #3 0x564151d006be in register_init_block32 hw/core/register.c:299:12 #4 0x56415293df75 in bbram_ctrl_init hw/nvram/xlnx-bbram.c:462:9 #5 0x564154891dc1 in object_init_with_type qom/object.c:420:9 #6 0x56415487909b in object_initialize_with_type qom/object.c:562:5 #7 0x56415487a93d in object_new_with_type qom/object.c:782:5 #8 0x56415487aa11 in object_new qom/object.c:797:12 #9 0x56415507883d in qmp_device_list_properties qom/qom-qmp-cmds.c:144:11 Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias Reviewed-by: Francisco Iglesias Reviewed-by: Alistair Francis Message-id: 20240822162127.705879-4-peter.maydell@linaro.org --- include/hw/nvram/xlnx-bbram.h | 1 + hw/nvram/xlnx-bbram.c | 13 ++++++++++--- 2 files changed, 11 insertions(+), 3 deletions(-) diff --git a/include/hw/nvram/xlnx-bbram.h b/include/hw/nvram/xlnx-bbram.h index 6fc13f8cc17..bce8e89d905 100644 --- a/include/hw/nvram/xlnx-bbram.h +++ b/include/hw/nvram/xlnx-bbram.h @@ -47,6 +47,7 @@ struct XlnxBBRam { bool bbram8_wo; bool blk_ro; + RegisterInfoArray *reg_array; uint32_t regs[RMAX_XLNX_BBRAM]; RegisterInfo regs_info[RMAX_XLNX_BBRAM]; }; diff --git a/hw/nvram/xlnx-bbram.c b/hw/nvram/xlnx-bbram.c index 09575a77d77..1bc58e90ad0 100644 --- a/hw/nvram/xlnx-bbram.c +++ b/hw/nvram/xlnx-bbram.c @@ -456,9 +456,8 @@ static void bbram_ctrl_init(Object *obj) { XlnxBBRam *s = XLNX_BBRAM(obj); SysBusDevice *sbd = SYS_BUS_DEVICE(obj); - RegisterInfoArray *reg_array; - reg_array = + s->reg_array = register_init_block32(DEVICE(obj), bbram_ctrl_regs_info, ARRAY_SIZE(bbram_ctrl_regs_info), s->regs_info, s->regs, @@ -466,10 +465,17 @@ static void bbram_ctrl_init(Object *obj) XLNX_BBRAM_ERR_DEBUG, R_MAX * 4); - sysbus_init_mmio(sbd, ®_array->mem); + sysbus_init_mmio(sbd, &s->reg_array->mem); sysbus_init_irq(sbd, &s->irq_bbram); } +static void bbram_ctrl_finalize(Object *obj) +{ + XlnxBBRam *s = XLNX_BBRAM(obj); + + register_finalize_block(s->reg_array); +} + static void bbram_prop_set_drive(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { @@ -537,6 +543,7 @@ static const TypeInfo bbram_ctrl_info = { .instance_size = sizeof(XlnxBBRam), .class_init = bbram_ctrl_class_init, .instance_init = bbram_ctrl_init, + .instance_finalize = bbram_ctrl_finalize, }; static void bbram_ctrl_register_types(void) From patchwork Thu Sep 5 13:00:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 825648 Delivered-To: patch@linaro.org Received: by 2002:adf:a345:0:b0:367:895a:4699 with SMTP id d5csp288096wrb; Thu, 5 Sep 2024 06:05:31 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXEb5d0VJ28pu9Vsu4XB8K8hyEEz9WpaIE6yeHGzYTtHZw0T8JArNxXEbRu73gjJgUdeSk9yQ==@linaro.org X-Google-Smtp-Source: AGHT+IH5Bj+H0egx2QYTp2rdJU1H3DzJYnvX67UNJFIWMVRP1aQWLkYqHZ9rUSl8kmWIN2zdg6bs X-Received: by 2002:a05:6122:ca2:b0:4ef:5e6b:98c0 with SMTP id 71dfb90a1353d-4fff16b0c7bmr26940152e0c.9.1725541531517; Thu, 05 Sep 2024 06:05:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1725541531; cv=none; d=google.com; s=arc-20160816; b=mo4EbIAJ8WfBapuB43BLurEuAA5tpQ2qnPHy+gJFwHBNl0kIzFEZLgd/ANDhOtKwCA DBmkT/qUuQxNMbbwhGBZWdDVFdoIF90uPfp1uWNDQM0jixGpYfOoGa42qsis6bGJS9Gt v0iQW5r6FNAeXyYGtkfvvI3shNq5kvaTJaMWlEuaXtoIosE1gC8ziEmcgmFykaltYoYI V6b0NiCXN3oXNsqPckdq9LsZv/gXScwyFUfI4Sck4zXZ6LrH1eKL68goQpHDay6voiMW Qv/xbRUX7vIsuJG9evjXw0lmJXoIpi0aRtiqsX5tK59vW8WAcsNjYHTy4xXFp44jdVcD uBjQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=gmfGmCF7V52uoovNppJezdO9CidRm7THzM8TZjnq7mI=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=qheZIZd8WtW5mN3gVgzosGR/Exaz8QCUcLQtA9jWucXTM+yly9e7WpLKGNsZMC/KCf Z96gTnHlElPkP0G2aYhEAc4HrlzMpf7svANV5EchIYX3CgzE+ARj2KJzpUxXSne+JnY+ E3IZzSmrIbriHxtUGt1NbohInUYvCOHbY6Q46bSZEOVBYTlxVF2D7PMx1NHFey+kNB5r XqZOEDyhPfoC8b8Mf5pC+zt5l5Cd3gXTa/28Ng/b3UEPBghthairZmIxlaZBA5ySNDWp 8C3TwNcAWvaIMYiYpfDl1T1DK+3z4T+gSUi+bicy5pqZxWL3WXXHE7fsvOOcHVK5FzCT PwcQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=SLzfDl2R; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42bb6e355dfsm232251365e9.46.2024.09.05.06.01.13 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Sep 2024 06:01:13 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 17/25] hw/nvram/xlnx-zynqmp-efuse: Call register_finalize_block Date: Thu, 5 Sep 2024 14:00:52 +0100 Message-Id: <20240905130100.298768-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240905130100.298768-1-peter.maydell@linaro.org> References: <20240905130100.298768-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The TYPE_XLNX_ZYNQMP_EFUSE device creates a register block with register_init_block32() in its instance_init method; we must therefore destroy it in our instance_finalize method to avoid a leak in the QOM introspection "init-inspect-finalize" lifecycle: Direct leak of 304 byte(s) in 1 object(s) allocated from: #0 0x55f3ff5839d8 in __interceptor_calloc (/mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/asan/qemu-system-aarch64+0x294d9d8) (BuildId: 23cf931c66865a71b6cc4da95156d03bc106fa72) #1 0x7f3f31c6bc50 in g_malloc0 debian/build/deb/../../../glib/gmem.c:161:13 #2 0x55f3ff9b8c5d in register_init_block hw/core/register.c:248:34 #3 0x55f3ff9b96be in register_init_block32 hw/core/register.c:299:12 #4 0x55f4005e5b25 in efuse_ctrl_init hw/nvram/xlnx-versal-efuse-ctrl.c:718:9 #5 0x55f40254afb1 in object_init_with_type qom/object.c:420:9 #6 0x55f40253228b in object_initialize_with_type qom/object.c:562:5 #7 0x55f402533b2d in object_new_with_type qom/object.c:782:5 #8 0x55f402533c01 in object_new qom/object.c:797:12 #9 0x55f402d31a2d in qmp_device_list_properties qom/qom-qmp-cmds.c:144:11 Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias Reviewed-by: Francisco Iglesias Reviewed-by: Alistair Francis Message-id: 20240822162127.705879-5-peter.maydell@linaro.org --- include/hw/nvram/xlnx-zynqmp-efuse.h | 1 + hw/nvram/xlnx-zynqmp-efuse.c | 13 ++++++++++--- 2 files changed, 11 insertions(+), 3 deletions(-) diff --git a/include/hw/nvram/xlnx-zynqmp-efuse.h b/include/hw/nvram/xlnx-zynqmp-efuse.h index f5beacc2e6a..7fb12df3fbb 100644 --- a/include/hw/nvram/xlnx-zynqmp-efuse.h +++ b/include/hw/nvram/xlnx-zynqmp-efuse.h @@ -37,6 +37,7 @@ struct XlnxZynqMPEFuse { qemu_irq irq; XlnxEFuse *efuse; + RegisterInfoArray *reg_array; uint32_t regs[XLNX_ZYNQMP_EFUSE_R_MAX]; RegisterInfo regs_info[XLNX_ZYNQMP_EFUSE_R_MAX]; }; diff --git a/hw/nvram/xlnx-zynqmp-efuse.c b/hw/nvram/xlnx-zynqmp-efuse.c index 2d465f0fc6a..4e2d1b9d1e7 100644 --- a/hw/nvram/xlnx-zynqmp-efuse.c +++ b/hw/nvram/xlnx-zynqmp-efuse.c @@ -803,9 +803,8 @@ static void zynqmp_efuse_init(Object *obj) { XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(obj); SysBusDevice *sbd = SYS_BUS_DEVICE(obj); - RegisterInfoArray *reg_array; - reg_array = + s->reg_array = register_init_block32(DEVICE(obj), zynqmp_efuse_regs_info, ARRAY_SIZE(zynqmp_efuse_regs_info), s->regs_info, s->regs, @@ -813,10 +812,17 @@ static void zynqmp_efuse_init(Object *obj) ZYNQMP_EFUSE_ERR_DEBUG, R_MAX * 4); - sysbus_init_mmio(sbd, ®_array->mem); + sysbus_init_mmio(sbd, &s->reg_array->mem); sysbus_init_irq(sbd, &s->irq); } +static void zynqmp_efuse_finalize(Object *obj) +{ + XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(obj); + + register_finalize_block(s->reg_array); +} + static const VMStateDescription vmstate_efuse = { .name = TYPE_XLNX_ZYNQMP_EFUSE, .version_id = 1, @@ -853,6 +859,7 @@ static const TypeInfo efuse_info = { .instance_size = sizeof(XlnxZynqMPEFuse), .class_init = zynqmp_efuse_class_init, .instance_init = zynqmp_efuse_init, + .instance_finalize = zynqmp_efuse_finalize, }; static void efuse_register_types(void) From patchwork Thu Sep 5 13:00:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 825650 Delivered-To: patch@linaro.org Received: by 2002:adf:a345:0:b0:367:895a:4699 with SMTP id d5csp288105wrb; Thu, 5 Sep 2024 06:05:32 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCX+ZYsnTBdCXYki/GvDpvp65X1no2wlWkWhwqrwuN9NvjA3mY8LSr4WyblrZMo+/xNKlug5Uw==@linaro.org X-Google-Smtp-Source: AGHT+IFOMFswdWiYAyyQyQTeYZLroKu27mlL1cTTLvWnqxHJnPK7mNq+qt/U4/3pFOiSm5k6b6tf X-Received: by 2002:a05:690c:f0e:b0:6bd:e76d:19ea with SMTP id 00721157ae682-6d40d88f66fmr247076457b3.8.1725541532257; Thu, 05 Sep 2024 06:05:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1725541532; cv=none; d=google.com; s=arc-20160816; b=VYPXnukyQGeCRVgj9WYQlP7O8aiOk3jMo0XnQmBdxx8ePKqtPMAZuMmKxUqbtuzoiH hbnrZ/7KS66OBVCNSjmzx6lVzKYeBhZe/HjSBER3xstAHhGFZZCz0bpo3BBHJ/O++IGz df8Fcz3U+LU+Ofa+cmthh+28Rr7CBZ98evegZDYIpVlBFWsR+kwWGw/xXifvJAM9j6kC uE+yDyWVOAiZaTYXEs3Dfs1Z+xo9sqrQ8PDI2m3ibW332scGYRQDVKT4rs0CCrLWHiMl j1ViYFOHAL3fHCUIvKD/zYRYY90yRFVdTytfV6GNt/nW2BcGFBdGkjA2g0DgF8kZ0jiC tViw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=yNRTbINTbj/l4s3T+Yhp0ouEZCk2q0YhAmbisqItYZM=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=KW1mbEEcNZCRKtNUF2kQfvI+6sUj5Plv67mi4nYobSiORIUeiw7ZWOSMnJv5gHB1e6 0ucgyYhP74mFfaHxghR01j29Nmg4b79FpJ78RW9bNS8m5klOLo0CcpYEkd+Wx/Vv+C0D fDTDeZIUYZmLj9HvAK+M2RjxQG1cQ5hMZjH7MmJZX016Md4jKOrZ7dSul4qIG8vdUyZd +a2SYmzJ4leLvJfDrKaWy3z5RppHbfPC/tFos+Zi/0JNX2cvbovMLL8W7ZOAILKadMLD kJV2XUWhMDsG9f2RHK8VndHYWIZ34++KfuPUAXAvanj3RbrOCfDL1RXvwB/qRbbEN/Ox zKrA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="Uf/Da5iw"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42bb6e355dfsm232251365e9.46.2024.09.05.06.01.14 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Sep 2024 06:01:14 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 18/25] hw/misc/xlnx-versal-trng: Call register_finalize_block Date: Thu, 5 Sep 2024 14:00:53 +0100 Message-Id: <20240905130100.298768-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240905130100.298768-1-peter.maydell@linaro.org> References: <20240905130100.298768-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The TYPE_XLNX_VERSAL_TRNG device creates a register block with register_init_block32() in its instance_init method; we must therefore destroy it in our instance_finalize method to avoid a leak in the QOM introspection "init-inspect-finalize" lifecycle: Direct leak of 304 byte(s) in 1 object(s) allocated from: #0 0x55842ec799d8 in __interceptor_calloc (/mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/asan/qemu-system-aarch64+0x294e9d8) (BuildId: 47496e53f3e779f1c7e9b82cbea07407152b498b) #1 0x7fe793c75c50 in g_malloc0 debian/build/deb/../../../glib/gmem.c:161:13 #2 0x55842f0aec5d in register_init_block hw/core/register.c:248:34 #3 0x55842f0af6be in register_init_block32 hw/core/register.c:299:12 #4 0x55842f801588 in trng_init hw/misc/xlnx-versal-trng.c:614:9 #5 0x558431c411a1 in object_init_with_type qom/object.c:420:9 #6 0x558431c2847b in object_initialize_with_type qom/object.c:562:5 #7 0x558431c29d1d in object_new_with_type qom/object.c:782:5 #8 0x558431c29df1 in object_new qom/object.c:797:12 #9 0x558432427c1d in qmp_device_list_properties qom/qom-qmp-cmds.c:144:11 Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias Reviewed-by: Francisco Iglesias Reviewed-by: Alistair Francis Message-id: 20240822162127.705879-6-peter.maydell@linaro.org --- include/hw/misc/xlnx-versal-trng.h | 1 + hw/misc/xlnx-versal-trng.c | 6 +++--- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/include/hw/misc/xlnx-versal-trng.h b/include/hw/misc/xlnx-versal-trng.h index 0bcef8a6132..d96f8f9eff3 100644 --- a/include/hw/misc/xlnx-versal-trng.h +++ b/include/hw/misc/xlnx-versal-trng.h @@ -50,6 +50,7 @@ typedef struct XlnxVersalTRng { uint64_t forced_prng_count; uint64_t tst_seed[2]; + RegisterInfoArray *reg_array; uint32_t regs[RMAX_XLNX_VERSAL_TRNG]; RegisterInfo regs_info[RMAX_XLNX_VERSAL_TRNG]; } XlnxVersalTRng; diff --git a/hw/misc/xlnx-versal-trng.c b/hw/misc/xlnx-versal-trng.c index c0d1dde8708..86905479b8f 100644 --- a/hw/misc/xlnx-versal-trng.c +++ b/hw/misc/xlnx-versal-trng.c @@ -608,9 +608,8 @@ static void trng_init(Object *obj) { XlnxVersalTRng *s = XLNX_VERSAL_TRNG(obj); SysBusDevice *sbd = SYS_BUS_DEVICE(obj); - RegisterInfoArray *reg_array; - reg_array = + s->reg_array = register_init_block32(DEVICE(obj), trng_regs_info, ARRAY_SIZE(trng_regs_info), s->regs_info, s->regs, @@ -618,7 +617,7 @@ static void trng_init(Object *obj) XLNX_VERSAL_TRNG_ERR_DEBUG, R_MAX * 4); - sysbus_init_mmio(sbd, ®_array->mem); + sysbus_init_mmio(sbd, &s->reg_array->mem); sysbus_init_irq(sbd, &s->irq); s->prng = g_rand_new(); @@ -628,6 +627,7 @@ static void trng_finalize(Object *obj) { XlnxVersalTRng *s = XLNX_VERSAL_TRNG(obj); + register_finalize_block(s->reg_array); g_rand_free(s->prng); s->prng = NULL; } From patchwork Thu Sep 5 13:00:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 825635 Delivered-To: patch@linaro.org Received: by 2002:adf:a345:0:b0:367:895a:4699 with SMTP id d5csp286161wrb; Thu, 5 Sep 2024 06:02:50 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXPiEWhA93EIJ8QKxks5WI9/lBpYQ+rvy5mkqpxgcS7GIzhYH8q4XgmoyuE+J2H5CNPfWS3Mw==@linaro.org X-Google-Smtp-Source: AGHT+IEl0mZtLyTtGG5gw7xGO+nf8volAwRKaLp8rKwVasamf5FsRxkNpkb2KP7QTnG/OhfQAGiB X-Received: by 2002:adf:f745:0:b0:374:bd00:d1e with SMTP id ffacd0b85a97d-377998aafbcmr3628814f8f.3.1725541370315; Thu, 05 Sep 2024 06:02:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1725541370; cv=none; d=google.com; s=arc-20160816; b=Wto40ckbd8Kex9QH1NasMEOQc+57f+9kmzcBoneUtPO6DLRUFUq0DCaO1zORPatdCM HJZigAgVPQWE9MWA3wA3ItqwF+m8rCIdPnzK4XAMzb43xMkVpvbsvNUSohgbs6LgkkHQ GetczO2e9dhjDRL/PQQmWNN4G2k4w7KFCeNKZvxB6+QnLcZbJlySsM9vwGPHJOuHNJkq jL3hpV0gK0hHWhEhbwTujHzyRPvR2seX+1gMZRHJR4xV+ioClnuYA4y7TvW9bry6EnOq L4inDhYBT2lR+wn+BJhfwcwDUDuKDIuN2ilKQhMYmWB3wdAC5L7IE+ROzZ+laXS1IQey 11bg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=MbgnugOLDPgGJXXw23NZotuiUGw5cYgIj0uJ8JeImbY=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=eTkd17feTNOs0Y5/e7vGE52A7a6a/w13fI1gQPxM/Au2zu4GoGeJd5r0QAAdp1FVqH 3/9Y75wUy+goCQ0RUH/dw/xycH4YdkJAkqS3p25Ta3xEJrgOgPCytd/0Ng2+P3FiM+5h 7d/oCKvT6lZaC8nKzZkfAkCbHePN78YxgISXsibJsjzs/ZspnpD+2gtrsgbQMGxx+FsN TLoIhJRprfODbBaDbCiI1Co2mGUMv8siqxlwW8ooKBaIxcoQZvY/Q7Mho6ynUkliL+Z/ oqqQm15Yl6j8jPAoGL1G/D9/f3reLDRO3z+zTUlS20qg69A+XolyT0oN+oqRvm81C7PZ 3aEw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=fwk9QPEf; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42bb6e355dfsm232251365e9.46.2024.09.05.06.01.14 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Sep 2024 06:01:14 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 19/25] hm/nvram/xlnx-versal-efuse-ctrl: Call register_finalize_block Date: Thu, 5 Sep 2024 14:00:54 +0100 Message-Id: <20240905130100.298768-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240905130100.298768-1-peter.maydell@linaro.org> References: <20240905130100.298768-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The TYPE_XLNX_VERSAL_EFUSE_CTRL device creates a register block with register_init_block32() in its instance_init method; we must therefore destroy it in our instance_finalize method to avoid a leak in the QOM introspection "init-inspect-finalize" lifecycle: Direct leak of 304 byte(s) in 1 object(s) allocated from: #0 0x55f222b5b9d8 in __interceptor_calloc (/mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/asan/qemu-system-aarch64+0x294e9d8) (BuildId: 420 43d49e1139e3f3071b1f22fac1e3e7249c9a6) #1 0x7fbb10669c50 in g_malloc0 debian/build/deb/../../../glib/gmem.c:161:13 #2 0x55f222f90c5d in register_init_block hw/core/register.c:248:34 #3 0x55f222f916be in register_init_block32 hw/core/register.c:299:12 #4 0x55f223bbdd15 in efuse_ctrl_init hw/nvram/xlnx-versal-efuse-ctrl.c:718:9 #5 0x55f225b23391 in object_init_with_type qom/object.c:420:9 #6 0x55f225b0a66b in object_initialize_with_type qom/object.c:562:5 #7 0x55f225b0bf0d in object_new_with_type qom/object.c:782:5 #8 0x55f225b0bfe1 in object_new qom/object.c:797:12 #9 0x55f226309e0d in qmp_device_list_properties qom/qom-qmp-cmds.c:144:11 Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias Reviewed-by: Francisco Iglesias Reviewed-by: Alistair Francis Message-id: 20240822162127.705879-7-peter.maydell@linaro.org --- include/hw/nvram/xlnx-versal-efuse.h | 1 + hw/nvram/xlnx-versal-efuse-ctrl.c | 6 +++--- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/include/hw/nvram/xlnx-versal-efuse.h b/include/hw/nvram/xlnx-versal-efuse.h index 86e2261b9a3..afa4f4f9960 100644 --- a/include/hw/nvram/xlnx-versal-efuse.h +++ b/include/hw/nvram/xlnx-versal-efuse.h @@ -44,6 +44,7 @@ struct XlnxVersalEFuseCtrl { void *extra_pg0_lock_spec; /* Opaque property */ uint32_t extra_pg0_lock_n16; + RegisterInfoArray *reg_array; uint32_t regs[XLNX_VERSAL_EFUSE_CTRL_R_MAX]; RegisterInfo regs_info[XLNX_VERSAL_EFUSE_CTRL_R_MAX]; }; diff --git a/hw/nvram/xlnx-versal-efuse-ctrl.c b/hw/nvram/xlnx-versal-efuse-ctrl.c index def6fe3302b..8252a5cabe0 100644 --- a/hw/nvram/xlnx-versal-efuse-ctrl.c +++ b/hw/nvram/xlnx-versal-efuse-ctrl.c @@ -712,9 +712,8 @@ static void efuse_ctrl_init(Object *obj) { XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(obj); SysBusDevice *sbd = SYS_BUS_DEVICE(obj); - RegisterInfoArray *reg_array; - reg_array = + s->reg_array = register_init_block32(DEVICE(obj), efuse_ctrl_regs_info, ARRAY_SIZE(efuse_ctrl_regs_info), s->regs_info, s->regs, @@ -722,7 +721,7 @@ static void efuse_ctrl_init(Object *obj) XLNX_VERSAL_EFUSE_CTRL_ERR_DEBUG, R_MAX * 4); - sysbus_init_mmio(sbd, ®_array->mem); + sysbus_init_mmio(sbd, &s->reg_array->mem); sysbus_init_irq(sbd, &s->irq_efuse_imr); } @@ -730,6 +729,7 @@ static void efuse_ctrl_finalize(Object *obj) { XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(obj); + register_finalize_block(s->reg_array); g_free(s->extra_pg0_lock_spec); } From patchwork Thu Sep 5 13:00:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 825640 Delivered-To: patch@linaro.org Received: by 2002:adf:a345:0:b0:367:895a:4699 with SMTP id d5csp286510wrb; Thu, 5 Sep 2024 06:03:18 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWX4kWgCdwEMia6+qTX1f8EgH581/VtWR0PzgjgGMyjIVeEYR0EBwBBPWWRSQjg8al8b30VjA==@linaro.org X-Google-Smtp-Source: AGHT+IEfhhrvKLltO7gPqjKEWb4L1gMPcpvO4CV6zRyWyzqB8f2DWvPNiIY7j9DE7UPZRXZ8QTqU X-Received: by 2002:adf:cf0f:0:b0:374:c2cb:a3c5 with SMTP id ffacd0b85a97d-374c2cba4f9mr9752530f8f.62.1725541397705; Thu, 05 Sep 2024 06:03:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1725541397; cv=none; d=google.com; s=arc-20160816; b=n92avwZ3lRg/BdiGV+6oBhZvsk9tcsONG5JYMSi3mL1Rw3fyBIK/fRpaxrlE+D+/2r FIHTpFd5G59eAAzyQfaVKjzgabX9/ny6bCqYthMtgHH14ci4v2sLt+phjO5lELAD5Brs lbRp40oxhKRwtXb+tZfZar25oiiUp1QtOxAB4nSFR4PAjij5c+2njXunuN6ZL/szOAbB G81WRvCf4BlXtNpiGLiu9y1E58Mcz2+xBjc6amX3GihYxPex5w6plEfSPzCrhdHW1Lgh HbrknG3zPe/xTe9ekUeQvy3Uoj7GRmXwV9fHYGDugAwYeZtHpgMi8LlrkzIow1O5Cyz0 t0VQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=QuDayuKh0MOoUDfgEF6uvM1JMAu44R2Rmq7U5Z8dKh8=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=LuIhGtPpcA/q5+j34W9K3XB3VCrCpuXlcatdLqFoVGMqu/UjAXghoYbirk0LVJ3TKB jKNMBa9UOsCrR0KdSFrP+l2JldmbmDDIdEdMrxaOqUMTxKlqzzSqTNQWNveqJD33NJY6 LlDHT9nMzWDBAD359c2GlU6l6Lei7LFeN68qjpMZKr7w1jOkGWypPhHPkdJbyq1i330c NBnOnmCdAvQhUIpiqcTqvs0oNNpF1clv4yAjlAQH9kZ2ah5i72IqglGd+ta2Ysu59uDf twJFEtVZ33sGmKuM6G5iNr4kFvgQYcP6tjoaDY878tZLxDrMxMmtW1sz9TLULAPo2GRI c/oQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=UGjMKH6b; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42bb6e355dfsm232251365e9.46.2024.09.05.06.01.15 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Sep 2024 06:01:15 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 20/25] hw/arm/sbsa-ref: Don't leak string in sbsa_fdt_add_gic_node() Date: Thu, 5 Sep 2024 14:00:55 +0100 Message-Id: <20240905130100.298768-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240905130100.298768-1-peter.maydell@linaro.org> References: <20240905130100.298768-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In sbsa_fdt_add_gic_node() we g_strdup_printf() two nodename strings, but only free one. Since the string is actually entirely constant and we don't make any use of printf's format-string operations, we can drop the g_strdup_printf() use entirely. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Gavin Shan Message-id: 20240822162323.706382-1-peter.maydell@linaro.org --- hw/arm/sbsa-ref.c | 15 ++++++--------- 1 file changed, 6 insertions(+), 9 deletions(-) diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index 396abe9c1bd..e3195d54497 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -164,23 +164,20 @@ static uint64_t sbsa_ref_cpu_mp_affinity(SBSAMachineState *sms, int idx) static void sbsa_fdt_add_gic_node(SBSAMachineState *sms) { - char *nodename; + const char *intc_nodename = "/intc"; + const char *its_nodename = "/intc/its"; - nodename = g_strdup_printf("/intc"); - qemu_fdt_add_subnode(sms->fdt, nodename); - qemu_fdt_setprop_sized_cells(sms->fdt, nodename, "reg", + qemu_fdt_add_subnode(sms->fdt, intc_nodename); + qemu_fdt_setprop_sized_cells(sms->fdt, intc_nodename, "reg", 2, sbsa_ref_memmap[SBSA_GIC_DIST].base, 2, sbsa_ref_memmap[SBSA_GIC_DIST].size, 2, sbsa_ref_memmap[SBSA_GIC_REDIST].base, 2, sbsa_ref_memmap[SBSA_GIC_REDIST].size); - nodename = g_strdup_printf("/intc/its"); - qemu_fdt_add_subnode(sms->fdt, nodename); - qemu_fdt_setprop_sized_cells(sms->fdt, nodename, "reg", + qemu_fdt_add_subnode(sms->fdt, its_nodename); + qemu_fdt_setprop_sized_cells(sms->fdt, its_nodename, "reg", 2, sbsa_ref_memmap[SBSA_GIC_ITS].base, 2, sbsa_ref_memmap[SBSA_GIC_ITS].size); - - g_free(nodename); } /* From patchwork Thu Sep 5 13:00:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 825656 Delivered-To: patch@linaro.org Received: by 2002:adf:a345:0:b0:367:895a:4699 with SMTP id d5csp288625wrb; Thu, 5 Sep 2024 06:06:15 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUM9VId2VzZRXy9AdxegSOttkiZyu76asNEuM1mSSaKJL9QfHKRuoAH0LWOFNGuHqkieBA5ZQ==@linaro.org X-Google-Smtp-Source: AGHT+IFY4DdKkTE6WLyVlA6kU0rJTQRT86pC/cjnlNkKfHgGMhvPYqIjND1eEv08uqCuwMmdeWvD X-Received: by 2002:a05:6830:2115:b0:703:6477:460a with SMTP id 46e09a7af769-70f7074603emr19085192a34.29.1725541574654; Thu, 05 Sep 2024 06:06:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1725541574; cv=none; d=google.com; s=arc-20160816; b=iPxbbKJ0KhDP3B4/f/95C+6HgTOcIpZFx5CspT6k2MboJckouUpYAUg/6CKx6gNoQz MvHCS8mmV2F9ptQSmVxwEs5LmWK0VveoQlFSPyXeMCfvzaJFeSurWedp/RV9egqZUbPU pN955S2++9joqoF/BHIeEKPf5IosBzyQeI3ObbaEcv6N0zHMadXS8Gai4W9LfVowKm98 zRTE6SQfilBwv0lUlkPDSf6iHWqsE++R2Qd/hoiNktdg0dhDLfddXW3OfwsIj+j+7ckQ eok1bGLyO2gA3EDlV11L3cojF+yemyb/2/Oi3j/lOfDG2C3S5EIZrmammcAZODV1WIe1 OL7g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=qIUBV+3eAKQWSLQmZz1TCwCdei1m98hDG02Oo3r/Z6c=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=maIbwol07CW8RYjwiuD04vCvfE7SKwWpuhcRxZiKRW69sECcT9DAw8MaxGI0V/yvLc k60megV+lRe22YvIMY91xcZ5XWjBMXtDcxmWAcH2g09FZTeuLv089UyjGcGB4FcwIdaU k3chNvG65cOrOfU8GwEnR+AZ5B+P3Ub/bPv+MDyxzsWsEE5oAOpceBdqn5gLhF9lQAUK QeHDJcvh4z7aMMvU18fTb5KSRKLI7mklvdc5X5FUvAiVbLheiEFaZjcLOrib9tPjdTIK D/A6xH3ilEeM226OeiTQGRQ3bwR7IYSmnKfe/Bx/XiShRCEeHtAlLJ+1yqWf3w9AHHOW u8jg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=EhHOiydU; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42bb6e355dfsm232251365e9.46.2024.09.05.06.01.16 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Sep 2024 06:01:16 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 21/25] target/arm: Correct names of VFP VFNMA and VFNMS insns Date: Thu, 5 Sep 2024 14:00:56 +0100 Message-Id: <20240905130100.298768-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240905130100.298768-1-peter.maydell@linaro.org> References: <20240905130100.298768-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In vfp.decode we have the names of the VFNMA and VFNMS instructions the wrong way around. The architecture says that bit 6 is the 'op' bit, which is 1 for VFNMA and 0 for VFNMS, but we label these two lines of decode the other way around. This doesn't cause any user-visible problem because in the handling of these functions in translate-vfp.c we give VFNMA the behaviour specified for VFNMS and vice-versa, but it's confusing when reading the code. Switch the names of the VFP VFNMA and VFNMS instructions in the decode file and flip the behaviour also. NB: the instructions VFMA and VFMS *are* decoded with op=0 for VFMA and op=1 for VFMS; the confusion probably arose because we assumed VFNMA and VFNMS to be the same way around. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2536 Signed-off-by: Peter Maydell Message-id: 20240830152156.2046590-1-peter.maydell@linaro.org Reviewed-by: Richard Henderson --- target/arm/tcg/vfp.decode | 12 ++++++------ target/arm/tcg/translate-vfp.c | 8 ++++---- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/target/arm/tcg/vfp.decode b/target/arm/tcg/vfp.decode index 5405e80197b..2dd87a27089 100644 --- a/target/arm/tcg/vfp.decode +++ b/target/arm/tcg/vfp.decode @@ -141,18 +141,18 @@ VDIV_dp ---- 1110 1.00 .... .... 1011 .0.0 .... @vfp_dnm_d VFMA_hp ---- 1110 1.10 .... .... 1001 .0. 0 .... @vfp_dnm_s VFMS_hp ---- 1110 1.10 .... .... 1001 .1. 0 .... @vfp_dnm_s -VFNMA_hp ---- 1110 1.01 .... .... 1001 .0. 0 .... @vfp_dnm_s -VFNMS_hp ---- 1110 1.01 .... .... 1001 .1. 0 .... @vfp_dnm_s +VFNMS_hp ---- 1110 1.01 .... .... 1001 .0. 0 .... @vfp_dnm_s +VFNMA_hp ---- 1110 1.01 .... .... 1001 .1. 0 .... @vfp_dnm_s VFMA_sp ---- 1110 1.10 .... .... 1010 .0. 0 .... @vfp_dnm_s VFMS_sp ---- 1110 1.10 .... .... 1010 .1. 0 .... @vfp_dnm_s -VFNMA_sp ---- 1110 1.01 .... .... 1010 .0. 0 .... @vfp_dnm_s -VFNMS_sp ---- 1110 1.01 .... .... 1010 .1. 0 .... @vfp_dnm_s +VFNMS_sp ---- 1110 1.01 .... .... 1010 .0. 0 .... @vfp_dnm_s +VFNMA_sp ---- 1110 1.01 .... .... 1010 .1. 0 .... @vfp_dnm_s VFMA_dp ---- 1110 1.10 .... .... 1011 .0.0 .... @vfp_dnm_d VFMS_dp ---- 1110 1.10 .... .... 1011 .1.0 .... @vfp_dnm_d -VFNMA_dp ---- 1110 1.01 .... .... 1011 .0.0 .... @vfp_dnm_d -VFNMS_dp ---- 1110 1.01 .... .... 1011 .1.0 .... @vfp_dnm_d +VFNMS_dp ---- 1110 1.01 .... .... 1011 .0.0 .... @vfp_dnm_d +VFNMA_dp ---- 1110 1.01 .... .... 1011 .1.0 .... @vfp_dnm_d VMOV_imm_hp ---- 1110 1.11 .... .... 1001 0000 .... \ vd=%vd_sp imm=%vmov_imm diff --git a/target/arm/tcg/translate-vfp.c b/target/arm/tcg/translate-vfp.c index cd5b8483576..b6fa28a7bf6 100644 --- a/target/arm/tcg/translate-vfp.c +++ b/target/arm/tcg/translate-vfp.c @@ -2190,8 +2190,8 @@ static bool do_vfm_sp(DisasContext *s, arg_VFMA_sp *a, bool neg_n, bool neg_d) static bool do_vfm_dp(DisasContext *s, arg_VFMA_dp *a, bool neg_n, bool neg_d) { /* - * VFNMA : fd = muladd(-fd, fn, fm) - * VFNMS : fd = muladd(-fd, -fn, fm) + * VFNMA : fd = muladd(-fd, -fn, fm) + * VFNMS : fd = muladd(-fd, fn, fm) * VFMA : fd = muladd( fd, fn, fm) * VFMS : fd = muladd( fd, -fn, fm) * @@ -2262,8 +2262,8 @@ static bool do_vfm_dp(DisasContext *s, arg_VFMA_dp *a, bool neg_n, bool neg_d) #define MAKE_VFM_TRANS_FNS(PREC) \ MAKE_ONE_VFM_TRANS_FN(VFMA, PREC, false, false) \ MAKE_ONE_VFM_TRANS_FN(VFMS, PREC, true, false) \ - MAKE_ONE_VFM_TRANS_FN(VFNMA, PREC, false, true) \ - MAKE_ONE_VFM_TRANS_FN(VFNMS, PREC, true, true) + MAKE_ONE_VFM_TRANS_FN(VFNMS, PREC, false, true) \ + MAKE_ONE_VFM_TRANS_FN(VFNMA, PREC, true, true) MAKE_VFM_TRANS_FNS(hp) MAKE_VFM_TRANS_FNS(sp) From patchwork Thu Sep 5 13:00:57 2024 Content-Type: text/plain; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42bb6e355dfsm232251365e9.46.2024.09.05.06.01.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Sep 2024 06:01:17 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 22/25] hw/arm/xilinx_zynq: Enable Security Extensions Date: Thu, 5 Sep 2024 14:00:57 +0100 Message-Id: <20240905130100.298768-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240905130100.298768-1-peter.maydell@linaro.org> References: <20240905130100.298768-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Sebastian Huber The system supports the Security Extensions (core and GIC). This change is necessary to run tests which pass on the real hardware. Signed-off-by: Sebastian Huber Reviewed-by: Edgar E. Iglesias Tested-by: Edgar E. Iglesias Message-id: 20240828005019.57705-1-sebastian.huber@embedded-brains.de Signed-off-by: Peter Maydell --- hw/arm/xilinx_zynq.c | 8 -------- 1 file changed, 8 deletions(-) diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index 3c56b9abe1c..37c234f5aba 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -219,14 +219,6 @@ static void zynq_init(MachineState *machine) for (n = 0; n < smp_cpus; n++) { Object *cpuobj = object_new(machine->cpu_type); - /* - * By default A9 CPUs have EL3 enabled. This board does not currently - * support EL3 so the CPU EL3 property is disabled before realization. - */ - if (object_property_find(cpuobj, "has_el3")) { - object_property_set_bool(cpuobj, "has_el3", false, &error_fatal); - } - object_property_set_int(cpuobj, "midr", ZYNQ_BOARD_MIDR, &error_fatal); object_property_set_int(cpuobj, "reset-cbar", MPCORE_PERIPHBASE, From patchwork Thu Sep 5 13:00:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 825641 Delivered-To: patch@linaro.org Received: by 2002:adf:a345:0:b0:367:895a:4699 with SMTP id d5csp286516wrb; Thu, 5 Sep 2024 06:03:18 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUed6DVZiuN/ahwG0y5A6xKY4UZOPFkHsJhfHdImokR9ARO8deoWVxt+FSr2O3kz6hAhI4yMQ==@linaro.org X-Google-Smtp-Source: AGHT+IGvJXHYZDJh7iUowGzC7JZmiWQI7M735hJzXAahFhYa07k9Jtm4f0/exHS5m2vEYb42tpuD X-Received: by 2002:a05:690c:4b85:b0:6d5:e768:4779 with SMTP id 00721157ae682-6db2604a8fcmr44322387b3.22.1725541398277; Thu, 05 Sep 2024 06:03:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1725541398; cv=none; d=google.com; s=arc-20160816; b=LAZQ+zS7W62eBVbttVlSRn344lb1Lu661By2nWG07nCFrYWiZQC/amvqZNAv+sWT2A +3odt3ZNQBGni6cFvOYde/EYCNzKcLW4mg5fLwME6kVtpbcHZFdTTB2IfW6ulAD305Cf FjJJBjbg9M+sfSx6MTCHx6JTnMUtrGlzIbhWgbBe1I1Y0lnuqTetgj820jd2fF8LXdTq x2jGoL4KNpn7iZyigAB8WBV+olwDpUSQwWSoX+3LBq1sXRjgN8idYn3cHYN6xw3vnA7A qf+6tOCAMeazCZm2YJQAt0+KX8/frbcqUpkwDqDFR+5OWXIhu+TeEI0CrMygYRuQwNgd OxVg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=VA29/g4wKHT5gPl+VZPcS59cjqvbl7e/0STDa0JUTUw=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=F6eRPlUi0AFmBj7seVlnx35OcbjgM5Po9u9U94BXHWlmzyqlr3xXOx4PKlQ4ycoJPJ ApPi1A6ApPuK3mWrMFf7ikODZ7I26tm9ybUD6Yf3He6HWayvVu0racIxeDdSnk7BI3mg IbkAQfycLcvn3CojmfTvrx6UWszdf9kKU5za0+X6vk5U8WkdeWFXJ2htob9jG5IoyljI L6pkeLXIpBlrW1XjUjXiTrDFQdasIUinxKQHho5UgeocLk2yz5acwlu3eyI/19T1U7za 0+kGLFuzIM5B1Ij/4sWEpS5Rna36pVMaWvEjPFpqB5FySdY5UJ6jlfOCOIOW1OHW7cX5 RU/A==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WW7pFIxC; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42bb6e355dfsm232251365e9.46.2024.09.05.06.01.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Sep 2024 06:01:17 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 23/25] hw/arm/boot: Report error msg if loading elf/dtb failed Date: Thu, 5 Sep 2024 14:00:58 +0100 Message-Id: <20240905130100.298768-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240905130100.298768-1-peter.maydell@linaro.org> References: <20240905130100.298768-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Changbin Du Print errors before exit. Do not exit silently. Cc: Philippe Mathieu-Daudé Signed-off-by: Changbin Du Reviewed-by: Philippe Mathieu-Daudé Message-id: 20240903133940.3447430-1-changbin.du@huawei.com Signed-off-by: Peter Maydell --- hw/arm/boot.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/arm/boot.c b/hw/arm/boot.c index d480a7da02c..6c895e05cbc 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -839,6 +839,8 @@ static ssize_t arm_load_elf(struct arm_boot_info *info, uint64_t *pentry, 1, data_swab, as); if (ret <= 0) { /* The header loaded but the image didn't */ + error_report("Couldn't load elf '%s': %s", + info->kernel_filename, load_elf_strerror(ret)); exit(1); } From patchwork Thu Sep 5 13:00:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 825646 Delivered-To: patch@linaro.org Received: by 2002:adf:a345:0:b0:367:895a:4699 with SMTP id d5csp287160wrb; Thu, 5 Sep 2024 06:04:10 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCV0cD9YEqt0Zqf8W9SGIf5taNJJTfIsLLYZx9nsDam6ze0n9xJmBBinyITN1PXMjazs3le/Vg==@linaro.org X-Google-Smtp-Source: AGHT+IFQ6FKOj4NxuBt4SyegKSqxLfWmu+gwxwBz0H1MvkJO1Eb8eyzc+849Fcd0cb9AKeFsjfYq X-Received: by 2002:adf:f608:0:b0:374:c05f:2313 with SMTP id ffacd0b85a97d-374c05f2775mr13019665f8f.45.1725541450168; Thu, 05 Sep 2024 06:04:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1725541450; cv=none; d=google.com; s=arc-20160816; b=vPeVLRLdSZ8cTS00oI18pddbE1ZobeJMffbCWyclPuNB2C90bjARjnFu0eybyHLTMQ X7XZgZALIklBYT7HdaONtmx/HG1vRSdohkZ75XyZJ6v183jScDOXTVcjMmZ0l926DALA G9qBvgN4ySJeDoJWr4nbgRw1c6wUoh1h8R0oJqyRiICU+MYMdrdumQExWR/srCEY7YO0 zN0Gp7ay8J4bGmesWGgk9wQuZ2aeHiRiRP4ZRrMF72JvGsI6POxzQo18C/wgdxj3Jr/V vQAjwtHQRD5JcyyObY3aX44Wk8aIfwit2rL4N7lZ01WYK6urnkxwFoAp94hKVUrYmxV0 Qy7A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=R9U4aWp8TraYxhIRkNKUBeZnraOIqezcaMpKqimPY0U=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=QQVOj4Bqox0PM+nz2bxen2v+ji5OYwsmKFIhzaQB1VPgr5ISxGQJaqSbIQsV+el1pn /3VWqJTWoIja8jnF/1coJmZj9JjrN/tDEjbT3FrHvvyBehT8CLTh7+NF5LEjufmNY92j G6s8q7sPL5hPw5ulNRAYkGjLlq6G8L24xVuYxufbu/nxCHy5Duw4NoJYNBOPQGbKp/5a iQ7lKk6GeG93dkTftttNqfgRkpKFvqedfHc7tB09X7jo/dyHBd9KQ4D99vd+QVf8AGFb g3ZaskEpLczxSniFYrumPBZMgxp9IzjVIVhIxgGhU2KSzj/A50ofojXGr7WkD8wlEWvX rzpQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WshvgZFc; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42bb6e355dfsm232251365e9.46.2024.09.05.06.01.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Sep 2024 06:01:18 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 24/25] hw/arm/boot: Explain why load_elf_hdr() error is ignored Date: Thu, 5 Sep 2024 14:00:59 +0100 Message-Id: <20240905130100.298768-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240905130100.298768-1-peter.maydell@linaro.org> References: <20240905130100.298768-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé If the file is not an ELF file, arm_setup_direct_kernel_boot() falls back to try it as a uimage or an AArch64 Image file or as last resort a bare raw binary. We can discard load_elf_hdr() error and silently return. Signed-off-by: Philippe Mathieu-Daudé Message-id: 20240903144154.17135-1-philmd@linaro.org Signed-off-by: Peter Maydell Reviewed-by: Peter Maydell --- hw/arm/boot.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/hw/arm/boot.c b/hw/arm/boot.c index 6c895e05cbc..5301d8d318c 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -799,14 +799,18 @@ static ssize_t arm_load_elf(struct arm_boot_info *info, uint64_t *pentry, } elf_header; int data_swab = 0; bool big_endian; - ssize_t ret = -1; + ssize_t ret; Error *err = NULL; load_elf_hdr(info->kernel_filename, &elf_header, &elf_is64, &err); if (err) { + /* + * If the file is not an ELF file we silently return. + * The caller will fall back to try other formats. + */ error_free(err); - return ret; + return -1; } if (elf_is64) { From patchwork Thu Sep 5 13:01:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 825643 Delivered-To: patch@linaro.org Received: by 2002:adf:a345:0:b0:367:895a:4699 with SMTP id d5csp286821wrb; Thu, 5 Sep 2024 06:03:44 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUpWkCbB3FOeQPABPegadCLKp59KGQpMtiMvZHVNA+EonTn4J0Zxe/2Yl/MI6AdjV6HlCZUkw==@linaro.org X-Google-Smtp-Source: AGHT+IFZYrJOxaHv0vHff5WblbkLzG5GdYuOvADGi0Lw1w/Rh94pSZvwEYO5xvQiq8T+OmIOoP+u X-Received: by 2002:a05:6902:e0e:b0:e1a:9336:8b54 with SMTP id 3f1490d57ef6-e1a93368caamr16792057276.32.1725541424403; Thu, 05 Sep 2024 06:03:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1725541424; cv=none; d=google.com; s=arc-20160816; b=eeqNs813Fj8iTZ4+JlxTO4A4yst5RkfqDb7BK4EolZGOzp2fQuHr6GoeXpDqHvSqYZ HadlqW5ef7tzs088kpPErB7Y3IsRctwOy098po/bcMtUip2mD/FMEpY0deIST2Y9lLbN Xk+7LM9+cnGdNKeuNQBvEGxtR7t2U5w1H8vBxUQlGG1wommfOFbCLcUhJq96nyypINYY cJiL6VT7who4ZW1HlcWhZdkCBifjjlnefi6+bYgj53EiGO385og/pG6HxNGa+Atd48gP dU01xfYccKAffQJq87B5m6CzqxrOjC+8k7L3u/PhqznAs3P6Z+wXfKYTEEXKMxx0UGoQ pteg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=gZRGtO6SmZHDabe4EZR6EK0mqdv3jxaN8ddZYk6gMA0=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=EUM4tAA40uEm4yr90FNC7pu82xIyUxVr9IK7vHadIYajJ7Zh31l/ugr7UxEpqodFA1 juupO2B50L4MZHvRdCMkMzNRxfgk6rfMFb9dqZDfBXBPQPaRUmbH+3SDOSOrcY+MUQiM q6dCkfWG3ocE6EAJBONH8i+TU/aoXp1vOBiU/4x5m5VxnuP2JYB7oVj6Z4sTj5Zm3snD HGA0FVNx37oyUDGroy1u9URjI3hmijuPKxkZTbXwhd2ZHhK900OpKcyyXZ3aPQ3vuJhC NJasrJrCsmTefJwfC+GNRgn4iqFqKpCW8AyrXUE2KVqW3L4DPH+AgjrRLIRxc3I3HkcB pYqA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NPshg+3c; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42bb6e355dfsm232251365e9.46.2024.09.05.06.01.18 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Sep 2024 06:01:18 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 25/25] platform-bus: fix refcount leak Date: Thu, 5 Sep 2024 14:01:00 +0100 Message-Id: <20240905130100.298768-26-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240905130100.298768-1-peter.maydell@linaro.org> References: <20240905130100.298768-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Gao Shiyuan memory_region_find() returns an MR which it is the caller's responsibility to unref, but platform_bus_map_mmio() was forgetting to do so, thus leaking the MR. Signed-off-by: Gao Shiyuan Message-id: 20240829131005.9196-1-gaoshiyuan@baidu.com Reviewed-by: Peter Maydell [PMM: tweaked commit message] Signed-off-by: Peter Maydell --- hw/core/platform-bus.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/hw/core/platform-bus.c b/hw/core/platform-bus.c index b8487b26b67..dc58bf505aa 100644 --- a/hw/core/platform-bus.c +++ b/hw/core/platform-bus.c @@ -145,9 +145,12 @@ static void platform_bus_map_mmio(PlatformBusDevice *pbus, SysBusDevice *sbdev, * the target device's memory region */ for (off = 0; off < pbus->mmio_size; off += alignment) { - if (!memory_region_find(&pbus->mmio, off, size).mr) { + MemoryRegion *mr = memory_region_find(&pbus->mmio, off, size).mr; + if (!mr) { found_region = true; break; + } else { + memory_region_unref(mr); } }