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Tue, 03 Sep 2024 09:13:33 -0700 (PDT) From: Neil Armstrong Date: Tue, 03 Sep 2024 18:13:30 +0200 Subject: [PATCH 1/2] soc: qcom: rpmh-rsc: add back __tcs_set_trigger() for SM8550/SM8650 MIME-Version: 1.0 Message-Id: <20240903-topic-sm8x50-regulators-support-v1-1-0857185bddc0@linaro.org> References: <20240903-topic-sm8x50-regulators-support-v1-0-0857185bddc0@linaro.org> In-Reply-To: <20240903-topic-sm8x50-regulators-support-v1-0-0857185bddc0@linaro.org> To: Caleb Connolly , Sumit Garg , Tom Rini , Jaehoon Chung Cc: u-boot-qcom@groups.io, u-boot@lists.denx.de, Neil Armstrong X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=2858; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=smjWN8nyrz0L2KEatxfzxGPqyWxT87Bxols/pVkOpFc=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBm1zWrC70kVHZ/i/ruCWdkyzLbcVH03srzXs7KSSUL H6202MyJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZtc1qwAKCRB33NvayMhJ0UVnD/ 0UKDYWPHANqAQt5YsFueE1R+4QERL2GjBgNmieCBhpNAnsxtePuxIg6CO3195EB1kM3NNp6q6ox1Ko hgZksreGpLbu5XV1dKlyo1LxlDI0Ck0EdV6nZBs4ioeUIOqjci7624hzrxpCs4N7l2w2cTZZ6ZA4Uh B5xOvTrGA9qb6iE36zqPNWS5DAkGoahjfuxm70V4ScdsEs47klKVqd4tl2XHXcvfGAezscSbLUunVr 4tZLiPyI3EK6QwQSfpiyACVnIAZmMH5ygD7Qz7s9FKP9Sjj2M3wHVyoHI6wX78YQMI+o7PFueMsWWC tlrgIDFIn+3QSpCIZJ7PCvXoi7hfEApaBlZ84jdS5S37Im/Iw4OCBFoNbBEwcfDGx47PlGtCnMvI25 zW0RqDstVAXcAe0OsdicKFmj4tkLplwRnEGBMrteHfZrQWhxbBQb6yNml4oJ9mUcDA+V4kPsZj0bbr vIQEvxtjhz3PexH6xn1krTfo3sKdyqcKPmp/XZaYRD6f+f+CAu8JFcYFaLjdOXYS56NV8cNQIYU9wW worCxgIFKoj3+phMNIF0MJns+WRaQ1TP9+R0bpEHIX/OpEjevvL9VJx/O7yvIi8V0A0diDWhXrkTVD dgavnHIlUb6Ek1ukq00LquLQbEVPN7oOs8JpMa/S4vkM/A0LBGwGZVKH08AQ== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean The TCS writes has no effect after the removal of the __tcs_set_trigger() call, obviously it seems the RSC version 3 requires it to complete the transactions. Fixes: 80c5be164ad ("soc: qcom: rpmh-rsc: drop unused multi-threading and non-active TCS support") Signed-off-by: Neil Armstrong --- drivers/soc/qcom/rpmh-rsc.c | 43 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/drivers/soc/qcom/rpmh-rsc.c b/drivers/soc/qcom/rpmh-rsc.c index 61fb2e69558..aee9e55194e 100644 --- a/drivers/soc/qcom/rpmh-rsc.c +++ b/drivers/soc/qcom/rpmh-rsc.c @@ -293,6 +293,48 @@ static void __tcs_buffer_write(struct rsc_drv *drv, int tcs_id, int cmd_id, write_tcs_reg(drv, drv->regs[RSC_DRV_CMD_ENABLE], tcs_id, cmd_enable); } +/** + * __tcs_set_trigger() - Start xfer on a TCS or unset trigger on a borrowed TCS + * @drv: The controller. + * @tcs_id: The global ID of this TCS. + * @trigger: If true then untrigger/retrigger. If false then just untrigger. + * + * In the normal case we only ever call with "trigger=true" to start a + * transfer. That will un-trigger/disable the TCS from the last transfer + * then trigger/enable for this transfer. + * + * If we borrowed a wake TCS for an active-only transfer we'll also call + * this function with "trigger=false" to just do the un-trigger/disable + * before using the TCS for wake purposes again. + * + * Note that the AP is only in charge of triggering active-only transfers. + * The AP never triggers sleep/wake values using this function. + */ +static void __tcs_set_trigger(struct rsc_drv *drv, int tcs_id, bool trigger) +{ + u32 enable; + u32 reg = drv->regs[RSC_DRV_CONTROL]; + + /* + * HW req: Clear the DRV_CONTROL and enable TCS again + * While clearing ensure that the AMC mode trigger is cleared + * and then the mode enable is cleared. + */ + enable = read_tcs_reg(drv, reg, tcs_id); + enable &= ~TCS_AMC_MODE_TRIGGER; + write_tcs_reg_sync(drv, reg, tcs_id, enable); + enable &= ~TCS_AMC_MODE_ENABLE; + write_tcs_reg_sync(drv, reg, tcs_id, enable); + + if (trigger) { + /* Enable the AMC mode on the TCS and then trigger the TCS */ + enable = TCS_AMC_MODE_ENABLE; + write_tcs_reg_sync(drv, reg, tcs_id, enable); + enable |= TCS_AMC_MODE_TRIGGER; + write_tcs_reg(drv, reg, tcs_id, enable); + } +} + /** * rpmh_rsc_send_data() - Write / trigger active-only message. * @drv: The controller. @@ -348,6 +390,7 @@ int rpmh_rsc_send_data(struct rsc_drv *drv, const struct tcs_request *msg) * of __tcs_set_trigger() below. */ __tcs_buffer_write(drv, tcs_id, 0, msg); + __tcs_set_trigger(drv, tcs_id, true); /* U-Boot: Now wait for the TCS to be cleared, indicating that we're done */ for (i = 0; i < USEC_PER_SEC; i++) { From patchwork Tue Sep 3 16:13:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 824935 Delivered-To: patch@linaro.org Received: by 2002:a5d:48c1:0:b0:367:895a:4699 with SMTP id p1csp2493420wrs; Tue, 3 Sep 2024 09:13:56 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWGoIsS9lvzkzq2HWFvi8Skv3BWxSl4YF5NE0lZRllrTgap+0ZEquu7/reaYFiUgxg1g7KPqA==@linaro.org X-Google-Smtp-Source: AGHT+IG2kxrLDDb7Z8qd0aze9zu+5uYemWoEGx0b/kze6v90qpODUS7i900V2JxFdGYcXWUL7iDC X-Received: by 2002:a05:6402:1d50:b0:5bb:9b09:8c7e with SMTP id 4fb4d7f45d1cf-5c21ed8c760mr13210559a12.26.1725380035963; Tue, 03 Sep 2024 09:13:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1725380035; cv=none; d=google.com; s=arc-20240605; b=k1HqigNaWOR5s8C1CqVcfbpxLS9WXF2hgdnF25VfTHPIVeHyPsaYkmvYwzHpIahxuz atDfjJ6sqFmNcZgyj9sSFg7Husls85pyd1qMeI0vB8FRkB6X1H35R/YyS98Y4/x1e4LY gS9A/OM4U/7XAa/rxbcYu1gwwon0Z7rmPjRz0/voy92p6LM9CffWktygHBLbTgGyZfqX iZkyImJiI3KjTZ4csFBh+AFlqIQdjwWAUxyHTplPwMJTs0c6ru7kP8Jw4coSI1kU6a5a TTc2kL8S2SooRqJgCUBr0hgBQ7oVBqLISSQAcAR1yhQAH/DrUrpXJoahGYqjERgqiEt4 Zhrg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:cc:to:in-reply-to:references :message-id:content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=lYugHg9w4t1Ub63UYl/9rcAF1NKvyqgE2W84/KqQrWc=; fh=9ZJWQu806dVuGexwEJ2o0ZGMKlW8Zk33j0uerkSNksM=; b=dL/e8qWKd7WR/88E+yACt1Y7vGynDh8eGdF9M7hXFTFo2LRctIXD7NVt7qIxwr0G5J 2eZ5rPJxUAsU/cok13nHm/YdrCaQV8CxpQNQ513VuXSo1K0I4o9TvngzT4syZ9g8mnIl 8c9HZ9AM3C63xixuh1WzTRn88tgaXoXS0akNyqKOdqBx4xvZn/CuhFeeFc8on/cuIsSL +FXTlHLDQ7vvLyb7yxQteDJ+NTmeXPqLpLWLCN+d9rdcjbjiiSFLncFZ/6QZA4Le7NPK mv2Lef3scb2yCbGWG+hqJ834E6sDjTRPIjCQFSCx8dbJXKgJKgJw9qDVgRKjLI4xicbc RL8A==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=iipw5dyW; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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Tue, 03 Sep 2024 09:13:34 -0700 (PDT) From: Neil Armstrong Date: Tue, 03 Sep 2024 18:13:31 +0200 Subject: [PATCH 2/2] regulator: qcom-rpmh-regulator: add support for PM8550 & related regulators MIME-Version: 1.0 Message-Id: <20240903-topic-sm8x50-regulators-support-v1-2-0857185bddc0@linaro.org> References: <20240903-topic-sm8x50-regulators-support-v1-0-0857185bddc0@linaro.org> In-Reply-To: <20240903-topic-sm8x50-regulators-support-v1-0-0857185bddc0@linaro.org> To: Caleb Connolly , Sumit Garg , Tom Rini , Jaehoon Chung Cc: u-boot-qcom@groups.io, u-boot@lists.denx.de, Neil Armstrong X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=6802; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=Fid6fZeFw3Kvdjg+Sw1MrfbE1HxCCFoaWW5H7HMfB8s=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBm1zWsfmrkr15MVyRItKsgi5Xrm8X8HJA2rd4uv7xu qidHGEmJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZtc1rAAKCRB33NvayMhJ0YujD/ 9b0oU8OLLijlnXNF6ucwDxji0Iu3oS9gvlRcjEJ7KIDbS4Jx7608pV3F8Ht2Uud+VAHka3zGGnvWAF B8kUyN41G4fdwCSBKtixtWeL9AM4VK7nwm0GTZtsz9CYxM0dW722uRdBnr9+s4+XO7ZNcb3PbnZVrP SYRAvwlt75Jd3nupCSiFq1+90ofOqmT0AGvatLCAiIa2F1kia223M/kJhDuxyvoWDoHUjzYkCDMesv dbXXjZmWOJxgIzc8EbXu2Q0MH+2JerZZ+tNxlnTWdhWoH02nMXdlAWvIkAqZX3E9XL6LN8i36UkHBE tFLUOGyCFf6rHzGj/oyj9J2AL5nEqcS7Bzq8dPNk1egTUjWW/U8/GjlzEL7zH3doKVOj1Mgbcj7Hqt 5rHVYtDORp2ecmWxbV2ZI9yo6VmWgFrEWXQpdlupPl81zKd2d4as1S19QzHSkVHTzUEUwp4dLEqYsN wHOckkNgDYHx3Zcg0/+i6Ft+wbWHSeAGPMNSPrODbNz9zCEx8IAEJD8osRsFjpOU+FPP6uN13rXmZs ZwMOdhB9UpXXkIam6tfDSN2DZou4SaCAoPL9v1sTVsH1YaNyjM9NndhO/ipJTeUXbctd45GWL8tAAm 9t7Z2QOFNwVP483rKgQpzeA5oM5LnmAi1TE2+EbHAvay2av6Orgtc4zR10OQ== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Add the PM8550 & related regulators found on the SM8550 and SM8650 platforms. The tables are imported from the Linux driver. Signed-off-by: Neil Armstrong --- drivers/power/regulator/qcom-rpmh-regulator.c | 136 ++++++++++++++++++++++++++ 1 file changed, 136 insertions(+) diff --git a/drivers/power/regulator/qcom-rpmh-regulator.c b/drivers/power/regulator/qcom-rpmh-regulator.c index 06fd3f31956..2dc261d83e3 100644 --- a/drivers/power/regulator/qcom-rpmh-regulator.c +++ b/drivers/power/regulator/qcom-rpmh-regulator.c @@ -357,6 +357,69 @@ static const struct dm_regulator_ops rpmh_regulator_vrm_drms_ops = { .get_mode = rpmh_regulator_vrm_get_mode, }; +static struct dm_regulator_mode pmic_mode_map_pmic5_bob[] = { + { + .id = REGULATOR_MODE_LPM, + .register_value = PMIC5_BOB_MODE_PFM, + .name = "PMIC5_BOB_MODE_PFM" + }, { + .id = REGULATOR_MODE_AUTO, + .register_value = PMIC5_BOB_MODE_AUTO, + .name = "PMIC5_BOB_MODE_AUTO" + }, { + .id = REGULATOR_MODE_HPM, + .register_value = PMIC5_BOB_MODE_PWM, + .name = "PMIC5_BOB_MODE_PWM" + }, +}; + +static struct dm_regulator_mode pmic_mode_map_pmic5_smps[] = { + { + .id = REGULATOR_MODE_RETENTION, + .register_value = PMIC5_SMPS_MODE_RETENTION, + .name = "PMIC5_SMPS_MODE_RETENTION" + }, { + .id = REGULATOR_MODE_LPM, + .register_value = PMIC5_SMPS_MODE_PFM, + .name = "PMIC5_SMPS_MODE_PFM" + }, { + .id = REGULATOR_MODE_AUTO, + .register_value = PMIC5_SMPS_MODE_AUTO, + .name = "PMIC5_SMPS_MODE_AUTO" + }, { + .id = REGULATOR_MODE_HPM, + .register_value = PMIC5_SMPS_MODE_PWM, + .name = "PMIC5_SMPS_MODE_PWM" + }, +}; + +static const struct rpmh_vreg_hw_data pmic5_bob = { + .regulator_type = VRM, + .ops = &rpmh_regulator_vrm_drms_ops, + .voltage_range = REGULATOR_LINEAR_RANGE(3000000, 0, 31, 32000), + .n_voltages = 32, + .pmic_mode_map = pmic_mode_map_pmic5_bob, + .n_modes = ARRAY_SIZE(pmic_mode_map_pmic5_bob), +}; + +static const struct rpmh_vreg_hw_data pmic5_ftsmps525_lv = { + .regulator_type = VRM, + .ops = &rpmh_regulator_vrm_drms_ops, + .voltage_range = REGULATOR_LINEAR_RANGE(300000, 0, 267, 4000), + .n_voltages = 268, + .pmic_mode_map = pmic_mode_map_pmic5_smps, + .n_modes = ARRAY_SIZE(pmic_mode_map_pmic5_smps), +}; + +static const struct rpmh_vreg_hw_data pmic5_ftsmps525_mv = { + .regulator_type = VRM, + .ops = &rpmh_regulator_vrm_drms_ops, + .voltage_range = REGULATOR_LINEAR_RANGE(600000, 0, 267, 8000), + .n_voltages = 268, + .pmic_mode_map = pmic_mode_map_pmic5_smps, + .n_modes = ARRAY_SIZE(pmic_mode_map_pmic5_smps), +}; + static struct dm_regulator_mode pmic_mode_map_pmic5_ldo[] = { { .id = REGULATOR_MODE_RETENTION, @@ -393,6 +456,16 @@ static const struct rpmh_vreg_hw_data pmic5_pldo_lv = { .n_modes = ARRAY_SIZE(pmic_mode_map_pmic5_ldo), }; +static const struct rpmh_vreg_hw_data pmic5_nldo515 = { + .regulator_type = VRM, + .ops = &rpmh_regulator_vrm_drms_ops, + .voltage_range = REGULATOR_LINEAR_RANGE(320000, 0, 210, 8000), + .n_voltages = 211, + .hpm_min_load_uA = 30000, + .pmic_mode_map = pmic_mode_map_pmic5_ldo, + .n_modes = ARRAY_SIZE(pmic_mode_map_pmic5_ldo), +}; + #define RPMH_VREG(_name, _resource_name, _hw_data, _supply_name) \ { \ .name = _name, \ @@ -412,6 +485,57 @@ static const struct rpmh_vreg_init_data pm8150l_vreg_data[] = { {} }; +static const struct rpmh_vreg_init_data pm8550_vreg_data[] = { + RPMH_VREG("ldo1", "ldo%s1", &pmic5_nldo515, "vdd-l1-l4-l10"), + RPMH_VREG("ldo2", "ldo%s2", &pmic5_pldo, "vdd-l2-l13-l14"), + RPMH_VREG("ldo3", "ldo%s3", &pmic5_nldo515, "vdd-l3"), + RPMH_VREG("ldo4", "ldo%s4", &pmic5_nldo515, "vdd-l1-l4-l10"), + RPMH_VREG("ldo5", "ldo%s5", &pmic5_pldo, "vdd-l5-l16"), + RPMH_VREG("ldo6", "ldo%s6", &pmic5_pldo, "vdd-l6-l7"), + RPMH_VREG("ldo7", "ldo%s7", &pmic5_pldo, "vdd-l6-l7"), + RPMH_VREG("ldo8", "ldo%s8", &pmic5_pldo, "vdd-l8-l9"), + RPMH_VREG("ldo9", "ldo%s9", &pmic5_pldo, "vdd-l8-l9"), + RPMH_VREG("ldo10", "ldo%s10", &pmic5_nldo515, "vdd-l1-l4-l10"), + RPMH_VREG("ldo11", "ldo%s11", &pmic5_nldo515, "vdd-l11"), + RPMH_VREG("ldo12", "ldo%s12", &pmic5_nldo515, "vdd-l12"), + RPMH_VREG("ldo13", "ldo%s13", &pmic5_pldo, "vdd-l2-l13-l14"), + RPMH_VREG("ldo14", "ldo%s14", &pmic5_pldo, "vdd-l2-l13-l14"), + RPMH_VREG("ldo15", "ldo%s15", &pmic5_nldo515, "vdd-l15"), + RPMH_VREG("ldo16", "ldo%s16", &pmic5_pldo, "vdd-l5-l16"), + RPMH_VREG("ldo17", "ldo%s17", &pmic5_pldo, "vdd-l17"), + RPMH_VREG("bob1", "bob%s1", &pmic5_bob, "vdd-bob1"), + RPMH_VREG("bob2", "bob%s2", &pmic5_bob, "vdd-bob2"), + {} +}; + +static const struct rpmh_vreg_init_data pm8550vs_vreg_data[] = { + RPMH_VREG("smps1", "smp%s1", &pmic5_ftsmps525_lv, "vdd-s1"), + RPMH_VREG("smps2", "smp%s2", &pmic5_ftsmps525_lv, "vdd-s2"), + RPMH_VREG("smps3", "smp%s3", &pmic5_ftsmps525_lv, "vdd-s3"), + RPMH_VREG("smps4", "smp%s4", &pmic5_ftsmps525_lv, "vdd-s4"), + RPMH_VREG("smps5", "smp%s5", &pmic5_ftsmps525_lv, "vdd-s5"), + RPMH_VREG("smps6", "smp%s6", &pmic5_ftsmps525_mv, "vdd-s6"), + RPMH_VREG("ldo1", "ldo%s1", &pmic5_nldo515, "vdd-l1"), + RPMH_VREG("ldo2", "ldo%s2", &pmic5_nldo515, "vdd-l2"), + RPMH_VREG("ldo3", "ldo%s3", &pmic5_nldo515, "vdd-l3"), + {} +}; + +static const struct rpmh_vreg_init_data pm8550ve_vreg_data[] = { + RPMH_VREG("smps1", "smp%s1", &pmic5_ftsmps525_lv, "vdd-s1"), + RPMH_VREG("smps2", "smp%s2", &pmic5_ftsmps525_lv, "vdd-s2"), + RPMH_VREG("smps3", "smp%s3", &pmic5_ftsmps525_lv, "vdd-s3"), + RPMH_VREG("smps4", "smp%s4", &pmic5_ftsmps525_mv, "vdd-s4"), + RPMH_VREG("smps5", "smp%s5", &pmic5_ftsmps525_lv, "vdd-s5"), + RPMH_VREG("smps6", "smp%s6", &pmic5_ftsmps525_lv, "vdd-s6"), + RPMH_VREG("smps7", "smp%s7", &pmic5_ftsmps525_lv, "vdd-s7"), + RPMH_VREG("smps8", "smp%s8", &pmic5_ftsmps525_lv, "vdd-s8"), + RPMH_VREG("ldo1", "ldo%s1", &pmic5_nldo515, "vdd-l1"), + RPMH_VREG("ldo2", "ldo%s2", &pmic5_nldo515, "vdd-l2"), + RPMH_VREG("ldo3", "ldo%s3", &pmic5_nldo515, "vdd-l3"), + {} +}; + /* probe an individual regulator */ static int rpmh_regulator_probe(struct udevice *dev) { @@ -526,6 +650,18 @@ static const struct udevice_id rpmh_regulator_ids[] = { .compatible = "qcom,pm8150l-rpmh-regulators", .data = (ulong)pm8150l_vreg_data, }, + { + .compatible = "qcom,pm8550-rpmh-regulators", + .data = (ulong)pm8550_vreg_data, + }, + { + .compatible = "qcom,pm8550ve-rpmh-regulators", + .data = (ulong)pm8550ve_vreg_data, + }, + { + .compatible = "qcom,pm8550vs-rpmh-regulators", + .data = (ulong)pm8550vs_vreg_data, + }, { /* sentinal */ }, };