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[209.132.180.131]) by mx.google.com with ESMTPS id m13si3987398edc.243.2019.11.14.02.08.04 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 14 Nov 2019 02:08:05 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-return-513344-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=PSZHwT9P; dkim=pass header.i=@linaro.org header.s=google header.b=CCOHNKYJ; spf=pass (google.com: domain of gcc-patches-return-513344-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom="gcc-patches-return-513344-patch=linaro.org@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references; q=dns; s= default; b=xf0oh6vNaku4+xFyBrEzIBjMmmlp8XGc8AKejP1j+G+NE5OmeiOiw Q+7WrTiWhBI9tsaqsj2lvazmWfdbTnfgty/p1HjLX+CF/L3Tt2ophlqezdr1ck20 DhLK4N+VzTeJCe3mJ4x8zc2hIreAvTLIEMKKd+8O7Lh7sEJCBtsmuo= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references; s= default; bh=H8ywbrHGz6cHUyslId+WGcMd6r4=; b=PSZHwT9P7bntKgMlxese 6tt+WOsKXT3F3UBVLP5J9M6rYxz98pIarhEDYfx57jS3B9d9ym8J2nGwQfGuOUpo HEdvAao8nUbXlWV4Y2KFuoec4S5FyxailC3BzTw5PKTMt1jYYw3D7h120cEJgEsL 3KjedBYjYrQc1EDImiiJbnU= Received: (qmail 74623 invoked by alias); 14 Nov 2019 10:07:37 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 74578 invoked by uid 89); 14 Nov 2019 10:07:36 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-16.7 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.1 spammy= X-HELO: mail-wr1-f65.google.com Received: from mail-wr1-f65.google.com (HELO mail-wr1-f65.google.com) (209.85.221.65) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 14 Nov 2019 10:07:35 +0000 Received: by mail-wr1-f65.google.com with SMTP id z10so5711705wrs.12 for ; Thu, 14 Nov 2019 02:07:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=kv8Pk7QLFje7jijJIJfsJv6Tsk/b8ftTEdiQ5o1gC9k=; b=CCOHNKYJCjqqGyUA+9FJ960Y8btcl2AeaocjRxk7lWi2LtfA/ccvfrvjGh0TQ3H9v1 4ZrYdiVnabTssDCSldIPpC7mEYgoKM/OMOdfX+hkHu+B7qYlo6sPe3G/OCuaasscKtBg rA4gD7/qYQ40oWzTSIWvegjkVz7eTzKNU8AILAUH20FZy7iQNQ+fpNjBF6G6eDbC63Uv kO+zfKEpA4bANdKPMtnm/4EwRdasCut0FaqQxMnAH1JwvLgllMskSGeMd24rjUATyiUs A9kmw+jDLN8xsxUkJ+RuF7gVHgKIzxvrO/gusFTkRP4eMp5A47Cac36lznl3V1ID2d9h TP4w== Return-Path: Received: from localhost.localdomain (184.red-37-158-56.dynamicip.rima-tde.net. [37.158.56.184]) by smtp.gmail.com with ESMTPSA id x26sm5359539wmc.14.2019.11.14.02.07.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2019 02:07:30 -0800 (PST) From: Richard Henderson To: gcc-patches@gcc.gnu.org Cc: richard.earnshaw@arm.com, kyrylo.tkachov@arm.com, richard.sandiford@arm.com Subject: [PATCH v2 1/6] aarch64: Add "c" constraint Date: Thu, 14 Nov 2019 11:07:11 +0100 Message-Id: <20191114100716.28827-2-richard.henderson@linaro.org> In-Reply-To: <20191114100716.28827-1-richard.henderson@linaro.org> References: <20191114100716.28827-1-richard.henderson@linaro.org> Mirror arm in letting "c" match the condition code register. * config/aarch64/constraints.md (c): New constraint. --- gcc/config/aarch64/constraints.md | 4 ++++ 1 file changed, 4 insertions(+) -- 2.17.1 diff --git a/gcc/config/aarch64/constraints.md b/gcc/config/aarch64/constraints.md index d0c3dd5bc1f..b9e5d13e851 100644 --- a/gcc/config/aarch64/constraints.md +++ b/gcc/config/aarch64/constraints.md @@ -39,6 +39,10 @@ (define_register_constraint "y" "FP_LO8_REGS" "Floating point and SIMD vector registers V0 - V7.") +(define_constraint "c" + "@internal The condition code register." + (match_operand 0 "cc_register")) + (define_constraint "I" "A constant that can be used with an ADD operation." (and (match_code "const_int") From patchwork Thu Nov 14 10:07:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 179387 Delivered-To: patch@linaro.org Received: by 2002:a92:38d5:0:0:0:0:0 with SMTP id g82csp10837032ilf; Thu, 14 Nov 2019 02:08:17 -0800 (PST) X-Google-Smtp-Source: APXvYqwF81+Gk/5FsRktGrawXfmPUqVXdsIqYE/DX2YXuMmBCgcG+PdpubVU3xXA2+kKqZRP1zFv X-Received: by 2002:a05:6402:2042:: with SMTP id bc2mr173657edb.167.1573726097592; Thu, 14 Nov 2019 02:08:17 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1573726097; cv=none; d=google.com; s=arc-20160816; b=C2DkILEfZRIlS7dwYbR+rHR+fv/mvpYPd5uT0uj8pIwdV01I/KK8YuiC2y7q0D2Ffd XPg6Zqz80O7QZGhKR02ab2yFW3peMEpgZF+2fdt7Ge5WrVlsoWNK3h7kM6d82QG7N44I CHDB1MwR/0SLivVOOdm8a3mEL40R97USK1qpmA+YoZhE/QzWUEA3ozNiYmiqRj5GdfRs cHXu/oo7heJbqmIl6i6AXc6cVt1yP702j37zTuEz3ZPHRznBmkhyBHi0r+ovHuSGETaQ MlQTrkGxV3A3ZvyECH4Kzxek7TZeZFhtcR4fvdV+AXMT31fz06kHTHamElSqnXEt534G /zqQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature:delivered-to:sender:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:mailing-list:dkim-signature :domainkey-signature; bh=089Bc4beoJzRBjhSd5mq9EoVlTd3JUiH87uldhE5CrI=; b=W7Gmkhv1FqUrsY0qLv7InQzANW5R8FN/0CSYilnrZ++myZ99dxkZ4L7PtikYyj5ES6 E3/K1yGB73NMtpZnBJk0xz84TL3Jfa7Zp5pB0idcdVCDX4Z41CAO2LNLDfp7fWC9qQzs l2Y8kCoYjVSzK4yXrrwDJyfN0ZtawXEhpfRru6gH/8f1fHRlOEW2FHlEMr71GSniV7uK /1zWcnFdeOPM/wWdmju1eo2Afg5Fb/SXxqldM5+XiviXKnfQ07zdgDVGUrRvQRNMcoiF B6jzZHtPB9c9r38wZyWY/L/nqo0H/kACGbRzWBdvcNdRxtwvssauf0ymQMgBTE3wlMRA qWJg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=BrHPhW9X; dkim=pass header.i=@linaro.org header.s=google header.b=tsudVjRd; spf=pass (google.com: domain of gcc-patches-return-513345-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom="gcc-patches-return-513345-patch=linaro.org@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from sourceware.org (server1.sourceware.org. [209.132.180.131]) by mx.google.com with ESMTPS id j22si3272015edq.415.2019.11.14.02.08.15 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 14 Nov 2019 02:08:17 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-return-513345-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=BrHPhW9X; dkim=pass header.i=@linaro.org header.s=google header.b=tsudVjRd; spf=pass (google.com: domain of gcc-patches-return-513345-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom="gcc-patches-return-513345-patch=linaro.org@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references; q=dns; s= default; b=xRVXTSEbPiWzRPiiNRm10nnDb7Oxj/w8VezXtYpvVY5cujjBPegM7 3dUsO06IcvOq15GyjUg4RRDXGhZXdpUydxfTzmNB/brg3RMFOfQRp/VXItM4Y2y9 C7a1ZUd16MyVPjOq6/a3BWCJ1eUCL7vZkkuPFvsZer/EHj6Kbw6v58= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references; s= default; bh=FMGzwvLLe1OshKMnoXIuBcXR6z0=; b=BrHPhW9X7g67xUVDLka3 oA8XmeWhZTRzSE1tGYSznaJCQEgZkHdANBeCCaBAOPeO/i+UB/eOMy2NNQJGK4c/ Ef1hEzxnvvTSyvpaL2MX1bYzq7qtsny17ruh9Il8rkubxqpDKkM3uSiA7h4jzaor xVqARfW3o6rT2EC2BONELZU= Received: (qmail 75162 invoked by alias); 14 Nov 2019 10:07:41 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 75104 invoked by uid 89); 14 Nov 2019 10:07:40 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-20.1 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.1 spammy= X-HELO: mail-wm1-f68.google.com Received: from mail-wm1-f68.google.com (HELO mail-wm1-f68.google.com) (209.85.128.68) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 14 Nov 2019 10:07:35 +0000 Received: by mail-wm1-f68.google.com with SMTP id u18so5012634wmc.3 for ; Thu, 14 Nov 2019 02:07:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=089Bc4beoJzRBjhSd5mq9EoVlTd3JUiH87uldhE5CrI=; b=tsudVjRdGUKsEoJHl7vhCZ/FJveHSHQ3P8h0a4pGKB4dYZl1RtTR14D+kDRVLk2hom P5PZi1GIuFcUom9q0oTtoWl4fdaEV7eINjUktcb4Kpkj5SjOgj9rsuvpH0YoOEMpp5Y+ yDVx5h1KePHR6hMjYFb3jmJRPLbjQJ72TgRfF3WXW17wcXqYtNxWQp7tLAvRKapo8O1n ZKcK78v7wnRSuQevahfRZmxCPxbW1aKgkN2Y7X0kTXn/zuCSFcyWUn8wmitnYLa1gvnJ 6ucJL4dl1urO67CL7rlJoz31Sin5Q8CUGrqfHOS74MaTYYPMOc7wMCTzsMEutz7CRqH5 ug6Q== Return-Path: Received: from localhost.localdomain (184.red-37-158-56.dynamicip.rima-tde.net. [37.158.56.184]) by smtp.gmail.com with ESMTPSA id x26sm5359539wmc.14.2019.11.14.02.07.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2019 02:07:32 -0800 (PST) From: Richard Henderson To: gcc-patches@gcc.gnu.org Cc: richard.earnshaw@arm.com, kyrylo.tkachov@arm.com, richard.sandiford@arm.com Subject: [PATCH v2 2/6] arm: Fix the "c" constraint Date: Thu, 14 Nov 2019 11:07:12 +0100 Message-Id: <20191114100716.28827-3-richard.henderson@linaro.org> In-Reply-To: <20191114100716.28827-1-richard.henderson@linaro.org> References: <20191114100716.28827-1-richard.henderson@linaro.org> The existing definition using register class CC_REG does not work because CC_REGNUM does not support normal modes, and so fails to match register_operand. Use a non-register constraint and the cc_register predicate instead. * config/arm/constraints.md (c): Use cc_register predicate. --- gcc/config/arm/constraints.md | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) -- 2.17.1 diff --git a/gcc/config/arm/constraints.md b/gcc/config/arm/constraints.md index b76de81b85c..e02b678d26d 100644 --- a/gcc/config/arm/constraints.md +++ b/gcc/config/arm/constraints.md @@ -94,8 +94,9 @@ "@internal Thumb only. The union of the low registers and the stack register.") -(define_register_constraint "c" "CC_REG" - "@internal The condition code register.") +(define_constraint "c" + "@internal The condition code register." + (match_operand 0 "cc_register")) (define_register_constraint "Cs" "CALLER_SAVE_REGS" "@internal The caller save registers. Useful for sibcalls.") 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[37.158.56.184]) by smtp.gmail.com with ESMTPSA id x26sm5359539wmc.14.2019.11.14.02.07.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2019 02:07:34 -0800 (PST) From: Richard Henderson To: gcc-patches@gcc.gnu.org Cc: richard.earnshaw@arm.com, kyrylo.tkachov@arm.com, richard.sandiford@arm.com Subject: [PATCH v2 3/6] arm: Rename CC_NOOVmode to CC_NZmode Date: Thu, 14 Nov 2019 11:07:13 +0100 Message-Id: <20191114100716.28827-4-richard.henderson@linaro.org> In-Reply-To: <20191114100716.28827-1-richard.henderson@linaro.org> References: <20191114100716.28827-1-richard.henderson@linaro.org> CC_NZmode is a more accurate description of what we require from the mode, and matches up with the definition in aarch64. Rename noov_comparison_operator to nz_comparison_operator in order to match. * config/arm/arm-modes.def (CC_NZ): Rename from CC_NOOV. * config/arm/predicates.md (nz_comparison_operator): Rename from noov_comparison_operator. * config/arm/arm.c (arm_select_cc_mode): Use CC_NZmode name. (arm_gen_dicompare_reg): Likewise. (maybe_get_arm_condition_code): Likewise. (thumb1_final_prescan_insn): Likewise. (arm_emit_coreregs_64bit_shift): Likewise. * config/arm/arm.md (addsi3_compare0): Likewise. (*addsi3_compare0_scratch, subsi3_compare0): Likewise. (*mulsi3_compare0, *mulsi3_compare0_v6): Likewise. (*mulsi3_compare0_scratch, *mulsi3_compare0_scratch_v6): Likewise. (*mulsi3addsi_compare0, *mulsi3addsi_compare0_v6): Likewise. (*mulsi3addsi_compare0_scratch): Likewise. (*mulsi3addsi_compare0_scratch_v6): Likewise. (*andsi3_compare0, *andsi3_compare0_scratch): Likewise. (*zeroextractsi_compare0_scratch): Likewise. (*ne_zeroextractsi, *ne_zeroextractsi_shifted): Likewise. (*ite_ne_zeroextractsi, *ite_ne_zeroextractsi_shifted): Likewise. (andsi_not_shiftsi_si_scc_no_reuse): Likewise. (andsi_not_shiftsi_si_scc): Likewise. (*andsi_notsi_si_compare0, *andsi_notsi_si_compare0_scratch): Likewise. (*iorsi3_compare0, *iorsi3_compare0_scratch): Likewise. (*xorsi3_compare0, *xorsi3_compare0_scratch): Likewise. (*shiftsi3_compare0, *shiftsi3_compare0_scratch): Likewise. (*not_shiftsi_compare0, *not_shiftsi_compare0_scratch): Likewise. (*notsi_compare0, *notsi_compare0_scratch): Likewise. (return_addr_mask, *check_arch2): Likewise. (*arith_shiftsi_compare0, *arith_shiftsi_compare0_scratch): Likewise. (*sub_shiftsi_compare0, *sub_shiftsi_compare0_scratch): Likewise. (compare_scc splitters): Likewise. (movcond_addsi): Likewise. * config/arm/thumb2.md (thumb2_addsi3_compare0): Likewise. (*thumb2_addsi3_compare0_scratch): Likewise. (*thumb2_mulsi_short_compare0): Likewise. (*thumb2_mulsi_short_compare0_scratch): Likewise. (compare peephole2s): Likewise. * config/arm/thumb1.md (thumb1_cbz): Use CC_NZmode and nz_comparison_operator names. (cbranchsi4_insn): Likewise. --- gcc/config/arm/arm.c | 12 +-- gcc/config/arm/arm-modes.def | 4 +- gcc/config/arm/arm.md | 186 +++++++++++++++++------------------ gcc/config/arm/predicates.md | 2 +- gcc/config/arm/thumb1.md | 8 +- gcc/config/arm/thumb2.md | 34 +++---- 6 files changed, 123 insertions(+), 123 deletions(-) -- 2.17.1 diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 9086cf65953..d996207853c 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -15376,7 +15376,7 @@ arm_select_cc_mode (enum rtx_code op, rtx x, rtx y) || GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT || GET_CODE (x) == ROTATERT || (TARGET_32BIT && GET_CODE (x) == ZERO_EXTRACT))) - return CC_NOOVmode; + return CC_NZmode; /* A comparison of ~reg with a const is really a special canoncialization of compare (~const, reg), which is a reverse @@ -15492,11 +15492,11 @@ arm_gen_dicompare_reg (rtx_code code, rtx x, rtx y, rtx scratch) } rtx clobber = gen_rtx_CLOBBER (VOIDmode, scratch); - cc_reg = gen_rtx_REG (CC_NOOVmode, CC_REGNUM); + cc_reg = gen_rtx_REG (CC_NZmode, CC_REGNUM); rtx set = gen_rtx_SET (cc_reg, - gen_rtx_COMPARE (CC_NOOVmode, + gen_rtx_COMPARE (CC_NZmode, gen_rtx_IOR (SImode, x_lo, x_hi), const0_rtx)); emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, @@ -23881,7 +23881,7 @@ maybe_get_arm_condition_code (rtx comparison) return code; return ARM_NV; - case E_CC_NOOVmode: + case E_CC_NZmode: switch (comp_code) { case NE: return ARM_NE; @@ -25304,7 +25304,7 @@ thumb1_final_prescan_insn (rtx_insn *insn) cfun->machine->thumb1_cc_insn = insn; cfun->machine->thumb1_cc_op0 = SET_DEST (set); cfun->machine->thumb1_cc_op1 = const0_rtx; - cfun->machine->thumb1_cc_mode = CC_NOOVmode; + cfun->machine->thumb1_cc_mode = CC_NZmode; if (INSN_CODE (insn) == CODE_FOR_thumb1_subsi3_insn) { rtx src1 = XEXP (SET_SRC (set), 1); @@ -30486,7 +30486,7 @@ arm_emit_coreregs_64bit_shift (enum rtx_code code, rtx out, rtx in, else { /* We have a shift-by-register. */ - rtx cc_reg = gen_rtx_REG (CC_NOOVmode, CC_REGNUM); + rtx cc_reg = gen_rtx_REG (CC_NZmode, CC_REGNUM); /* This alternative requires the scratch registers. */ gcc_assert (scratch1 && REG_P (scratch1)); diff --git a/gcc/config/arm/arm-modes.def b/gcc/config/arm/arm-modes.def index a6b520df32d..2ce53e0efba 100644 --- a/gcc/config/arm/arm-modes.def +++ b/gcc/config/arm/arm-modes.def @@ -29,7 +29,7 @@ ADJUST_FLOAT_FORMAT (HF, ((arm_fp16_format == ARM_FP16_FORMAT_ALTERNATIVE) /* CCFPEmode should be used with floating inequalities, CCFPmode should be used with floating equalities. - CC_NOOVmode should be used with SImode integer equalities. + CC_NZmode should be used if only the N and Z bits are set correctly. CC_Zmode should be used if only the Z flag is set correctly CC_Cmode should be used if only the C flag is set correctly, after an addition. @@ -47,7 +47,7 @@ ADJUST_FLOAT_FORMAT (HF, ((arm_fp16_format == ARM_FP16_FORMAT_ALTERNATIVE) against one of the other operands. CCmode should be used otherwise. */ -CC_MODE (CC_NOOV); +CC_MODE (CC_NZ); CC_MODE (CC_Z); CC_MODE (CC_NV); CC_MODE (CC_SWP); diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index f1d27ffbb4a..823312e7eac 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -1078,8 +1078,8 @@ ) (define_insn "addsi3_compare0" - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (plus:SI (match_operand:SI 1 "s_register_operand" "r, r,r") (match_operand:SI 2 "arm_add_operand" "I,L,r")) (const_int 0))) @@ -1095,8 +1095,8 @@ ) (define_insn "*addsi3_compare0_scratch" - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (plus:SI (match_operand:SI 0 "s_register_operand" "r, r, r") (match_operand:SI 1 "arm_add_operand" "I,L, r")) (const_int 0)))] @@ -2017,8 +2017,8 @@ ) (define_insn "subsi3_compare0" - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (minus:SI (match_operand:SI 1 "arm_rhs_operand" "r,r,I") (match_operand:SI 2 "arm_rhs_operand" "I,r,r")) (const_int 0))) @@ -2256,8 +2256,8 @@ ) (define_insn "*mulsi3_compare0" - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV (mult:SI + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (mult:SI (match_operand:SI 2 "s_register_operand" "r,r") (match_operand:SI 1 "s_register_operand" "%0,r")) (const_int 0))) @@ -2270,8 +2270,8 @@ ) (define_insn "*mulsi3_compare0_v6" - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV (mult:SI + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (mult:SI (match_operand:SI 2 "s_register_operand" "r") (match_operand:SI 1 "s_register_operand" "r")) (const_int 0))) @@ -2284,8 +2284,8 @@ ) (define_insn "*mulsi_compare0_scratch" - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV (mult:SI + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (mult:SI (match_operand:SI 2 "s_register_operand" "r,r") (match_operand:SI 1 "s_register_operand" "%0,r")) (const_int 0))) @@ -2297,8 +2297,8 @@ ) (define_insn "*mulsi_compare0_scratch_v6" - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV (mult:SI + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (mult:SI (match_operand:SI 2 "s_register_operand" "r") (match_operand:SI 1 "s_register_operand" "r")) (const_int 0))) @@ -2310,8 +2310,8 @@ ) (define_insn "*mulsi3addsi_compare0" - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (plus:SI (mult:SI (match_operand:SI 2 "s_register_operand" "r,r,r,r") (match_operand:SI 1 "s_register_operand" "%0,r,0,r")) @@ -2327,8 +2327,8 @@ ) (define_insn "*mulsi3addsi_compare0_v6" - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (plus:SI (mult:SI (match_operand:SI 2 "s_register_operand" "r") (match_operand:SI 1 "s_register_operand" "r")) @@ -2344,8 +2344,8 @@ ) (define_insn "*mulsi3addsi_compare0_scratch" - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (plus:SI (mult:SI (match_operand:SI 2 "s_register_operand" "r,r,r,r") (match_operand:SI 1 "s_register_operand" "%0,r,0,r")) @@ -2359,8 +2359,8 @@ ) (define_insn "*mulsi3addsi_compare0_scratch_v6" - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (plus:SI (mult:SI (match_operand:SI 2 "s_register_operand" "r") (match_operand:SI 1 "s_register_operand" "r")) @@ -3004,8 +3004,8 @@ ) (define_insn "*andsi3_compare0" - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (and:SI (match_operand:SI 1 "s_register_operand" "r,r,r") (match_operand:SI 2 "arm_not_operand" "I,K,r")) (const_int 0))) @@ -3021,8 +3021,8 @@ ) (define_insn "*andsi3_compare0_scratch" - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (and:SI (match_operand:SI 0 "s_register_operand" "r,r,r") (match_operand:SI 1 "arm_not_operand" "I,K,r")) (const_int 0))) @@ -3037,8 +3037,8 @@ ) (define_insn "*zeroextractsi_compare0_scratch" - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV (zero_extract:SI + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (zero_extract:SI (match_operand:SI 0 "s_register_operand" "r") (match_operand 1 "const_int_operand" "n") (match_operand 2 "const_int_operand" "n")) @@ -3078,12 +3078,12 @@ && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) + (INTVAL (operands[3]) & 1) <= 8 && INTVAL (operands[2]) + INTVAL (operands[3]) <= 32)" - [(parallel [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV (and:SI (match_dup 1) (match_dup 2)) + [(parallel [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (and:SI (match_dup 1) (match_dup 2)) (const_int 0))) (set (match_dup 0) (and:SI (match_dup 1) (match_dup 2)))]) (set (match_dup 0) - (if_then_else:SI (eq (reg:CC_NOOV CC_REGNUM) (const_int 0)) + (if_then_else:SI (eq (reg:CC_NZ CC_REGNUM) (const_int 0)) (match_dup 0) (const_int 1)))] " operands[2] = GEN_INT (((1 << INTVAL (operands[2])) - 1) @@ -3108,12 +3108,12 @@ "TARGET_ARM" "#" "TARGET_ARM" - [(parallel [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV (ashift:SI (match_dup 1) (match_dup 2)) + [(parallel [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (ashift:SI (match_dup 1) (match_dup 2)) (const_int 0))) (set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 2)))]) (set (match_dup 0) - (if_then_else:SI (eq (reg:CC_NOOV CC_REGNUM) (const_int 0)) + (if_then_else:SI (eq (reg:CC_NZ CC_REGNUM) (const_int 0)) (match_dup 0) (const_int 1)))] " operands[2] = GEN_INT (32 - INTVAL (operands[2])); @@ -3146,12 +3146,12 @@ && INTVAL (operands[2]) + (INTVAL (operands[3]) & 1) <= 8 && INTVAL (operands[2]) + INTVAL (operands[3]) <= 32) && !reg_overlap_mentioned_p (operands[0], operands[4])" - [(parallel [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV (and:SI (match_dup 1) (match_dup 2)) + [(parallel [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (and:SI (match_dup 1) (match_dup 2)) (const_int 0))) (set (match_dup 0) (and:SI (match_dup 1) (match_dup 2)))]) (set (match_dup 0) - (if_then_else:SI (eq (reg:CC_NOOV CC_REGNUM) (const_int 0)) + (if_then_else:SI (eq (reg:CC_NZ CC_REGNUM) (const_int 0)) (match_dup 0) (match_dup 4)))] " operands[2] = GEN_INT (((1 << INTVAL (operands[2])) - 1) @@ -3175,12 +3175,12 @@ "TARGET_ARM && !reg_overlap_mentioned_p (operands[0], operands[3])" "#" "TARGET_ARM && !reg_overlap_mentioned_p (operands[0], operands[3])" - [(parallel [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV (ashift:SI (match_dup 1) (match_dup 2)) + [(parallel [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (ashift:SI (match_dup 1) (match_dup 2)) (const_int 0))) (set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 2)))]) (set (match_dup 0) - (if_then_else:SI (eq (reg:CC_NOOV CC_REGNUM) (const_int 0)) + (if_then_else:SI (eq (reg:CC_NZ CC_REGNUM) (const_int 0)) (match_dup 0) (match_dup 3)))] " operands[2] = GEN_INT (32 - INTVAL (operands[2])); @@ -3498,8 +3498,8 @@ ;; bics output. Pattern restricts Thumb2 shift operand as bics for Thumb2 ;; does not support shift by register. (define_insn "andsi_not_shiftsi_si_scc_no_reuse" - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (and:SI (not:SI (match_operator:SI 0 "shift_operator" [(match_operand:SI 1 "s_register_operand" "r,r") (match_operand:SI 2 "shift_amount_operand" "M,r")])) @@ -3518,8 +3518,8 @@ ;; Same as andsi_not_shiftsi_si_scc_no_reuse, but the bics result is also ;; getting reused later. (define_insn "andsi_not_shiftsi_si_scc" - [(parallel [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV + [(parallel [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (and:SI (not:SI (match_operator:SI 0 "shift_operator" [(match_operand:SI 1 "s_register_operand" "r,r") (match_operand:SI 2 "shift_amount_operand" "M,r")])) @@ -3540,8 +3540,8 @@ ) (define_insn "*andsi_notsi_si_compare0" - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (and:SI (not:SI (match_operand:SI 2 "s_register_operand" "r")) (match_operand:SI 1 "s_register_operand" "r")) (const_int 0))) @@ -3554,8 +3554,8 @@ ) (define_insn "*andsi_notsi_si_compare0_scratch" - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (and:SI (not:SI (match_operand:SI 2 "s_register_operand" "r")) (match_operand:SI 1 "s_register_operand" "r")) (const_int 0))) @@ -3644,8 +3644,8 @@ ) (define_insn "*iorsi3_compare0" - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (ior:SI (match_operand:SI 1 "s_register_operand" "%r,0,r") (match_operand:SI 2 "arm_rhs_operand" "I,l,r")) (const_int 0))) @@ -3660,8 +3660,8 @@ ) (define_insn "*iorsi3_compare0_scratch" - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (ior:SI (match_operand:SI 1 "s_register_operand" "%r,0,r") (match_operand:SI 2 "arm_rhs_operand" "I,l,r")) (const_int 0))) @@ -3734,8 +3734,8 @@ ) (define_insn "*xorsi3_compare0" - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV (xor:SI (match_operand:SI 1 "s_register_operand" "r,r") + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (xor:SI (match_operand:SI 1 "s_register_operand" "r,r") (match_operand:SI 2 "arm_rhs_operand" "I,r")) (const_int 0))) (set (match_operand:SI 0 "s_register_operand" "=r,r") @@ -3747,8 +3747,8 @@ ) (define_insn "*xorsi3_compare0_scratch" - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV (xor:SI (match_operand:SI 0 "s_register_operand" "r,r") + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (xor:SI (match_operand:SI 0 "s_register_operand" "r,r") (match_operand:SI 1 "arm_rhs_operand" "I,r")) (const_int 0)))] "TARGET_32BIT" @@ -4524,8 +4524,8 @@ ) (define_insn "*shiftsi3_compare0" - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV (match_operator:SI 3 "shift_operator" + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (match_operator:SI 3 "shift_operator" [(match_operand:SI 1 "s_register_operand" "r,r") (match_operand:SI 2 "arm_rhs_operand" "M,r")]) (const_int 0))) @@ -4539,8 +4539,8 @@ ) (define_insn "*shiftsi3_compare0_scratch" - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV (match_operator:SI 3 "shift_operator" + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (match_operator:SI 3 "shift_operator" [(match_operand:SI 1 "s_register_operand" "r,r") (match_operand:SI 2 "arm_rhs_operand" "M,r")]) (const_int 0))) @@ -4565,8 +4565,8 @@ (set_attr "type" "mvn_shift,mvn_shift_reg")]) (define_insn "*not_shiftsi_compare0" - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (not:SI (match_operator:SI 3 "shift_operator" [(match_operand:SI 1 "s_register_operand" "r,r") (match_operand:SI 2 "shift_amount_operand" "M,r")])) @@ -4581,8 +4581,8 @@ (set_attr "type" "mvn_shift,mvn_shift_reg")]) (define_insn "*not_shiftsi_compare0_scratch" - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (not:SI (match_operator:SI 3 "shift_operator" [(match_operand:SI 1 "s_register_operand" "r,r") (match_operand:SI 2 "shift_amount_operand" "M,r")])) @@ -5172,8 +5172,8 @@ ) (define_insn "*notsi_compare0" - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV (not:SI (match_operand:SI 1 "s_register_operand" "r")) + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (not:SI (match_operand:SI 1 "s_register_operand" "r")) (const_int 0))) (set (match_operand:SI 0 "s_register_operand" "=r") (not:SI (match_dup 1)))] @@ -5184,8 +5184,8 @@ ) (define_insn "*notsi_compare0_scratch" - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV (not:SI (match_operand:SI 1 "s_register_operand" "r")) + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (not:SI (match_operand:SI 1 "s_register_operand" "r")) (const_int 0))) (clobber (match_scratch:SI 0 "=r"))] "TARGET_32BIT" @@ -8787,7 +8787,7 @@ (define_expand "return_addr_mask" [(set (match_dup 1) - (compare:CC_NOOV (unspec [(const_int 0)] UNSPEC_CHECK_ARCH) + (compare:CC_NZ (unspec [(const_int 0)] UNSPEC_CHECK_ARCH) (const_int 0))) (set (match_operand:SI 0 "s_register_operand") (if_then_else:SI (eq (match_dup 1) (const_int 0)) @@ -8795,12 +8795,12 @@ (const_int 67108860)))] ; 0x03fffffc "TARGET_ARM" " - operands[1] = gen_rtx_REG (CC_NOOVmode, CC_REGNUM); + operands[1] = gen_rtx_REG (CC_NZmode, CC_REGNUM); ") (define_insn "*check_arch2" - [(set (match_operand:CC_NOOV 0 "cc_register" "") - (compare:CC_NOOV (unspec [(const_int 0)] UNSPEC_CHECK_ARCH) + [(set (match_operand:CC_NZ 0 "cc_register" "") + (compare:CC_NZ (unspec [(const_int 0)] UNSPEC_CHECK_ARCH) (const_int 0)))] "TARGET_ARM" "teq\\t%|r0, %|r0\;teq\\t%|pc, %|pc" @@ -9336,8 +9336,8 @@ "") (define_insn "*arith_shiftsi_compare0" - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (match_operator:SI 1 "shiftable_operator" [(match_operator:SI 3 "shift_operator" [(match_operand:SI 4 "s_register_operand" "r,r") @@ -9355,8 +9355,8 @@ (set_attr "type" "alus_shift_imm,alus_shift_reg")]) (define_insn "*arith_shiftsi_compare0_scratch" - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (match_operator:SI 1 "shiftable_operator" [(match_operator:SI 3 "shift_operator" [(match_operand:SI 4 "s_register_operand" "r,r") @@ -9386,8 +9386,8 @@ (set_attr "type" "alus_shift_imm,alus_shift_reg")]) (define_insn "*sub_shiftsi_compare0" - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (minus:SI (match_operand:SI 1 "s_register_operand" "r,r") (match_operator:SI 2 "shift_operator" [(match_operand:SI 3 "s_register_operand" "r,r") @@ -9404,8 +9404,8 @@ (set_attr "type" "alus_shift_imm,alus_shift_reg")]) (define_insn "*sub_shiftsi_compare0_scratch" - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (minus:SI (match_operand:SI 1 "s_register_operand" "r,r") (match_operator:SI 2 "shift_operator" [(match_operand:SI 3 "s_register_operand" "r,r") @@ -9549,11 +9549,11 @@ (clobber (reg:CC CC_REGNUM))] "TARGET_32BIT && reload_completed" [(parallel - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV (minus:SI (match_dup 1) (match_dup 2)) + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (minus:SI (match_dup 1) (match_dup 2)) (const_int 0))) (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))]) - (cond_exec (ne:CC_NOOV (reg:CC_NOOV CC_REGNUM) (const_int 0)) + (cond_exec (ne:CC_NZ (reg:CC_NZ CC_REGNUM) (const_int 0)) (set (match_dup 0) (const_int 1)))]) (define_insn_and_split "*compare_scc" @@ -10258,8 +10258,8 @@ ) (define_split - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV (ior:SI + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (ior:SI (and:SI (match_operand:SI 0 "s_register_operand" "") (const_int 1)) (match_operator:SI 1 "arm_comparison_operator" @@ -10271,14 +10271,14 @@ [(set (match_dup 4) (ior:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)]) (match_dup 0))) - (set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV (and:SI (match_dup 4) (const_int 1)) + (set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (and:SI (match_dup 4) (const_int 1)) (const_int 0)))] "") (define_split - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV (ior:SI + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (ior:SI (match_operator:SI 1 "arm_comparison_operator" [(match_operand:SI 2 "s_register_operand" "") (match_operand:SI 3 "arm_add_operand" "")]) @@ -10290,8 +10290,8 @@ [(set (match_dup 4) (ior:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)]) (match_dup 0))) - (set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV (and:SI (match_dup 4) (const_int 1)) + (set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (and:SI (match_dup 4) (const_int 1)) (const_int 0)))] "") ;; ??? The conditional patterns above need checking for Thumb-2 usefulness @@ -10380,8 +10380,8 @@ "TARGET_32BIT" "#" "&& reload_completed" - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (plus:SI (match_dup 3) (match_dup 4)) (const_int 0))) diff --git a/gcc/config/arm/predicates.md b/gcc/config/arm/predicates.md index c1f655c7040..6e9263553cc 100644 --- a/gcc/config/arm/predicates.md +++ b/gcc/config/arm/predicates.md @@ -430,7 +430,7 @@ (match_operand 0 "arm_vsel_comparison_operator")) (match_operand 0 "expandable_comparison_operator"))) -(define_special_predicate "noov_comparison_operator" +(define_special_predicate "nz_comparison_operator" (match_code "lt,ge,eq,ne")) (define_special_predicate "minmax_operator" diff --git a/gcc/config/arm/thumb1.md b/gcc/config/arm/thumb1.md index 5c70200bef3..9df793cc47c 100644 --- a/gcc/config/arm/thumb1.md +++ b/gcc/config/arm/thumb1.md @@ -1023,9 +1023,9 @@ if (!rtx_equal_p (cfun->machine->thumb1_cc_op0, operands[1]) || !rtx_equal_p (cfun->machine->thumb1_cc_op1, operands[2])) t = NULL_RTX; - if (cfun->machine->thumb1_cc_mode == CC_NOOVmode) + if (cfun->machine->thumb1_cc_mode == CC_NZmode) { - if (!noov_comparison_operator (operands[0], VOIDmode)) + if (!nz_comparison_operator (operands[0], VOIDmode)) t = NULL_RTX; } else if (cfun->machine->thumb1_cc_mode != CCmode) @@ -1097,9 +1097,9 @@ if (!rtx_equal_p (cfun->machine->thumb1_cc_op0, operands[1]) || !rtx_equal_p (cfun->machine->thumb1_cc_op1, operands[2])) t = NULL_RTX; - if (cfun->machine->thumb1_cc_mode == CC_NOOVmode) + if (cfun->machine->thumb1_cc_mode == CC_NZmode) { - if (!noov_comparison_operator (operands[0], VOIDmode)) + if (!nz_comparison_operator (operands[0], VOIDmode)) t = NULL_RTX; } else if (cfun->machine->thumb1_cc_mode != CCmode) diff --git a/gcc/config/arm/thumb2.md b/gcc/config/arm/thumb2.md index 7fce50b045b..2558e404b88 100644 --- a/gcc/config/arm/thumb2.md +++ b/gcc/config/arm/thumb2.md @@ -1287,8 +1287,8 @@ ) (define_insn "thumb2_addsi3_compare0" - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (plus:SI (match_operand:SI 1 "s_register_operand" "l, 0, r") (match_operand:SI 2 "arm_add_operand" "lPt,Ps,rIL")) (const_int 0))) @@ -1321,8 +1321,8 @@ ) (define_insn "*thumb2_addsi3_compare0_scratch" - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (plus:SI (match_operand:SI 0 "s_register_operand" "l, r") (match_operand:SI 1 "arm_add_operand" "lPv,rIL")) (const_int 0)))] @@ -1359,8 +1359,8 @@ (set_attr "type" "muls")]) (define_insn "*thumb2_mulsi_short_compare0" - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (mult:SI (match_operand:SI 1 "register_operand" "%0") (match_operand:SI 2 "register_operand" "l")) (const_int 0))) @@ -1372,8 +1372,8 @@ (set_attr "type" "muls")]) (define_insn "*thumb2_mulsi_short_compare0_scratch" - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (mult:SI (match_operand:SI 1 "register_operand" "%0") (match_operand:SI 2 "register_operand" "l")) (const_int 0))) @@ -1477,15 +1477,15 @@ ) (define_peephole2 - [(set (match_operand:CC_NOOV 0 "cc_register" "") - (compare:CC_NOOV (zero_extract:SI + [(set (match_operand:CC_NZ 0 "cc_register" "") + (compare:CC_NZ (zero_extract:SI (match_operand:SI 1 "low_register_operand" "") (const_int 1) (match_operand:SI 2 "const_int_operand" "")) (const_int 0))) (match_scratch:SI 3 "l") (set (pc) - (if_then_else (match_operator:CC_NOOV 4 "equality_operator" + (if_then_else (match_operator:CC_NZ 4 "equality_operator" [(match_dup 0) (const_int 0)]) (match_operand 5 "" "") (match_operand 6 "" "")))] @@ -1493,7 +1493,7 @@ && (INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) < 32) && peep2_reg_dead_p (2, operands[0])" [(parallel [(set (match_dup 0) - (compare:CC_NOOV (ashift:SI (match_dup 1) (match_dup 2)) + (compare:CC_NZ (ashift:SI (match_dup 1) (match_dup 2)) (const_int 0))) (clobber (match_dup 3))]) (set (pc) @@ -1506,15 +1506,15 @@ ") (define_peephole2 - [(set (match_operand:CC_NOOV 0 "cc_register" "") - (compare:CC_NOOV (zero_extract:SI + [(set (match_operand:CC_NZ 0 "cc_register" "") + (compare:CC_NZ (zero_extract:SI (match_operand:SI 1 "low_register_operand" "") (match_operand:SI 2 "const_int_operand" "") (const_int 0)) (const_int 0))) (match_scratch:SI 3 "l") (set (pc) - (if_then_else (match_operator:CC_NOOV 4 "equality_operator" + (if_then_else (match_operator:CC_NZ 4 "equality_operator" [(match_dup 0) (const_int 0)]) (match_operand 5 "" "") (match_operand 6 "" "")))] @@ -1522,8 +1522,8 @@ && (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 32) && peep2_reg_dead_p (2, operands[0])" [(parallel [(set (match_dup 0) - (compare:CC_NOOV (ashift:SI (match_dup 1) (match_dup 2)) - (const_int 0))) + (compare:CC_NZ (ashift:SI (match_dup 1) (match_dup 2)) + (const_int 0))) (clobber (match_dup 3))]) (set (pc) (if_then_else (match_op_dup 4 [(match_dup 0) (const_int 0)]) From patchwork Thu Nov 14 10:07:14 2019 Content-Type: text/plain; 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[37.158.56.184]) by smtp.gmail.com with ESMTPSA id x26sm5359539wmc.14.2019.11.14.02.07.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2019 02:07:36 -0800 (PST) From: Richard Henderson To: gcc-patches@gcc.gnu.org Cc: richard.earnshaw@arm.com, kyrylo.tkachov@arm.com, richard.sandiford@arm.com Subject: [PATCH v2 4/6] arm, aarch64: Add support for __GCC_ASM_FLAG_OUTPUTS__ Date: Thu, 14 Nov 2019 11:07:14 +0100 Message-Id: <20191114100716.28827-5-richard.henderson@linaro.org> In-Reply-To: <20191114100716.28827-1-richard.henderson@linaro.org> References: <20191114100716.28827-1-richard.henderson@linaro.org> Since all but a couple of lines is shared between the two targets, enable them both at once. * config/arm/aarch-common-protos.h (arm_md_asm_adjust): Declare. * config/arm/aarch-common.c (arm_md_asm_adjust): New. * config/arm/arm-c.c (arm_cpu_builtins): Define __GCC_ASM_FLAG_OUTPUTS__. * config/arm/arm.c (TARGET_MD_ASM_ADJUST): New. * config/aarch64/aarch64-c.c (aarch64_define_unconditional_macros): Define __GCC_ASM_FLAG_OUTPUTS__. * config/aarch64/aarch64.c (TARGET_MD_ASM_ADJUST): New. * doc/extend.texi (FlagOutputOperands): Add documentation for ARM and AArch64. --- gcc/config/arm/aarch-common-protos.h | 6 ++ gcc/config/aarch64/aarch64-c.c | 2 + gcc/config/aarch64/aarch64.c | 3 + gcc/config/arm/aarch-common.c | 136 +++++++++++++++++++++++++++ gcc/config/arm/arm-c.c | 1 + gcc/config/arm/arm.c | 3 + gcc/doc/extend.texi | 39 ++++++++ 7 files changed, 190 insertions(+) -- 2.17.1 diff --git a/gcc/config/arm/aarch-common-protos.h b/gcc/config/arm/aarch-common-protos.h index 3bf38a104f6..f15cf336e9d 100644 --- a/gcc/config/arm/aarch-common-protos.h +++ b/gcc/config/arm/aarch-common-protos.h @@ -23,6 +23,8 @@ #ifndef GCC_AARCH_COMMON_PROTOS_H #define GCC_AARCH_COMMON_PROTOS_H +#include "hard-reg-set.h" + extern int aarch_accumulator_forwarding (rtx_insn *, rtx_insn *); extern bool aarch_rev16_p (rtx); extern bool aarch_rev16_shleft_mask_imm_p (rtx, machine_mode); @@ -141,5 +143,9 @@ struct cpu_cost_table const struct vector_cost_table vect; }; +rtx_insn * +arm_md_asm_adjust (vec &outputs, vec &/*inputs*/, + vec &constraints, + vec &clobbers, HARD_REG_SET &clobbered_regs); #endif /* GCC_AARCH_COMMON_PROTOS_H */ diff --git a/gcc/config/aarch64/aarch64-c.c b/gcc/config/aarch64/aarch64-c.c index 7c322ca0813..0af859f1c14 100644 --- a/gcc/config/aarch64/aarch64-c.c +++ b/gcc/config/aarch64/aarch64-c.c @@ -69,6 +69,8 @@ aarch64_define_unconditional_macros (cpp_reader *pfile) builtin_define ("__ARM_FEATURE_UNALIGNED"); builtin_define ("__ARM_PCS_AAPCS64"); builtin_define_with_int_value ("__ARM_SIZEOF_WCHAR_T", WCHAR_TYPE_SIZE / 8); + + builtin_define ("__GCC_ASM_FLAG_OUTPUTS__"); } /* Undefine/redefine macros that depend on the current backend state and may diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index d2a3c7ef90a..9a5f27fea3a 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -21933,6 +21933,9 @@ aarch64_libgcc_floating_mode_supported_p #undef TARGET_STRICT_ARGUMENT_NAMING #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true +#undef TARGET_MD_ASM_ADJUST +#define TARGET_MD_ASM_ADJUST arm_md_asm_adjust + struct gcc_target targetm = TARGET_INITIALIZER; #include "gt-aarch64.h" diff --git a/gcc/config/arm/aarch-common.c b/gcc/config/arm/aarch-common.c index 965a07a43e3..760ef6c9c0a 100644 --- a/gcc/config/arm/aarch-common.c +++ b/gcc/config/arm/aarch-common.c @@ -26,10 +26,16 @@ #include "config.h" #include "system.h" #include "coretypes.h" +#include "insn-modes.h" #include "tm.h" #include "rtl.h" #include "rtl-iter.h" #include "memmodel.h" +#include "diagnostic.h" +#include "tree.h" +#include "expr.h" +#include "function.h" +#include "emit-rtl.h" /* Return TRUE if X is either an arithmetic shift left, or is a multiplication by a power of two. */ @@ -520,3 +526,133 @@ arm_mac_accumulator_is_mul_result (rtx producer, rtx consumer) && !reg_overlap_mentioned_p (mul_result, mac_op0) && !reg_overlap_mentioned_p (mul_result, mac_op1)); } + +/* Worker function for TARGET_MD_ASM_ADJUST. + We implement asm flag outputs. */ + +rtx_insn * +arm_md_asm_adjust (vec &outputs, vec &/*inputs*/, + vec &constraints, + vec &/*clobbers*/, HARD_REG_SET &/*clobbered_regs*/) +{ + bool saw_asm_flag = false; + + start_sequence (); + for (unsigned i = 0, n = outputs.length (); i < n; ++i) + { + const char *con = constraints[i]; + if (strncmp (con, "=@cc", 4) != 0) + continue; + con += 4; + if (strchr (con, ',') != NULL) + { + error ("alternatives not allowed in % flag output"); + continue; + } + + machine_mode mode; + rtx_code code; + int con01 = 0; + +#define C(X, Y) (unsigned char)(X) * 256 + (unsigned char)(Y) + + /* All of the condition codes are two characters. */ + if (con[0] != 0 && con[1] != 0 && con[2] == 0) + con01 = C(con[0], con[1]); + + switch (con01) + { + case C('c', 'c'): + case C('l', 'o'): + mode = CC_Cmode, code = GEU; + break; + case C('c', 's'): + case C('h', 's'): + mode = CC_Cmode, code = LTU; + break; + case C('e', 'q'): + mode = CC_NZmode, code = EQ; + break; + case C('g', 'e'): + mode = CCmode, code = GE; + break; + case C('g', 't'): + mode = CCmode, code = GT; + break; + case C('h', 'i'): + mode = CCmode, code = GTU; + break; + case C('l', 'e'): + mode = CCmode, code = LE; + break; + case C('l', 's'): + mode = CCmode, code = LEU; + break; + case C('l', 't'): + mode = CCmode, code = LT; + break; + case C('m', 'i'): + mode = CC_NZmode, code = LT; + break; + case C('n', 'e'): + mode = CC_NZmode, code = NE; + break; + case C('p', 'l'): + mode = CC_NZmode, code = GE; + break; + case C('v', 'c'): + mode = CC_Vmode, code = EQ; + break; + case C('v', 's'): + mode = CC_Vmode, code = NE; + break; + default: + error ("unknown % flag output %qs", constraints[i]); + continue; + } + +#undef C + + rtx dest = outputs[i]; + machine_mode dest_mode = GET_MODE (dest); + if (!SCALAR_INT_MODE_P (dest_mode)) + { + error ("invalid type for % flag output"); + continue; + } + + if (!saw_asm_flag) + { + /* This is the first asm flag output. Here we put the flags + register in as the real output and adjust the condition to + allow it. */ + constraints[i] = "=c"; + outputs[i] = gen_rtx_REG (CCmode, CC_REGNUM); + saw_asm_flag = true; + } + else + { + /* We don't need the flags register as output twice. */ + constraints[i] = "=X"; + outputs[i] = gen_rtx_SCRATCH (word_mode); + } + + rtx x = gen_rtx_REG (mode, CC_REGNUM); + x = gen_rtx_fmt_ee (code, word_mode, x, const0_rtx); + + if (dest_mode == word_mode) + emit_insn (gen_rtx_SET (dest, x)); + else + { + rtx tmp = gen_reg_rtx (word_mode); + emit_insn (gen_rtx_SET (tmp, x)); + + tmp = convert_modes (dest_mode, word_mode, tmp, true); + emit_move_insn (dest, tmp); + } + } + rtx_insn *seq = get_insns (); + end_sequence (); + + return saw_asm_flag ? seq : NULL; +} diff --git a/gcc/config/arm/arm-c.c b/gcc/config/arm/arm-c.c index 34695fa0112..c4485ce7af1 100644 --- a/gcc/config/arm/arm-c.c +++ b/gcc/config/arm/arm-c.c @@ -122,6 +122,7 @@ arm_cpu_builtins (struct cpp_reader* pfile) if (arm_arch_notm) builtin_define ("__ARM_ARCH_ISA_ARM"); builtin_define ("__APCS_32__"); + builtin_define ("__GCC_ASM_FLAG_OUTPUTS__"); def_or_undef_macro (pfile, "__thumb__", TARGET_THUMB); def_or_undef_macro (pfile, "__thumb2__", TARGET_THUMB2); diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index d996207853c..fea3882a2a6 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -816,6 +816,9 @@ static const struct attribute_spec arm_attribute_table[] = #undef TARGET_CONSTANT_ALIGNMENT #define TARGET_CONSTANT_ALIGNMENT arm_constant_alignment + +#undef TARGET_MD_ASM_ADJUST +#define TARGET_MD_ASM_ADJUST arm_md_asm_adjust /* Obstack for minipool constant handling. */ static struct obstack minipool_obstack; diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index 9db4f9b1d29..1c8ae0d5cd3 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -9771,6 +9771,45 @@ referenced within the assembler template via @code{%0} etc, as there's no corresponding text in the assembly language. @table @asis +@item ARM +@itemx AArch64 +The flag output constraints for the ARM family are of the form +@samp{=@@cc@var{cond}} where @var{cond} is one of the standard +conditions defined in the ARM ARM for @code{ConditionHolds}. + +@table @code +@item eq +Z flag set, or equal +@item ne +Z flag clear or not equal +@item cs +@itemx hs +C flag set or unsigned greater than equal +@item cc +@itemx lo +C flag clear or unsigned less than +@item mi +N flag set or ``minus'' +@item pl +N flag clear or ``plus'' +@item vs +V flag set or signed overflow +@item vc +V flag clear +@item hi +unsigned greater than +@item ls +unsigned less than equal +@item ge +signed greater than equal +@item lt +signed less than +@item gt +signed greater than +@item le +signed less than equal +@end table + @item x86 family The flag output constraints for the x86 family are of the form @samp{=@@cc@var{cond}} where @var{cond} is one of the standard From patchwork Thu Nov 14 10:07:15 2019 Content-Type: text/plain; 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[37.158.56.184]) by smtp.gmail.com with ESMTPSA id x26sm5359539wmc.14.2019.11.14.02.07.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2019 02:07:37 -0800 (PST) From: Richard Henderson To: gcc-patches@gcc.gnu.org Cc: richard.earnshaw@arm.com, kyrylo.tkachov@arm.com, richard.sandiford@arm.com Subject: [PATCH v2 5/6] arm: Add testsuite checks for asm-flag Date: Thu, 14 Nov 2019 11:07:15 +0100 Message-Id: <20191114100716.28827-6-richard.henderson@linaro.org> In-Reply-To: <20191114100716.28827-1-richard.henderson@linaro.org> References: <20191114100716.28827-1-richard.henderson@linaro.org> Inspired by the tests in gcc.target/i386. Testing code generation, diagnostics, and execution. * gcc.target/arm/asm-flag-1.c: New test. * gcc.target/arm/asm-flag-3.c: New test. * gcc.target/arm/asm-flag-5.c: New test. * gcc.target/arm/asm-flag-6.c: New test. --- gcc/testsuite/gcc.target/arm/asm-flag-1.c | 36 +++++++++++++ gcc/testsuite/gcc.target/arm/asm-flag-3.c | 38 ++++++++++++++ gcc/testsuite/gcc.target/arm/asm-flag-5.c | 30 +++++++++++ gcc/testsuite/gcc.target/arm/asm-flag-6.c | 62 +++++++++++++++++++++++ 4 files changed, 166 insertions(+) create mode 100644 gcc/testsuite/gcc.target/arm/asm-flag-1.c create mode 100644 gcc/testsuite/gcc.target/arm/asm-flag-3.c create mode 100644 gcc/testsuite/gcc.target/arm/asm-flag-5.c create mode 100644 gcc/testsuite/gcc.target/arm/asm-flag-6.c -- 2.17.1 diff --git a/gcc/testsuite/gcc.target/arm/asm-flag-1.c b/gcc/testsuite/gcc.target/arm/asm-flag-1.c new file mode 100644 index 00000000000..9707ebfcebb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/asm-flag-1.c @@ -0,0 +1,36 @@ +/* Test the valid @cc asm flag outputs. */ +/* { dg-do compile } */ +/* { dg-options "-O" } */ + +#ifndef __GCC_ASM_FLAG_OUTPUTS__ +#error "missing preprocessor define" +#endif + +void f(char *out) +{ + asm("" + : "=@ccne"(out[0]), "=@cceq"(out[1]), + "=@cccs"(out[2]), "=@cccc"(out[3]), + "=@ccmi"(out[4]), "=@ccpl"(out[5]), + "=@ccvs"(out[6]), "=@ccvc"(out[7]), + "=@cchi"(out[8]), "=@ccls"(out[9]), + "=@ccge"(out[10]), "=@cclt"(out[11]), + "=@ccgt"(out[12]), "=@ccle"(out[13]), + "=@cchs"(out[14]), "=@cclo"(out[15])); +} + +/* There will be at least one of each. */ +/* { dg-final { scan-assembler "movne" } } */ +/* { dg-final { scan-assembler "moveq" } } */ +/* { dg-final { scan-assembler "movcs" } } */ +/* { dg-final { scan-assembler "movcc" } } */ +/* { dg-final { scan-assembler "movmi" } } */ +/* { dg-final { scan-assembler "movpl" } } */ +/* { dg-final { scan-assembler "movvs" } } */ +/* { dg-final { scan-assembler "movvc" } } */ +/* { dg-final { scan-assembler "movhi" } } */ +/* { dg-final { scan-assembler "movls" } } */ +/* { dg-final { scan-assembler "movge" } } */ +/* { dg-final { scan-assembler "movls" } } */ +/* { dg-final { scan-assembler "movgt" } } */ +/* { dg-final { scan-assembler "movle" } } */ diff --git a/gcc/testsuite/gcc.target/arm/asm-flag-3.c b/gcc/testsuite/gcc.target/arm/asm-flag-3.c new file mode 100644 index 00000000000..e84e3431277 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/asm-flag-3.c @@ -0,0 +1,38 @@ +/* Test some of the valid @cc asm flag outputs. */ +/* { dg-do compile } */ +/* { dg-options "-O" } */ + +#define DO(C) \ +void f##C(void) { char x; asm("" : "=@cc"#C(x)); if (!x) asm(""); asm(""); } + +DO(ne) +DO(eq) +DO(cs) +DO(cc) +DO(hs) +DO(lo) +DO(mi) +DO(pl) +DO(vs) +DO(vc) +DO(hi) +DO(ls) +DO(ge) +DO(lt) +DO(gt) +DO(le) + +/* { dg-final { scan-assembler "bne" } } */ +/* { dg-final { scan-assembler "beq" } } */ +/* { dg-final { scan-assembler "bcs" } } */ +/* { dg-final { scan-assembler "bcc" } } */ +/* { dg-final { scan-assembler "bmi" } } */ +/* { dg-final { scan-assembler "bpl" } } */ +/* { dg-final { scan-assembler "bvs" } } */ +/* { dg-final { scan-assembler "bvc" } } */ +/* { dg-final { scan-assembler "bhi" } } */ +/* { dg-final { scan-assembler "bls" } } */ +/* { dg-final { scan-assembler "bge" } } */ +/* { dg-final { scan-assembler "blt" } } */ +/* { dg-final { scan-assembler "bgt" } } */ +/* { dg-final { scan-assembler "ble" } } */ diff --git a/gcc/testsuite/gcc.target/arm/asm-flag-5.c b/gcc/testsuite/gcc.target/arm/asm-flag-5.c new file mode 100644 index 00000000000..4d4394e1478 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/asm-flag-5.c @@ -0,0 +1,30 @@ +/* Test error conditions of asm flag outputs. */ +/* { dg-do compile } */ +/* { dg-options "" } */ + +void f_B(void) { _Bool x; asm("" : "=@cccc"(x)); } +void f_c(void) { char x; asm("" : "=@cccc"(x)); } +void f_s(void) { short x; asm("" : "=@cccc"(x)); } +void f_i(void) { int x; asm("" : "=@cccc"(x)); } +void f_l(void) { long x; asm("" : "=@cccc"(x)); } +void f_ll(void) { long long x; asm("" : "=@cccc"(x)); } + +void f_f(void) +{ + float x; + asm("" : "=@cccc"(x)); /* { dg-error invalid type } */ +} + +void f_d(void) +{ + double x; + asm("" : "=@cccc"(x)); /* { dg-error invalid type } */ +} + +struct S { int x[3]; }; + +void f_S(void) +{ + struct S x; + asm("" : "=@cccc"(x)); /* { dg-error invalid type } */ +} diff --git a/gcc/testsuite/gcc.target/arm/asm-flag-6.c b/gcc/testsuite/gcc.target/arm/asm-flag-6.c new file mode 100644 index 00000000000..09174e04ae6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/asm-flag-6.c @@ -0,0 +1,62 @@ +/* Executable testcase for 'output flags.' */ +/* { dg-do run } */ + +int test_bits (long nzcv) +{ + long n, z, c, v; + + __asm__ ("msr APSR_nzcvq, %[in]" + : "=@ccmi"(n), "=@cceq"(z), "=@cccs"(c), "=@ccvs"(v) + : [in] "r"(nzcv << 28)); + + return n * 8 + z * 4 + c * 2 + v == nzcv; +} + +int test_cmps (long x, long y) +{ + long gt, lt, ge, le; + + __asm__ ("cmp %[x], %[y]" + : "=@ccgt"(gt), "=@cclt"(lt), "=@ccge"(ge), "=@ccle"(le) + : [x] "r"(x), [y] "r"(y)); + + return (gt == (x > y) + && lt == (x < y) + && ge == (x >= y) + && le == (x <= y)); +} + +int test_cmpu (unsigned long x, unsigned long y) +{ + long gt, lt, ge, le; + + __asm__ ("cmp %[x], %[y]" + : "=@cchi"(gt), "=@cclo"(lt), "=@cchs"(ge), "=@ccls"(le) + : [x] "r"(x), [y] "r"(y)); + + return (gt == (x > y) + && lt == (x < y) + && ge == (x >= y) + && le == (x <= y)); +} + +int main () +{ + long i, j; + + for (i = 0; i < 16; ++i) + if (!test_bits (i)) + __builtin_abort (); + + for (i = -1; i <= 1; ++i) + for (j = -1; j <= 1; ++j) + if (!test_cmps (i, j)) + __builtin_abort (); + + for (i = 0; i <= 2; ++i) + for (j = 0; j <= 2; ++j) + if (!test_cmpu (i, j)) + __builtin_abort (); + + return 0; +} From patchwork Thu Nov 14 10:07:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 179391 Delivered-To: patch@linaro.org Received: by 2002:a92:38d5:0:0:0:0:0 with SMTP id g82csp10837977ilf; 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[37.158.56.184]) by smtp.gmail.com with ESMTPSA id x26sm5359539wmc.14.2019.11.14.02.07.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2019 02:07:39 -0800 (PST) From: Richard Henderson To: gcc-patches@gcc.gnu.org Cc: richard.earnshaw@arm.com, kyrylo.tkachov@arm.com, richard.sandiford@arm.com Subject: [PATCH v2 6/6] aarch64: Add testsuite checks for asm-flag Date: Thu, 14 Nov 2019 11:07:16 +0100 Message-Id: <20191114100716.28827-7-richard.henderson@linaro.org> In-Reply-To: <20191114100716.28827-1-richard.henderson@linaro.org> References: <20191114100716.28827-1-richard.henderson@linaro.org> Inspired by the tests in gcc.target/i386. Testing code generation, diagnostics, and execution. * gcc.target/aarch64/asm-flag-1.c: New test. * gcc.target/aarch64/asm-flag-3.c: New test. * gcc.target/aarch64/asm-flag-5.c: New test. * gcc.target/aarch64/asm-flag-6.c: New test. --- gcc/testsuite/gcc.target/aarch64/asm-flag-1.c | 35 +++++++++++ gcc/testsuite/gcc.target/aarch64/asm-flag-3.c | 38 ++++++++++++ gcc/testsuite/gcc.target/aarch64/asm-flag-5.c | 30 +++++++++ gcc/testsuite/gcc.target/aarch64/asm-flag-6.c | 62 +++++++++++++++++++ 4 files changed, 165 insertions(+) create mode 100644 gcc/testsuite/gcc.target/aarch64/asm-flag-1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/asm-flag-3.c create mode 100644 gcc/testsuite/gcc.target/aarch64/asm-flag-5.c create mode 100644 gcc/testsuite/gcc.target/aarch64/asm-flag-6.c -- 2.17.1 diff --git a/gcc/testsuite/gcc.target/aarch64/asm-flag-1.c b/gcc/testsuite/gcc.target/aarch64/asm-flag-1.c new file mode 100644 index 00000000000..49901e59c38 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/asm-flag-1.c @@ -0,0 +1,35 @@ +/* Test the valid @cc asm flag outputs. */ +/* { dg-do compile } */ +/* { dg-options "-O" } */ + +#ifndef __GCC_ASM_FLAG_OUTPUTS__ +#error "missing preprocessor define" +#endif + +void f(char *out) +{ + asm("" + : "=@ccne"(out[0]), "=@cceq"(out[1]), + "=@cccs"(out[2]), "=@cccc"(out[3]), + "=@ccmi"(out[4]), "=@ccpl"(out[5]), + "=@ccvs"(out[6]), "=@ccvc"(out[7]), + "=@cchi"(out[8]), "=@ccls"(out[9]), + "=@ccge"(out[10]), "=@cclt"(out[11]), + "=@ccgt"(out[12]), "=@ccle"(out[13]), + "=@cchs"(out[14]), "=@cclo"(out[15])); +} + +/* { dg-final { scan-assembler "cset.*, ne" } } */ +/* { dg-final { scan-assembler "cset.*, eq" } } */ +/* { dg-final { scan-assembler "cset.*, cs" } } */ +/* { dg-final { scan-assembler "cset.*, cc" } } */ +/* { dg-final { scan-assembler "cset.*, mi" } } */ +/* { dg-final { scan-assembler "cset.*, pl" } } */ +/* { dg-final { scan-assembler "cset.*, vs" } } */ +/* { dg-final { scan-assembler "cset.*, vc" } } */ +/* { dg-final { scan-assembler "cset.*, hi" } } */ +/* { dg-final { scan-assembler "cset.*, ls" } } */ +/* { dg-final { scan-assembler "cset.*, ge" } } */ +/* { dg-final { scan-assembler "cset.*, ls" } } */ +/* { dg-final { scan-assembler "cset.*, gt" } } */ +/* { dg-final { scan-assembler "cset.*, le" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/asm-flag-3.c b/gcc/testsuite/gcc.target/aarch64/asm-flag-3.c new file mode 100644 index 00000000000..e84e3431277 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/asm-flag-3.c @@ -0,0 +1,38 @@ +/* Test some of the valid @cc asm flag outputs. */ +/* { dg-do compile } */ +/* { dg-options "-O" } */ + +#define DO(C) \ +void f##C(void) { char x; asm("" : "=@cc"#C(x)); if (!x) asm(""); asm(""); } + +DO(ne) +DO(eq) +DO(cs) +DO(cc) +DO(hs) +DO(lo) +DO(mi) +DO(pl) +DO(vs) +DO(vc) +DO(hi) +DO(ls) +DO(ge) +DO(lt) +DO(gt) +DO(le) + +/* { dg-final { scan-assembler "bne" } } */ +/* { dg-final { scan-assembler "beq" } } */ +/* { dg-final { scan-assembler "bcs" } } */ +/* { dg-final { scan-assembler "bcc" } } */ +/* { dg-final { scan-assembler "bmi" } } */ +/* { dg-final { scan-assembler "bpl" } } */ +/* { dg-final { scan-assembler "bvs" } } */ +/* { dg-final { scan-assembler "bvc" } } */ +/* { dg-final { scan-assembler "bhi" } } */ +/* { dg-final { scan-assembler "bls" } } */ +/* { dg-final { scan-assembler "bge" } } */ +/* { dg-final { scan-assembler "blt" } } */ +/* { dg-final { scan-assembler "bgt" } } */ +/* { dg-final { scan-assembler "ble" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/asm-flag-5.c b/gcc/testsuite/gcc.target/aarch64/asm-flag-5.c new file mode 100644 index 00000000000..4d4394e1478 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/asm-flag-5.c @@ -0,0 +1,30 @@ +/* Test error conditions of asm flag outputs. */ +/* { dg-do compile } */ +/* { dg-options "" } */ + +void f_B(void) { _Bool x; asm("" : "=@cccc"(x)); } +void f_c(void) { char x; asm("" : "=@cccc"(x)); } +void f_s(void) { short x; asm("" : "=@cccc"(x)); } +void f_i(void) { int x; asm("" : "=@cccc"(x)); } +void f_l(void) { long x; asm("" : "=@cccc"(x)); } +void f_ll(void) { long long x; asm("" : "=@cccc"(x)); } + +void f_f(void) +{ + float x; + asm("" : "=@cccc"(x)); /* { dg-error invalid type } */ +} + +void f_d(void) +{ + double x; + asm("" : "=@cccc"(x)); /* { dg-error invalid type } */ +} + +struct S { int x[3]; }; + +void f_S(void) +{ + struct S x; + asm("" : "=@cccc"(x)); /* { dg-error invalid type } */ +} diff --git a/gcc/testsuite/gcc.target/aarch64/asm-flag-6.c b/gcc/testsuite/gcc.target/aarch64/asm-flag-6.c new file mode 100644 index 00000000000..963b5a48c70 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/asm-flag-6.c @@ -0,0 +1,62 @@ +/* Executable testcase for 'output flags.' */ +/* { dg-do run } */ + +int test_bits (long nzcv) +{ + long n, z, c, v; + + __asm__ ("msr nzcv, %[in]" + : "=@ccmi"(n), "=@cceq"(z), "=@cccs"(c), "=@ccvs"(v) + : [in] "r"(nzcv << 28)); + + return n * 8 + z * 4 + c * 2 + v == nzcv; +} + +int test_cmps (long x, long y) +{ + long gt, lt, ge, le; + + __asm__ ("cmp %[x], %[y]" + : "=@ccgt"(gt), "=@cclt"(lt), "=@ccge"(ge), "=@ccle"(le) + : [x] "r"(x), [y] "r"(y)); + + return (gt == (x > y) + && lt == (x < y) + && ge == (x >= y) + && le == (x <= y)); +} + +int test_cmpu (unsigned long x, unsigned long y) +{ + long gt, lt, ge, le; + + __asm__ ("cmp %[x], %[y]" + : "=@cchi"(gt), "=@cclo"(lt), "=@cchs"(ge), "=@ccls"(le) + : [x] "r"(x), [y] "r"(y)); + + return (gt == (x > y) + && lt == (x < y) + && ge == (x >= y) + && le == (x <= y)); +} + +int main () +{ + long i, j; + + for (i = 0; i < 16; ++i) + if (!test_bits (i)) + __builtin_abort (); + + for (i = -1; i <= 1; ++i) + for (j = -1; j <= 1; ++j) + if (!test_cmps (i, j)) + __builtin_abort (); + + for (i = 0; i <= 2; ++i) + for (j = 0; j <= 2; ++j) + if (!test_cmpu (i, j)) + __builtin_abort (); + + return 0; +}