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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42bb37f7849sm58471775e9.7.2024.08.30.10.34.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Aug 2024 10:34:54 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Cc: Thomas Huth , Laurent Vivier Subject: [PATCH 1/3] hw/m68k/mcf5208: Avoid shifting off end of integer Date: Fri, 30 Aug 2024 18:34:50 +0100 Message-Id: <20240830173452.2086140-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240830173452.2086140-1-peter.maydell@linaro.org> References: <20240830173452.2086140-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In m5208_sys_read(), we have a loop of n from 0 to 31, and we calculate (2u << n). For the n == 31 iteration this will shift off the top of the unsigned 32 bit integer. This is harmless, because we're going to stop the loop with n == 31 anyway, but we can avoid the error by using 64-bit arithmetic here. (The SDCS0 register is documented at https://www.nxp.com/docs/en/reference-manual/MCF5208RM.pdf section 18.4.5; we want the lower 5 bits to indicate the RAM size, where 31 == 4GB, 30 == 2GB, and so on down. As it happens, the layout of the mcf5208evb board memory map means it doesn't make sense to have more than 1GB of RAM in any case.) Resolves: Coverity CID 1547727 Signed-off-by: Peter Maydell Reviewed-by: Thomas Huth --- hw/m68k/mcf5208.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/m68k/mcf5208.c b/hw/m68k/mcf5208.c index ec14096aa43..0ad347dfa81 100644 --- a/hw/m68k/mcf5208.c +++ b/hw/m68k/mcf5208.c @@ -158,7 +158,7 @@ static uint64_t m5208_sys_read(void *opaque, hwaddr addr, { int n; for (n = 0; n < 32; n++) { - if (current_machine->ram_size < (2u << n)) { + if (current_machine->ram_size < (2ULL << n)) { break; } } From patchwork Fri Aug 30 17:34:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 824020 Delivered-To: patch@linaro.org Received: by 2002:a5d:48c1:0:b0:367:895a:4699 with SMTP id p1csp900864wrs; Fri, 30 Aug 2024 10:35:58 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWvUZE3cHJajHBzucrEFL6dLE0wIp1Q1fh8dw5L+dQxDrkmJ/z5fB3ZbJChJbZ4x9CNDdEZkQ==@linaro.org X-Google-Smtp-Source: AGHT+IH7bZ8qWnmf9nSuXn9CXqWFlzvnhm//60rEQRsK+8eLri4E8PAUbzfV6Z7yXpsAvoBhSzeZ X-Received: by 2002:a05:622a:581a:b0:456:4655:34e6 with SMTP id d75a77b69052e-4567f52ab93mr72587751cf.23.1725039358284; Fri, 30 Aug 2024 10:35:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1725039358; cv=none; d=google.com; s=arc-20160816; b=R6vEIzfsOYNTyi/oN3vE/tWydjhKWaKpAYDks830lF5PQLkjBqy9COAHCKWH9VAD2H luH6ktqI7dLv1G6aUsPso8jdvuP0vrraukuB9OQJpkRqwKq9V7nZZa2s5Wo/zGKP5G4P PvnU04oI9w+iQLB90Xh/vRluo7bCMsRhLoVGWfZAIxoDo9ri7+iYt3ORkyWh7KcehowY f63sYd4dukYqNxX5pg7lzmS5K06ujrzBHTO53s65glkNA1e+eYFiQVEiFHR2u4HZv5iC 8pr7vrgCKL5ynZUSbnbYR8RZugZqJlJnwqcK42NpVMvc504bMCB9tIH5SLsFgNgUHeOp TocQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=RAPk9TkgHuJzLy5angeKNdvCxMHfEkd/1HkV7jTog4w=; fh=jEMUlOhRchVnwxdOriHWDghOaH0lX23dQXVcYqElGvo=; b=SCMW0xUveWE/ZMElLrDXQd+My3P4CAmJDZOhtDQxZxXEWSq+HqTTQt07OeAUydpeED 2/zFBHH8xV/6/L5YTlxgQsbJQ7wsQiQZ3smW7OM33JWq5P/Hpb1Z9PovMnP9GBfLGboa 2snxabbGIsYeo6tCHH/UH7T9cxUEsq89zVbo8FGftvpgr2nETo5QdXcY//oVn++2VpmK g5MgnhTfbrP80zGfEE2f0xRUb6HWxEbfB06aGRHYoU7H085qRv014kozp6hUr4igk6hu xJ/p0zMv4FxrLARjf7xO0Acu8mxwWFkBOV34211KuCEXSNOKrr7PoSecydX/0Y8XW8BM SSBg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZTCIBFov; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42bb37f7849sm58471775e9.7.2024.08.30.10.34.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Aug 2024 10:34:54 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Cc: Thomas Huth , Laurent Vivier Subject: [PATCH 2/3] hw/m68k/mcf5208: Add URLs for datasheets Date: Fri, 30 Aug 2024 18:34:51 +0100 Message-Id: <20240830173452.2086140-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240830173452.2086140-1-peter.maydell@linaro.org> References: <20240830173452.2086140-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The datasheets for the SoC and board we model here are still available from the NXP website; add their URLs and titles for future reference. Signed-off-by: Peter Maydell Reviewed-by: Thomas Huth --- hw/m68k/mcf5208.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/hw/m68k/mcf5208.c b/hw/m68k/mcf5208.c index 0ad347dfa81..b6677ad6bc3 100644 --- a/hw/m68k/mcf5208.c +++ b/hw/m68k/mcf5208.c @@ -4,6 +4,14 @@ * Copyright (c) 2007 CodeSourcery. * * This code is licensed under the GPL + * + * This file models both the MCF5208 SoC, and the + * MCF5208EVB evaluation board. For details see + * + * "MCF5208 Reference Manual" + * https://www.nxp.com/docs/en/reference-manual/MCF5208RM.pdf + * "M5208EVB-RevB 32-bit Microcontroller User Manual" + * https://www.nxp.com/docs/en/reference-manual/M5208EVBUM.pdf */ #include "qemu/osdep.h" From patchwork Fri Aug 30 17:34:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 824022 Delivered-To: patch@linaro.org Received: by 2002:a5d:48c1:0:b0:367:895a:4699 with SMTP id p1csp900906wrs; Fri, 30 Aug 2024 10:36:03 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWGNg41AGii9P26l+oIag9yCUd4YXlySLbUg7N7ykxzAgF+9sAxDkJ8XnDR0b8jn4dTZdp7mA==@linaro.org X-Google-Smtp-Source: AGHT+IFVP0Jq5C3KNPRS4BacrauzCcQGq4qmAP4YW66pFPkuyDGxpZTWsTjVmlgtb3YpRi0nripo X-Received: by 2002:a05:622a:5c86:b0:446:6018:5f7b with SMTP id d75a77b69052e-457054235a9mr2135341cf.46.1725039363582; Fri, 30 Aug 2024 10:36:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1725039363; cv=none; d=google.com; s=arc-20160816; b=aDZCDpsEiwQ1HjQjWwWlpLgFFRV6PMYSuse3S0TU3WrEsd+UFsGnibydzHK+6Z5Aot J/iX5LaYrTwtKYiXYkKmtqkEslgxxLud+MRzLX2c7jtdRqvlq/3fVGppmhK+59WAkL+Y LNuctCey2fb5XA2TGL9Y87ioMnGqIfn4rMhT07kFrgGzOc3gEZzB6oUVHBt+ucxP7xX+ 79467aQL/88R82mYF/AjI3iLS4sKObwkwXx1+KC5XFrpabK1gKLl33RB7cQ5D+eBIP2z UpS/P9Nl+0PAu8brwXuqPaW9X3kNhZ89qWBh1Qj2Xmq4IXHKOsS6D0FRJOoPfewh/0O6 /vDw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=iYtUTT0TIbHg3HS+ud7uRweJ2SSTTNwBbnoH0NdYWvc=; fh=jEMUlOhRchVnwxdOriHWDghOaH0lX23dQXVcYqElGvo=; b=cFN6/7FdVb/TLfRJMgqKZ3KFz2lCG7kaQnC4q57I6B3MaEWrA+9ys9PM6DN5K6cA8I UeZCRE8lFabIQ5xnxSyrgnmZsB8LT9BMA8+3bAA0IsNAxATzP+jNw+Fff3V5lZJczVvc jg+EmOfaqFl3exIxw1bEllRrFfdK0d3F0wCQaD+pOODE/cyI4vBwNaRHGe79wyk3OXAD Q0Bg7xO2vsikcVtmWd58t3Rlo+c4q7V7QY4hl7tsGpfGLgFRrWbJwTcV1Vz294wQ8lRr IZH2i7QGKA79+LeNmJ3ehCW8OHH8OEU4iqbhsK4cYFjIyA86GTwPeGMbGij0cZcg/3gi qBhQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jeDWUsLO; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42bb37f7849sm58471775e9.7.2024.08.30.10.34.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Aug 2024 10:34:55 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Cc: Thomas Huth , Laurent Vivier Subject: [PATCH 3/3] hw/nubus/nubus-device: Range check 'slot' property Date: Fri, 30 Aug 2024 18:34:52 +0100 Message-Id: <20240830173452.2086140-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240830173452.2086140-1-peter.maydell@linaro.org> References: <20240830173452.2086140-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The TYPE_NUBUS_DEVICE class lets the user specify the nubus slot using an int32 "slot" QOM property. Its realize method doesn't do any range checking on this value, which Coverity notices by way of the possibility that 'nd->slot * NUBUS_SUPER_SLOT_SIZE' might overflow the 32-bit arithmetic it is using. Constrain the slot value to be less than NUBUS_SLOT_NB (16). Resolves: Coverity CID 1464070 Signed-off-by: Peter Maydell Reviewed-by: Thomas Huth Reviewed-by: Mark Cave-Ayland --- hw/nubus/nubus-device.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/hw/nubus/nubus-device.c b/hw/nubus/nubus-device.c index be4cb246966..26fbcf29a2b 100644 --- a/hw/nubus/nubus-device.c +++ b/hw/nubus/nubus-device.c @@ -35,6 +35,13 @@ static void nubus_device_realize(DeviceState *dev, Error **errp) uint8_t *rom_ptr; int ret; + if (nd->slot < 0 || nd->slot >= NUBUS_SLOT_NB) { + error_setg(errp, + "'slot' value %d out of range (must be between 0 and %d)", + nd->slot, NUBUS_SLOT_NB - 1); + return; + } + /* Super */ slot_offset = nd->slot * NUBUS_SUPER_SLOT_SIZE;